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268 lines
16 KiB
C
268 lines
16 KiB
C
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/******************************************************************************
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* Filename: hw_soc_adc.h
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* Revised: $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
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* Revision: $Revision: 9943 $
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_SOC_ADC_H__
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#define __HW_SOC_ADC_H__
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//*****************************************************************************
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//
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// The following are defines for the SOC_ADC register offsets.
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//
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//*****************************************************************************
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#define SOC_ADC_ADCCON1 0x400D7000 // This register controls the ADC.
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#define SOC_ADC_ADCCON2 0x400D7004 // This register controls the ADC.
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#define SOC_ADC_ADCCON3 0x400D7008 // This register controls the ADC.
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#define SOC_ADC_ADCL 0x400D700C // This register contains the
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// least-significant part of ADC
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// conversion result.
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#define SOC_ADC_ADCH 0x400D7010 // This register contains the
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// most-significant part of ADC
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// conversion result.
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#define SOC_ADC_RNDL 0x400D7014 // This registers contains
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// random-number-generator data;
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// low byte.
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#define SOC_ADC_RNDH 0x400D7018 // This register contains
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// random-number-generator data;
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// high byte.
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#define SOC_ADC_CMPCTL 0x400D7024 // Analog comparator control and
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// status register.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// SOC_ADC_ADCCON1 register.
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//
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//*****************************************************************************
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#define SOC_ADC_ADCCON1_EOC 0x00000080 // End of conversion. Cleared when
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// ADCH has been read. If a new
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// conversion is completed before
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// the previous data has been read,
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// the EOC bit remains high. 0:
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// Conversion not complete 1:
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// Conversion completed
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#define SOC_ADC_ADCCON1_EOC_M 0x00000080
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#define SOC_ADC_ADCCON1_EOC_S 7
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#define SOC_ADC_ADCCON1_ST 0x00000040 // Start conversion Read as 1
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// until conversion completes 0: No
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// conversion in progress. 1: Start
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// a conversion sequence if
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// ADCCON1.STSEL = 11 and no
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// sequence is running.
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#define SOC_ADC_ADCCON1_ST_M 0x00000040
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#define SOC_ADC_ADCCON1_ST_S 6
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#define SOC_ADC_ADCCON1_STSEL_M 0x00000030 // Start select Selects the event
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// that starts a new conversion
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// sequence 00: Not implemented 01:
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// Full speed. Do not wait for
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// triggers 10: Timer 1 channel 0
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// compare event 11: ADCCON1.ST = 1
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#define SOC_ADC_ADCCON1_STSEL_S 4
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#define SOC_ADC_ADCCON1_RCTRL_M 0x0000000C // Controls the 16-bit
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// random-number generator (see
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// User Guide Chapter 16) When 01
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// is written, the setting
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// automatically returns to 00 when
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// the operation completes. 00:
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// Normal operation (13x unrolling)
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// 01: Clock the LFSR once (13x
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// unrolling) 10: Reserved 11:
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// Stopped. The random-number
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// generator is turned off.
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#define SOC_ADC_ADCCON1_RCTRL_S 2
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// SOC_ADC_ADCCON2 register.
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//
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//*****************************************************************************
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#define SOC_ADC_ADCCON2_SREF_M 0x000000C0 // Selects reference voltage used
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// for the sequence of conversions
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// 00: Internal reference 01:
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// External reference on AIN7 pin
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// 10: AVDD5 pin 11: External
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// reference on AIN6-AIN7
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// differential input
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#define SOC_ADC_ADCCON2_SREF_S 6
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#define SOC_ADC_ADCCON2_SDIV_M 0x00000030 // Sets the decimation rate for
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// channels included in the
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// sequence of conversions. The
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// decimation rate also determines
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// the resolution and time required
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// to complete a conversion. 00: 64
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// decimation rate (7 bits ENOB
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// setting) 01: 128 decimation rate
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// (9 bits ENOB setting) 10: 256
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// decimation rate (10 bits ENOB
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// setting) 11: 512 decimation rate
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// (12 bits ENOB setting)
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#define SOC_ADC_ADCCON2_SDIV_S 4
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#define SOC_ADC_ADCCON2_SCH_M 0x0000000F // Sequence channel select Selects
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// the end of the sequence A
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// sequence can either be from AIN0
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// to AIN7 (SCH <= 7) or from
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// differential input AIN0-AIN1 to
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// AIN6-AIN7 (8 <= SCH <= 11). For
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// other settings, only one
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// conversions is performed. When
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// read, these bits indicate the
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// channel number on which a
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// conversion is ongoing: 0000:
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// AIN0 0001: AIN1 0010: AIN2 0011:
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// AIN3 0100: AIN4 0101: AIN5 0110:
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// AIN6 0111: AIN7 1000: AIN0-AIN1
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// 1001: AIN2-AIN3 1010: AIN4-AIN5
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// 1011: AIN6-AIN7 1100: GND 1101:
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// Reserved 1110: Temperature
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// sensor 1111: VDD/3
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#define SOC_ADC_ADCCON2_SCH_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// SOC_ADC_ADCCON3 register.
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//
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//*****************************************************************************
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#define SOC_ADC_ADCCON3_EREF_M 0x000000C0 // Selects reference voltage used
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// for the extra conversion 00:
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// Internal reference 01: External
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// reference on AIN7 pin 10: AVDD5
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// pin 11: External reference on
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// AIN6-AIN7 differential input
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#define SOC_ADC_ADCCON3_EREF_S 6
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#define SOC_ADC_ADCCON3_EDIV_M 0x00000030 // Sets the decimation rate used
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// for the extra conversion The
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// decimation rate also determines
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// the resolution and the time
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// required to complete the
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// conversion. 00: 64 decimation
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// rate (7 bits ENOB) 01: 128
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// decimation rate (9 bits ENOB)
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// 10: 256 decimation rate (10 bits
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// ENOB) 11: 512 decimation rate
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// (12 bits ENOB)
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#define SOC_ADC_ADCCON3_EDIV_S 4
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#define SOC_ADC_ADCCON3_ECH_M 0x0000000F // Single channel select. Selects
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// the channel number of the single
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// conversion that is triggered by
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// writing to ADCCON3. 0000: AIN0
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// 0001: AIN1 0010: AIN2 0011: AIN3
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// 0100: AIN4 0101: AIN5 0110: AIN6
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// 0111: AIN7 1000: AIN0-AIN1 1001:
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// AIN2-AIN3 1010: AIN4-AIN5 1011:
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// AIN6-AIN7 1100: GND 1101:
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// Reserved 1110: Temperature
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// sensor 1111: VDD/3
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#define SOC_ADC_ADCCON3_ECH_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SOC_ADC_ADCL register.
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//
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//*****************************************************************************
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#define SOC_ADC_ADCL_ADC_M 0x000000FC // Least-significant part of ADC
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// conversion result
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#define SOC_ADC_ADCL_ADC_S 2
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SOC_ADC_ADCH register.
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//
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//*****************************************************************************
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#define SOC_ADC_ADCH_ADC_M 0x000000FF // Most-significant part of ADC
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// conversion result
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#define SOC_ADC_ADCH_ADC_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SOC_ADC_RNDL register.
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//
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//*****************************************************************************
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#define SOC_ADC_RNDL_RNDL_M 0x000000FF // Random value/seed or CRC
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// result, low byte When used for
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// random-number generation,
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// writing to this register twice
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// seeds the random-number
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// generator. Writing to this
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// register copies the 8 LSBs of
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// the LFSR to the 8 MSBs and
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// replaces the 8 LSBs with the
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// data value written. The value
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// returned when reading from this
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// register is the 8 LSBs of the
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// LFSR. When used for
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// random-number generation,
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// reading this register returns
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// the 8 LSBs of the random number.
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// When used for CRC calculations,
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// reading this register returns
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// the 8 LSBs of the CRC result.
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#define SOC_ADC_RNDL_RNDL_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SOC_ADC_RNDH register.
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//
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//*****************************************************************************
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#define SOC_ADC_RNDH_RNDH_M 0x000000FF // Random value or CRC
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// result/input data, high byte
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// When written, a CRC16
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// calculation is triggered, and
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// the data value written is
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// processed starting with the MSB.
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// The value returned when reading
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// from this register is the 8 MSBs
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// of the LFSR. When used for
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// random-number generation,
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// reading this register returns
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// the 8 MSBs of the random number.
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// When used for CRC calculations,
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// reading this register returns
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// the 8 MSBs of the CRC result.
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#define SOC_ADC_RNDH_RNDH_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// SOC_ADC_CMPCTL register.
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//
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//*****************************************************************************
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#define SOC_ADC_CMPCTL_EN 0x00000002 // Comparator enable
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#define SOC_ADC_CMPCTL_EN_M 0x00000002
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#define SOC_ADC_CMPCTL_EN_S 1
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#define SOC_ADC_CMPCTL_OUTPUT 0x00000001 // Comparator output
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#define SOC_ADC_CMPCTL_OUTPUT_M 0x00000001
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#define SOC_ADC_CMPCTL_OUTPUT_S 0
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#endif // __HW_SOC_ADC_H__
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