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19 lines
585 B
Plaintext
19 lines
585 B
Plaintext
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/*
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* NXP Kinetis CPU with the following memory layout:
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* 256 kB flash @ 0x00000000
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* 32 kB RAM, split into two banks: 16 kB SRAM_L, 16 kB SRAM_U.
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* SRAM_L ends at 0x1fffffff, SRAM_U begins at 0x20000000
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*/
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OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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MEMORY
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{
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vectors (rx) : ORIGIN = 0x00000000, LENGTH = 0x400
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flashsec (rx) : ORIGIN = 0x00000400, LENGTH = 0x10
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rom (rx) : ORIGIN = 0x00000410, LENGTH = 256K - 0x410
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ram (rwx) : ORIGIN = 0x20000000 - 16K, LENGTH = 32K
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}
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INCLUDE kinetis.ld
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