mirror of
https://github.com/RIOT-OS/RIOT.git
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293 lines
10 KiB
C
293 lines
10 KiB
C
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/*
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* Copyright (C) 2014 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup board_nucleo-l1
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* @{
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*
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* @file periph_conf.h
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* @brief Peripheral MCU configuration for the nucleo-l1 board
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*
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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*/
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#ifndef __PERIPH_CONF_H
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#define __PERIPH_CONF_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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**/
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#define CLOCK_HSI (16000000U) /* frequency of external oscillator */
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#define CLOCK_CORECLOCK (32000000U) /* targeted core clock frequency */
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/* configuration of PLL prescaler and multiply values */
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/* CORECLOCK := HSI / PLL_HSI_DIV * PLL_HSI_MUL */
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#define CLOCK_PLL_HSE_DIV RCC_CFGR_PLLDIV2
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#define CLOCK_PLL_HSE_MUL RCC_CFGR_PLLMUL4
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/* configuration of peripheral bus clock prescalers */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
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/* configuration of flash access cycles */
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#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
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/** @} */
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/**
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* @brief Timer configuration
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* @{
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*/
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#define TIMER_NUMOF (2U)
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#define TIMER_0_EN 1
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#define TIMER_1_EN 1
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/* Timer 0 configuration */
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#define TIMER_0_DEV_0 TIM2
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#define TIMER_0_DEV_1 TIM3
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#define TIMER_0_CHANNELS 4
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#define TIMER_0_PRESCALER (32U)
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#define TIMER_0_MAX_VALUE (0xffff)
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#define TIMER_0_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN | RCC_APB1ENR_TIM3EN))
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#define TIMER_0_ISR_0 isr_tim2
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#define TIMER_0_ISR_1 isr_tim3
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#define TIMER_0_IRQ_CHAN_0 TIM2_IRQn
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#define TIMER_0_IRQ_CHAN_1 TIM3_IRQn
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#define TIMER_0_IRQ_PRIO 1
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#define TIMER_0_TRIG_SEL TIM_SMCR_TS_0
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/* Timer 1 configuration */
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#define TIMER_1_DEV_0 TIM4
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#define TIMER_1_DEV_1 TIM5
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#define TIMER_1_CHANNELS 4
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#define TIMER_1_PRESCALER (32U)
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#define TIMER_1_MAX_VALUE (0xffff)
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#define TIMER_1_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN | RCC_APB1ENR_TIM5EN))
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#define TIMER_1_ISR_0 isr_tim4
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#define TIMER_1_ISR_1 isr_tim5
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#define TIMER_1_IRQ_CHAN_0 TIM4_IRQn
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#define TIMER_1_IRQ_CHAN_1 TIM5_IRQn
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#define TIMER_1_IRQ_PRIO 1
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#define TIMER_1_TRIG_SEL TIM_SMCR_TS_1
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/** @} */
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/**
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* @brief UART configuration
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*/
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#define UART_NUMOF (1U)
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#define UART_0_EN 1
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#define UART_IRQ_PRIO 1
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/* UART 0 device configuration */
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#define UART_0_DEV USART2
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#define UART_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART2EN)
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#define UART_0_CLK (CLOCK_CORECLOCK) /* UART clock runs with 32MHz (F_CPU / 1) */
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#define UART_0_IRQ USART2_IRQn
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#define UART_0_ISR isr_usart2
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#define UART_0_BUS_FREQ 32000000
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/* UART 0 pin configuration */
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#define UART_0_PORT GPIOA
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#define UART_0_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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#define UART_0_RX_PIN 3
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#define UART_0_TX_PIN 2
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#define UART_0_AF 7
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/**
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* @brief GPIO configuration
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*/
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#define GPIO_NUMOF 16
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#define GPIO_0_EN 1
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#define GPIO_1_EN 1
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#define GPIO_2_EN 1
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#define GPIO_3_EN 1
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#define GPIO_4_EN 1
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#define GPIO_5_EN 1
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#define GPIO_6_EN 1
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#define GPIO_7_EN 1
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#define GPIO_8_EN 1
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#define GPIO_9_EN 1
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#define GPIO_10_EN 1
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#define GPIO_11_EN 1
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#define GPIO_12_EN 1
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#define GPIO_13_EN 1
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#define GPIO_14_EN 1
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#define GPIO_15_EN 1
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#define GPIO_IRQ_PRIO 1
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/* IRQ config */
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#define GPIO_IRQ_0 GPIO_13
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#define GPIO_IRQ_1 GPIO_14
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#define GPIO_IRQ_2 GPIO_7
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#define GPIO_IRQ_3 GPIO_0
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#define GPIO_IRQ_4 GPIO_5
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#define GPIO_IRQ_5 GPIO_12
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#define GPIO_IRQ_6 GPIO_11
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#define GPIO_IRQ_7 GPIO_1
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#define GPIO_IRQ_8 GPIO_3
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#define GPIO_IRQ_9 GPIO_2
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#define GPIO_IRQ_10 GPIO_4
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#define GPIO_IRQ_11 GPIO_6
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#define GPIO_IRQ_12 GPIO_15
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#define GPIO_IRQ_13 GPIO_8
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#define GPIO_IRQ_14 GPIO_9
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#define GPIO_IRQ_15 GPIO_10
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/* GPIO channel 0 config */
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#define GPIO_0_PORT GPIOA /* Used for user button 1 */
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#define GPIO_0_PIN 3
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#define GPIO_0_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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#define GPIO_0_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI3_PA)
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#define GPIO_0_IRQ EXTI3_IRQn
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/* GPIO channel 1 config */
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#define GPIO_1_PORT GPIOC
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#define GPIO_1_PIN 7
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#define GPIO_1_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOCEN)
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#define GPIO_1_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI7_PC)
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#define GPIO_1_IRQ EXTI9_5_IRQn
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/* GPIO channel 2 config */
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#define GPIO_2_PORT GPIOA
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#define GPIO_2_PIN 9
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#define GPIO_2_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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#define GPIO_2_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI9_PA)
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#define GPIO_2_IRQ EXTI9_5_IRQn
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/* GPIO channel 3 config */
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#define GPIO_3_PORT GPIOA
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#define GPIO_3_PIN 8
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#define GPIO_3_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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#define GPIO_3_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI8_PA)
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#define GPIO_3_IRQ EXTI9_5_IRQn
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/* GPIO channel 4 config */
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#define GPIO_4_PORT GPIOB
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#define GPIO_4_PIN 10
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#define GPIO_4_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
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#define GPIO_4_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI10_PB)
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#define GPIO_4_IRQ EXTI15_10_IRQn
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/* GPIO channel 5 config */
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#define GPIO_5_PORT GPIOB
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#define GPIO_5_PIN 4
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#define GPIO_5_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
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#define GPIO_5_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI4_PB)
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#define GPIO_5_IRQ EXTI4_IRQn
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/* GPIO channel 6 config */
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#define GPIO_6_PORT GPIOC
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#define GPIO_6_PIN 11
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#define GPIO_6_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOCEN)
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#define GPIO_6_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI11_PC)
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#define GPIO_6_IRQ EXTI15_10_IRQn
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/* GPIO channel 7 config */
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#define GPIO_7_PORT GPIOC
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#define GPIO_7_PIN 2
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#define GPIO_7_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOCEN)
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#define GPIO_7_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI2_PC)
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#define GPIO_7_IRQ EXTI2_IRQn
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/* GPIO channel 8 config */
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#define GPIO_8_PORT GPIOA
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#define GPIO_8_PIN 13
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#define GPIO_8_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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#define GPIO_8_EXTI_CFG() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI13_PA)
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#define GPIO_8_IRQ EXTI15_10_IRQn
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/* GPIO channel 9 config */
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#define GPIO_9_PORT GPIOA
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#define GPIO_9_PIN 14
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#define GPIO_9_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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#define GPIO_9_EXTI_CFG() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI14_PA)
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#define GPIO_9_IRQ EXTI15_10_IRQn
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/* GPIO channel 10 config */
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#define GPIO_10_PORT GPIOA
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#define GPIO_10_PIN 15
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#define GPIO_10_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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#define GPIO_10_EXTI_CFG() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI15_PA)
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#define GPIO_10_IRQ EXTI15_10_IRQn
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/* GPIO channel 11 config */
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#define GPIO_11_PORT GPIOB /* SPI CS Pin */
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#define GPIO_11_PIN 6
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#define GPIO_11_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
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#define GPIO_11_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI6_PB)
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#define GPIO_11_IRQ EXTI9_5_IRQn
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/* GPIO channel 12 config */
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#define GPIO_12_PORT GPIOC
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#define GPIO_12_PIN 5
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#define GPIO_12_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOCEN)
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#define GPIO_12_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI5_PC)
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#define GPIO_12_IRQ EXTI9_5_IRQn
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/* GPIO channel 13 config */
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#define GPIO_13_PORT GPIOA
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#define GPIO_13_PIN 0
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#define GPIO_13_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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#define GPIO_13_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PA)
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#define GPIO_13_IRQ EXTI0_IRQn
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/* GPIO channel 14 config */
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#define GPIO_14_PORT GPIOA
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#define GPIO_14_PIN 1
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#define GPIO_14_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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#define GPIO_14_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI1_PA)
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#define GPIO_14_IRQ EXTI1_IRQn
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/* GPIO channel 15 config */
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#define GPIO_15_PORT GPIOC
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#define GPIO_15_PIN 12
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#define GPIO_15_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOCEN)
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#define GPIO_15_EXTI_CFG() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI12_PC)
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#define GPIO_15_IRQ EXTI15_10_IRQn
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/**
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* @brief SPI configuration
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* @{
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*/
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#define SPI_NUMOF (1U)
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#define SPI_0_EN 1
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/* SPI 0 device configuration */
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#define SPI_0_DEV SPI1
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#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
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#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
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#define SPI_0_IRQ SPI1_IRQn
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#define SPI_0_ISR isr_spi1
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/* SPI 0 pin configuration */
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#define SPI_0_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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#define SPI_0_PORT GPIOA
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#define SPI_0_PIN_SCK 5
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#define SPI_0_PIN_MOSI 7
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#define SPI_0_PIN_MISO 6
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#define SPI_0_PIN_AF 5
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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#define I2C_NUMOF (1U)
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#define I2C_0_EN 1
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#define I2C_IRQ_PRIO 1
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#define I2C_APBCLK (36000000U)
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/* I2C 0 device configuration */
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#define I2C_0_DEV I2C1
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#define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
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#define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
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#define I2C_0_EVT_IRQ I2C1_EV_IRQn
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#define I2C_0_EVT_ISR isr_i2c1_ev
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#define I2C_0_ERR_IRQ I2C1_ER_IRQn
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#define I2C_0_ERR_ISR isr_i2c1_er
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/* I2C 0 pin configuration */
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#define I2C_0_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN)
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#define I2C_0_PORT GPIOB
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#define I2C_0_SCL_PIN 8
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#define I2C_0_SCL_AF 4
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#define I2C_0_SDA_PIN 9
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#define I2C_0_SDA_AF 4
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __PERIPH_CONF_H */
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/** @} */
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