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https://github.com/RIOT-OS/RIOT.git
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79 lines
1.7 KiB
C
79 lines
1.7 KiB
C
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/*
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* Copyright (C) 2020 Savoir-faire Linux
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup boards_stm32mp157c-dk2
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* @{
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*
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* @file
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* @brief Board specific implementations for the STM32MP157C-DK2 board
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*
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* @author Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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/* This board provides an LSE */
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE 1
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#endif
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/* This board provides an HSE */
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CONFIG_BOARD_HAS_HSE 1
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#endif
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#include "periph_cpu.h"
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#include "clk_conf.h"
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#include "cfg_timer_tim2.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART3,
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.rcc_mask = RCC_MC_APB1ENSETR_USART3EN,
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.rx_pin = GPIO_PIN(PORT_B, 12),
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.tx_pin = GPIO_PIN(PORT_B, 10),
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.rx_af = GPIO_AF8,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART3_IRQn,
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.type = STM32_USART,
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#ifdef UART_USE_DMA
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.dma_stream = 4,
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.dma_chan = 4,
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#endif
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#if IS_USED(MODULE_STM32MP1_ENG_MODE)
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.clk_src = RCC_UART35CKSELR_UART35SRC_4, /* HSE clock source */
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#else
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.clk_src = RCC_UART35CKSELR_UART35SRC_2, /* HSI clock source */
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#endif
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},
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};
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#define UART_0_ISR (isr_usart3)
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#define UART_0_DMA_ISR (isr_dma1_stream4)
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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