2014-05-20 14:22:24 +02:00
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/*
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2014-06-11 15:21:59 +02:00
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* LPC 2000 Loader, http://www.pjrc.com/arm/lpc2k_pgm
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* Copyright (c) 2004, PJRC.COM, LLC, <paul@pjrc.com>
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2014-05-20 14:22:24 +02:00
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*
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2014-06-11 15:21:59 +02:00
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; version 2 of the License.
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2014-05-20 14:22:24 +02:00
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*
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2014-06-11 15:21:59 +02:00
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
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* Public License for more details.
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2014-05-20 14:22:24 +02:00
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*
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2014-06-11 15:21:59 +02:00
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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2014-05-20 14:22:24 +02:00
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*/
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2010-09-22 15:10:42 +02:00
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#include "control_2xxx.h"
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#include <stdio.h>
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#include <time.h>
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#include <unistd.h>
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#include "serial.h"
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void hard_reset_to_bootloader(void)
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{
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2014-07-31 20:34:28 +02:00
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/* Use this lines for flashing a node with interrupted DTR line */
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/* printf("Press Reset - confirm with anykey\n");
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2012-08-01 17:00:48 +02:00
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getchar();
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*/
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printf("Reset CPU (into bootloader)\r\n");
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2014-07-31 20:34:28 +02:00
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set_rts(1); // RTS (ttl level) connects to P0.14
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2012-08-01 17:00:48 +02:00
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/* the next two lines should be commented for the prepared node */
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2014-07-31 20:34:28 +02:00
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set_dtr(1); // DTR (ttl level) connects to RST
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send_break_signal(); // or break detect circuit to RST
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2013-07-29 16:41:43 +02:00
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usleep(75000);
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2014-07-31 20:34:28 +02:00
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/* Use this lines for flashing a node with interrupted DTR line */
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2012-11-20 21:30:03 +01:00
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/* printf("Release Reset - confirm with anykey\n");
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2012-08-01 17:00:48 +02:00
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getchar();
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2012-11-20 21:30:03 +01:00
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*/
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2014-07-31 20:34:28 +02:00
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set_dtr(0); // allow the CPU to run:
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2013-07-29 16:41:43 +02:00
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set_baud(baud_rate);
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2014-07-31 20:34:28 +02:00
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set_rts(1); // set RTS again (as it has been reset by set_baudrate)
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2013-07-29 16:41:43 +02:00
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usleep(40000);
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2010-09-22 15:10:42 +02:00
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}
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void hard_reset_to_user_code(void)
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{
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2013-07-29 16:41:43 +02:00
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printf("Reset CPU (into user code)\r\n");
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2014-07-31 20:34:28 +02:00
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set_rts(0); // RTS (ttl level) connects to P0.14
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set_dtr(1); // DTR (ttl level) connects to RST
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send_break_signal(); // or break detect circuit to RST
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2013-07-29 16:41:43 +02:00
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usleep(75000);
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2014-07-31 20:34:28 +02:00
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set_dtr(0); // allow the CPU to run
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2013-07-29 16:41:43 +02:00
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usleep(40000);
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2010-09-22 15:10:42 +02:00
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}
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