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RIOT/cpu/stm32/include/vendor/stm32mp157cxx_cm4.h

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cpu/stm32: add stm32mp157x vendor headers Add vendor CMSIS headers from STMicroelectronics: https://wiki.st.com/stm32mpu/wiki/STM32CubeMP1_architecture#CMSIS Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-08-03 00:06:39 +02:00
/**
******************************************************************************
* @file stm32mp157cxx_cm4.h
* @author MCD Application Team
* @brief CMSIS stm32mp157cxx_cm4 Device Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripherals registers hardware
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS_Device
* @{
*/
/** @addtogroup stm32mp157cxx_cm4
* @{
*/
#ifndef __STM32MP157Cxx_CM4_H
#define __STM32MP157Cxx_CM4_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/**
* @brief Bit position definition inside a 32 bits registers
*/
#define B(x) \
((uint32_t) 1 << x)
/**
* @}
*/
/** @addtogroup Peripheral_interrupt_number_definition
* @{
*/
/**
* @brief STM32MP1XX Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum IRQn
{
/****** Cortex-M Processor Exceptions Numbers *******************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
/****** STM32 specific Interrupt Numbers ************************************************************************/
WWDG1_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_AVD_IRQn = 1, /*!< PVD & AVD detector through EXTI */
TAMP_IRQn = 2, /*!< Tamper interrupts through the EXTI line */
RTC_WKUP_ALARM_IRQn = 3, /*!< RTC Wakeup and Alarm (A & B) interrupt through the EXTI line */
RESERVED_4 = 4, /*!< RESERVED interrupt */
RCC_IRQn = 5, /*!< RCC global Interrupt */
EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
ADC1_IRQn = 18, /*!< ADC1 global Interrupts */
FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */
FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */
FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */
FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */
EXTI5_IRQn = 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_IRQn = 24, /*!< TIM1 Break interrupt */
TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
USART1_IRQn = 37, /*!< USART1 global Interrupt */
USART2_IRQn = 38, /*!< USART2 global Interrupt */
USART3_IRQn = 39, /*!< USART3 global Interrupt */
EXTI10_IRQn = 40, /*!< EXTI Line 10 Interrupts */
RTC_TIMESTAMP_IRQn = 41, /*!< RTC TimeStamp through EXTI Line Interrupt */
EXTI11_IRQn = 42, /*!< EXTI Line 11 Interrupts */
TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
FMC_IRQn = 48, /*!< FMC global Interrupt */
SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt */
UART5_IRQn = 53, /*!< UART5 global Interrupt */
TIM6_IRQn = 54, /*!< TIM6 global */
TIM7_IRQn = 55, /*!< TIM7 global interrupt */
DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
DMA2_Stream3_IRQn = 59, /*!< GPDMA2 Stream 3 global Interrupt */
DMA2_Stream4_IRQn = 60, /*!< GPDMA2 Stream 4 global Interrupt */
ETH1_IRQn = 61, /*!< Ethernet global Interrupt */
ETH1_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
FDCAN_CAL_IRQn = 63, /*!< CAN calibration unit interrupt */
EXTI6_IRQn = 64, /*!< EXTI Line 6 Interrupts */
EXTI7_IRQn = 65, /*!< EXTI Line 7 Interrupts */
EXTI8_IRQn = 66, /*!< EXTI Line 8 Interrupts */
EXTI9_IRQn = 67, /*!< EXTI Line 9 Interrupts */
DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
USART6_IRQn = 71, /*!< USART6 global interrupt */
I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
USBH_OHCI_IRQn = 74, /*!< USB OHCI global interrupt */
USBH_EHCI_IRQn = 75, /*!< USB EHCI global interrupt */
EXTI12_IRQn = 76, /*!< EXTI Line 76 Interrupts */
EXTI13_IRQn = 77, /*!< EXTI Line 77 Interrupts */
DCMI_IRQn = 78, /*!< DCMI global interrupt */
CRYP1_IRQn = 79, /*!< CRYP crypto global interrupt */
HASH1_IRQn = 80, /*!< Hash global interrupt */
FPU_IRQn = 81, /*!< FPU global interrupt */
UART7_IRQn = 82, /*!< UART7 global interrupt */
UART8_IRQn = 83, /*!< UART8 global interrupt */
SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
LTDC_IRQn = 88, /*!< LTDC global Interrupt */
LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
ADC2_IRQn = 90, /*!< ADC2 global Interrupts */
SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
OTG_IRQn = 98, /*!< USB On The Go global interrupt */
RESERVED_99 = 99, /*!< RESERVED interrupt */
IPCC_RX0_IRQn = 100, /*!< IPCC RX0 Occupied interrupt (interrupt going to AIEC input as well) */
IPCC_TX0_IRQn = 101, /*!< IPCC TX0 Free interrupt (interrupt going to AIEC input as well) */
DMAMUX1_OVR_IRQn = 102, /*!< DMAMUX1 Overrun interrupt */
IPCC_RX1_IRQn = 103, /*!< IPCC RX1 Occupied interrupt (interrupt going to AIEC input as well) */
IPCC_TX1_IRQn = 104, /*!< IPCC TX1 Free interrupt (interrupt going to AIEC input as well) */
CRYP2_IRQn = 105, /*!< CRYP2 crypto global interrupt */
HASH2_IRQn = 106, /*!< Crypto Hash2 interrupt */
I2C5_EV_IRQn = 107, /*!< I2C5 Event Interrupt */
I2C5_ER_IRQn = 108, /*!< I2C5 Error Interrupt */
GPU_IRQn = 109, /*!< GPU global Interrupt */
DFSDM1_FLT0_IRQn = 110, /*!< DFSDM Filter1 Interrupt */
DFSDM1_FLT1_IRQn = 111, /*!< DFSDM Filter2 Interrupt */
DFSDM1_FLT2_IRQn = 112, /*!< DFSDM Filter3 Interrupt */
DFSDM1_FLT3_IRQn = 113, /*!< DFSDM Filter4 Interrupt */
SAI3_IRQn = 114, /*!< SAI3 global Interrupt */
DFSDM1_FLT4_IRQn = 115, /*!< DFSDM Filter5 Interrupt */
TIM15_IRQn = 116, /*!< TIM15 global Interrupt */
TIM16_IRQn = 117, /*!< TIM16 global Interrupt */
TIM17_IRQn = 118, /*!< TIM17 global Interrupt */
TIM12_IRQn = 119, /*!< TIM12 global Interrupt */
MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */
EXTI14_IRQn = 121, /*!< EXTI Line 14 Interrupts */
MDMA_IRQn = 122, /*!< MDMA global Interrupt */
DSI_IRQn = 123, /*!< DSI global Interrupt */
SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */
HSEM_IT2_IRQn = 125, /*!< HSEM Semaphore Interrupt 2 */
DFSDM1_FLT5_IRQn = 126, /*!< DFSDM Filter6 Interrupt */
EXTI15_IRQn = 127, /*!< EXTI Line 15 Interrupts */
nCTIIRQ1_IRQn = 128, /*!< Cortex-M4 CTI interrupt 1 */
nCTIIRQ2_IRQn = 129, /*!< Cortex-M4 CTI interrupt 2 */
TIM13_IRQn = 130, /*!< TIM13 global interrupt */
TIM14_IRQn = 131, /*!< TIM14 global interrupt */
DAC_IRQn = 132, /*!< DAC1 and DAC2 underrun error interrupts */
RNG1_IRQn = 133, /*!< RNG1 interrupt */
RNG2_IRQn = 134, /*!< RNG2 interrupt */
I2C6_EV_IRQn = 135, /*!< I2C6 Event Interrupt */
I2C6_ER_IRQn = 136, /*!< I2C6 Error Interrupt */
SDMMC3_IRQn = 137, /*!< SDMMC3 global Interrupt */
LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */
LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */
LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */
LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */
ETH1_LPI_IRQn = 142, /*!< ETH1_LPI interrupt (LPI: lpi_intr_o) */
RESERVED_143 = 143, /*!< RESERVED interrupt */
MPU_SEV_IRQn = 144, /*!< MPU Send Event interrupt */
RCC_WAKEUP_IRQn = 145, /*!< RCC Wake up interrupt */
SAI4_IRQn = 146, /*!< SAI4 global interrupt */
DTS_IRQn = 147, /*!< Temperature sensor Global Interrupt */
RESERVED_148 = 148, /*!< RESERVED interrupt */
WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */
MAX_IRQ_n
} IRQn_Type;
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
#define SDC /*!< Step Down Converter feature */
/**
* @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals
*/
#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */
#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */
#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
#include "system_stm32mp1xx.h"
#include <stdint.h>
/** @addtogroup Peripheral_registers_structures
* @{
*/
/**
* @brief Analog to Digital Converter
*/
typedef struct
{
__IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
__IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
__IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
__IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
__IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
__IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
__IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */
__IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
__IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
uint32_t RESERVED1; /*!< Reserved, 0x028 */
uint32_t RESERVED2; /*!< Reserved, 0x02C */
__IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
__IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
__IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
__IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
__IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
uint32_t RESERVED3; /*!< Reserved, 0x044 */
uint32_t RESERVED4; /*!< Reserved, 0x048 */
__IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
__IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
__IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
__IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
__IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
__IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
__IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
__IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
__IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
__IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
__IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
uint32_t RESERVED9; /*!< Reserved, 0x0AC */
__IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */
__IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */
__IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */
__IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */
__IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */
__IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */
__IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */
uint32_t RESERVED10; /*!< Reserved, 0x0CC */
__IO uint32_t OR; /*!< ADC Calibration Factors, Address offset: 0x0D0 */
uint32_t RESERVED11[200]; /*!< Reserved, 0x0D4 - 0x3F0 */
__IO uint32_t VERR; /*!< ADC version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< ADC ID register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< ADC Size ID register, Address offset: 0x3FC */
} ADC_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
} ADC_Common_TypeDef;
/**
* @brief FD Controller Area Network
*/
typedef struct
{
__IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
__IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
__IO uint32_t RESERVED1; /*!< Reserved, 0x008 */
__IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
__IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
__IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
__IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
__IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
__IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
__IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
__IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
__IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
__IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
__IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
__IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
__IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
__IO uint32_t RESERVED3; /*!< Reserved, 0x04C */
__IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
__IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
__IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
__IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
__IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
__IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
__IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */
__IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */
__IO uint32_t RESERVED5; /*!< Reserved, 0x08C */
__IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */
__IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */
__IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */
__IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */
__IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */
__IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */
__IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */
__IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */
__IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */
__IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */
__IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */
__IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */
__IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
__IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
__IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */
__IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */
__IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */
__IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */
__IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */
__IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */
__IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */
__IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
__IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */
__IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */
__IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */
__IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */
__IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */
} FDCAN_GlobalTypeDef;
/**
* @brief TTFD Controller Area Network
*/
typedef struct
{
__IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */
__IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */
__IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */
__IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */
__IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */
__IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */
__IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */
__IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */
__IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */
__IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */
__IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */
__IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */
__IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */
__IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */
__IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */
__IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */
__IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */
__IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */
__IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */
} TTCAN_TypeDef;
/**
* @brief FD Controller Area Network
*/
typedef struct
{
__IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
__IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */
__IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */
__IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */
__IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */
__IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */
} FDCAN_ClockCalibrationUnit_TypeDef;
/**
* @brief Consumer Electronics Control
*/
typedef struct
{
__IO uint32_t CR; /*!< CEC control register, Address offset: 0x000 */
__IO uint32_t CFGR; /*!< CEC configuration register, Address offset: 0x004 */
__IO uint32_t TXDR; /*!< CEC Tx data register , Address offset: 0x008 */
__IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset: 0x00C */
__IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset: 0x010 */
__IO uint32_t IER; /*!< CEC interrupt enable register, Address offset: 0x014 */
uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */
__IO uint32_t VERR; /*!< CEC version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< CEC ID register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< CEC Size ID register, Address offset: 0x3FC */
}CEC_TypeDef;
/**
* @brief CRC calculation unit
*/
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x000 */
__IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x004 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x008 */
uint32_t RESERVED2; /*!< Reserved, 0x00C */
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x010 */
__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x014 */
uint32_t RESERVED3[247]; /*!< Reserved, 0x018 - 0x3F0 */
__IO uint32_t VERR; /*!< CRC version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< CRC ID register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< CRC Size ID register, Address offset: 0x3FC */
} CRC_TypeDef;
/**
* @brief Clock Recovery System
*/
typedef struct
{
__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
} CRS_TypeDef;
/**
* @brief Digital to Analog Converter
*/
typedef struct
{
__IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
__IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
__IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
__IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
__IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
__IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
__IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
__IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
__IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
uint32_t RESERVED0[232]; /*!< Reserved, Address offset: 0x50 - 0x3EC */
__IO uint32_t HWCFGR0; /*!< DAC x IP hardware configuration register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< DAC version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< DAC ID register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< DAC magic ID register, Address offset: 0x3FC */
} DAC_TypeDef;
/**
* @brief DFSDM module registers
*/
typedef struct
{
__IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
__IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
__IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
__IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
__IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
__IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
__IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
__IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
__IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
__IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
__IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
__IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
__IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
__IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
__IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
} DFSDM_Filter_TypeDef;
/**
* @brief DFSDM channel configuration registers
*/
typedef struct
{
__IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
__IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
__IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
short circuit detector register, Address offset: 0x08 */
__IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
__IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
__IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */
} DFSDM_Channel_TypeDef;
/**
* @brief DFSDM registers
*/
typedef struct
{
uint32_t RESERVED[508];/*!< Reserved, 0x000 - 0x7F0 */
__IO uint32_t HWCFGR; /*!< DFSDM HW Configuration register , Address offset: 0x7F0 */
__IO uint32_t VERR; /*!< DFSDM Version register, Address offset: 0x7F4 */
__IO uint32_t IPDR; /*!< DFSDM Identification register, Address offset: 0x7F8 */
__IO uint32_t SIDR; /*!< DFSDM Size Identification register, Address offset: 0x7FC */
} DFSDM_TypeDef;
/**
* @brief Debug MCU
*/
typedef struct
{
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
__IO uint32_t RESERVED4[9]; /*!< Reserved, Address offset: 0x08 */
__IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register CPU1, Address offset: 0x2C */
__IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register CPU2, Address offset: 0x30 */
__IO uint32_t APB1FZ1; /*!< Debug MCU APB1FZ1 freeze register CPU1, Address offset: 0x34 */
__IO uint32_t APB1FZ2; /*!< Debug MCU APB1FZ2 freeze register CPU2, Address offset: 0x38 */
__IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register CPU1, Address offset: 0x3C */
__IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register CPU2, Address offset: 0x40 */
__IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register CPU1, Address offset: 0x44 */
__IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register CPU2, Address offset: 0x48 */
__IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register CPU1, Address offset: 0x4C */
__IO uint32_t APB5FZ2; /*!< Debug MCU APB5FZ2 freeze register CPU2, Address offset: 0x50 */
}DBGMCU_TypeDef;
/**
* @brief DCMI
*/
typedef struct
{
__IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x000 */
__IO uint32_t SR; /*!< DCMI status register, Address offset: 0x004 */
__IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x008 */
__IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x00C */
__IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x010 */
__IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x014 */
__IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x018 */
__IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x01C */
__IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x020 */
__IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x024 */
__IO uint32_t DR; /*!< DCMI data register, Address offset: 0x028 */
uint32_t RESERVED[242]; /*!< Reserved, 0x02C - 0x3F0 */
__IO uint32_t VERR; /*!< DCMI Version register, Address offset: 0x3F4 */
__IO uint32_t IPDR; /*!< DCMI Identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< DCMI Size Identification register, Address offset: 0x3FC */
} DCMI_TypeDef;
/**
* @brief DMA Controller
*/
typedef struct
{
__IO uint32_t CR; /*!< DMA stream x configuration register */
__IO uint32_t NDTR; /*!< DMA stream x number of data register */
__IO uint32_t PAR; /*!< DMA stream x peripheral address register */
__IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
__IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
__IO uint32_t FCR; /*!< DMA stream x FIFO control register */
} DMA_Stream_TypeDef;
typedef struct
{
__IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
__IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
__IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
__IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
__IO uint32_t RESERVED[247]; /*!< Reserved, Address offset: 0x10 - 0x3E8 */
__IO uint32_t HWCFGR2; /*!< DMA HW Configuration register 2, Address offset: 0x3EC */
__IO uint32_t HWCFGR1; /*!< DMA HW Configuration register 1, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< DMA Version register, Address offset: 0x3F4 */
__IO uint32_t IPDR; /*!< DMA Identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< DMA Size Identification register, Address offset: 0x3FC */
} DMA_TypeDef;
typedef struct
{
__IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */
}DMAMUX_Channel_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< DMA Channel Status Register */
__IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */
}DMAMUX_ChannelStatus_TypeDef;
typedef struct
{
__IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */
}DMAMUX_RequestGen_TypeDef;
typedef struct
{
__IO uint32_t RGSR; /*!< DMAMUX Request Generator Status Register, Address offset: 0x140 */
__IO uint32_t RGCFR; /*!< DMAMUX Request Generator Clear Flag Register, Address offset: 0x144 */
uint32_t RESERVED0[169]; /*!< Reserved, 0x144 -> 0x144 */
__IO uint32_t HWCFGR2; /*!< DMAMUX Configuration register 2, Address offset: 0x3EC */
__IO uint32_t HWCFGR1; /*!< DMAMUX Configuration register 1, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< DMAMUX Verion Register, Address offset: 0x3F4 */
__IO uint32_t IPDR; /*!< DMAMUX Identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< DMAMUX Size Identification register, Address offset: 0x3FC */
}DMAMUX_RequestGenStatus_TypeDef;
/**
* @brief MDMA Controller
*/
typedef struct
{
__IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x000 */
uint32_t RESERVED1; /*!< Reserved, 0x004 */
// __IO uint32_t GISR1; /*!< MDMA Global Interrupt/Status Register 1, Address offset: 0x004 */
__IO uint32_t SGISR0; /*!< MDMA Secure Global Interrupt/Status Register 0, Address offset: 0x008 */
// __IO uint32_t SGISR1; /*!< MDMA Secure Global Interrupt/Status Register 1, Address offset: 0x00C */
uint32_t RESERVED2[250]; /*!< Reserved, 0x10 - 0x3F0 */
__IO uint32_t VERR; /*!< MDMA Verion Register, Address offset: 0x3F4 */
__IO uint32_t IPDR; /*!< MDMA Identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< MDMA Size Identification register, Address offset: 0x3FC */
}MDMA_TypeDef;
typedef struct
{
__IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */
__IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */
__IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */
__IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */
__IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */
__IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */
__IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */
__IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */
__IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
__IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
__IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
uint32_t RESERVED0; /*!< Reserved, 0x68 */
__IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
__IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
}MDMA_Channel_TypeDef;
/**
* @brief DSI Controller
*/
typedef struct
{
__IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */
__IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */
__IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */
__IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */
__IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */
__IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */
__IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */
uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */
__IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */
__IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */
__IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */
__IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */
__IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */
__IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */
__IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */
__IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */
__IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */
__IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */
__IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */
__IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */
__IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */
__IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */
__IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */
__IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */
__IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */
__IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */
__IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */
__IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
__IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */
__IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */
__IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */
__IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */
__IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */
__IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */
__IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */
__IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */
__IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */
uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */
__IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
__IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */
__IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
uint32_t RESERVED3[5]; /*!< Reserved, 0xE0 - 0xF3 */
__IO uint32_t DLTRCR; /*!< DSI Host Data Lane Timer Read Configuration Register, Address offset: 0xF4 */
uint32_t RESERVED4[2]; /*!< Reserved, 0xF8 - 0xFF */
__IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */
uint32_t RESERVED5[2]; /*!< Reserved, 0x104 - 0x10B */
__IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */
__IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */
uint32_t RESERVED6; /*!< Reserved, 0x114 */
__IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */
uint32_t RESERVED7[7]; /*!< Reserved, 0x11C - 0x137 */
__IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
__IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
__IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
__IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
__IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
__IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
__IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */
__IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */
__IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */
__IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */
__IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */
uint32_t RESERVED8[11]; /*!< Reserved, 0x164 - 0x18F */
__IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */
uint32_t RESERVED9[155]; /*!< Reserved, 0x194 - 0x3FF */
__IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */
__IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */
__IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */
__IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */
__IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */
uint32_t RESERVED10; /*!< Reserved, 0x414 */
__IO uint32_t WPCR[2]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-41C */
uint32_t RESERVED11[4]; /*!< Reserved, 0x420 - 0x42F */
__IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */
uint32_t RESERVED12[239]; /*!< Reserved, 0x434 - 0x7EC */
__IO uint32_t HWCFGR; /*!< DSI Host hardware configuration register, Address offset: 0x7F0 */
__IO uint32_t VERR; /*!< DSI Host version register, Address offset: 0x7F4 */
__IO uint32_t IPIDR; /*!< DSI Host Identification register, Address offset: 0x7F8 */
__IO uint32_t SIDR; /*!< DSI Host Size ID register, Address offset: 0x7FC */
} DSI_TypeDef;
/**
* @brief Ethernet MAC
*/
typedef struct
{
__IO uint32_t MACCR; /*!< Operating mode configuration register Address offset: 0x0000 */
__IO uint32_t MACECR; /*!< Extended operating mode configuration register Address offset: 0x0004 */
__IO uint32_t MACPFR; /*!< Packet filtering control register Address offset: 0x0008 */
__IO uint32_t MACWTR; /*!< Watchdog timeout register Address offset: 0x000C */
__IO uint32_t MACHT0R; /*!< Hash Table 0 register Address offset: 0x0010 */
__IO uint32_t MACHT1R; /*!< Hash Table 1 register Address offset: 0x0014 */
uint32_t RESERVED0[14]; /*!< Reserved Address offset: 0x0018-0x004C */
__IO uint32_t MACVTR; /*!< VLAN tag register Address offset: 0x0050 */
uint32_t RESERVED1; /*!< Reserved Address offset: 0x0054 */
__IO uint32_t MACVHTR; /*!< VLAN Hash table register Address offset: 0x0058 */
uint32_t RESERVED2; /*!< Reserved Address offset: 0x005C */
__IO uint32_t MACVIR; /*!< VLAN inclusion register Address offset: 0x0060 */
__IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register Address offset: 0x0064 */
uint32_t RESERVED3[2]; /*!< Reserved Address offset: 0x0068-0x006C */
__IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register Address offset: 0x0070 */
uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x0074-0x008C */
__IO uint32_t MACRXFCR; /*!< Rx flow control register Address offset: 0x0090 */
uint32_t RESERVED5; /*!< Reserved Address offset: 0x0094 */
__IO uint32_t MACTXQPMR; /*!< Tx queue priority mapping 0 register Address offset: 0x0098 */
uint32_t RESERVED6; /*!< Reserved Address offset: 0x009C */
__IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register Address offset: 0x00A0 */
__IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register Address offset: 0x00A4 */
__IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register Address offset: 0x00A8 */
uint32_t RESERVED7; /*!< Reserved Address offset: 0x00AC */
__IO uint32_t MACISR; /*!< Interrupt status register Address offset: 0x00B0 */
__IO uint32_t MACIER; /*!< Interrupt enable register Address offset: 0x00B4 */
__IO uint32_t MACRXTXSR; /*!< Rx Tx status register Address offset: 0x00B8 */
uint32_t RESERVED8; /*!< Reserved Address offset: 0x00BC */
__IO uint32_t MACPCSR; /*!< PMT control status register Address offset: 0x00C0 */
__IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register Address offset: 0x00C4 */
uint32_t RESERVED9[2]; /*!< Reserved Address offset: 0x00C8-0x00CC */
__IO uint32_t MACLCSR; /*!< LPI control status register Address offset: 0x00D0 */
__IO uint32_t MACLTCR; /*!< LPI timers control register Address offset: 0x00D4 */
__IO uint32_t MACLETR; /*!< LPI entry timer register Address offset: 0x00D8 */
__IO uint32_t MAC1USTCR; /*!< microsecond-tick counter register Address offset: 0x00DC */
uint32_t RESERVED10[6]; /*!< Reserved Address offset: 0x00E0-0x00F4 */
__IO uint32_t MACPHYCSR; /*!< PHYIF control status register Address offset: 0x00F8 */
uint32_t RESERVED11[5]; /*!< Reserved Address offset: 0x00FC-0x010C */
__IO uint32_t MACVR; /*!< Version register Address offset: 0x0110 */
__IO uint32_t MACDR; /*!< Debug register Address offset: 0x0114 */
uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x0118-0x011C */
__IO uint32_t MACHWF1R; /*!< HW feature 1 register Address offset: 0x0120 */
__IO uint32_t MACHWF2R; /*!< HW feature 2 register Address offset: 0x0124 */
uint32_t RESERVED13[54]; /*!< Reserved Address offset: 0x0128-0x01FC */
__IO uint32_t MACMDIOAR; /*!< MDIO address register Address offset: 0x0200 */
__IO uint32_t MACMDIODR; /*!< MDIO data register Address offset: 0x0204 */
uint32_t RESERVED14[62]; /*!< Reserved Address offset: 0x0208-0x02FC */
__IO uint32_t MACA0HR; /*!< Address 0 high register Address offset: 0x0300 */
__IO uint32_t MACA0LR; /*!< Address 0 low register Address offset: 0x0304 */
__IO uint32_t MACA1HR; /*!< Address 1 high register Address offset: 0x0308 */
__IO uint32_t MACA1LR; /*!< Address 1 low register Address offset: 0x030C */
__IO uint32_t MACA2HR; /*!< Address 2 high register Address offset: 0x0310 */
__IO uint32_t MACA2LR; /*!< Address 2 low register Address offset: 0x0314 */
__IO uint32_t MACA3HR; /*!< Address 3 high register Address offset: 0x0318 */
__IO uint32_t MACA3LR; /*!< Address 3 low register Address offset: 0x031C */
uint32_t RESERVED15[248]; /*!< Reserved Address offset: 0x0320-0x06FC */
__IO uint32_t MMCCR; /*!< MMC control register Address offset: 0x0700 */
__IO uint32_t MMCRXIR; /*!< MMC Rx interrupt register Address offset: 0x704 */
__IO uint32_t MMCTXIR; /*!< MMC Tx interrupt register Address offset: 0x708 */
__IO uint32_t MMCRXIMR; /*!< MMC Rx interrupt mask register Address offset: 0x70C */
__IO uint32_t MMCTXIMR; /*!< MMC Tx interrupt mask register Address offset: 0x710 */
uint32_t RESERVED16[14]; /*!< Reserved Address offset: 0x0714-0x0748 */
__IO uint32_t MMCTXSCGPR; /*!< Tx single collision good packets register Address offset: 0x74C */
__IO uint32_t MMCTXMCGPR; /*!< Tx multiple collision good packets register Address offset: 0x750 */
uint32_t RESERVED16_1[5]; /*!< Reserved Address offset: 0x0754-0x0764 */
__IO uint32_t MMCTXPCGR; /*!< Tx packet count good register Address offset: 0x768 */
uint32_t RESERVED16_2[10]; /*!< Reserved Address offset: 0x076C-0x0790 */
__IO uint32_t MMCRXCRCEPR; /*!< Rx CRC error packets register Address offset: 0x794 */
__IO uint32_t MMCRXAEPR; /*!< Rx alignment error packets register Address offset: 0x798 */
uint32_t RESERVED16_3[10]; /*!< Reserved Address offset: 0x079C-0x07C0 */
__IO uint32_t MMCRXUPGR; /*!< Rx unicast packets good register Address offset: 0x7C4 */
uint32_t RESERVED16_4[9]; /*!< Reserved Address offset: 0x07C8-0x07E8 */
__IO uint32_t MMCTXLPIMSTR; /*!< Tx LPI microsecond timer register Address offset: 0x7EC */
__IO uint32_t MMCTXLPITCR; /*!< Tx LPI transition counter register Address offset: 0x7F0 */
__IO uint32_t MMCRXLPIMSTR; /*!< Rx LPI microsecond counter register Address offset: 0x7F4 */
__IO uint32_t MMCRXLPITCR; /*!< Rx LPI transition counter register Address offset: 0x7F8 */
uint32_t RESERVED16_5[65]; /*!< Reserved Address offset: 0x07FC-0x08FC */
__IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register Address offset: 0x0900 */
__IO uint32_t MACL4A0R; /*!< Layer4 address filter 0 register Address offset: 0x0904 */
uint32_t RESERVED17[2]; /*!< Reserved Address offset: 0x0908-0x090C */
__IO uint32_t MACL3A00R; /*!< Layer 3 Address 0 filter 0 register Address offset: 0x0910 */
__IO uint32_t MACL3A10R; /*!< Layer3 address 1 filter 0 register Address offset: 0x0914 */
__IO uint32_t MACL3A20; /*!< Layer3 Address 2 filter 0 register Address offset: 0x0918 */
__IO uint32_t MACL3A30; /*!< Layer3 Address 3 filter 0 register Address offset: 0x091C */
uint32_t RESERVED18[4]; /*!< Reserved Address offset: 0x0920-0x092C */
__IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register Address offset: 0x0930 */
__IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register Address offset: 0x0934 */
uint32_t RESERVED19[2]; /*!< Reserved Address offset: 0x0938-0x093C */
__IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register Address offset: 0x0940 */
__IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register Address offset: 0x0944 */
__IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register Address offset: 0x0948 */
__IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register Address offset: 0x094C */
uint32_t RESERVED20[100]; /*!< Reserved Address offset: 0x0950-0x0ADC */
__IO uint32_t MACARPAR; /*!< ARP address register Address offset: 0x0AE0 */
uint32_t RESERVED21[7]; /*!< Reserved Address offset: 0x0AE4-0x0AFC */
__IO uint32_t MACTSCR; /*!< Timestamp control Register Address offset: 0x0B00 */
__IO uint32_t MACSSIR; /*!< Sub-second increment register Address offset: 0x0B04 */
__IO uint32_t MACSTSR; /*!< System time seconds register Address offset: 0x0B08 */
__IO uint32_t MACSTNR; /*!< System time nanoseconds register Address offset: 0x0B0C */
__IO uint32_t MACSTSUR; /*!< System time seconds update register Address offset: 0x0B10 */
__IO uint32_t MACSTNUR; /*!< System time nanoseconds update register Address offset: 0x0B14 */
__IO uint32_t MACTSAR; /*!< Timestamp addend register Address offset: 0x0B18 */
uint32_t RESERVED22; /*!< Reserved Address offset: 0x0B1C */
__IO uint32_t MACTSSR; /*!< Timestamp status register Address offset: 0x0B20 */
uint32_t RESERVED23[3]; /*!< Reserved Address offset: 0x0B24-0x0B2C */
__IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register Address offset: 0x0B30 */
__IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register Address offset: 0x0B34 */
uint32_t RESERVED24[2]; /*!< Reserved Address offset: 0x0B38-0x0B3C */
__IO uint32_t MACACR; /*!< Auxiliary control register Address offset: 0x0B40 */
uint32_t RESERVED25; /*!< Reserved Address offset: 0x0B44 */
__IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register Address offset: 0x0B48 */
__IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register Address offset: 0x0B4C */
__IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register Address offset: 0x0B50 */
__IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register Address offset: 0x0B54 */
__IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register Address offset: 0x0B58 */
__IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register Address offset: 0x0B5C */
uint32_t RESERVED26[4]; /*!< Reserved Address offset: 0x0B60-0x0B6C */
__IO uint32_t MACPPSCR; /*!< PPS control register [alternate] Address offset: 0x0B70 */
uint32_t RESERVED27[3]; /*!< Reserved Address offset: 0x0B74-0x0B7C */
__IO uint32_t MACPPSTTSR; /*!< PPS target time seconds register Address offset: 0x0B80 */
__IO uint32_t MACPPSTTNR; /*!< PPS target time nanoseconds register Address offset: 0x0B84 */
__IO uint32_t MACPPSIR; /*!< PPS interval register Address offset: 0x0B88 */
__IO uint32_t MACPPSWR; /*!< PPS width register Address offset: 0x0B8C */
uint32_t RESERVED28[12]; /*!< Reserved Address offset: 0x0B90-0x0BBC */
__IO uint32_t MACPOCR; /*!< PTP Offload control register Address offset: 0x0BC0 */
__IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register Address offset: 0x0BC4 */
__IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register Address offset: 0x0BC8 */
__IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register Address offset: 0x0BCC */
__IO uint32_t MACLMIR; /*!< Log message interval register Address offset: 0x0BD0 */
uint32_t RESERVED29[11]; /*!< Reserved Address offset: 0x0BD4-0x0BFC */
__IO uint32_t MTLOMR; /*!< Operating mode Register Address offset: 0x0C00 */
uint32_t RESERVED30[7]; /*!< Reserved Address offset: 0x0C04-0x0C1C */
__IO uint32_t MTLISR; /*!< Interrupt status Register Address offset: 0x0C20 */
uint32_t RESERVED31[55]; /*!< Reserved Address offset: 0x0C24-0x0CFC */
__IO uint32_t MTLTXQ0OMR; /*!< Tx queue 0 operating mode Register Address offset: 0x0D00 */
__IO uint32_t MTLTXQ0UR; /*!< Tx queue 0 underflow register Address offset: 0x0D04 */
__IO uint32_t MTLTXQ0DR; /*!< Tx queue 0 debug Register Address offset: 0x0D08 */
uint32_t RESERVED32[2]; /*!< Reserved Address offset: 0x0D0C-0x0D10 */
__IO uint32_t MTLTXQ0ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D14 */
uint32_t RESERVED33[5]; /*!< Reserved Address offset: 0x0D18-0x0D28 */
__IO uint32_t MTLQ0ICSR; /*!< Queue 0 interrupt control status Register Address offset: 0x0D2C */
__IO uint32_t MTLRXQ0OMR; /*!< Rx queue 0 operating mode register Address offset: 0x0D30 */
__IO uint32_t MTLRXQ0MPOCR; /*!< Rx queue 0 missed packet and overflow counter register Address offset: 0x0D34 */
__IO uint32_t MTLRXQ0DR; /*!< Rx queue 0 debug register Address offset: 0x0D38 */
__IO uint32_t MTLRXQ0CR; /*!< Rx queue 0 control register Address offset: 0x0D3C */
__IO uint32_t MTLTXQ1OMR; /*!< Tx queue 1 operating mode Register Address offset: 0x0D40 */
__IO uint32_t MTLTXQ1UR; /*!< Tx queue 1 underflow register Address offset: 0x0D44 */
__IO uint32_t MTLTXQ1DR; /*!< Tx queue 1 debug Register Address offset: 0x0D48 */
uint32_t RESERVED34; /*!< Reserved Address offset: 0x0D4C */
__IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register Address offset: 0x0D50 */
__IO uint32_t MTLTXQ1ESR; /*!< Tx queue x ETS status Register Address offset: 0x0D54 */
__IO uint32_t MTLTXQ1QWR; /*!< Tx queue 1 quantum weight register Address offset: 0x0D58 */
__IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register Address offset: 0x0D5C */
__IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register Address offset: 0x0D60 */
__IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register Address offset: 0x0D64 */
uint32_t RESERVED35; /*!< Reserved Address offset: 0x0D68 */
__IO uint32_t MTLQ1ICSR; /*!< Queue 1 interrupt control status Register Address offset: 0x0D6C */
__IO uint32_t MTLRXQ1OMR; /*!< Rx queue 1 operating mode register Address offset: 0x0D70 */
__IO uint32_t MTLRXQ1MPOCR; /*!< Rx queue 1 missed packet and overflow counter register Address offset: 0x0D74 */
__IO uint32_t MTLRXQ1DR; /*!< Rx queue 1 debug register Address offset: 0x0D78 */
__IO uint32_t MTLRXQ1CR; /*!< Rx queue 1 control register Address offset: 0x0D7C */
uint32_t RESERVED36[160]; /*!< Reserved Address offset: 0x0D80-0x0FFC */
__IO uint32_t DMAMR; /*!< DMA mode register Address offset: 0x1000 */
__IO uint32_t DMASBMR; /*!< System bus mode register Address offset: 0x1004 */
__IO uint32_t DMAISR; /*!< Interrupt status register Address offset: 0x1008 */
__IO uint32_t DMADSR; /*!< Debug status register Address offset: 0x100C */
uint32_t RESERVED37[4]; /*!< Reserved Address offset: 0x1010-0x101C */
__IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register Address offset: 0x1020 */
__IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register Address offset: 0x1024 */
__IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register Address offset: 0x1028 */
uint32_t RESERVED38[53]; /*!< Reserved Address offset: 0x102C-0x10FC */
__IO uint32_t DMAC0CR; /*!< Channel 0 control register Address offset: 0x1100 */
__IO uint32_t DMAC0TXCR; /*!< Channel 0 transmit control register Address offset: 0x1104 */
__IO uint32_t DMAC0RXCR; /*!< Channel 0 receive control register Address offset: 0x1108 */
uint32_t RESERVED39[2]; /*!< Reserved Address offset: 0x110C-0x1110 */
__IO uint32_t DMAC0TXDLAR; /*!< Channel 0 Tx descriptor list address register Address offset: 0x1114 */
uint32_t RESERVED40; /*!< Reserved Address offset: 0x1118 */
__IO uint32_t DMAC0RXDLAR; /*!< Channel 0 Rx descriptor list address register Address offset: 0x111C */
__IO uint32_t DMAC0TXDTPR; /*!< Channel 0 Tx descriptor tail pointer register Address offset: 0x1120 */
uint32_t RESERVED41; /*!< Reserved Address offset: 0x1124 */
__IO uint32_t DMAC0RXDTPR; /*!< Channel 0 Rx descriptor tail pointer register Address offset: 0x1128 */
__IO uint32_t DMAC0TXRLR; /*!< Channel 0 Tx descriptor ring length register Address offset: 0x112C */
__IO uint32_t DMAC0RXRLR; /*!< Channel 0 Rx descriptor ring length register Address offset: 0x1130 */
__IO uint32_t DMAC0IER; /*!< Channel 0 interrupt enable register Address offset: 0x1134 */
__IO uint32_t DMAC0RXIWTR; /*!< Channel 0 Rx interrupt watchdog timer register Address offset: 0x1138 */
__IO uint32_t DMAC0SFCSR; /*!< Channel 0 slot function control status register Address offset: 0x113C */
uint32_t RESERVED42; /*!< Reserved Address offset: 0x1140 */
__IO uint32_t DMAC0CATXDR; /*!< Channel 0 current application transmit descriptor register Address offset: 0x1144 */
uint32_t RESERVED43; /*!< Reserved Address offset: 0x1148 */
__IO uint32_t DMAC0CARXDR; /*!< Channel 0 current application receive descriptor register Address offset: 0x114C */
uint32_t RESERVED44; /*!< Reserved Address offset: 0x1150 */
__IO uint32_t DMAC0CATXBR; /*!< Channel 0 current application transmit buffer register Address offset: 0x1154 */
uint32_t RESERVED45; /*!< Reserved Address offset: 0x1158 */
__IO uint32_t DMAC0CARXBR; /*!< Channel 0 current application receive buffer register Address offset: 0x115C */
__IO uint32_t DMAC0SR; /*!< Channel 0 status register Address offset: 0x1160 */
uint32_t RESERVED46[2]; /*!< Reserved Address offset: 0x1164-0x1168 */
__IO uint32_t DMAC0MFCR; /*!< Channel 0 missed frame count register Address offset: 0x116C */
uint32_t RESERVED47[4]; /*!< Reserved Address offset: 0x1170-0x117C */
__IO uint32_t DMAC1CR; /*!< Channel 1 control register Address offset: 0x1180 */
__IO uint32_t DMAC1TXCR; /*!< Channel 1 transmit control register Address offset: 0x1184 */
uint32_t RESERVED48[3]; /*!< Reserved Address offset: 0x1188-0x1190 */
__IO uint32_t DMAC1TXDLAR; /*!< Channel 1 Tx descriptor list address register Address offset: 0x1194 */
uint32_t RESERVED49[2]; /*!< Reserved Address offset: 0x1198-0x119C */
__IO uint32_t DMAC1TXDTPR; /*!< Channel 1 Tx descriptor tail pointer register Address offset: 0x11A0 */
uint32_t RESERVED50[2]; /*!< Reserved Address offset: 0x11A4-0x11A8 */
__IO uint32_t DMAC1TXRLR; /*!< Channel 1 Tx descriptor ring length register Address offset: 0x11AC */
uint32_t RESERVED51; /*!< Reserved Address offset: 0x11B0 */
__IO uint32_t DMAC1IER; /*!< Channel 1 interrupt enable register Address offset: 0x11B4 */
uint32_t RESERVED52; /*!< Reserved Address offset: 0x11B8 */
__IO uint32_t DMAC1SFCSR; /*!< Channel 1 slot function control status register Address offset: 0x11BC */
uint32_t RESERVED53; /*!< Reserved Address offset: 0x11C0 */
__IO uint32_t DMAC1CATXDR; /*!< Channel 1 current application transmit descriptor register Address offset: 0x11C4 */
uint32_t RESERVED54[3]; /*!< Reserved Address offset: 0x11C8-0x11D0 */
__IO uint32_t DMAC1CATXBR; /*!< Channel 1 current application transmit buffer register Address offset: 0x11D4 */
uint32_t RESERVED55[2]; /*!< Reserved Address offset: 0x11D8-0x11DC */
__IO uint32_t DMAC1SR; /*!< Channel 1 status register Address offset: 0x11E0 */
uint32_t RESERVED56[2]; /*!< Reserved Address offset: 0x11E4-0x11E8 */
__IO uint32_t DMAC1MFCR; /*!< Channel 1 missed frame count register Address offset: 0x11EC */
} ETH_TypeDef;
/**
* @brief External Interrupt/Event Controller
*/
typedef struct
{
__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */
__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */
__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */
__IO uint32_t RPR1; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x0C */
__IO uint32_t FPR1; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x10 */
__IO uint32_t TZENR1; /*!< EXTI Trust Zone enable register, Address offset: 0x14 */
uint32_t RESERVED1[2]; /*!< Reserved, offset 0x18 -> 0x20 */
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */
__IO uint32_t RPR2; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x2C */
__IO uint32_t FPR2; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x30 */
__IO uint32_t TZENR2; /*!< EXTI Trust Zone enable register, Address offset: 0x34 */
uint32_t RESERVED2[2]; /*!< Reserved, offset 0x38 -> 0x40 */
__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */
__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */
__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */
__IO uint32_t RPR3; /*!< EXTI Rising Edge Pending mask register, Address offset: 0x4C */
__IO uint32_t FPR3; /*!< EXTI Falling Edge Pending mask register, Address offset: 0x50 */
__IO uint32_t TZENR3; /*!< EXTI Trust Zone enable register, Address offset: 0x54 */
uint32_t RESERVED3[2]; /*!< Reserved, offset 0x58 -> 0x5C */
__IO uint32_t EXTICR[4]; /*!< EXTI Configuration Register mask register, Address offset: 0x60 */
uint32_t RESERVED4[4]; /*!< Reserved, offset 0x70 -> 0x7C */
__IO uint32_t C1IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */
__IO uint32_t C1EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */
__IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */
__IO uint32_t C1IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */
__IO uint32_t C1EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */
__IO uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x98 - 0x9C */
__IO uint32_t C1IMR3; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0xA0 */
__IO uint32_t C1EMR3; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0xA4 */
__IO uint32_t RESERVED7[6]; /*!< Reserved, Address offset: 0xA8 - 0xBC */
__IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */
__IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */
__IO uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */
__IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */
__IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */
__IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xD8 - 0xDC */
__IO uint32_t C2IMR3; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xE0 */
__IO uint32_t C2EMR3; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xE4 */
uint32_t RESERVED10[182]; /*!< Reserved, offset 0xE8 -> 0x3BC */
__IO uint32_t HWCFGR13; /*!< EXTI HW Configuration Register 13, Address offset: 0x3C0 */
__IO uint32_t HWCFGR12; /*!< EXTI HW Configuration Register 12, Address offset: 0x3C4 */
__IO uint32_t HWCFGR11; /*!< EXTI HW Configuration Register 11, Address offset: 0x3C8 */
__IO uint32_t HWCFGR10; /*!< EXTI HW Configuration Register 10, Address offset: 0x3CC */
__IO uint32_t HWCFGR9; /*!< EXTI HW Configuration Register 9, Address offset: 0x3D0 */
__IO uint32_t HWCFGR8; /*!< EXTI HW Configuration Register 8, Address offset: 0x3D4 */
__IO uint32_t HWCFGR7; /*!< EXTI HW Configuration Register 7, Address offset: 0x3D8 */
__IO uint32_t HWCFGR6; /*!< EXTI HW Configuration Register 6, Address offset: 0x3DC */
__IO uint32_t HWCFGR5; /*!< EXTI HW Configuration Register 5, Address offset: 0x3E0 */
__IO uint32_t HWCFGR4; /*!< EXTI HW Configuration Register 4, Address offset: 0x3E4 */
__IO uint32_t HWCFGR3; /*!< EXTI HW Configuration Register 3, Address offset: 0x3E8 */
__IO uint32_t HWCFGR2; /*!< EXTI HW Configuration Register 2, Address offset: 0x3EC */
__IO uint32_t HWCFGR1; /*!< EXTI HW Configuration Register 1, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< EXTI Version Register , Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< EXTI Identification Register , Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< EXTI Size ID Register , Address offset: 0x3FC */
}EXTI_TypeDef;
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */
uint32_t RESERVED1[2]; /*!< Reserved, offset 0x08 -> 0x10 */
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */
__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */
uint32_t RESERVED2[2]; /*!< Reserved, offset 0x18 -> 0x20 */
__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */
uint32_t RESERVED3[6]; /*!< Reserved, offset 0x28 -> 0x40 */
}EXTI_Core_TypeDef;
/**
* @brief Flexible Memory Controller
*/
typedef struct
{
__IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
__IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register(PCSCNTR), Address offset: 0x20 */
} FMC_Bank1_TypeDef;
/**
* @brief Flexible Memory Controller Bank1E
*/
typedef struct
{
__IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
} FMC_Bank1E_TypeDef;
/**
* @brief Flexible Memory Controller Bank3
*/
typedef struct
{
__IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */
__IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
__IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
__IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
__IO uint32_t HPR; /*!< NAND Flash Hamming Parity result registers 3, Address offset: 0x90 */
__IO uint32_t HECCR; /*!< NAND Flash Hamming ECC result registers 3, Address offset: 0x94 */
uint32_t RESERVED[110]; /*!< Reserved, 0x94->0x250 */
__IO uint32_t BCHIER; /*!< BCH Interrupt Enable Register, Address offset: 0x250 */
__IO uint32_t BCHISR; /*!< BCH Interrupt Status Register, Address offset: 0x254 */
__IO uint32_t BCHICR; /*!< BCH Interrupt Clear Register, Address offset: 0x258 */
uint32_t RESERVED1; /*!< Reserved, 0x25C */
__IO uint32_t BCHPBR1; /*!< BCH Parity Bits Register 1, Address offset: 0x260 */
__IO uint32_t BCHPBR2; /*!< BCH Parity Bits Register 2, Address offset: 0x264 */
__IO uint32_t BCHPBR3; /*!< BCH Parity Bits Register 3, Address offset: 0x268 */
__IO uint32_t BCHPBR4; /*!< BCH Parity Bits Register 4, Address offset: 0x26C */
uint32_t RESERVED2[3]; /*!< Reserved, 0x25C */
__IO uint32_t BCHDSR0; /*!< BCH Decoder Status Register 0, Address offset: 0x27C */
__IO uint32_t BCHDSR1; /*!< BCH Decoder Status Register 1, Address offset: 0x280 */
__IO uint32_t BCHDSR2; /*!< BCH Decoder Status Register 2, Address offset: 0x284 */
__IO uint32_t BCHDSR3; /*!< BCH Decoder Status Register 3, Address offset: 0x288 */
__IO uint32_t BCHDSR4; /*!< BCH Decoder Status Register 4, Address offset: 0x28C */
uint32_t RESERVED3[87]; /*!< Reserved, 0x28C->0x3EC */
__IO uint32_t HWCFGR2; /*!< FMC HW Configuration register 2, Address offset: 0x3EC */
__IO uint32_t HWCFGR1; /*!< FMC HW Configuration register 1, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< FMC Version register , Address offset: 0x3F4 */
__IO uint32_t IDR; /*!< FMC Identification register , Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< FMC Size ID register , Address offset: 0x3FC */
} FMC_Bank3_TypeDef;
/**
* @brief General Purpose I/O
*/
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x000 */
__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x004 */
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x008 */
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x00C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x010 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x014 */
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x018 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x01C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x020-0x024 */
__IO uint32_t BRR; /*!< GPIO port bit reset register, Address offset: 0x028 */
uint32_t RESERVED0; /*!< Reserved, Address offset: 0x02C */
__IO uint32_t SECCFGR; /*!< GPIO secure configuration register for GPIOZ, Address offset: 0x030 */
uint32_t RESERVED1[229]; /*!< Reserved, Address offset: 0x034-0x3C4 */
__IO uint32_t HWCFGR10; /*!< GPIO hardware configuration register 10, Address offset: 0x3C8 */
__IO uint32_t HWCFGR9; /*!< GPIO hardware configuration register 9, Address offset: 0x3CC */
__IO uint32_t HWCFGR8; /*!< GPIO hardware configuration register 8, Address offset: 0x3D0 */
__IO uint32_t HWCFGR7; /*!< GPIO hardware configuration register 7, Address offset: 0x3D4 */
__IO uint32_t HWCFGR6; /*!< GPIO hardware configuration register 6, Address offset: 0x3D8 */
__IO uint32_t HWCFGR5; /*!< GPIO hardware configuration register 5, Address offset: 0x3DC */
__IO uint32_t HWCFGR4; /*!< GPIO hardware configuration register 4, Address offset: 0x3E0 */
__IO uint32_t HWCFGR3; /*!< GPIO hardware configuration register 3, Address offset: 0x3E4 */
__IO uint32_t HWCFGR2; /*!< GPIO hardware configuration register 2, Address offset: 0x3E8 */
__IO uint32_t HWCFGR1; /*!< GPIO hardware configuration register 1, Address offset: 0x3EC */
__IO uint32_t HWCFGR0; /*!< GPIO hardware configuration register 0, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< GPIO version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< GPIO identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< GPIO size identification register, Address offset: 0x3FC */
} GPIO_TypeDef;
/**
* @brief System configuration controller
*/
typedef struct
{
__IO uint32_t BOOTR; /*!< SYSCFG Boot pin control register, Address offset: 0x00 */
__IO uint32_t PMCSETR; /*!< SYSCFG Peripheral Mode configuration set register, Address offset: 0x04 */
__IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x08-0x18 */
__IO uint32_t IOCTRLSETR; /*!< SYSCFG ioctl set register, Address offset: 0x18 */
__IO uint32_t ICNR; /*!< SYSCFG interconnect control register, Address offset: 0x1C */
__IO uint32_t CMPCR; /*!< SYSCFG compensation cell control register, Address offset: 0x20 */
__IO uint32_t CMPENSETR; /*!< SYSCFG compensation cell enable set register, Address offset: 0x24 */
__IO uint32_t CMPENCLRR; /*!< SYSCFG compensation cell enable clear register, Address offset: 0x28 */
__IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x2C */
__IO uint32_t RESERVED2[5]; /*!< Reserved, Address offset: 0x30-0x40 */
__IO uint32_t PMCCLRR; /*!< SYSCFG Peripheral Mode configuration clear register, Address offset: 0x44 */
__IO uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x48-0x54 */
__IO uint32_t IOCTRLCLRR; /*!< SYSCFG ioctl clear register, Address offset: 0x58 */
uint32_t RESERVED4[230]; /*!< Reserved, Address offset: 0x5C->0x3F4 */
__IO uint32_t VERR; /*!< SYSCFG version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< SYSCFG ID register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< SYSCFG magic ID register, Address offset: 0x3FC */
} SYSCFG_TypeDef;
/**
* @briefVoltage reference buffer
*/
typedef struct
{
__IO uint32_t CSR; /*VREF control and status register Address offset: 0x00 */
__IO uint32_t CCR; /*VREF control and status register Address offset: 0x04 */
} VREF_TypeDef;
/**
* @brief Inter-integrated Circuit Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
__IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
__IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
__IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
__IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
__IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
__IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
__IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
__IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
__IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
uint32_t RESERVED[241]; /*!< Reserved, 0x2C->0x3F0 */
__IO uint32_t HWCFGR; /*!< I2C hardware configuration register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< I2C version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< I2C identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< I2C size identification register, Address offset: 0x3FC */
} I2C_TypeDef;
/**
* @brief Independent WATCHDOG
*/
typedef struct
{
__IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
__IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
__IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
__IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
__IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
__IO uint32_t EWCR; /*!< IWDG Window register, Address offset: 0x14 */
uint32_t RESERVED[246]; /*!< Reserved, 0x18->0x3EC */
__IO uint32_t HWCFGR; /*!< IWDG hardware configuration register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< IWDG version register, Address offset: 0x3F4 */
__IO uint32_t IDR; /*!< IWDG identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< IWDG size identification register, Address offset: 0x3FC */
} IWDG_TypeDef;
/**
* @brief JPEG Codec
*/
typedef struct
{
__IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
__IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
__IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
__IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
__IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
__IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
__IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
__IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
__IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
__IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
__IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
__IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
__IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
__IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
__IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
__IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
__IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
__IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
__IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
__IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
__IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
__IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
__IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
__IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
__IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
} JPEG_TypeDef;
/**
* @brief LCD
*/
typedef struct
{
__IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
__IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
__IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
__IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
__IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
} LCD_TypeDef;
/**
* @brief LCD-TFT Display Controller
*/
typedef struct
{
uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
__IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
__IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
__IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
__IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
__IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
__IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
__IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
__IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
__IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
__IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
__IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
__IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
__IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
} LTDC_TypeDef;
/**
* @brief LCD-TFT Display layer x Controller
*/
typedef struct
{
__IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
__IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
__IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
__IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
__IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
__IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
__IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
__IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
uint32_t RESERVED0[2]; /*!< Reserved */
__IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
__IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
__IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
uint32_t RESERVED1[3]; /*!< Reserved */
__IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
} LTDC_Layer_TypeDef;
/**
* @brief DDRPHYC DDR Physical Interface Control
*/
typedef struct
{
__IO uint32_t RIDR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x000 */
__IO uint32_t PIR; /*!< DDR_PHY: PUBL PHY Initialization register, Address offset: 0x004 */
__IO uint32_t PGCR; /*!< DDR_PHY: Address offset: 0x008 */
__IO uint32_t PGSR; /*!< DDR_PHY: Address offset: 0x00C */
__IO uint32_t DLLGCR; /*!< DDR_PHY: Address offset: 0x010 */
__IO uint32_t ACDLLCR; /*!< DDR_PHY: Address offset: 0x014 */
__IO uint32_t PTR0; /*!< DDR_PHY: Address offset: 0x018 */
__IO uint32_t PTR1; /*!< DDR_PHY: Address offset: 0x01C */
__IO uint32_t PTR2; /*!< DDR_PHY: Address offset: 0x020 */
__IO uint32_t ACIOCR; /*!< DDR_PHY: PUBL AC I/O Configuration Register, Address offset: 0x024 */
__IO uint32_t DXCCR; /*!< DDR_PHY: PUBL DATX8 Common Configuration Register, Address offset: 0x028 */
__IO uint32_t DSGCR; /*!< DDR_PHY: PUBL DDR System General Configuration Register, Address offset: 0x02C */
__IO uint32_t DCR; /*!< DDR_PHY: Address offset: 0x030 */
__IO uint32_t DTPR0; /*!< DDR_PHY: Address offset: 0x034 */
__IO uint32_t DTPR1; /*!< DDR_PHY: Address offset: 0x038 */
__IO uint32_t DTPR2; /*!< DDR_PHY: Address offset: 0x03C */
__IO uint32_t MR0; /*!< DDR_PHY:H Address offset: 0x040 */
__IO uint32_t MR1; /*!< DDR_PHY:H Address offset: 0x044 */
__IO uint32_t MR2; /*!< DDR_PHY:H Address offset: 0x048 */
__IO uint32_t MR3; /*!< DDR_PHY:B Address offset: 0x04C */
__IO uint32_t ODTCR; /*!< DDR_PHY:H Address offset: 0x050 */
__IO uint32_t DTAR; /*!< DDR_PHY: Address offset: 0x054 */
__IO uint32_t DTDR0; /*!< DDR_PHY: Address offset: 0x058 */
__IO uint32_t DTDR1; /*!< DDR_PHY: Address offset: 0x05C */
uint32_t RESERVED0[24]; /*!< Reserved */
__IO uint32_t DCUAR; /*!< DDR_PHY:H Address offset: 0x0C0 */
__IO uint32_t DCUDR; /*!< DDR_PHY: Address offset: 0x0C4 */
__IO uint32_t DCURR; /*!< DDR_PHY: Address offset: 0x0C8 */
__IO uint32_t DCULR; /*!< DDR_PHY: Address offset: 0x0CC */
__IO uint32_t DCUGCR; /*!< DDR_PHY:H Address offset: 0x0D0 */
__IO uint32_t DCUTPR; /*!< DDR_PHY: Address offset: 0x0D4 */
__IO uint32_t DCUSR0; /*!< DDR_PHY:B Address offset: 0x0D8 */
__IO uint32_t DCUSR1; /*!< DDR_PHY: Address offset: 0x0DC */
uint32_t RESERVED1[8]; /*!< Reserved */
__IO uint32_t BISTRR; /*!< DDR_PHY: Address offset: 0x100 */
__IO uint32_t BISTMSKR0; /*!< DDR_PHY: Address offset: 0x104 */
__IO uint32_t BISTMSKR1; /*!< DDR_PHY: Address offset: 0x108 */
__IO uint32_t BISTWCR; /*!< DDR_PHY:H Address offset: 0x10C */
__IO uint32_t BISTLSR; /*!< DDR_PHY: Address offset: 0x110 */
__IO uint32_t BISTAR0; /*!< DDR_PHY: Address offset: 0x114 */
__IO uint32_t BISTAR1; /*!< DDR_PHY:H Address offset: 0x118 */
__IO uint32_t BISTAR2; /*!< DDR_PHY: Address offset: 0x11C */
__IO uint32_t BISTUDPR; /*!< DDR_PHY: Address offset: 0x120 */
__IO uint32_t BISTGSR; /*!< DDR_PHY: Address offset: 0x124 */
__IO uint32_t BISTWER; /*!< DDR_PHY: Address offset: 0x128 */
__IO uint32_t BISTBER0; /*!< DDR_PHY: Address offset: 0x12C */
__IO uint32_t BISTBER1; /*!< DDR_PHY: Address offset: 0x130 */
__IO uint32_t BISTBER2; /*!< DDR_PHY: Address offset: 0x134 */
__IO uint32_t BISTWCSR; /*!< DDR_PHY: Address offset: 0x138 */
__IO uint32_t BISTFWR0; /*!< DDR_PHY: Address offset: 0x13C */
__IO uint32_t BISTFWR1; /*!< DDR_PHY: Address offset: 0x140 */
uint32_t RESERVED2[13]; /*!< Reserved */
__IO uint32_t GPR0; /*!< DDR_PHY: Address offset: 0x178 */
__IO uint32_t GPR1; /*!< DDR_PHY: Address offset: 0x17C */
__IO uint32_t ZQ0CR0; /*!< DDR_PHY: Address offset: 0x180 */
__IO uint32_t ZQ0CR1; /*!< DDR_PHY:B Address offset: 0x184 */
__IO uint32_t ZQ0SR0; /*!< DDR_PHY: Address offset: 0x188 */
__IO uint32_t ZQ0SR1; /*!< DDR_PHY:B Address offset: 0x18C */
uint32_t RESERVED3[12]; /*!< Reserved */
__IO uint32_t DX0GCR; /*!< DDR_PHY: Address offset: 0x1C0 */
__IO uint32_t DX0GSR0; /*!< DDR_PHY:H Address offset: 0x1C4 */
__IO uint32_t DX0GSR1; /*!< DDR_PHY: Address offset: 0x1C8 */
__IO uint32_t DX0DLLCR; /*!< DDR_PHY: Address offset: 0x1CC */
__IO uint32_t DX0DQTR; /*!< DDR_PHY: Address offset: 0x1D0 */
__IO uint32_t DX0DQSTR; /*!< DDR_PHY: Address offset: 0x1D4 */
uint32_t RESERVED4[10]; /*!< Reserved */
__IO uint32_t DX1GCR; /*!< DDR_PHY: Address offset: 0x200 */
__IO uint32_t DX1GSR0; /*!< DDR_PHY:H Address offset: 0x204 */
__IO uint32_t DX1GSR1; /*!< DDR_PHY: Address offset: 0x208 */
__IO uint32_t DX1DLLCR; /*!< DDR_PHY: Address offset: 0x20C */
__IO uint32_t DX1DQTR; /*!< DDR_PHY: Address offset: 0x210 */
__IO uint32_t DX1DQSTR; /*!< DDR_PHY: Address offset: 0x214 */
uint32_t RESERVED5[10]; /*!< Reserved */
__IO uint32_t DX2GCR; /*!< DDR_PHY: Address offset: 0x240 */
__IO uint32_t DX2GSR0; /*!< DDR_PHY:H Address offset: 0x244 */
__IO uint32_t DX2GSR1; /*!< DDR_PHY: Address offset: 0x248 */
__IO uint32_t DX2DLLCR; /*!< DDR_PHY: Address offset: 0x24C */
__IO uint32_t DX2DQTR; /*!< DDR_PHY: Address offset: 0x250 */
__IO uint32_t DX2DQSTR; /*!< DDR_PHY: Address offset: 0x254 */
uint32_t RESERVED6[10]; /*!< Reserved */
__IO uint32_t DX3GCR; /*!< DDR_PHY: Address offset: 0x280 */
__IO uint32_t DX3GSR0; /*!< DDR_PHY:H Address offset: 0x284 */
__IO uint32_t DX3GSR1; /*!< DDR_PHY: Address offset: 0x288 */
__IO uint32_t DX3DLLCR; /*!< DDR_PHY: Address offset: 0x28C */
__IO uint32_t DX3DQTR; /*!< DDR_PHY: Address offset: 0x290 */
__IO uint32_t DX3DQSTR; /*!< DDR_PHY: Address offset: 0x294 */
}DDRPHYC_TypeDef;
/**
* @brief DDRC DDR3/LPDDR2 Controller (DDRCTRL)
*/
typedef struct
{
__IO uint32_t MSTR; /*!< DDR_PHY: PUBL revision Identification register, Address offset: 0x00 */
/* @TODO : TypeDef to be compleated */
}DDRC_TypeDef;
/**
* @brief USBPHYC USB HS PHY Control
*/
typedef struct
{
__IO uint32_t PLL; /*!< USBPHYC PLL control register, Address offset: 0x000 */
uint32_t RESERVED0; /*! Reserved Address offset: 0x004 */
__IO uint32_t MISC; /*!< USBPHYC Misc Control register, Address offset: 0x008 */
uint32_t RESERVED1[250] ; /*! Reserved Address offset: 0x00C - 0x3F0*/
__IO uint32_t VERR; /*!< USBPHYC Version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< USBPHYC Identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< USBPHYC Size ID register, Address offset: 0x3FC */
}USBPHYC_GlobalTypeDef;
/**
* @brief USBPHYC USB HS PHY Control PHYx
*/
typedef struct
{
uint32_t RESERVED0[3]; /*! Reserved Address offset: 0x000 - 0x008 */
__IO uint32_t TUNE; /*!< USBPHYC x TUNE register ter, Address offset: 0x00C */
}USBPHYC_InstanceTypeDef;
/**
* @brief TZC TrustZone Address Space Controller for DDR
*/
typedef struct
{
__IO uint32_t BUILD_CONFIG; /*!< Build config register, Address offset: 0x00 */
__IO uint32_t ACTION; /*!< Action register, Address offset: 0x04 */
__IO uint32_t GATE_KEEPER; /*!< Gate keeper register, Address offset: 0x08 */
__IO uint32_t SPECULATION_CTRL; /*!< Speculation control register, Address offset: 0x0C */
uint8_t RESERVED0[0x100 - 0x10];
__IO uint32_t REG_BASE_LOWO; /*!< Region 0 base address low register, Address offset: 0x100 */
__IO uint32_t REG_BASE_HIGHO; /*!< Region 0 base address high register, Address offset: 0x104 */
__IO uint32_t REG_TOP_LOWO; /*!< Region 0 top address low register, Address offset: 0x108 */
__IO uint32_t REG_TOP_HIGHO; /*!< Region 0 top address high register, Address offset: 0x10C */
__IO uint32_t REG_ATTRIBUTESO; /*!< Region 0 attribute register, Address offset: 0x110 */
__IO uint32_t REG_ID_ACCESSO; /*!< Region 0 ID access register, Address offset: 0x114 */
/* @TODO : TypeDef to be compleated if needed*/
}TZC_TypeDef;
/**
* @brief TZPC TrustZone Protection Controller
*/
typedef struct
{
__IO uint32_t TZMA0_SIZE; /*!<TZPC ROM Secure Size Definition register, Address offset: 0x00 */
__IO uint32_t TZMA1_SIZE; /*!<TZPC SYSRAM Secure Size Definition register, Address offset: 0x04 */
uint32_t RESERVED0[2]; /*!< Reserved */
__IO uint32_t DECPROT0; /*!<TZPC Securable peripheral definition register 0, Address offset: 0x10 */
__IO uint32_t DECPROT1; /*!<TZPC Securable peripheral definition register 1, Address offset: 0x14 */
__IO uint32_t DECPROT2; /*!<TZPC Securable peripheral definition register 2, Address offset: 0x18 */
__IO uint32_t DECPROT3; /*!<TZPC Securable peripheral definition register 3, Address offset: 0x1C */
__IO uint32_t DECPROT4; /*!<TZPC Securable peripheral definition register 4, Address offset: 0x20 */
__IO uint32_t DECPROT5; /*!<TZPC Securable peripheral definition register 5, Address offset: 0x24 */
uint32_t RESERVED1[2]; /*!< Reserved */
__IO uint32_t DECPROT_LOCK0; /*!<TZPC Securable lock of security register 0, Address offset: 0x30 */
__IO uint32_t DECPROT_LOCK1; /*!<TZPC Securable lock of security register 1, Address offset: 0x34 */
__IO uint32_t DECPROT_LOCK2; /*!<TZPC Securable lock of security register 2, Address offset: 0x38 */
uint32_t RESERVED2[237]; /*!< Reserved */
__IO uint32_t HWCFGR; /*!< TZPC IP HW configuration register Address offset:0x3F0 */
__IO uint32_t IP_VER; /*!< TZPC IP version register Address offset:0x3F4 */
__IO uint32_t ID; /*!< TZPC IP version register Address offset:0x3F8 */
__IO uint32_t SID; /*!< TZPC IP version register Address offset:0x3FC */
}TZPC_TypeDef;
/**
* @brief STGENC System Generic Counter Control
*/
typedef struct
{
__IO uint32_t CNTCR; /*!< STGEN Counter Control Register, Address offset: 0x00 */
/* @TODO : TypeDef to be compleated if needed*/
}STGENC_TypeDef;
/**
* @brief Firewall
*/
typedef struct
{
__IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
__IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
__IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
__IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
__IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
__IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
__IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
} FIREWALL_TypeDef;
/**
* @brief Power Control
*/
typedef struct
{
__IO uint32_t CR1; /*!< PWR control register 1, Address offset: 0x00 */
__IO uint32_t CSR1; /*!< PWR control status register 1, Address offset: 0x04 */
__IO uint32_t CR2; /*!< PWR control register 2, Address offset: 0x08 */
__IO uint32_t CR3; /*!< PWR control register 3, Address offset: 0x0C */
__IO uint32_t MPUCR; /*!< PWR MPU control register, Address offset: 0x10 */
__IO uint32_t MCUCR; /*!< PWR MCU control register, Address offset: 0x14 */
uint32_t RESERVED0[2]; /*!< Reserved, 0x18-0x1C Address offset: 0x18 */
__IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */
__IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */
__IO uint32_t MPUWKUPENR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
__IO uint32_t MCUWKUPENR; /*!< PWR wakeup enable and polarity register, Address offset: 0x2C */
uint32_t RESERVED1[241]; /*!< Reserved, 0x30-0x3F0 Address offset: 0x30 */
__IO uint32_t VER; /*!< PWR IP version register, Address offset: 0x3F4 */
__IO uint32_t ID; /*!< PWR IP identification register, Address offset: 0x3F8 */
__IO uint32_t SID; /*!< PWR size ID register, Address offset: 0x3FC */
} PWR_TypeDef;
/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t TZCR; /*!< RCC TrustZone Control Register Address offset: 0x00 */
uint32_t RESERVED0[2]; /*!< Reserved, 0x04-0x08 Address offset: 0x04 */
__IO uint32_t OCENSETR; /*!< RCC Oscillator Clock Enable Set Register Address offset: 0x0C */
__IO uint32_t OCENCLRR; /*!< RCC Oscillator Enable Control Clear Register Address offset: 0x10 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
__IO uint32_t HSICFGR; /*!< RCC HSI Configuration Register Address offset: 0x18 */
__IO uint32_t CSICFGR; /*!< RCC CSI Configuration Register Address offset: 0x1C */
__IO uint32_t MPCKSELR; /*!< RCC MPU Clock Selection Register Address offset: 0x20 */
__IO uint32_t ASSCKSELR; /*!< RCC AXI Sub-System Clock Selection Register Address offset: 0x24 */
__IO uint32_t RCK12SELR; /*!< RCC PLL 1 and 2 Ref. Clock Selection Register Address offset: 0x28 */
__IO uint32_t MPCKDIVR; /*!< RCC MPU Clock Divider Register Address offset: 0x2C */
__IO uint32_t AXIDIVR; /*!< RCC AXI Clock Divider Register Address offset: 0x30 */
uint32_t RESERVED2[2]; /*!< Reserved, 0x34-0x38 Address offset: 0x34 */
__IO uint32_t APB4DIVR; /*!< RCC APB4 Clock Divider Register Address offset: 0x3C */
__IO uint32_t APB5DIVR; /*!< RCC APB5 Clock Divider Register Address offset: 0x40 */
__IO uint32_t RTCDIVR; /*!< RCC RTC Clock Division Register Address offset: 0x44 */
__IO uint32_t MSSCKSELR; /*!< RCC MCU Sub-System Clock Selection Register Address offset: 0x48 */
uint32_t RESERVED3[13]; /*!< Reserved, 0x4C-0x7C Address offset: 0x4C */
__IO uint32_t PLL1CR; /*!< RCC PLL1 Control Register Address offset: 0x80 */
__IO uint32_t PLL1CFGR1; /*!< RCC PLL1 Configuration Register 1 Address offset: 0x84 */
__IO uint32_t PLL1CFGR2; /*!< RCC PLL1 Configuration Register 2 Address offset: 0x88 */
__IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Register Address offset: 0x8C */
__IO uint32_t PLL1CSGR; /*!< RCC PLL1 Clock Spreading Generator Register Address offset: 0x90 */
__IO uint32_t PLL2CR; /*!< RCC PLL2 Control Register Address offset: 0x94 */
__IO uint32_t PLL2CFGR1; /*!< RCC PLL2 Configuration Register 1 Address offset: 0x98 */
__IO uint32_t PLL2CFGR2; /*!< RCC PLL2 Configuration Register 2 Address offset: 0x9C */
__IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Register Address offset: 0xA0 */
__IO uint32_t PLL2CSGR; /*!< RCC PLL2 Clock Spreading Generator Register Address offset: 0xA4 */
uint32_t RESERVED4[6]; /*!< Reserved, 0xA8-0xBC Address offset: 0xA8 */
__IO uint32_t I2C46CKSELR; /*!< RCC I2C46 Kernel Clock Selection Register Address offset: 0xC0 */
__IO uint32_t SPI6CKSELR; /*!< RCC SPI6 Kernel Clock Selection Register Address offset: 0xC4 */
__IO uint32_t UART1CKSELR; /*!< RCC USART1 Kernel Clock Selection Register Address offset: 0xC8 */
__IO uint32_t RNG1CKSELR; /*!< RCC RNG1 Kernel Clock Selection Register Address offset: 0xCC */
__IO uint32_t CPERCKSELR; /*!< RCC Common Peripheral Clock Selection Register Address offset: 0xD0 */
__IO uint32_t STGENCKSELR; /*!< RCC STGEN Clock Selection Register Address offset: 0xD4 */
__IO uint32_t DDRITFCR; /*!< RCC control DDR interface, DDRC and DDRPHYC Register Address offset: 0xD8 */
uint32_t RESERVED5; /*!< Reserved, Address offset: 0xDC */
uint32_t RESERVED6[8]; /*!< Reserved, 0xE0-0xFC Address offset: 0xE0 */
__IO uint32_t MP_BOOTCR; /*!< RCC Hold Boot Control Register Address offset: 0x100 */
__IO uint32_t MP_SREQSETR; /*!< RCC Stop Request Set Register Address offset: 0x104 */
__IO uint32_t MP_SREQCLRR; /*!< RCC Stop Request Clear Register Address offset: 0x108 */
__IO uint32_t MP_GCR; /*!< RCC Global Control Register Address offset: 0x10C */
__IO uint32_t MP_APRSTCR; /*!< RCC Application Reset Control Register Address offset: 0x110 */
__IO uint32_t MP_APRSTSR; /*!< RCC Application Reset Status Register Address offset: 0x114 */
uint32_t RESERVED7[10]; /*!< Reserved, 0x118-0x13C Address offset: 0x118 */
__IO uint32_t BDCR; /*!< RCC Backup Domain Control Register Address offset: 0x140 */
__IO uint32_t RDLSICR; /*!< RCC Reset Duration and LSI Control Register Address offset: 0x144 */
uint32_t RESERVED8[14]; /*!< Reserved, 0x148-0x17C Address offset: 0x148 */
__IO uint32_t APB4RSTSETR; /*!< RCC APB4 Peripheral Reset Set Register Address offset: 0x180 */
__IO uint32_t APB4RSTCLRR; /*!< RCC APB4 Peripheral Reset Clear Register Address offset: 0x184 */
__IO uint32_t APB5RSTSETR; /*!< RCC APB5 Peripheral Reset Set Register Address offset: 0x188 */
__IO uint32_t APB5RSTCLRR; /*!< RCC APB5 Peripheral Reset Clear Register Address offset: 0x18C */
__IO uint32_t AHB5RSTSETR; /*!< RCC AHB5 Peripheral Reset Set Register Address offset: 0x190 */
__IO uint32_t AHB5RSTCLRR; /*!< RCC AHB5 Peripheral Reset Clear Register Address offset: 0x194 */
__IO uint32_t AHB6RSTSETR; /*!< RCC AHB6 Peripheral Reset Set Register Address offset: 0x198 */
__IO uint32_t AHB6RSTCLRR; /*!< RCC AHB6 Peripheral Reset Clear Register Address offset: 0x19C */
__IO uint32_t TZAHB6RSTSETR; /*!< RCC AHB6 Peripheral Reset Set Register Address offset: 0x1A0 */
__IO uint32_t TZAHB6RSTCLRR; /*!< RCC AHB6 Peripheral Reset Clear Register Address offset: 0x1A4 */
uint32_t RESERVED9[22]; /*!< Reserved, 0x1A8-0x1FC Address offset: 0x1A8 */
__IO uint32_t MP_APB4ENSETR; /*!< RCC APB4 Periph. Enable For MPU Set Register Address offset: 0x200 */
__IO uint32_t MP_APB4ENCLRR; /*!< RCC APB4 Periph. Enable For MPU Clear Register Address offset: 0x204 */
__IO uint32_t MP_APB5ENSETR; /*!< RCC APB5 Periph. Enable For MPU Set Register Address offset: 0x208 */
__IO uint32_t MP_APB5ENCLRR; /*!< RCC APB5 Periph. Enable For MPU Clear Register Address offset: 0x20C */
__IO uint32_t MP_AHB5ENSETR; /*!< RCC AHB5 Periph. Enable For MPU Set Register Address offset: 0x210 */
__IO uint32_t MP_AHB5ENCLRR; /*!< RCC AHB5 Periph. Enable For MPU Clear Register Address offset: 0x214 */
__IO uint32_t MP_AHB6ENSETR; /*!< RCC AHB6 Periph. Enable For MPU Set Register Address offset: 0x218 */
__IO uint32_t MP_AHB6ENCLRR; /*!< RCC AHB6 Periph. Enable For MPU Clear Register Address offset: 0x21C */
uint32_t RESERVED10[24]; /*!< Reserved, 0x220-0x27C Address offset: 0x220 */
__IO uint32_t MC_APB4ENSETR; /*!< RCC APB4 Periph. Enable For MCU Set Register Address offset: 0x280 */
__IO uint32_t MC_APB4ENCLRR; /*!< RCC APB4 Periph. Enable For MCU Clear Register Address offset: 0x284 */
__IO uint32_t MC_APB5ENSETR; /*!< RCC APB5 Periph. Enable For MCU Set Register Address offset: 0x288 */
__IO uint32_t MC_APB5ENCLRR; /*!< RCC APB5 Periph. Enable For MCU Clear Register Address offset: 0x28C */
__IO uint32_t MC_AHB5ENSETR; /*!< RCC AHB5 Periph. Enable For MCU Set Register Address offset: 0x290 */
__IO uint32_t MC_AHB5ENCLRR; /*!< RCC AHB5 Periph. Enable For MCU Clear Register Address offset: 0x294 */
__IO uint32_t MC_AHB6ENSETR; /*!< RCC AHB6 Periph. Enable For MCU Set Register Address offset: 0x298 */
__IO uint32_t MC_AHB6ENCLRR; /*!< RCC AHB6 Periph. Enable For MCU Clear Register Address offset: 0x29C */
uint32_t RESERVED11[24]; /*!< Reserved, 0x2A0-0x2FC Address offset: 0x2A0 */
__IO uint32_t MP_APB4LPENSETR; /*!< RCC APB4 Sleep Clock Ena. For MPU Set Register Address offset: 0x300 */
__IO uint32_t MP_APB4LPENCLRR; /*!< RCC APB4 Sleep Clock Ena. For MPU Clear Register Address offset: 0x304 */
__IO uint32_t MP_APB5LPENSETR; /*!< RCC APB5 Sleep Clock Ena. For MPU Set Register Address offset: 0x308 */
__IO uint32_t MP_APB5LPENCLRR; /*!< RCC APB5 Sleep Clock Ena. For MPU Clear Register Address offset: 0x30C */
__IO uint32_t MP_AHB5LPENSETR; /*!< RCC AHB5 Sleep Clock Ena. For MPU Set Register Address offset: 0x310 */
__IO uint32_t MP_AHB5LPENCLRR; /*!< RCC AHB5 Sleep Clock Ena. For MPU Clear Register Address offset: 0x314 */
__IO uint32_t MP_AHB6LPENSETR; /*!< RCC AHB6 Sleep Clock Ena. For MPU Set Register Address offset: 0x318 */
__IO uint32_t MP_AHB6LPENCLRR; /*!< RCC AHB6 Sleep Clock Ena. For MPU Clear Register Address offset: 0x31C */
uint32_t RESERVED12[24]; /*!< Reserved, 0x320-0x30C Address offset: 0x320 */
__IO uint32_t MC_APB4LPENSETR; /*!< RCC APB4 Sleep Clock Ena. For MCU Set Register Address offset: 0x380 */
__IO uint32_t MC_APB4LPENCLRR; /*!< RCC APB4 Sleep Clock Ena. For MCU Clear Register Address offset: 0x384 */
__IO uint32_t MC_APB5LPENSETR; /*!< RCC APB5 Sleep Clock Ena. For MCU Set Register Address offset: 0x388 */
__IO uint32_t MC_APB5LPENCLRR; /*!< RCC APB5 Sleep Clock Ena. For MCU Clear Register Address offset: 0x38C */
__IO uint32_t MC_AHB5LPENSETR; /*!< RCC AHB5 Sleep Clock Ena. For MCU Set Register Address offset: 0x390 */
__IO uint32_t MC_AHB5LPENCLRR; /*!< RCC AHB5 Sleep Clock Ena. For MCU Clear Register Address offset: 0x394 */
__IO uint32_t MC_AHB6LPENSETR; /*!< RCC AHB6 Sleep Clock Ena. For MCU Set Register Address offset: 0x398 */
__IO uint32_t MC_AHB6LPENCLRR; /*!< RCC AHB6 Sleep Clock Ena. For MCU Clear Register Address offset: 0x39C */
uint32_t RESERVED13[24]; /*!< Reserved, 0x3A0-0x3FC Address offset: 0x3A0 */
__IO uint32_t BR_RSTSCLRR; /*!< RCC BootRom Reset Status Clear Register Address offset: 0x400 */
__IO uint32_t MP_GRSTCSETR; /*!< RCC Global Reset Control Set Register Address offset: 0x404 */
__IO uint32_t MP_RSTSCLRR; /*!< RCC MPU Reset Status Clear Register Address offset: 0x408 */
__IO uint32_t MP_IWDGFZSETR; /*!< RCC IWDG Clock Freeze Set Register Address offset: 0x40C */
__IO uint32_t MP_IWDGFZCLRR; /*!< RCC IWDG Clock Freeze Clear Register Address offset: 0x410 */
__IO uint32_t MP_CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x414 */
__IO uint32_t MP_CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x418 */
__IO uint32_t PWRLPDLYCR; /*!< RCC PWR_LP Delay Control Register Address offset: 0x41C */
__IO uint32_t MP_RSTSSETR; /*!< RCC MPU Reset Status Set Register Address offset: 0x420 */
uint32_t RESERVED14[247]; /*!< Reserved, 0x424-0x7FC Address offset: 0x424 */
__IO uint32_t MCO1CFGR; /*!< RCC MCO1 Configuration Register Address offset: 0x800 */
__IO uint32_t MCO2CFGR; /*!< RCC MCO2 Configuration Register Address offset: 0x804 */
__IO uint32_t OCRDYR; /*!< RCC Oscillator Clock Ready Register Address offset: 0x808 */
__IO uint32_t DBGCFGR; /*!< Debug Configuration Register Address offset: 0x80C */
uint32_t RESERVED15[4]; /*!< Reserved, 0x810-0x81C Address offset: 0x810 */
__IO uint32_t RCK3SELR; /*!< RCC PLL 3 Ref. Clock Selection Register Address offset: 0x820 */
__IO uint32_t RCK4SELR; /*!< RCC PLL4 Ref. Clock Selection Register Address offset: 0x824 */
__IO uint32_t TIMG1PRER; /*!< RCC TIM Group 1 Prescaler Register Address offset: 0x828 */
__IO uint32_t TIMG2PRER; /*!< RCC TIM Group 2 Prescaler Register Address offset: 0x82C */
__IO uint32_t MCUDIVR; /*!< RCC MCU Clock Prescaler Register Address offset: 0x830 */
__IO uint32_t APB1DIVR; /*!< RCC APB1 Clock Prescaler Register Address offset: 0x834 */
__IO uint32_t APB2DIVR; /*!< RCC APB2 Clock Prescaler Register Address offset: 0x838 */
__IO uint32_t APB3DIVR; /*!< RCC APB3 Clock Prescaler Register Address offset: 0x83C */
uint32_t RESERVED16[16]; /*!< Reserved, 0x840-0x87C Address offset: 0x840 */
__IO uint32_t PLL3CR; /*!< RCC PLL3 Control Register Address offset: 0x880 */
__IO uint32_t PLL3CFGR1; /*!< RCC PLL3 Configuration Register 1 Address offset: 0x884 */
__IO uint32_t PLL3CFGR2; /*!< RCC PLL3 Configuration Register 2 Address offset: 0x888 */
__IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Register Address offset: 0x88C */
__IO uint32_t PLL3CSGR; /*!< RCC PLL3 Clock Spreading Generator Register Address offset: 0x890 */
__IO uint32_t PLL4CR; /*!< RCC PLL4 Control Register Address offset: 0x894 */
__IO uint32_t PLL4CFGR1; /*!< RCC PLL4 Configuration Register 1 Address offset: 0x898 */
__IO uint32_t PLL4CFGR2; /*!< RCC PLL4 Configuration Register 2 Address offset: 0x89C */
__IO uint32_t PLL4FRACR; /*!< RCC PLL4 Fractional Register Address offset: 0x8A0 */
__IO uint32_t PLL4CSGR; /*!< RCC PLL4 Clock Spreading Generator Register Address offset: 0x8A4 */
uint32_t RESERVED17[6]; /*!< Reserved, 0x8A8-0x8BC Address offset: 0x8A8 */
__IO uint32_t I2C12CKSELR; /*!< RCC I2C1,2 Kernel Clock Selection Register Address offset: 0x8C0 */
__IO uint32_t I2C35CKSELR; /*!< RCC I2C3,5 Kernel Clock Selection Register Address offset: 0x8C4 */
__IO uint32_t SAI1CKSELR; /*!< RCC SAI1 Kernel Clock Selection Register Address offset: 0x8C8 */
__IO uint32_t SAI2CKSELR; /*!< RCC SAI2 Kernel Clock Selection Register Address offset: 0x8CC */
__IO uint32_t SAI3CKSELR; /*!< RCC SAI3 Kernel Clock Selection Register Address offset: 0x8D0 */
__IO uint32_t SAI4CKSELR; /*!< RCC SAI4 Kernel Clock Selection Register Address offset: 0x8D4 */
__IO uint32_t SPI2S1CKSELR; /*!< RCC SPI/I2S1 Kernel Clock Selection Register Address offset: 0x8D8 */
__IO uint32_t SPI2S23CKSELR; /*!< RCC SPI/I2S2,3 Kernel Clock Selection Register Address offset: 0x8DC */
__IO uint32_t SPI45CKSELR; /*!< RCC SPI4,5 Kernel Clock Selection Register Address offset: 0x8E0 */
__IO uint32_t UART6CKSELR; /*!< RCC USART6 Kernel Clock Selection Register Address offset: 0x8E4 */
__IO uint32_t UART24CKSELR; /*!< RCC UART2,4 Kernel Clock Selection Register Address offset: 0x8E8 */
__IO uint32_t UART35CKSELR; /*!< RCC UART3,5 Kernel Clock Selection Register Address offset: 0x8EC */
__IO uint32_t UART78CKSELR; /*!< RCC UART7,8 Kernel Clock Selection Register Address offset: 0x8F0 */
__IO uint32_t SDMMC12CKSELR; /*!< RCC SDMMC1&2 Kernel Clock Selection Register Address offset: 0x8F4 */
__IO uint32_t SDMMC3CKSELR; /*!< RCC SDMMC3 Kernel Clock Selection Register Address offset: 0x8F8 */
__IO uint32_t ETHCKSELR; /*!< RCC Ethernet Kernel Clock Selection Register Address offset: 0x8FC */
__IO uint32_t QSPICKSELR; /*!< RCC QUADSPI Kernel Clock Selection Register Address offset: 0x900 */
__IO uint32_t FMCCKSELR; /*!< RCC FMC Kernel Clock Selection Register Address offset: 0x904 */
uint32_t RESERVED18; /*!< Reserved, Address offset: 0x908 */
__IO uint32_t FDCANCKSELR; /*!< RCC FDCAN Kernel Clock Selection Register Address offset: 0x90C */
uint32_t RESERVED19; /*!< Reserved, Address offset: 0x910 */
__IO uint32_t SPDIFCKSELR; /*!< RCC SPDIF Kernel Clock Selection Register Address offset: 0x914 */
__IO uint32_t CECCKSELR; /*!< RCC CEC Kernel Clock Selection Register Address offset: 0x918 */
__IO uint32_t USBCKSELR; /*!< RCC USB Kernel Clock Selection Register Address offset: 0x91C */
__IO uint32_t RNG2CKSELR; /*!< RCC RNG2 Kernel Clock Selection Register Address offset: 0x920 */
__IO uint32_t DSICKSELR; /*!< RCC DSI Kernel Clock Selection Register Address offset: 0x924 */
__IO uint32_t ADCCKSELR; /*!< RCC ADC Kernel Clock Selection Register Address offset: 0x928 */
__IO uint32_t LPTIM45CKSELR; /*!< RCC LPTIM4&5 Kernel Clock Selection Register Address offset: 0x92C */
__IO uint32_t LPTIM23CKSELR; /*!< RCC LPTIM2&3 Kernel Clock Selection Register Address offset: 0x930 */
__IO uint32_t LPTIM1CKSELR; /*!< RCC LPTIM1 Kernel Clock Selection Register Address offset: 0x934 */
uint32_t RESERVED20[18]; /*!< Reserved, 0x938-0x97C Address offset: 0x938 */
__IO uint32_t APB1RSTSETR; /*!< RCC APB1 Peripheral Reset Set Register Address offset: 0x980 */
__IO uint32_t APB1RSTCLRR; /*!< RCC APB1 Peripheral Reset Clear Register Address offset: 0x984 */
__IO uint32_t APB2RSTSETR; /*!< RCC APB2 Peripheral Reset Set Register Address offset: 0x988 */
__IO uint32_t APB2RSTCLRR; /*!< RCC APB2 Peripheral Reset Clear Register Address offset: 0x98C */
__IO uint32_t APB3RSTSETR; /*!< RCC APB3 Peripheral Reset Set Register Address offset: 0x990 */
__IO uint32_t APB3RSTCLRR; /*!< RCC APB3 Peripheral Reset Clear Register Address offset: 0x994 */
__IO uint32_t AHB2RSTSETR; /*!< RCC AHB2 Peripheral Reset Set Register Address offset: 0x998 */
__IO uint32_t AHB2RSTCLRR; /*!< RCC AHB2 Peripheral Reset Clear Register Address offset: 0x99C */
__IO uint32_t AHB3RSTSETR; /*!< RCC AHB3 Peripheral Reset Set Register Address offset: 0x9A0 */
__IO uint32_t AHB3RSTCLRR; /*!< RCC AHB3 Peripheral Reset Clear Register Address offset: 0x9A4 */
__IO uint32_t AHB4RSTSETR; /*!< RCC AHB4 Peripheral Reset Set Register Address offset: 0x9A8 */
__IO uint32_t AHB4RSTCLRR; /*!< RCC AHB4 Peripheral Reset Clear Register Address offset: 0x9AC */
uint32_t RESERVED21[20]; /*!< Reserved, 0x9B0-0x9FC Address offset: 0x9B0 */
__IO uint32_t MP_APB1ENSETR; /*!< RCC APB1 Peripheral Enable For MPU Set Register Address offset: 0xA00 */
__IO uint32_t MP_APB1ENCLRR; /*!< RCC APB1 Peripheral Enable For MPU Clear Register Address offset: 0xA04 */
__IO uint32_t MP_APB2ENSETR; /*!< RCC APB2 Peripheral Enable For MPU Set Register Address offset: 0xA08 */
__IO uint32_t MP_APB2ENCLRR; /*!< RCC APB2 Peripheral Enable For MPU Clear Register Address offset: 0xA0C */
__IO uint32_t MP_APB3ENSETR; /*!< RCC APB3 Peripheral Enable For MPU Set Register Address offset: 0xA10 */
__IO uint32_t MP_APB3ENCLRR; /*!< RCC APB3 Peripheral Enable For MPU Clear Register Address offset: 0xA14 */
__IO uint32_t MP_AHB2ENSETR; /*!< RCC AHB2 Peripheral Enable For MPU Set Register Address offset: 0xA18 */
__IO uint32_t MP_AHB2ENCLRR; /*!< RCC AHB2 Peripheral Enable For MPU Clear Register Address offset: 0xA1C */
__IO uint32_t MP_AHB3ENSETR; /*!< RCC AHB3 Peripheral Enable For MPU Set Register Address offset: 0xA20 */
__IO uint32_t MP_AHB3ENCLRR; /*!< RCC AHB3 Peripheral Enable For MPU Clear Register Address offset: 0xA24 */
__IO uint32_t MP_AHB4ENSETR; /*!< RCC AHB4 Peripheral Enable For MPU Set Register Address offset: 0xA28 */
__IO uint32_t MP_AHB4ENCLRR; /*!< RCC AHB4 Peripheral Enable For MPU Clear Register Address offset: 0xA2C */
uint32_t RESERVED22[2]; /*!< Reserved, 0xA30-0xA34 Address offset: 0xA30 */
__IO uint32_t MP_MLAHBENSETR; /*!< RCC MLAHB Periph. Enable For MPU Set Register Address offset: 0xA38 */
__IO uint32_t MP_MLAHBENCLRR; /*!< RCC MLAHB Periph. Enable For MPU Clear Register Address offset: 0xA3C */
uint32_t RESERVED23[16]; /*!< Reserved, 0x940-0xA7C Address offset: 0x940 */
__IO uint32_t MC_APB1ENSETR; /*!< RCC APB1 Peripheral Enable For MCU Set Register Address offset: 0xA80 */
__IO uint32_t MC_APB1ENCLRR; /*!< RCC APB1 Peripheral Enable For MCU Clear Register Address offset: 0xA84 */
__IO uint32_t MC_APB2ENSETR; /*!< RCC APB2 Peripheral Enable For MCU Set Register Address offset: 0xA88 */
__IO uint32_t MC_APB2ENCLRR; /*!< RCC APB2 Peripheral Enable For MCU Clear Register Address offset: 0xA8C */
__IO uint32_t MC_APB3ENSETR; /*!< RCC APB3 Peripheral Enable For MCU Set Register Address offset: 0xA90 */
__IO uint32_t MC_APB3ENCLRR; /*!< RCC APB3 Peripheral Enable For MCU Clear Register Address offset: 0xA94 */
__IO uint32_t MC_AHB2ENSETR; /*!< RCC AHB2 Peripheral Enable For MCU Set Register Address offset: 0xA98 */
__IO uint32_t MC_AHB2ENCLRR; /*!< RCC AHB2 Peripheral Enable For MCU Clear Register Address offset: 0xA9C */
__IO uint32_t MC_AHB3ENSETR; /*!< RCC AHB3 Peripheral Enable For MCU Set Register Address offset: 0xAA0 */
__IO uint32_t MC_AHB3ENCLRR; /*!< RCC AHB3 Peripheral Enable For MCU Clear Register Address offset: 0xAA4 */
__IO uint32_t MC_AHB4ENSETR; /*!< RCC AHB4 Peripheral Enable For MCU Set Register Address offset: 0xAA8 */
__IO uint32_t MC_AHB4ENCLRR; /*!< RCC AHB4 Peripheral Enable For MCU Clear Register Address offset: 0xAAC */
__IO uint32_t MC_AXIMENSETR; /*!< RCC AXI Periph. Enable For MCU Set Register Address offset: 0xAB0 */
__IO uint32_t MC_AXIMENCLRR; /*!< RCC AXI Periph. Enable For MCU Clear Register Address offset: 0xAB4 */
__IO uint32_t MC_MLAHBENSETR; /*!< RCC MLAHB Periph. Enable For MCU Set Register Address offset: 0xAB8 */
__IO uint32_t MC_MLAHBENCLRR; /*!< RCC MLAHB Periph. Enable For MCU Clear Register Address offset: 0xABC */
uint32_t RESERVED24[16]; /*!< Reserved, 0xAC0-0xAFC Address offset: 0xAC0 */
__IO uint32_t MP_APB1LPENSETR; /*!< RCC APB1 Sleep Clock Ena. For MPU Set Register Address offset: 0xB00 */
__IO uint32_t MP_APB1LPENCLRR; /*!< RCC APB1 Sleep Clock Ena. For MPU Clear Register Address offset: 0xB04 */
__IO uint32_t MP_APB2LPENSETR; /*!< RCC APB2 Sleep Clock Ena. For MPU Set Register Address offset: 0xB08 */
__IO uint32_t MP_APB2LPENCLRR; /*!< RCC APB2 Sleep Clock Ena. For MPU Clear Register Address offset: 0xB0C */
__IO uint32_t MP_APB3LPENSETR; /*!< RCC APB3 Sleep Clock Ena. For MPU Set Register Address offset: 0xB10 */
__IO uint32_t MP_APB3LPENCLRR; /*!< RCC APB3 Sleep Clock Ena. For MPU Clear Register Address offset: 0xB14 */
__IO uint32_t MP_AHB2LPENSETR; /*!< RCC AHB2 Sleep Clock Ena. For MPU Set Register Address offset: 0xB18 */
__IO uint32_t MP_AHB2LPENCLRR; /*!< RCC AHB2 Sleep Clock Ena. For MPU Clear Register Address offset: 0xB1C */
__IO uint32_t MP_AHB3LPENSETR; /*!< RCC AHB3 Sleep Clock Ena. For MPU Set Register Address offset: 0xB20 */
__IO uint32_t MP_AHB3LPENCLRR; /*!< RCC AHB3 Sleep Clock Ena. For MPU Clear Register Address offset: 0xB24 */
__IO uint32_t MP_AHB4LPENSETR; /*!< RCC AHB4 Sleep Clock Ena. For MPU Set Register Address offset: 0xB28 */
__IO uint32_t MP_AHB4LPENCLRR; /*!< RCC AHB4 Sleep Clock Ena. For MPU Clear Register Address offset: 0xB2C */
__IO uint32_t MP_AXIMLPENSETR; /*!< RCC AXI Sleep Clock Ena. For MPU Set Register Address offset: 0xB30 */
__IO uint32_t MP_AXIMLPENCLRR; /*!< RCC AXI Sleep Clock Ena. For MPU Clear Register Address offset: 0xB34 */
__IO uint32_t MP_MLAHBLPENSETR; /*!< RCC MLAHB Sleep Clock Ena. For MPU Set Register Address offset: 0xB38 */
__IO uint32_t MP_MLAHBLPENCLRR; /*!< RCC MLAHB Sleep Clock Ena. For MPU Clear Register Address offset: 0xB3C */
uint32_t RESERVED25[16]; /*!< Reserved, 0xB40-0xB7C Address offset: 0xB40 */
__IO uint32_t MC_APB1LPENSETR; /*!< RCC APB1 Sleep Clock Ena. For MCU Set Register Address offset: 0xB80 */
__IO uint32_t MC_APB1LPENCLRR; /*!< RCC APB1 Sleep Clock Ena. For MCU Clear Register Address offset: 0xB84 */
__IO uint32_t MC_APB2LPENSETR; /*!< RCC APB2 Sleep Clock Ena. For MCU Set Register Address offset: 0xB88 */
__IO uint32_t MC_APB2LPENCLRR; /*!< RCC APB2 Sleep Clock Ena. For MCU Clear Register Address offset: 0xB8C */
__IO uint32_t MC_APB3LPENSETR; /*!< RCC APB3 Sleep Clock Ena. For MCU Set Register Address offset: 0xB90 */
__IO uint32_t MC_APB3LPENCLRR; /*!< RCC APB3 Sleep Clock Ena. For MCU Clear Register Address offset: 0xB94 */
__IO uint32_t MC_AHB2LPENSETR; /*!< RCC AHB2 Sleep Clock Ena. For MCU Set Register Address offset: 0xB98 */
__IO uint32_t MC_AHB2LPENCLRR; /*!< RCC AHB2 Sleep Clock Ena. For MCU Clear Register Address offset: 0xB9C */
__IO uint32_t MC_AHB3LPENSETR; /*!< RCC AHB3 Sleep Clock Ena. For MCU Set Register Address offset: 0xBA0 */
__IO uint32_t MC_AHB3LPENCLRR; /*!< RCC AHB3 Sleep Clock Ena. For MCU Clear Register Address offset: 0xBA4 */
__IO uint32_t MC_AHB4LPENSETR; /*!< RCC AHB4 Sleep Clock Ena. For MCU Set Register Address offset: 0xBA8 */
__IO uint32_t MC_AHB4LPENCLRR; /*!< RCC AHB4 Sleep Clock Ena. For MCU Clear Register Address offset: 0xBAC */
__IO uint32_t MC_AXIMLPENSETR; /*!< RCC AXI Sleep Clock Ena. For MCU Set Register Address offset: 0xBB0 */
__IO uint32_t MC_AXIMLPENCLRR; /*!< RCC AXI Sleep Clock Ena. For MCU Clear Register Address offset: 0xBB4 */
__IO uint32_t MC_MLAHBLPENSETR; /*!< RCC MLAHB Sleep Clock Ena. For MCU Set Register Address offset: 0xBB8 */
__IO uint32_t MC_MLAHBLPENCLRR; /*!< RCC MLAHB Sleep Clock Ena. For MCU Clear Register Address offset: 0xBBC */
uint32_t RESERVED26[16]; /*!< Reserved, 0xBC0-0xBFC Address offset: 0xBC0 */
__IO uint32_t MC_RSTSCLRR; /*!< RCC MCU Reset Status Clear Register Address offset: 0xC00 */
uint32_t RESERVED27[4]; /*!< Reserved, 0xC04-0xC10 Address offset: 0xC04 */
__IO uint32_t MC_CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0xC14 */
__IO uint32_t MC_CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0xC18 */
uint32_t RESERVED28[246]; /*!< Reserved, 0xC1C-0xFF0 Address offset: 0xC1C */
__IO uint32_t VERR; /*!< RCC Version register Address offset: 0xFF4 */
__IO uint32_t IPIDR; /*!< RCC ID register Address offset: 0xFF8 */
__IO uint32_t SIDR; /*!< Size ID register Address offset: 0xFFC */
} RCC_TypeDef;
/**
* @brief Hardware Debug Port
*/
typedef struct
{
__IO uint32_t HDP_CTRL; /*!< HDP Control Register, Address offset: 0x00 */
__IO uint32_t HDP_MUX; /*!< HDP Multiplexers Control Register, Address offset: 0x04 */
uint32_t RESERVED0[2]; /*!< Reserved, 0x08-0x0C Address offset: 0x08 */
__IO uint32_t HDP_VAL; /*!< HDP Read Back Value Register, Address offset: 0x10 */
__IO uint32_t HDP_GPOSET; /*!< HDP General Purpose Output Set Register, Address offset: 0x14 */
__IO uint32_t HDP_GPOCLR; /*!< HDP General Purpose Output Clear Register, Address offset: 0x18 */
__IO uint32_t HDP_GPOVAL; /*!< HDP General Purpose Output Value Register, Address offset: 0x1C */
uint32_t RESERVED1[245]; /*!< Reserved, 0x20-0x3F4 Address offset: 0x20 */
__IO uint32_t VERR; /*!< HDP Version Register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< HDP IP Identification Register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< HDP Size Identification register, Address offset: 0x3FC */
} HDP_TypeDef;
/**
* @brief Boot and Security and OTP Control
*/
typedef struct
{
__IO uint32_t BSEC_OTP_CONFIG; /*!< BSEC OTP Configuration, Address offset: 0x00 */
__IO uint32_t BSEC_OTP_CONTROL; /*!< BSEC OTP Control, Address offset: 0x04 */
__IO uint32_t BSEC_OTP_WRDATA; /*!< BSEC OTP Write Data, Address offset: 0x08 */
__IO uint32_t BSEC_OTP_STATUS; /*!< BSEC OTP Status, Address offset: 0x0C */
__IO uint32_t BSEC_OTP_LOCK; /*!< BSEC OTP Configuration, Address offset: 0x10 */
__IO uint32_t BSEC_DENABLE; /*!< BSEC Debug Configuration, Address offset: 0x14 */
__IO uint32_t BSEC_FENABLE; /*!< BSEC Feature Configuration, Address offset: 0x18 */
__IO uint32_t BSEC_OTP_DISTURBED0; /*!< BSEC OTP Disturbed Status, Address offset: 0x1C */
__IO uint32_t BSEC_OTP_DISTURBED1; /*!< BSEC OTP Disturbed Status, Address offset: 0x20 */
__IO uint32_t BSEC_OTP_DISTURBED2; /*!< BSEC OTP Disturbed Status, Address offset: 0x24 */
uint32_t RESERVED0x28; /*!< Reserved, Address offset: 0x28 */
uint32_t RESERVED0x2C; /*!< Reserved, Address offset: 0x2C */
uint32_t RESERVED0x30; /*!< Reserved, Address offset: 0x30 */
__IO uint32_t BSEC_OTP_ERROR0; /*!< BSEC OTP Error Status, Address offset: 0x34 */
__IO uint32_t BSEC_OTP_ERROR1; /*!< BSEC OTP Error Status, Address offset: 0x38 */
__IO uint32_t BSEC_OTP_ERROR2; /*!< BSEC OTP Error Status, Address offset: 0x3C */
uint32_t RESERVED0x40; /*!< Reserved, Address offset: 0x40 */
uint32_t RESERVED0x44; /*!< Reserved, Address offset: 0x44 */
uint32_t RESERVED0x48; /*!< Reserved, Address offset: 0x48 */
__IO uint32_t BSEC_OTP_WRLOCK0; /*!< BSEC OTP Lock status, Address offset: 0x4C */
__IO uint32_t BSEC_OTP_WRLOCK1; /*!< BSEC OTP Lock status, Address offset: 0x50 */
__IO uint32_t BSEC_OTP_WRLOCK2; /*!< BSEC OTP Lock status, Address offset: 0x54 */
uint32_t RESERVED0x58; /*!< Reserved, Address offset: 0x58 */
uint32_t RESERVED0x5C; /*!< Reserved, Address offset: 0x5C */
uint32_t RESERVED0x60; /*!< Reserved, Address offset: 0x60 */
__IO uint32_t BSEC_OTP_SPLOCK0; /*!< BSEC OTP prg lock under ctrl by stick bits, Address offset: 0x64 */
__IO uint32_t BSEC_OTP_SPLOCK1; /*!< BSEC OTP prg lock under ctrl by stick bits, Address offset: 0x68 */
__IO uint32_t BSEC_OTP_SPLOCK2; /*!< BSEC OTP prg lock under ctrl by stick bits, Address offset: 0x6C */
uint32_t RESERVED0x70; /*!< Reserved, Address offset: 0x70 */
uint32_t RESERVED0x74; /*!< Reserved, Address offset: 0x74 */
uint32_t RESERVED0x78; /*!< Reserved, Address offset: 0x78 */
__IO uint32_t BSEC_OTP_SWLOCK0; /*!< BSEC OTP Shadow Write Lck under ctrl by sticky bits, Address offset: 0x7C */
__IO uint32_t BSEC_OTP_SWLOCK1; /*!< BSEC OTP Shadow Write Lck under ctrl by sticky bits, Address offset: 0x80 */
__IO uint32_t BSEC_OTP_SWLOCK2; /*!< BSEC OTP Shadow Write Lck under ctrl by sticky bits, Address offset: 0x84 */
uint32_t RESERVED0x88; /*!< Reserved, Address offset: 0x88 */
uint32_t RESERVED0x8C; /*!< Reserved, Address offset: 0x8C */
uint32_t RESERVED0x90; /*!< Reserved, Address offset: 0x90 */
__IO uint32_t BSEC_OTP_SRLOCK0; /*!< BSEC OTP Shadow read lock under ctrl by sticky bits, Address offset: 0x94 */
__IO uint32_t BSEC_OTP_SRLOCK1; /*!< BSEC OTP Shadow read lock under ctrl by sticky bits, Address offset: 0x98 */
__IO uint32_t BSEC_OTP_SRLOCK2; /*!< BSEC OTP Shadow read lock under ctrl by sticky bits, Address offset: 0x9C */
uint32_t RESERVED0xA0; /*!< Reserved, Address offset: 0xA0 */
uint32_t RESERVED0xA4; /*!< Reserved, Address offset: 0xA4 */
uint32_t RESERVED0xA8; /*!< Reserved, Address offset: 0xA8 */
__IO uint32_t BSEC_JTAGIN; /*!< BSEC JTAG Input, Address offset: 0xAC */
__IO uint32_t BSEC_JTAGOUT; /*!< BSEC JTAG Output, Address offset: 0xB0 */
__IO uint32_t BSEC_SCRATCH; /*!< BSEC SCRATCH, Address offset: 0xB4 */
uint32_t RESERVED0xB8[82]; /*!< Reserved, 0x0B8-0x200 Address offset: 0xB8 */
__IO uint32_t BSEC_OTP_DATA[96]; /*!< BSEC Shadow Registers, Address offset: 0x200 */
uint32_t RESERVED0x380[796]; /*!< Reserved, 0x0380-0xFF0 Address offset: 0x380 */
__IO uint32_t HWCFGR; /*!< BSEC IP HW Configuration Register, Address offset: 0xFF0 */
__IO uint32_t VERR; /*!< BSEC IP version Register, Address offset: 0xFF4 */
__IO uint32_t IPIDR; /*!< BSEC ID Register, Address offset: 0xFF8 */
__IO uint32_t SIDR; /*!< BSEC SID Register, Address offset: 0xFFC */
} BSEC_TypeDef;
/**
* @brief RTC Specific device feature definitions
*/
#define RTC_BACKUP_NB 32u /* Backup registers implemented */
#define RTC_TAMP_NB 3u /* External tamper events (input pins) supported */
/**
* @brief Real-Time Clock
*/
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
__IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
__IO uint32_t SSR; /*!< RTC sub-second register, Address offset: 0x08 */
__IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
__IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
__IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
__IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
uint32_t RESERVED; /*!< Reserved */
__IO uint32_t SMCR; /*!< RTC secure mode control register, Address offset: 0x20 */
__IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
__IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
__IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
__IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
__IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
__IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */
uint32_t RESERVED1; /*!< Reserved */
__IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
__IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
__IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
__IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
__IO uint32_t SR; /*!< RTC status register, Address offset: 0x50 */
__IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */
__IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */
__IO uint32_t SCR; /*!< RTC status clear register, Address offset: 0x5C */
__IO uint32_t CFGR; /*!< RTC Configuration register, Address offset: 0x60 */
uint32_t RESERVED2[227]; /*!< Reserved */
__IO uint32_t HWCFGR; /*!< RTC hardware configuration register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< RTC version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< RTC identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< RTC size identification register, Address offset: 0x3FC */
} RTC_TypeDef;
/**
* @brief Tamper and Backup registers
*/
typedef struct
{
__IO uint32_t CR1; /*!< TAMP tamper control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TAMP tamper control register 2, Address offset: 0x04 */
uint32_t RESERVED; /*!< Reserved */
__IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */
__IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */
__IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */
__IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved */
__IO uint32_t SMCR; /*!< TAMP secure mode control register, Address offset: 0x20 */
uint32_t RESERVED2[2]; /*!< Reserved, 0x024 - 0x028 */
__IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */
__IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */
__IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */
__IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */
__IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */
__IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */
uint32_t RESERVED3[3]; /*!< Reserved, 0x044 - 0x04C */
__IO uint32_t CFGR; /*!< TAMP Configuration register, Address offset: 0x50 */
uint32_t RESERVED4[43]; /*!< Reserved, 0x054 - 0x0FC */
__IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
__IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
__IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
__IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
__IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
__IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */
__IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */
__IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */
__IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */
__IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */
__IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */
__IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */
__IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */
__IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */
__IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */
__IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */
__IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */
__IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */
__IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */
__IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */
__IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */
__IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */
__IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */
__IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */
__IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */
__IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */
__IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */
__IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */
__IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */
__IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */
__IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */
__IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */
uint32_t RESERVED5[155]; /*!< Reserved, 0x180 - 0x3E8 */
__IO uint32_t HWCFGR2; /*!< TAMP hardware configuration register, Address offset: 0x3EC */
__IO uint32_t HWCFGR1; /*!< TAMP hardware configuration register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< TAMP version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< TAMP identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< TAMP size identification register, Address offset: 0x3FC */
} TAMP_TypeDef;
/**
* @brief Serial Audio Interface
*/
typedef struct
{
__IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
__IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
__IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
uint32_t RESERVED1[233]; /*!< Reserved, 0x4C - 0x3EC */
__IO uint32_t HWCFGR; /*!< SAI HW Configuration register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< SAI PVersion register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< SAI Identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< SAI Size Identification register, Address offset: 0x3FC */
} SAI_TypeDef;
typedef struct
{
__IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
__IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
__IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
__IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
__IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
__IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
__IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
__IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
} SAI_Block_TypeDef;
/**
* @brief Process Monitor Block
*/
typedef struct
{
uint32_t Reserved; /*!< Reserved, Address offset: 0x00 */
__IO uint32_t SENS_CTRL; /*!< PMB Sensor control, Address offset: 0x04 */
__IO uint32_t REF_COUNTER; /*!< PMB Reference counter, Address offset: 0x08 */
__IO uint32_t SENSOR_STATUS; /*!< PMB Sensor Status, Address offset: 0x0C */
}PMB_TypeDef;
/**
* @brief SPDIF-RX Interface
*/
typedef struct
{
__IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
__IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
__IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
__IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
__IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
__IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
__IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
uint32_t RESERVED2[246]; /*!< Reserved, 0x1C - 0x3F0 */
__IO uint32_t VERR; /*!< SPDIFRX version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< SPDIFRX Identificationn register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< SPDIFRX Size Identification register, Address offset: 0x3FC */
} SPDIFRX_TypeDef;
/**
* @brief Secure digital input/output Interface
*/
typedef struct
{
__IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
__IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
__IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
__IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
__I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
__I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
__I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
__I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
__I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
__IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
__IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
__IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
__I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
__I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
__IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
__IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
__IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
__IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
__IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
__IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
__IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
uint32_t RESERVED1[1]; /*!< Reserved, 0x60 */
__IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */
__IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register, Address offset: 0x68 */
uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */
__IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 - 0xBC */
uint32_t RESERVED3[220]; /*!< Reserved, 0xBC-0x3F4 */
__IO uint32_t VERR; /*!< SDMMC version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< SDMMC identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< SDMMCsize ID register, Address offset: 0x3FC */
} SDMMC_TypeDef;
/**
* @brief Delay Block DLYB
*/
typedef struct
{
__IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */
__IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */
uint32_t Reserved[249]; /* Reserved Address offset: 0x08 - 0x3F0 */
__IO uint32_t VERR; /*!< DELAY BLOCK Version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< DELAY BLOCK Identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< DELAY BLOCK Size ID register, Address offset: 0x3FC */
} DLYB_TypeDef;
/**
* @brief HW Semaphore HSEM
*/
typedef struct
{
__IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */
__IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */
__IO uint32_t C1IER; /*!< HSEM Interrupt 0 enable register , Address offset: 100h */
__IO uint32_t C1ICR; /*!< HSEM Interrupt 0 clear register , Address offset: 104h */
__IO uint32_t C1ISR; /*!< HSEM Interrupt 0 Status register , Address offset: 108h */
__IO uint32_t C1MISR; /*!< HSEM Interrupt 0 Masked Status register , Address offset: 10Ch */
__IO uint32_t C2IER; /*!< HSEM Interrupt 1 enable register , Address offset: 110h */
__IO uint32_t C2ICR; /*!< HSEM Interrupt 1 clear register , Address offset: 114h */
__IO uint32_t C2ISR; /*!< HSEM Interrupt 1 Status register , Address offset: 118h */
__IO uint32_t C2MISR; /*!< HSEM Interrupt 1 Masked Status register , Address offset: 11Ch */
uint32_t Reserved[8]; /* Reserved Address offset: 120h-13Ch*/
__IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */
__IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */
uint32_t Reserved1[169]; /* Reserved Address offset: 148h-3E8h */
__IO uint32_t HWCFGR2; /*!< HSEM Hardware Configuration Register 2 , Address offset: 3ECh */
__IO uint32_t HWCFGR1; /*!< HSEM Hardware Configuration Register 1 , Address offset: 3F0h */
__IO uint32_t VERR; /*!< HSEM IP Version Register , Address offset: 3F4h */
__IO uint32_t IPIDR; /*!< HSEM IP Identification Register , Address offset: 3F8h */
__IO uint32_t SIDR; /*!< HSEM Size Identification Register , Address offset: 3FCh */
} HSEM_TypeDef;
typedef struct
{
__IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */
__IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */
__IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */
__IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */
} HSEM_Common_TypeDef;
/**
* @brief Serial Peripheral Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
__IO uint32_t CFG1; /*!< SPI Status register, Address offset: 0x08 */
__IO uint32_t CFG2; /*!< SPI Status register, Address offset: 0x0C */
__IO uint32_t IER; /*!< SPI data register, Address offset: 0x10 */
__IO uint32_t SR; /*!< SPI data register, Address offset: 0x14 */
__IO uint32_t IFCR; /*!< SPI data register, Address offset: 0x18 */
uint32_t RESERVED0; /*!< SPI data register, Address offset: 0x1C */
__IO uint32_t TXDR; /*!< SPI data register, Address offset: 0x20 */
uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */
__IO uint32_t RXDR; /*!< SPI data register, Address offset: 0x30 */
uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
__IO uint32_t CRCPOLY; /*!< SPI data register, Address offset: 0x40 */
__IO uint32_t TXCRC; /*!< SPI data register, Address offset: 0x44 */
__IO uint32_t RXCRC; /*!< SPI data register, Address offset: 0x48 */
__IO uint32_t UDRDR; /*!< SPI data register, Address offset: 0x4C */
__IO uint32_t I2SCFGR; /*!< SPI data register, Address offset: 0x50 */
uint32_t RESERVED3[231]; /*!< Reserved, 0x54-0x3EC */
__IO uint32_t HWCFGR; /*!< SPI HW Configuration register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< SPI Version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< SPI identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< SPI Size Identification register, Address offset: 0x3FC */
} SPI_TypeDef;
/**
* @brief QUAD Serial Peripheral Interface
*/
typedef struct
{
__IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
__IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
__IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
__IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
__IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
__IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
__IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
__IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
__IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
__IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
__IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
__IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
uint32_t RESERVED[239]; /*!< Reserved, 0x34-0x3EC */
__IO uint32_t HWCFGR; /*!< QUADSPI HW configuration register, Address offset: 0x3F0*/
__IO uint32_t VERR; /*!< QUADSPI version register, Address offset: 0x3F4*/
__IO uint32_t IPIDR; /*!< QUADSPI dentification register, Address offset: 0x3F8*/
__IO uint32_t SIDR; /*!< QUADSPI size identification register, Address offset: 0x3FC*/
} QUADSPI_TypeDef;
/**
* @brief Temperature Sensor
*/
/* TMPSENS has been renamed in DTS*/
typedef struct
{
__IO uint32_t CFGR1; /*!< Temperature Sensor Configuration Register 1, Address offset: 0x00 */
uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */
__IO uint32_t T0VALR1; /*!< Temperature sensor T0 Value Register 1, Address offset: 0x08 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */
__IO uint32_t RAMPVALR; /*!< Temperature sensor Ramp Value Register, Address offset: 0x10 */
__IO uint32_t ITR1; /*!< Temperature sensor Interrupt Threshold Register 1, Address offset: 0x14 */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
__IO uint32_t DR; /*!< Temperature sensor Data Register, Address offset: 0x1C */
__IO uint32_t SR; /*!< Temperature sensor Status Register, Address offset: 0x20 */
__IO uint32_t ITENR; /*!< Temperature sensor Interrupt Enable Register, Address offset: 0x24 */
__IO uint32_t ICIFR; /*!< Temperature sensor clear interrupt flag register, Address offset: 0x28 */
__IO uint32_t OR; /*!< Temperature sensor option register, Address offset: 0x2C */
}DTS_TypeDef;
/**
* @brief TIM
*/
typedef struct
{
__IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
__IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
__IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
__IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
__IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
__IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
__IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
__IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
__IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
__IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
__IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
uint32_t RESERVED0; /*!< Reserved, Address offset: 0x50 */
__IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
__IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
__IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
__IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
__IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
__IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
uint32_t RESERVED1[226]; /*!< Reserved, Address offset: 0x6C-0x3F0 */
__IO uint32_t VERR; /*!< TIM version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< TIM Identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< TIM Size Identification register, Address offset: 0x3FC */
} TIM_TypeDef;
/**
* @brief LPTIMIMER
*/
typedef struct
{
__IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
__IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
__IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
__IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
__IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
__IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
__IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
uint16_t RESERVED1; /*!< Reserved, 0x20 */
__IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */
uint32_t RESERVED2[242]; /*!< Reserved, 0x28-0x3EC */
__IO uint32_t HWCFGR; /*!< LPTIM HW configuration register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< LPTIM version register, Address offset: 0x3F4 */
__IO uint32_t PIDR; /*!< LPTIM Identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< LPTIM Size Identification register, Address offset: 0x3FC */
} LPTIM_TypeDef;
/**
* @brief Comparator
*/
typedef struct
{
__IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */
__IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */
__IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */
} COMPOPT_TypeDef;
typedef struct
{
__IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */
} COMP_TypeDef;
typedef struct
{
__IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
} COMP_Common_TypeDef;
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
typedef struct
{
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
__IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
uint16_t RESERVED2; /*!< Reserved, 0x12 */
__IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
__IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
uint16_t RESERVED3; /*!< Reserved, 0x1A */
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
__IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
uint16_t RESERVED4; /*!< Reserved, 0x26 */
__IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
uint16_t RESERVED5; /*!< Reserved, 0x2A */
__IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */
uint32_t RESERVED6[239]; /*!< Reserved, 0x30 - 0x3E8 */
__IO uint32_t HWCFGR2; /*!< USART Configuration2 register, Address offset: 0x3EC */
__IO uint32_t HWCFGR1; /*!< USART Configuration1 register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< USART Version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< USART Identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< USART clock Size Identification register, Address offset: 0x3FC */
} USART_TypeDef;
/**
* @brief Single Wire Protocol Master Interface SPWMI
*/
typedef struct
{
__IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
__IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
uint32_t RESERVED1; /*!< Reserved, 0x08 */
__IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
__IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
__IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
__IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
__IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
__IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
__IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
} SWPMI_TypeDef;
/**
* @brief Window WATCHDOG
*/
typedef struct
{
__IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
uint32_t RESERVED1[249]; /*!< Reserved, 0x0C - 0x3EC */
__IO uint32_t HWCFGR; /*!< WWDG HW Config register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< WWDG Version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< WWDG Identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< WWDG Size ID register, Address offset: 0x3FC */
} WWDG_TypeDef;
/**
* @brief Crypto Processor
*/
typedef struct
{
__IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
__IO uint32_t DIN; /*!< CRYP data input register, Address offset: 0x08 */
__IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
__IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
__IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
__IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
__IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
__IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
__IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
__IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
__IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
__IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
__IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
__IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
__IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
__IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
__IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
__IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
__IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
__IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
__IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
__IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
__IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
__IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
__IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
__IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
__IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
__IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
__IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
__IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
__IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
__IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
__IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
__IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
__IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
uint32_t RESERVED[216];
__IO uint32_t HWCFGR; /*!< CRYP HW Configuration, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< CRYP version register , Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< CRYP Identification register, Address offset: 0x3F8 */
__IO uint32_t MID; /*!< CRYP HW Magic ID register, Address offset: 0x3FC */
} CRYP_TypeDef;
/**
* @brief HASH
*/
typedef struct
{
__IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
__IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
__IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
__IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
__IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
__IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
__IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
uint32_t RESERVED2[80];
__IO uint32_t HR2[8];
uint32_t RESERVED3[48];
__IO uint32_t HWCFGR; /*!< HASH Hardware configuration register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< HASH Version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< HASH identification register, Address offset: 0x3F8 */
__IO uint32_t MID; /*!< HASH Hardware Magic ID register, Address offset: 0x3FC */
} HASH_TypeDef;
/**
* @brief HASH_DIGEST
*/
typedef struct
{
__IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
} HASH_DIGEST_TypeDef;
/**
* @brief RNG
*/
typedef struct
{
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
__IO uint32_t RESERVED1[249]; /*!< Reserved 0x0C - 0x3EC */
__IO uint32_t HWCFGR; /*!< RNG HW Configuration register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< RNG Version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< RNG identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< RNG HW magic ID, Address offset: 0x3FC */
} RNG_TypeDef;
/**
* @brief Inter-Processor Communication
*/
typedef struct
{
__IO uint32_t C1CR; /*!< Inter-Processor Communication: C1 control register, Address offset: 0x000 */
__IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, Address offset: 0x004 */
__IO uint32_t C1SCR; /*!< Inter-Processor Communication: C1 status set clear register, Address offset: 0x008 */
__IO uint32_t C1TOC2SR; /*!< Inter-Processor Communication: C1 to processor M4 status register, Address offset: 0x00C */
__IO uint32_t C2CR; /*!< Inter-Processor Communication: C2 control register, Address offset: 0x010 */
__IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, Address offset: 0x014 */
__IO uint32_t C2SCR; /*!< Inter-Processor Communication: C2 status set clear register, Address offset: 0x018 */
__IO uint32_t C2TOC1SR; /*!< Inter-Processor Communication: C2 to processor M4 status register, Address offset: 0x01C */
__IO uint32_t RESERVED1[244]; /*!< Reserved */
__IO uint32_t HWCFGR; /*!< Inter-Processor Communication hardware configuration register, Address offset: 0x3F0 */
__IO uint32_t VER; /*!< Inter-Processor Communication version register, Address offset: 0x3F4 */
__IO uint32_t ID; /*!< Inter-Processor Communication identification register, Address offset: 0x3F8 */
__IO uint32_t SID; /*!< Inter-Processor Communication size identification register, Address offset: 0x3FC */
} IPCC_TypeDef;
typedef struct
{
__IO uint32_t CR; /*!< Control register, Address offset: 0x000 */
__IO uint32_t MR; /*!< Mask register, Address offset: 0x004 */
__IO uint32_t SCR; /*!< Status set clear register, Address offset: 0x008 */
__IO uint32_t SR; /*!< Status register, Address offset: 0x00C */
} IPCC_CommonTypeDef;
/**
* @brief MDIOS
*/
typedef struct
{
__IO uint32_t CR; /*!< Control register, Address offset: 0x000 */
__IO uint32_t WRFR; /*!< Write Flag register, Address offset: 0x004 */
__IO uint32_t CWRFR; /*!< Clear Write Flag register, Address offset: 0x008 */
__IO uint32_t RDFR; /*!< Read Flag register, Address offset: 0x00C */
__IO uint32_t CRDFR; /*!< Clear Read Flag register, Address offset: 0x010 */
__IO uint32_t SR; /*!< Status register, Address offset: 0x014 */
__IO uint32_t CLRFR; /*!< Clear Flag register, Address offset: 0x018 */
uint32_t RESERVED[57]; /*!< Reserved, Address offset: 0x01C - 0x0FC */
__IO uint32_t DINR0; /*!< Input Data register 0 Address offset: 0x100 */
__IO uint32_t DINR1; /*!< Input Data register 1 Address offset: 0x104 */
__IO uint32_t DINR2; /*!< Input Data register 2 Address offset: 0x108 */
__IO uint32_t DINR3; /*!< Input Data register 3 Address offset: 0x10C */
__IO uint32_t DINR4; /*!< Input Data register 4 Address offset: 0x110 */
__IO uint32_t DINR5; /*!< Input Data register 5 Address offset: 0x114 */
__IO uint32_t DINR6; /*!< Input Data register 6 Address offset: 0x118 */
__IO uint32_t DINR7; /*!< Input Data register 7 Address offset: 0x11C */
__IO uint32_t DINR8; /*!< Input Data register 8 Address offset: 0x120 */
__IO uint32_t DINR9; /*!< Input Data register 9 Address offset: 0x124 */
__IO uint32_t DINR10; /*!< Input Data register 10 Address offset: 0x128 */
__IO uint32_t DINR11; /*!< Input Data register 11 Address offset: 0x12C */
__IO uint32_t DINR12; /*!< Input Data register 12 Address offset: 0x130 */
__IO uint32_t DINR13; /*!< Input Data register 13 Address offset: 0x134 */
__IO uint32_t DINR14; /*!< Input Data register 14 Address offset: 0x138 */
__IO uint32_t DINR15; /*!< Input Data register 15 Address offset: 0x13C */
__IO uint32_t DINR16; /*!< Input Data register 16 Address offset: 0x140 */
__IO uint32_t DINR17; /*!< Input Data register 17 Address offset: 0x144 */
__IO uint32_t DINR18; /*!< Input Data register 18 Address offset: 0x148 */
__IO uint32_t DINR19; /*!< Input Data register 19 Address offset: 0x14C */
__IO uint32_t DINR20; /*!< Input Data register 20 Address offset: 0x150 */
__IO uint32_t DINR21; /*!< Input Data register 21 Address offset: 0x154 */
__IO uint32_t DINR22; /*!< Input Data register 22 Address offset: 0x158 */
__IO uint32_t DINR23; /*!< Input Data register 23 Address offset: 0x15C */
__IO uint32_t DINR24; /*!< Input Data register 24 Address offset: 0x160 */
__IO uint32_t DINR25; /*!< Input Data register 25 Address offset: 0x164 */
__IO uint32_t DINR26; /*!< Input Data register 26 Address offset: 0x168 */
__IO uint32_t DINR27; /*!< Input Data register 27 Address offset: 0x16C */
__IO uint32_t DINR28; /*!< Input Data register 28 Address offset: 0x170 */
__IO uint32_t DINR29; /*!< Input Data register 29 Address offset: 0x174 */
__IO uint32_t DINR30; /*!< Input Data register 30 Address offset: 0x178 */
__IO uint32_t DINR31; /*!< Input Data register 31 Address offset: 0x17C */
__IO uint32_t DOUTR0; /*!< Output Data register 0 Address offset: 0x180 */
__IO uint32_t DOUTR1; /*!< Output Data register 1 Address offset: 0x184 */
__IO uint32_t DOUTR2; /*!< Output Data register 2 Address offset: 0x188 */
__IO uint32_t DOUTR3; /*!< Output Data register 3 Address offset: 0x18C */
__IO uint32_t DOUTR4; /*!< Output Data register 4 Address offset: 0x190 */
__IO uint32_t DOUTR5; /*!< Output Data register 5 Address offset: 0x194 */
__IO uint32_t DOUTR6; /*!< Output Data register 6 Address offset: 0x198 */
__IO uint32_t DOUTR7; /*!< Output Data register 7 Address offset: 0x19C */
__IO uint32_t DOUTR8; /*!< Output Data register 8 Address offset: 0x1A0 */
__IO uint32_t DOUTR9; /*!< Output Data register 9 Address offset: 0x1A4 */
__IO uint32_t DOUTR10; /*!< Output Data register 10 Address offset: 0x1A8 */
__IO uint32_t DOUTR11; /*!< Output Data register 11 Address offset: 0x1AC */
__IO uint32_t DOUTR12; /*!< Output Data register 12 Address offset: 0x1B0 */
__IO uint32_t DOUTR13; /*!< Output Data register 13 Address offset: 0x1B4 */
__IO uint32_t DOUTR14; /*!< Output Data register 14 Address offset: 0x1B8 */
__IO uint32_t DOUTR15; /*!< Output Data register 15 Address offset: 0x1BC */
__IO uint32_t DOUTR16; /*!< Output Data register 16 Address offset: 0x1C0 */
__IO uint32_t DOUTR17; /*!< Output Data register 17 Address offset: 0x1C4 */
__IO uint32_t DOUTR18; /*!< Output Data register 18 Address offset: 0x1C8 */
__IO uint32_t DOUTR19; /*!< Output Data register 19 Address offset: 0x1CC */
__IO uint32_t DOUTR20; /*!< Output Data register 20 Address offset: 0x1D0 */
__IO uint32_t DOUTR21; /*!< Output Data register 21 Address offset: 0x1D4 */
__IO uint32_t DOUTR22; /*!< Output Data register 22 Address offset: 0x1D8 */
__IO uint32_t DOUTR23; /*!< Output Data register 23 Address offset: 0x1DC */
__IO uint32_t DOUTR24; /*!< Output Data register 24 Address offset: 0x1E0 */
__IO uint32_t DOUTR25; /*!< Output Data register 25 Address offset: 0x1E4 */
__IO uint32_t DOUTR26; /*!< Output Data register 26 Address offset: 0x1E8 */
__IO uint32_t DOUTR27; /*!< Output Data register 27 Address offset: 0x1EC */
__IO uint32_t DOUTR28; /*!< Output Data register 28 Address offset: 0x1F0 */
__IO uint32_t DOUTR29; /*!< Output Data register 29 Address offset: 0x1F4 */
__IO uint32_t DOUTR30; /*!< Output Data register 30 Address offset: 0x1F8 */
__IO uint32_t DOUTR31; /*!< Output Data register 31 Address offset: 0x1FC */
uint32_t RESERVED1[124]; /*!< Reserved 0x200 - 0x3EC */
__IO uint32_t HWCFGR; /*!< MDIOS HW Configuration register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< MDIOS Version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< MDIOS identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< MDIOS Size ID register, Address offset: 0x3FC */
} MDIOS_TypeDef;
/**
* @brief USB_OTG_Core_Registers
*/
typedef struct
{
__IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
__IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
__IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
__IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
__IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
__IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
__IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
__IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
__IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
__IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
__IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
__IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
__IO uint32_t GI2CCTL; /*!< I2C Access Register 030h */
uint32_t Reserved30; /*!< Reserved 034h */
__IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
__IO uint32_t CID; /*!< User ID Register 03Ch */
uint32_t Reserved5[4]; /*!< Reserved 040h-048h */
uint32_t Reserved6; /*!< Reserved 050h */
__IO uint32_t GLPMCFG; /*!< LPM Register 054h */
uint32_t Reserved43[42]; /*!< Reserved 058h-0FFh */
__IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
__IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
} USB_OTG_GlobalTypeDef;
/**
* @brief USB_OTG_device_Registers
*/
typedef struct
{
__IO uint32_t DCFG; /*!< dev Configuration Register 800h */
__IO uint32_t DCTL; /*!< dev Control Register 804h */
__IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
uint32_t Reserved0C; /*!< Reserved 80Ch */
__IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
__IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
__IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
__IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
uint32_t Reserved20; /*!< Reserved 820h */
uint32_t Reserved9; /*!< Reserved 824h */
__IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
__IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
__IO uint32_t DTHRCTL; /*!< dev threshold 830h */
__IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
__IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
__IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
uint32_t Reserved40; /*!< dedicated EP mask 840h */
__IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
__IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
} USB_OTG_DeviceTypeDef;
/**
* @brief USB_OTG_IN_Endpoint-Specific_Register
*/
typedef struct
{
__IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
__IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
__IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
__IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
__IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
} USB_OTG_INEndpointTypeDef;
/**
* @brief USB_OTG_OUT_Endpoint-Specific_Registers
*/
typedef struct
{
__IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
__IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
__IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
__IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
} USB_OTG_OUTEndpointTypeDef;
/**
* @brief USB_OTG_Host_Mode_Register_Structures
*/
typedef struct
{
__IO uint32_t HCFG; /*!< Host Configuration Register 400h */
__IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
__IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
uint32_t Reserved40C; /*!< Reserved 40Ch */
__IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
__IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
__IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
__IO uint32_t HFLBADDR; /*!< Host frame list base address register 41Ch */
uint32_t Reserved420[8]; /*!< Reserved 420h */
__IO uint32_t HPRT; /*!< Host port control and status register 440h */
} USB_OTG_HostTypeDef;
/**
* @brief USB_OTG_Host_Channel_Specific_Registers
*/
typedef struct
{
__IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
__IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
__IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
__IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
__IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
__IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
uint32_t Reserved0; /*!< Reserved 518h */
__IO uint32_t HCDMAB; /*!< Host Channel DMA Address Buffer Register 51Ch */
uint32_t Reserved[2]; /*!< Reserved */
} USB_OTG_HostChannelTypeDef;
/**
* @}
*/
/**
* @brief USB_EHCI Capability Registers
*/
typedef struct
{
__IO uint32_t HCCAPBASE; /*!< Capability Register register, Address offset: 0x00 */
__IO uint32_t HCSPARAMS; /*!< Structural Parameter register Address offset: 0x04 */
__IO uint32_t HCCPARAMS; /*!< Capability Parameter register, Address offset: 0x08 */
uint32_t RESERVED; /*!< USB Command register, Address offset: 0x0C */
__IO uint32_t USBCMD; /*!< USB Command register, Address offset: 0x10 */
__IO uint32_t USBSTS; /*!< USB Status register, Address offset: 0x14 */
__IO uint32_t USBINTR; /*!< USB Interrupt Enable register, Address offset: 0x18 */
__IO uint32_t FRINDEX; /*!< USB Frame Index register , Address offset: 0x1C */
__IO uint32_t CTRLDSSEGMENT; /*!< 4G Segment Selector register, Address offset: 0x20 */
__IO uint32_t PERIODICLISTBASE; /*!< Periodic Frame List Base Address register, Address offset: 0x24 */
__IO uint32_t ASYNCLISTADDR; /*!< Asynchronous List Address register, Address offset: 0x28 */
} USB_EHCI_CapabilityTypeDef;
/**
* @}
*/
/**
* @brief GPU host interface registers
*/
typedef struct
{
__IO uint32_t CLKCTRLR; /*!< Clock control register Address offset: 0x00 */
__IO uint32_t IDLESR; /*!< IDLE status register Address offset: 0x04 */
__IO uint32_t AXICFGR; /*!< AXI Configuration register Address offset: 0x08 */
__IO uint32_t AXISR; /*!< AXI Status register, Address offset: 0x0C */
__IO uint32_t INTRACK; /*!< Interrupt acknowledge register, Address offset: 0x10 */
__IO uint32_t INTREN; /*!< Interrupt enable register, Address offset: 0x14 */
__IO uint32_t CHIPID; /*!< Chip ID, Address offset: 0x18 */
__IO uint32_t CHIPREV; /*!< Chip revision register, Address offset: 0x1C */
__IO uint32_t CHIPDATE; /*!< Release date register, Address offset: 0x20 */
__IO uint32_t CHIPTIME; /*!< Release Time register, Address offset: 0x24 */
__IO uint32_t TOTALCYCLES; /*!< Total number of Cycles register, Address offset: 0x28 */
__IO uint32_t PRODUCTID; /*!< Product ID register, Address offset: 0x2C */
__IO uint32_t POWERCTRLR; /*!< Power control register, Address offset: 0x30 */
__IO uint32_t MMUCTRLR; /*!< MMU control register, Address offset: 0x34 */
__IO uint32_t MEMDEBUG; /*!< Memory debug register, Address offset: 0x38 */
__IO uint32_t CMDBUFADDR; /*!< Command buffer base address register, Address offset: 0x3C */
__IO uint32_t CMDBUFCTRL; /*!< Command buffer control register, Address offset: 0x40 */
} GPU_Host_InterfaceTypeDef;
/**
* @}
*/
/** @addtogroup Peripheral_memory_map
* @{
*/
#define MCU_AHB_SRAM ((uint32_t)0x10000000) /*!< Base address of : (up to 288KB) system data RAM accessible over over AHB */
#define MCU_AHB_RETRAM ((uint32_t)0x00000000) /*!< Base address of : (up to 64KB) Retention RAM accessible over over AHB */
#define SYSRAM_BASE ((uint32_t)0x2FFC0000) /*!< Base address of : (up to 256KB) System RAM accessible over over AXI */
#define RETRAM_BASE MCU_AHB_RETRAM
#define SRAM_BASE MCU_AHB_SRAM
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */
#define MPU_AXI_BUS_MEMORY_BASE ((uint32_t)0x60000000) /*!< Base address of : AXI Bus */
#define FMC_NOR_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE) /*!< Base address of : FMC NOR memories accessible over AXI */
#define QSPI_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x10000000) /*!< Base address of : QSPI memories accessible over AXI */
#define FMC_NAND_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x20000000) /*!< Base address of : FMC NAND memories accessible over AXI */
#define STM_DATA_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x30000000) /*!< Base address of : STM Data accessible over AXI */
#define DRAM_MEM_BASE (MPU_AXI_BUS_MEMORY_BASE + 0x60000000) /*!< Base address of : DRAM (DDR) over AXI */
/*!< Device electronic signature memory map */
#define UID_BASE (0x5C005234L) /*!< Unique Device ID register base address */
#define PACKAGE_BASE (0x5C005240L) /*!< Package Data register base address */
#define RPN_BASE (0x5C005204L) /*!< Device Part Number register base address */
#define DV_BASE (0x50081000L) /*!< Device Version register base address */
/*!< Peripheral memory map */
#define MCU_APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000)
#define MCU_APB2_PERIPH_BASE (PERIPH_BASE + 0x04000000)
#define MCU_AHB2_PERIPH_BASE (PERIPH_BASE + 0x08000000)
#define MCU_AHB3_PERIPH_BASE (PERIPH_BASE + 0x0C000000)
#define MCU_AHB4_PERIPH_BASE (PERIPH_BASE + 0x10000000)
#define MCU_APB3_PERIPH_BASE (PERIPH_BASE + 0x10020000)
#define APB_DEBUG_PERIPH_BASE (PERIPH_BASE + 0x10080000)
#define MPU_AHB5_PERIPH_BASE (PERIPH_BASE + 0x14000000)
#define GPV_PERIPH_BASE (PERIPH_BASE + 0x17000000)
#define MPU_AHB6_PERIPH_BASE (PERIPH_BASE + 0x18000000)
#define MPU_APB4_PERIPH_BASE (PERIPH_BASE + 0x1A000000)
#define MPU_APB5_PERIPH_BASE (PERIPH_BASE + 0x1C000000)
/*!< MCU_APB1 */
#define TIM2_BASE (MCU_APB1_PERIPH_BASE + 0x0000)
#define TIM3_BASE (MCU_APB1_PERIPH_BASE + 0x1000)
#define TIM4_BASE (MCU_APB1_PERIPH_BASE + 0x2000)
#define TIM5_BASE (MCU_APB1_PERIPH_BASE + 0x3000)
#define TIM6_BASE (MCU_APB1_PERIPH_BASE + 0x4000)
#define TIM7_BASE (MCU_APB1_PERIPH_BASE + 0x5000)
#define TIM12_BASE (MCU_APB1_PERIPH_BASE + 0x6000)
#define TIM13_BASE (MCU_APB1_PERIPH_BASE + 0x7000)
#define TIM14_BASE (MCU_APB1_PERIPH_BASE + 0x8000)
#define LPTIM1_BASE (MCU_APB1_PERIPH_BASE + 0x9000)
#define WWDG1_BASE (MCU_APB1_PERIPH_BASE + 0xA000)
#define SPI2_BASE (MCU_APB1_PERIPH_BASE + 0xB000)
#define SPI3_BASE (MCU_APB1_PERIPH_BASE + 0xC000)
#define SPDIFRX_BASE (MCU_APB1_PERIPH_BASE + 0xD000)
#define USART2_BASE (MCU_APB1_PERIPH_BASE + 0xE000)
#define USART3_BASE (MCU_APB1_PERIPH_BASE + 0xF000)
#define UART4_BASE (MCU_APB1_PERIPH_BASE + 0x10000)
#define UART5_BASE (MCU_APB1_PERIPH_BASE + 0x11000)
#define I2C1_BASE (MCU_APB1_PERIPH_BASE + 0x12000)
#define I2C2_BASE (MCU_APB1_PERIPH_BASE + 0x13000)
#define I2C3_BASE (MCU_APB1_PERIPH_BASE + 0x14000)
#define I2C5_BASE (MCU_APB1_PERIPH_BASE + 0x15000)
#define CEC_BASE (MCU_APB1_PERIPH_BASE + 0x16000)
#define DAC1_BASE (MCU_APB1_PERIPH_BASE + 0x17000)
#define UART7_BASE (MCU_APB1_PERIPH_BASE + 0x18000)
#define UART8_BASE (MCU_APB1_PERIPH_BASE + 0x19000)
#define MDIOS_BASE (MCU_APB1_PERIPH_BASE + 0x1C000)
/*!< MCU_APB2 */
#define TIM1_BASE (MCU_APB2_PERIPH_BASE + 0x0000)
#define TIM8_BASE (MCU_APB2_PERIPH_BASE + 0x1000)
#define USART6_BASE (MCU_APB2_PERIPH_BASE + 0x3000)
#define SPI1_BASE (MCU_APB2_PERIPH_BASE + 0x4000)
#define SPI4_BASE (MCU_APB2_PERIPH_BASE + 0x5000)
#define TIM15_BASE (MCU_APB2_PERIPH_BASE + 0x6000)
#define TIM16_BASE (MCU_APB2_PERIPH_BASE + 0x7000)
#define TIM17_BASE (MCU_APB2_PERIPH_BASE + 0x8000)
#define SPI5_BASE (MCU_APB2_PERIPH_BASE + 0x9000)
#define SAI1_BASE (MCU_APB2_PERIPH_BASE + 0xA000)
#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
#define SAI2_BASE (MCU_APB2_PERIPH_BASE + 0xB000)
#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
#define SAI3_BASE (MCU_APB2_PERIPH_BASE + 0xC000)
#define SAI3_Block_A_BASE (SAI3_BASE + 0x004)
#define SAI3_Block_B_BASE (SAI3_BASE + 0x024)
#define DFSDM1_BASE (MCU_APB2_PERIPH_BASE + 0xD000)
#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00)
#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20)
#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40)
#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60)
#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80)
#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0)
#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0)
#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0)
#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100)
#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180)
#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200)
#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280)
#define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300)
#define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380)
#define FDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE000)
#define FDCAN2_BASE (MCU_APB2_PERIPH_BASE + 0xF000)
#define TTFDCAN1_BASE (MCU_APB2_PERIPH_BASE + 0xE100)
#define FDCAN_CCU_BASE (MCU_APB2_PERIPH_BASE + 0x10000)
#define SRAMCAN_BASE (MCU_APB2_PERIPH_BASE + 0x11000)
/*!< MCU_AHB2 */
#define DMA1_BASE (MCU_AHB2_PERIPH_BASE + 0x0000)
#define DMA2_BASE (MCU_AHB2_PERIPH_BASE + 0x1000)
#define DMAMUX1_BASE (MCU_AHB2_PERIPH_BASE + 0x2000)
#define ADC1_BASE (MCU_AHB2_PERIPH_BASE + 0x3000)
#define ADC2_BASE (MCU_AHB2_PERIPH_BASE + 0x3100)
#define ADC12_COMMON_BASE (MCU_AHB2_PERIPH_BASE + 0x3300)
#define SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x4000)
#define DLYB_SDMMC3_BASE (MCU_AHB2_PERIPH_BASE + 0x5000)
#define USBOTG_BASE (MCU_AHB2_PERIPH_BASE + 0x1000000)
/*!< MCU_AHB3 */
#define HSEM_BASE (MCU_AHB3_PERIPH_BASE + 0x0000)
#define IPCC_BASE (MCU_AHB3_PERIPH_BASE + 0x1000)
#define HASH2_BASE (MCU_AHB3_PERIPH_BASE + 0x2000)
#define HASH2_DIGEST_BASE (MCU_AHB3_PERIPH_BASE + 0x2310)
#define RNG2_BASE (MCU_AHB3_PERIPH_BASE + 0x3000)
#define CRC2_BASE (MCU_AHB3_PERIPH_BASE + 0x4000)
#define CRYP2_BASE (MCU_AHB3_PERIPH_BASE + 0x5000)
#define DCMI_BASE (MCU_AHB3_PERIPH_BASE + 0x6000)
/*!< MCU_AHB4 */
#define RCC_BASE (MCU_AHB4_PERIPH_BASE + 0x0000)
#define PWR_BASE (MCU_AHB4_PERIPH_BASE + 0x1000)
#define GPIOA_BASE (MCU_AHB4_PERIPH_BASE + 0x2000)
#define GPIOB_BASE (MCU_AHB4_PERIPH_BASE + 0x3000)
#define GPIOC_BASE (MCU_AHB4_PERIPH_BASE + 0x4000)
#define GPIOD_BASE (MCU_AHB4_PERIPH_BASE + 0x5000)
#define GPIOE_BASE (MCU_AHB4_PERIPH_BASE + 0x6000)
#define GPIOF_BASE (MCU_AHB4_PERIPH_BASE + 0x7000)
#define GPIOG_BASE (MCU_AHB4_PERIPH_BASE + 0x8000)
#define GPIOH_BASE (MCU_AHB4_PERIPH_BASE + 0x9000)
#define GPIOI_BASE (MCU_AHB4_PERIPH_BASE + 0xA000)
#define GPIOJ_BASE (MCU_AHB4_PERIPH_BASE + 0xB000)
#define GPIOK_BASE (MCU_AHB4_PERIPH_BASE + 0xC000)
#define AIEC_BASE (MCU_AHB4_PERIPH_BASE + 0xD000)
#define AIEC_C1_BASE (AIEC_BASE + 0x0080)
#define AIEC_C2_BASE (AIEC_BASE + 0x00C0)
/* Alias EXTI_BASE defined because HAL code not yet reworked with new name AIEC*/
#define EXTI_BASE AIEC_BASE
#define EXTI_C1_BASE AIEC_C1_BASE
#define EXTI_C2_BASE AIEC_C2_BASE
/*!< MCU_APB3 */
#define SYSCFG_BASE (MCU_APB3_PERIPH_BASE + 0x0000)
#define LPTIM2_BASE (MCU_APB3_PERIPH_BASE + 0x1000)
#define LPTIM3_BASE (MCU_APB3_PERIPH_BASE + 0x2000)
#define LPTIM4_BASE (MCU_APB3_PERIPH_BASE + 0x3000)
#define LPTIM5_BASE (MCU_APB3_PERIPH_BASE + 0x4000)
#define VREFBUF_BASE (MCU_APB3_PERIPH_BASE + 0x5000)
#define SAI4_BASE (MCU_APB3_PERIPH_BASE + 0x7000)
#define SAI4_Block_A_BASE (SAI4_BASE + 0x004)
#define SAI4_Block_B_BASE (SAI4_BASE + 0x024)
#define DTS_BASE (MCU_APB3_PERIPH_BASE + 0x8000)
#define PMB_BASE (MCU_APB3_PERIPH_BASE + 0x9000)
#define HDP_BASE (MCU_APB3_PERIPH_BASE + 0xA000)
/*!< MCU_AHB4 _APB_Debug */
#define DBGMCU_BASE ((uint32_t )0x50081000)
/*!< MCU_AHB5 */
#define BKPSRAM_BASE (MPU_AHB5_PERIPH_BASE + 0x0000)
#define CRYP1_BASE (MPU_AHB5_PERIPH_BASE + 0x1000)
#define HASH1_BASE (MPU_AHB5_PERIPH_BASE + 0x2000)
#define HASH1_DIGEST_BASE (MPU_AHB5_PERIPH_BASE + 0x2310)
#define RNG1_BASE (MPU_AHB5_PERIPH_BASE + 0x3000)
#define GPIOZ_BASE (MPU_AHB5_PERIPH_BASE + 0x4000)
/*!< GPV */
/*!< MPU_AHB6 */
#define MDMA_BASE (MPU_AHB6_PERIPH_BASE + 0x0000)
#define FMC_R_BASE (MPU_AHB6_PERIPH_BASE + 0x2000)
#define QSPI_R_BASE (MPU_AHB6_PERIPH_BASE + 0x3000)
#define DLYB_QSPI_BASE (MPU_AHB6_PERIPH_BASE + 0x4000)
#define SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x5000)
#define DLYB_SDMMC1_BASE (MPU_AHB6_PERIPH_BASE + 0x6000)
#define SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x7000)
#define DLYB_SDMMC2_BASE (MPU_AHB6_PERIPH_BASE + 0x8000)
#define CRC1_BASE (MPU_AHB6_PERIPH_BASE + 0x9000)
#define ETH_BASE (MPU_AHB6_PERIPH_BASE + 0xA000)
#define ETH_MAC_BASE (ETH_BASE)
#define USB1HSFSP2_BASE (MPU_AHB6_PERIPH_BASE + 0xC000)
#define USB1HSFSP1_BASE (MPU_AHB6_PERIPH_BASE + 0xD000)
#define GPU_BASE (MPU_AHB6_PERIPH_BASE + 0x1000000)
/*!< MPU_APB4 */
#define DSI_BASE (MPU_APB4_PERIPH_BASE + 0x0000)
#define LTDC_BASE (MPU_APB4_PERIPH_BASE + 0x1000)
#define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
#define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
#define IWDG2_BASE (MPU_APB4_PERIPH_BASE + 0x2000)
#define DDRC_BASE (MPU_APB4_PERIPH_BASE + 0x3000)
#define DDRPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x4000)
#define STGENR_BASE (MPU_APB4_PERIPH_BASE + 0x5000)
#define USBPHYC_BASE (MPU_APB4_PERIPH_BASE + 0x6000)
#define USBPHYC_PHY1_BASE (USBPHYC_BASE + 0x100)
#define USBPHYC_PHY2_BASE (USBPHYC_BASE + 0x200)
/*!< MPU_APB5 */
#define USART1_BASE (MPU_APB5_PERIPH_BASE + 0x0000)
#define SPI6_BASE (MPU_APB5_PERIPH_BASE + 0x1000)
#define I2C4_BASE (MPU_APB5_PERIPH_BASE + 0x2000)
#define IWDG1_BASE (MPU_APB5_PERIPH_BASE + 0x3000)
#define RTC_BASE (MPU_APB5_PERIPH_BASE + 0x4000)
#define BSEC_BASE (MPU_APB5_PERIPH_BASE + 0x5000)
#define TZC_BASE (MPU_APB5_PERIPH_BASE + 0x6000)
#define TZPC_BASE (MPU_APB5_PERIPH_BASE + 0x7000)
#define STGENC_BASE (MPU_APB5_PERIPH_BASE + 0x8000)
#define I2C6_BASE (MPU_APB5_PERIPH_BASE + 0x9000)
#define TAMP_BASE (MPU_APB5_PERIPH_BASE + 0xA000)
/*!< USB registers base address */
#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
#define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
#define USB_OTG_HOST_BASE ((uint32_t )0x400)
#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
#define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004)
#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008)
#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000C)
#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010)
#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014)
#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018)
#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001C)
#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020)
#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024)
#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028)
#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002C)
#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030)
#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034)
#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038)
#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003C)
#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100)
#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104)
#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108)
#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010C)
#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080)
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140)
/*!< FMC Banks registers base address */
#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060)
#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
#define MDMA_NB_CHANNELS 32
#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040)
#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080)
#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0)
#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100)
#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140)
#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180)
#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0)
#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200)
#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240)
#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280)
#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0)
#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300)
#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340)
#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380)
#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0)
#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400)
#define MDMA_Channel16_BASE (MDMA_BASE + 0x00000440)
#define MDMA_Channel17_BASE (MDMA_BASE + 0x00000480)
#define MDMA_Channel18_BASE (MDMA_BASE + 0x000004C0)
#define MDMA_Channel19_BASE (MDMA_BASE + 0x00000500)
#define MDMA_Channel20_BASE (MDMA_BASE + 0x00000540)
#define MDMA_Channel21_BASE (MDMA_BASE + 0x00000580)
#define MDMA_Channel22_BASE (MDMA_BASE + 0x000005C0)
#define MDMA_Channel23_BASE (MDMA_BASE + 0x00000600)
#define MDMA_Channel24_BASE (MDMA_BASE + 0x00000640)
#define MDMA_Channel25_BASE (MDMA_BASE + 0x00000680)
#define MDMA_Channel26_BASE (MDMA_BASE + 0x000006C0)
#define MDMA_Channel27_BASE (MDMA_BASE + 0x00000700)
#define MDMA_Channel28_BASE (MDMA_BASE + 0x00000740)
#define MDMA_Channel29_BASE (MDMA_BASE + 0x00000780)
#define MDMA_Channel30_BASE (MDMA_BASE + 0x000007C0)
#define MDMA_Channel31_BASE (MDMA_BASE + 0x00000800)
/**
* @}
*/
/** @addtogroup Peripheral_declaration
* @{
*/
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
#define LCD ((LCD_TypeDef *) LCD_BASE)
#define RTC ((RTC_TypeDef *) RTC_BASE)
#define TAMP ((TAMP_TypeDef *) TAMP_BASE)
#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)
#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)
#define IWDG2 ((IWDG_TypeDef *) IWDG2_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define USART6 ((USART_TypeDef *) USART6_BASE)
#define UART7 ((USART_TypeDef *) UART7_BASE)
#define UART8 ((USART_TypeDef *) UART8_BASE)
#define UART4 ((USART_TypeDef *) UART4_BASE)
#define UART5 ((USART_TypeDef *) UART5_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
#define I2C5 ((I2C_TypeDef *) I2C5_BASE)
#define I2C6 ((I2C_TypeDef *) I2C6_BASE)
#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
#define TTFDCAN1 ((TTCAN_TypeDef *) TTFDCAN1_BASE)
#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
#define CEC ((CEC_TypeDef *) CEC_BASE)
#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)
#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)
#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define VREFBUF ((VREF_TypeDef *) VREFBUF_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define EXTI_C1 ((EXTI_Core_TypeDef *) EXTI_C1_BASE)
#define EXTI_C2 ((EXTI_Core_TypeDef *) EXTI_C2_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
#define SAI3 ((SAI_TypeDef *) SAI3_BASE)
#define SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)
#define SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)
#define SAI4 ((SAI_TypeDef *) SAI4_BASE)
#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
#define DTS1 ((DTS_TypeDef *) DTS_BASE)
#define PMB ((PMB_TypeDef *) PMB_BASE)
#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
#define DFSDM1 ((DFSDM_TypeDef *) DFSDM1_BASE)
#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
#define DFSDM1_Filter4 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter4_BASE)
#define DFSDM1_Filter5 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter5_BASE)
#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define HDP ((HDP_TypeDef *) HDP_BASE)
#define BSEC ((BSEC_TypeDef *) BSEC_BASE)
#define CRC2 ((CRC_TypeDef *) CRC2_BASE)
#define CRC1 ((CRC_TypeDef *) CRC1_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
#define IPCC ((IPCC_TypeDef *) IPCC_BASE)
#define IPCC_C1 ((IPCC_CommonTypeDef *) IPCC_BASE)
#define IPCC_C2 ((IPCC_CommonTypeDef *) (IPCC_BASE + 0x10U))
#define CRYP2 ((CRYP_TypeDef *) CRYP2_BASE)
#define CRYP1 ((CRYP_TypeDef *) CRYP1_BASE)
#define HASH2 ((HASH_TypeDef *) HASH2_BASE)
#define HASH1 ((HASH_TypeDef *) HASH1_BASE)
#define HASH2_DIGEST ((HASH_DIGEST_TypeDef *) HASH2_DIGEST_BASE)
#define HASH1_DIGEST ((HASH_DIGEST_TypeDef *) HASH1_DIGEST_BASE)
#define HASH ((HASH_TypeDef *) HASH2)
#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH2_DIGEST)
#define RNG2 ((RNG_TypeDef *) RNG2_BASE)
#define RNG1 ((RNG_TypeDef *) RNG1_BASE)
#define GPIOZ ((GPIO_TypeDef *) GPIOZ_BASE)
#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
#define DLYB_SDMMC3 ((DLYB_TypeDef *) DLYB_SDMMC3_BASE)
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
#define DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)
#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
#define SDMMC3 ((SDMMC_TypeDef *) SDMMC3_BASE)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define JPEG ((JPEG_TypeDef *) JPGDEC_BASE)
#define HSEM ((HSEM_TypeDef *) HSEM_BASE)
#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x110U))
#define USBPHYC ((USBPHYC_GlobalTypeDef *)USBPHYC_BASE)
#define USBPHYC_PHY1 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY1_BASE)
#define USBPHYC_PHY2 ((USBPHYC_InstanceTypeDef *)USBPHYC_PHY2_BASE)
#define DDRC ((DDRC_TypeDef *)DDRC_BASE)
#define DDRPHYC ((DDRPHYC_TypeDef *)DDRPHYC_BASE)
#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
#define DSI ((DSI_TypeDef *)DSI_BASE)
#define TZC ((TZC_TypeDef *)TZC_BASE)
#define TZPC ((TZPC_TypeDef *)TZPC_BASE)
#define STGENC ((STGENC_TypeDef *)STGENC_BASE)
#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
#define ETH ((ETH_TypeDef *) ETH_BASE)
#define MDMA ((MDMA_TypeDef *) MDMA_BASE)
#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
#define MDMA_Channel16 ((MDMA_Channel_TypeDef *)MDMA_Channel16_BASE)
#define MDMA_Channel17 ((MDMA_Channel_TypeDef *)MDMA_Channel17_BASE)
#define MDMA_Channel18 ((MDMA_Channel_TypeDef *)MDMA_Channel18_BASE)
#define MDMA_Channel19 ((MDMA_Channel_TypeDef *)MDMA_Channel19_BASE)
#define MDMA_Channel20 ((MDMA_Channel_TypeDef *)MDMA_Channel20_BASE)
#define MDMA_Channel21 ((MDMA_Channel_TypeDef *)MDMA_Channel21_BASE)
#define MDMA_Channel22 ((MDMA_Channel_TypeDef *)MDMA_Channel22_BASE)
#define MDMA_Channel23 ((MDMA_Channel_TypeDef *)MDMA_Channel23_BASE)
#define MDMA_Channel24 ((MDMA_Channel_TypeDef *)MDMA_Channel24_BASE)
#define MDMA_Channel25 ((MDMA_Channel_TypeDef *)MDMA_Channel25_BASE)
#define MDMA_Channel26 ((MDMA_Channel_TypeDef *)MDMA_Channel26_BASE)
#define MDMA_Channel27 ((MDMA_Channel_TypeDef *)MDMA_Channel27_BASE)
#define MDMA_Channel28 ((MDMA_Channel_TypeDef *)MDMA_Channel28_BASE)
#define MDMA_Channel29 ((MDMA_Channel_TypeDef *)MDMA_Channel29_BASE)
#define MDMA_Channel30 ((MDMA_Channel_TypeDef *)MDMA_Channel30_BASE)
#define MDMA_Channel31 ((MDMA_Channel_TypeDef *)MDMA_Channel31_BASE)
#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USBOTG_BASE)
/* backward compatibility */
#define USB1_OTG_HS USB_OTG_HS
#define USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) 0x00000000)
#define USB_OTG_FS USB2_OTG_FS
#define USB1_EHCI ((USB_EHCI_CapabilityTypeDef *) USB1HSFSP1_BASE)
#define GPU ((GPU_Host_InterfaceTypeDef *) GPU_BASE)
/**
* @}
*/
/** @addtogroup Exported_constants
* @{
*/
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
/******************************************************************************/
/* Peripheral Registers_Bits_Definition */
/******************************************************************************/
/******************************************************************************/
/* */
/* Device Electronic Signature */
/* */
/******************************************************************************/
#define PKG_ID_Pos (27U)
#define PKG_ID_Msk (0x7U << PKG_ID_Pos) /*!< 0x38000000 */
#define PKG_ID PKG_ID_Msk /*!< Package Type */
#define RPN_ID_Pos (0U)
#define RPN_ID_Msk (0xFFU << RPN_ID_Pos) /*!< 0x000000FF */
#define RPN_ID RPN_ID_Msk /*!< Device Part Number */
#define DV_DEV_ID_Pos (0U)
#define DV_DEV_ID_Msk (0xFFFU << DV_DEV_ID_Pos) /*!< 0x00000FFF */
#define DV_DEV_ID DV_DEV_ID_Msk /*!< Device ID */
#define DV_REV_ID_Pos (16U)
#define DV_REV_ID_Msk (0xFFFFU << DV_REV_ID_Pos) /*!< 0xFFFF0000 */
#define DV_REV_ID DV_REV_ID_Msk /*!< Device Rev ID */
/******************************************************************************/
/* */
/* Analog to Digital Converter */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions
*/
#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
/******************** Bit definition for ADC_ISR register ********************/
#define ADC_ISR_ADRDY_Pos (0U)
#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */
#define ADC_ISR_EOSMP_Pos (1U)
#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */
#define ADC_ISR_EOC_Pos (2U)
#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */
#define ADC_ISR_EOS_Pos (3U)
#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */
#define ADC_ISR_OVR_Pos (4U)
#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */
#define ADC_ISR_JEOC_Pos (5U)
#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */
#define ADC_ISR_JEOS_Pos (6U)
#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */
#define ADC_ISR_AWD1_Pos (7U)
#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */
#define ADC_ISR_AWD2_Pos (8U)
#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */
#define ADC_ISR_AWD3_Pos (9U)
#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
/******************** Bit definition for ADC_IER register ********************/
#define ADC_IER_ADRDYIE_Pos (0U)
#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */
#define ADC_IER_EOSMPIE_Pos (1U)
#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */
#define ADC_IER_EOCIE_Pos (2U)
#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */
#define ADC_IER_EOSIE_Pos (3U)
#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */
#define ADC_IER_OVRIE_Pos (4U)
#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */
#define ADC_IER_JEOCIE_Pos (5U)
#define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */
#define ADC_IER_JEOSIE_Pos (6U)
#define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */
#define ADC_IER_AWD1IE_Pos (7U)
#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */
#define ADC_IER_AWD2IE_Pos (8U)
#define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */
#define ADC_IER_AWD3IE_Pos (9U)
#define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */
#define ADC_IER_JQOVFIE_Pos (10U)
#define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */
/******************** Bit definition for ADC_CR register ********************/
#define ADC_CR_ADEN_Pos (0U)
#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */
#define ADC_CR_ADDIS_Pos (1U)
#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */
#define ADC_CR_ADSTART_Pos (2U)
#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */
#define ADC_CR_JADSTART_Pos (3U)
#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */
#define ADC_CR_ADSTP_Pos (4U)
#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */
#define ADC_CR_JADSTP_Pos (5U)
#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */
#define ADC_CR_BOOST_Pos (8U)
#define ADC_CR_BOOST_Msk (0x1U << ADC_CR_BOOST_Pos) /*!< 0x00000100 */
#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode */
#define ADC_CR_ADCALLIN_Pos (16U)
#define ADC_CR_ADCALLIN_Msk (0x1U << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */
#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */
#define ADC_CR_LINCALRDYW1_Pos (22U)
#define ADC_CR_LINCALRDYW1_Msk (0x1U << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */
#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */
#define ADC_CR_LINCALRDYW2_Pos (23U)
#define ADC_CR_LINCALRDYW2_Msk (0x1U << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */
#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */
#define ADC_CR_LINCALRDYW3_Pos (24U)
#define ADC_CR_LINCALRDYW3_Msk (0x1U << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */
#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */
#define ADC_CR_LINCALRDYW4_Pos (25U)
#define ADC_CR_LINCALRDYW4_Msk (0x1U << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */
#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */
#define ADC_CR_LINCALRDYW5_Pos (26U)
#define ADC_CR_LINCALRDYW5_Msk (0x1U << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */
#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */
#define ADC_CR_LINCALRDYW6_Pos (27U)
#define ADC_CR_LINCALRDYW6_Msk (0x1U << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */
#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */
#define ADC_CR_ADVREGEN_Pos (28U)
#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */
#define ADC_CR_DEEPPWD_Pos (29U)
#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */
#define ADC_CR_ADCALDIF_Pos (30U)
#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */
#define ADC_CR_ADCAL_Pos (31U)
#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */
/******************** Bit definition for ADC_CFGR register ********************/
#define ADC_CFGR_DMNGT_Pos (0U)
#define ADC_CFGR_DMNGT_Msk (0x3U << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */
#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */
#define ADC_CFGR_DMNGT_0 (0x1U << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */
#define ADC_CFGR_DMNGT_1 (0x2U << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */
#define ADC_CFGR_RES_Pos (2U)
#define ADC_CFGR_RES_Msk (0x7U << ADC_CFGR_RES_Pos) /*!< 0x0000001C */
#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */
#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000004 */
#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
#define ADC_CFGR_RES_2 (0x4U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
#define ADC_CFGR_EXTSEL_Pos (5U)
#define ADC_CFGR_EXTSEL_Msk (0x1FU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */
#define ADC_CFGR_EXTSEL_0 (0x01U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
#define ADC_CFGR_EXTSEL_1 (0x02U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
#define ADC_CFGR_EXTSEL_2 (0x04U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
#define ADC_CFGR_EXTSEL_3 (0x08U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
#define ADC_CFGR_EXTSEL_4 (0x10U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
#define ADC_CFGR_EXTEN_Pos (10U)
#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */
#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
#define ADC_CFGR_OVRMOD_Pos (12U)
#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */
#define ADC_CFGR_CONT_Pos (13U)
#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */
#define ADC_CFGR_AUTDLY_Pos (14U)
#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */
#define ADC_CFGR_DISCEN_Pos (16U)
#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */
#define ADC_CFGR_DISCNUM_Pos (17U)
#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
#define ADC_CFGR_JDISCEN_Pos (20U)
#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
#define ADC_CFGR_JQM_Pos (21U)
#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */
#define ADC_CFGR_AWD1SGL_Pos (22U)
#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */
#define ADC_CFGR_AWD1EN_Pos (23U)
#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */
#define ADC_CFGR_JAWD1EN_Pos (24U)
#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */
#define ADC_CFGR_JAUTO_Pos (25U)
#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */
#define ADC_CFGR_AWD1CH_Pos (26U)
#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */
#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
#define ADC_CFGR_JQDIS_Pos (31U)
#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */
/******************** Bit definition for ADC_CFGR2 register ********************/
#define ADC_CFGR2_ROVSE_Pos (0U)
#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */
#define ADC_CFGR2_JOVSE_Pos (1U)
#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */
#define ADC_CFGR2_OVSR_Pos (2U)
#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC Regular group oversampler enable TO Be removed after ADC driver update*/
#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
#define ADC_CFGR2_OVSS_Pos (5U)
#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */
#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
#define ADC_CFGR2_TROVS_Pos (9U)
#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */
#define ADC_CFGR2_ROVSM_Pos (10U)
#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */
#define ADC_CFGR2_RSHIFT1_Pos (11U)
#define ADC_CFGR2_RSHIFT1_Msk (0x1U << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */
#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */
#define ADC_CFGR2_RSHIFT2_Pos (12U)
#define ADC_CFGR2_RSHIFT2_Msk (0x1U << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */
#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */
#define ADC_CFGR2_RSHIFT3_Pos (13U)
#define ADC_CFGR2_RSHIFT3_Msk (0x1U << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */
#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */
#define ADC_CFGR2_RSHIFT4_Pos (14U)
#define ADC_CFGR2_RSHIFT4_Msk (0x1U << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */
#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */
#define ADC_CFGR2_OSR_Pos (16U)
#define ADC_CFGR2_OSR_Msk (0x3FFU << ADC_CFGR2_OSR_Pos) /*!< 0x03FF0000 */
#define ADC_CFGR2_OSR ADC_CFGR2_OSR_Msk /*!< ADC oversampling Ratio */
#define ADC_CFGR2_OSR_0 (0x001U << ADC_CFGR2_OSR_Pos) /*!< 0x00010000 */
#define ADC_CFGR2_OSR_1 (0x002U << ADC_CFGR2_OSR_Pos) /*!< 0x00020000 */
#define ADC_CFGR2_OSR_2 (0x004U << ADC_CFGR2_OSR_Pos) /*!< 0x00040000 */
#define ADC_CFGR2_OSR_3 (0x008U << ADC_CFGR2_OSR_Pos) /*!< 0x00080000 */
#define ADC_CFGR2_OSR_4 (0x010U << ADC_CFGR2_OSR_Pos) /*!< 0x00100000 */
#define ADC_CFGR2_OSR_5 (0x020U << ADC_CFGR2_OSR_Pos) /*!< 0x00200000 */
#define ADC_CFGR2_OSR_6 (0x040U << ADC_CFGR2_OSR_Pos) /*!< 0x00400000 */
#define ADC_CFGR2_OSR_7 (0x080U << ADC_CFGR2_OSR_Pos) /*!< 0x00800000 */
#define ADC_CFGR2_OSR_8 (0x100U << ADC_CFGR2_OSR_Pos) /*!< 0x01000000 */
#define ADC_CFGR2_OSR_9 (0x200U << ADC_CFGR2_OSR_Pos) /*!< 0x02000000 */
#define ADC_CFGR2_LSHIFT_Pos (28U)
#define ADC_CFGR2_LSHIFT_Msk (0xFU << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */
#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */
#define ADC_CFGR2_LSHIFT_0 (0x1U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */
#define ADC_CFGR2_LSHIFT_1 (0x2U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */
#define ADC_CFGR2_LSHIFT_2 (0x4U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */
#define ADC_CFGR2_LSHIFT_3 (0x8U << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_SMPR1 register ********************/
#define ADC_SMPR1_SMP0_Pos (0U)
#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */
#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
#define ADC_SMPR1_SMP1_Pos (3U)
#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */
#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
#define ADC_SMPR1_SMP2_Pos (6U)
#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */
#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
#define ADC_SMPR1_SMP3_Pos (9U)
#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */
#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
#define ADC_SMPR1_SMP4_Pos (12U)
#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */
#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
#define ADC_SMPR1_SMP5_Pos (15U)
#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */
#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
#define ADC_SMPR1_SMP6_Pos (18U)
#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */
#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
#define ADC_SMPR1_SMP7_Pos (21U)
#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */
#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
#define ADC_SMPR1_SMP8_Pos (24U)
#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */
#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
#define ADC_SMPR1_SMP9_Pos (27U)
#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */
#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
/******************** Bit definition for ADC_SMPR2 register ********************/
#define ADC_SMPR2_SMP10_Pos (0U)
#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */
#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
#define ADC_SMPR2_SMP11_Pos (3U)
#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */
#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
#define ADC_SMPR2_SMP12_Pos (6U)
#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */
#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
#define ADC_SMPR2_SMP13_Pos (9U)
#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */
#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
#define ADC_SMPR2_SMP14_Pos (12U)
#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */
#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
#define ADC_SMPR2_SMP15_Pos (15U)
#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */
#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
#define ADC_SMPR2_SMP16_Pos (18U)
#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */
#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
#define ADC_SMPR2_SMP17_Pos (21U)
#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */
#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
#define ADC_SMPR2_SMP18_Pos (24U)
#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */
#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
#define ADC_SMPR2_SMP19_Pos (27U)
#define ADC_SMPR2_SMP19_Msk (0x7U << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */
#define ADC_SMPR2_SMP19_0 (0x1U << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
#define ADC_SMPR2_SMP19_1 (0x2U << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
#define ADC_SMPR2_SMP19_2 (0x4U << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
/******************** Bit definition for ADC_PCSEL register ********************/
#define ADC_PCSEL_PCSEL_Pos (0U)
#define ADC_PCSEL_PCSEL_Msk (0xFFFFFU << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */
#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */
#define ADC_PCSEL_PCSEL_0 (0x00001U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */
#define ADC_PCSEL_PCSEL_1 (0x00002U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */
#define ADC_PCSEL_PCSEL_2 (0x00004U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */
#define ADC_PCSEL_PCSEL_3 (0x00008U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */
#define ADC_PCSEL_PCSEL_4 (0x00010U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */
#define ADC_PCSEL_PCSEL_5 (0x00020U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */
#define ADC_PCSEL_PCSEL_6 (0x00040U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */
#define ADC_PCSEL_PCSEL_7 (0x00080U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */
#define ADC_PCSEL_PCSEL_8 (0x00100U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */
#define ADC_PCSEL_PCSEL_9 (0x00200U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */
#define ADC_PCSEL_PCSEL_10 (0x00400U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */
#define ADC_PCSEL_PCSEL_11 (0x00800U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */
#define ADC_PCSEL_PCSEL_12 (0x01000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */
#define ADC_PCSEL_PCSEL_13 (0x02000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */
#define ADC_PCSEL_PCSEL_14 (0x04000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */
#define ADC_PCSEL_PCSEL_15 (0x08000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */
#define ADC_PCSEL_PCSEL_16 (0x10000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */
#define ADC_PCSEL_PCSEL_17 (0x20000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */
#define ADC_PCSEL_PCSEL_18 (0x40000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */
#define ADC_PCSEL_PCSEL_19 (0x80000U << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */
/******************** Bit definition for ADC_LTR1 register ********************/
#define ADC_LTR1_LT1_Pos (0U)
#define ADC_LTR1_LT1_Msk (0x3FFFFFFU << ADC_LTR1_LT1_Pos) /*!< 0x03FFFFFF */
#define ADC_LTR1_LT1 ADC_LTR1_LT1_Msk /*!< ADC Analog watchdog 1 lower threshold */
#define ADC_LTR1_LT1_0 (0x0000001U << ADC_LTR1_LT1_Pos) /*!< 0x00000001 */
#define ADC_LTR1_LT1_1 (0x0000002U << ADC_LTR1_LT1_Pos) /*!< 0x00000002 */
#define ADC_LTR1_LT1_2 (0x0000004U << ADC_LTR1_LT1_Pos) /*!< 0x00000004 */
#define ADC_LTR1_LT1_3 (0x0000008U << ADC_LTR1_LT1_Pos) /*!< 0x00000008 */
#define ADC_LTR1_LT1_4 (0x0000010U << ADC_LTR1_LT1_Pos) /*!< 0x00000010 */
#define ADC_LTR1_LT1_5 (0x0000020U << ADC_LTR1_LT1_Pos) /*!< 0x00000020 */
#define ADC_LTR1_LT1_6 (0x0000040U << ADC_LTR1_LT1_Pos) /*!< 0x00000040 */
#define ADC_LTR1_LT1_7 (0x0000080U << ADC_LTR1_LT1_Pos) /*!< 0x00000080 */
#define ADC_LTR1_LT1_8 (0x0000100U << ADC_LTR1_LT1_Pos) /*!< 0x00000100 */
#define ADC_LTR1_LT1_9 (0x0000200U << ADC_LTR1_LT1_Pos) /*!< 0x00000200 */
#define ADC_LTR1_LT1_10 (0x0000400U << ADC_LTR1_LT1_Pos) /*!< 0x00000400 */
#define ADC_LTR1_LT1_11 (0x0000800U << ADC_LTR1_LT1_Pos) /*!< 0x00000800 */
#define ADC_LTR1_LT1_12 (0x0001000U << ADC_LTR1_LT1_Pos) /*!< 0x00001000 */
#define ADC_LTR1_LT1_13 (0x0002000U << ADC_LTR1_LT1_Pos) /*!< 0x00002000 */
#define ADC_LTR1_LT1_14 (0x0004000U << ADC_LTR1_LT1_Pos) /*!< 0x00004000 */
#define ADC_LTR1_LT1_15 (0x0008000U << ADC_LTR1_LT1_Pos) /*!< 0x00008000 */
#define ADC_LTR1_LT1_16 (0x0010000U << ADC_LTR1_LT1_Pos) /*!< 0x00010000 */
#define ADC_LTR1_LT1_17 (0x0020000U << ADC_LTR1_LT1_Pos) /*!< 0x00020000 */
#define ADC_LTR1_LT1_18 (0x0040000U << ADC_LTR1_LT1_Pos) /*!< 0x00040000 */
#define ADC_LTR1_LT1_19 (0x0080000U << ADC_LTR1_LT1_Pos) /*!< 0x00080000 */
#define ADC_LTR1_LT1_20 (0x0100000U << ADC_LTR1_LT1_Pos) /*!< 0x00100000 */
#define ADC_LTR1_LT1_21 (0x0200000U << ADC_LTR1_LT1_Pos) /*!< 0x00200000 */
#define ADC_LTR1_LT1_22 (0x0400000U << ADC_LTR1_LT1_Pos) /*!< 0x00400000 */
#define ADC_LTR1_LT1_23 (0x0800000U << ADC_LTR1_LT1_Pos) /*!< 0x00800000 */
#define ADC_LTR1_LT1_24 (0x1000000U << ADC_LTR1_LT1_Pos) /*!< 0x01000000 */
#define ADC_LTR1_LT1_25 (0x2000000U << ADC_LTR1_LT1_Pos) /*!< 0x02000000 */
/******************** Bit definition for ADC_HTR1 register ********************/
#define ADC_HTR1_HT1 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 1 higher threshold */
#define ADC_HTR1_HT1_0 ((uint32_t)0x00000001) /*!< ADC HT1 bit 0 */
#define ADC_HTR1_HT1_1 ((uint32_t)0x00000002) /*!< ADC HT1 bit 1 */
#define ADC_HTR1_HT1_2 ((uint32_t)0x00000004) /*!< ADC HT1 bit 2 */
#define ADC_HTR1_HT1_3 ((uint32_t)0x00000008) /*!< ADC HT1 bit 3 */
#define ADC_HTR1_HT1_4 ((uint32_t)0x00000010) /*!< ADC HT1 bit 4 */
#define ADC_HTR1_HT1_5 ((uint32_t)0x00000020) /*!< ADC HT1 bit 5 */
#define ADC_HTR1_HT1_6 ((uint32_t)0x00000040) /*!< ADC HT1 bit 6 */
#define ADC_HTR1_HT1_7 ((uint32_t)0x00000080) /*!< ADC HT1 bit 7 */
#define ADC_HTR1_HT1_8 ((uint32_t)0x00000100) /*!< ADC HT1 bit 8 */
#define ADC_HTR1_HT1_9 ((uint32_t)0x00000200) /*!< ADC HT1 bit 9 */
#define ADC_HTR1_HT1_10 ((uint32_t)0x00000400) /*!< ADC HT1 bit 10 */
#define ADC_HTR1_HT1_11 ((uint32_t)0x00000800) /*!< ADC HT1 bit 11 */
#define ADC_HTR1_HT1_12 ((uint32_t)0x00001000) /*!< ADC HT1 bit 12 */
#define ADC_HTR1_HT1_13 ((uint32_t)0x00002000) /*!< ADC HT1 bit 13 */
#define ADC_HTR1_HT1_14 ((uint32_t)0x00004000) /*!< ADC HT1 bit 14 */
#define ADC_HTR1_HT1_15 ((uint32_t)0x00008000) /*!< ADC HT1 bit 15 */
#define ADC_HTR1_HT1_16 ((uint32_t)0x00010000) /*!< ADC HT1 bit 16 */
#define ADC_HTR1_HT1_17 ((uint32_t)0x00020000) /*!< ADC HT1 bit 17 */
#define ADC_HTR1_HT1_18 ((uint32_t)0x00040000) /*!< ADC HT1 bit 18 */
#define ADC_HTR1_HT1_19 ((uint32_t)0x00080000) /*!< ADC HT1 bit 19 */
#define ADC_HTR1_HT1_20 ((uint32_t)0x00100000) /*!< ADC HT1 bit 20 */
#define ADC_HTR1_HT1_21 ((uint32_t)0x00200000) /*!< ADC HT1 bit 21 */
#define ADC_HTR1_HT1_22 ((uint32_t)0x00400000) /*!< ADC HT1 bit 22 */
#define ADC_HTR1_HT1_23 ((uint32_t)0x00800000) /*!< ADC HT1 bit 23 */
#define ADC_HTR1_HT1_24 ((uint32_t)0x01000000) /*!< ADC HT1 bit 24 */
#define ADC_HTR1_HT1_25 ((uint32_t)0x02000000) /*!< ADC HT1 bit 25 */
/******************** Bit definition for ADC_LTR2 register ********************/
#define ADC_LTR2_LT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 lower threshold */
#define ADC_LTR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */
#define ADC_LTR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */
#define ADC_LTR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */
#define ADC_LTR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */
#define ADC_LTR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */
#define ADC_LTR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */
#define ADC_LTR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */
#define ADC_LTR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */
#define ADC_LTR2_LT2_8 ((uint32_t)0x00000100) /*!< ADC LT2 bit 8 */
#define ADC_LTR2_LT2_9 ((uint32_t)0x00000200) /*!< ADC LT2 bit 9 */
#define ADC_LTR2_LT2_10 ((uint32_t)0x00000400) /*!< ADC LT2 bit 10 */
#define ADC_LTR2_LT2_11 ((uint32_t)0x00000800) /*!< ADC LT2 bit 11 */
#define ADC_LTR2_LT2_12 ((uint32_t)0x00001000) /*!< ADC LT2 bit 12 */
#define ADC_LTR2_LT2_13 ((uint32_t)0x00002000) /*!< ADC LT2 bit 13 */
#define ADC_LTR2_LT2_14 ((uint32_t)0x00004000) /*!< ADC LT2 bit 14 */
#define ADC_LTR2_LT2_15 ((uint32_t)0x00008000) /*!< ADC LT2 bit 15 */
#define ADC_LTR2_LT2_16 ((uint32_t)0x00010000) /*!< ADC LT2 bit 16 */
#define ADC_LTR2_LT2_17 ((uint32_t)0x00020000) /*!< ADC LT2 bit 17 */
#define ADC_LTR2_LT2_18 ((uint32_t)0x00040000) /*!< ADC LT2 bit 18 */
#define ADC_LTR2_LT2_19 ((uint32_t)0x00080000) /*!< ADC LT2 bit 19 */
#define ADC_LTR2_LT2_20 ((uint32_t)0x00100000) /*!< ADC LT2 bit 20 */
#define ADC_LTR2_LT2_21 ((uint32_t)0x00200000) /*!< ADC LT2 bit 21 */
#define ADC_LTR2_LT2_22 ((uint32_t)0x00400000) /*!< ADC LT2 bit 22 */
#define ADC_LTR2_LT2_23 ((uint32_t)0x00800000) /*!< ADC LT2 bit 23 */
#define ADC_LTR2_LT2_24 ((uint32_t)0x01000000) /*!< ADC LT2 bit 24 */
#define ADC_LTR2_LT2_25 ((uint32_t)0x02000000) /*!< ADC LT2 bit 25 */
/******************** Bit definition for ADC_HTR2 register ********************/
#define ADC_HTR2_HT2 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 2 higher threshold */
#define ADC_HTR2_HT2_0 ((uint32_t)0x00000001) /*!< ADC HT2 bit 0 */
#define ADC_HTR2_HT2_1 ((uint32_t)0x00000002) /*!< ADC HT2 bit 1 */
#define ADC_HTR2_HT2_2 ((uint32_t)0x00000004) /*!< ADC HT2 bit 2 */
#define ADC_HTR2_HT2_3 ((uint32_t)0x00000008) /*!< ADC HT2 bit 3 */
#define ADC_HTR2_HT2_4 ((uint32_t)0x00000010) /*!< ADC HT2 bit 4 */
#define ADC_HTR2_HT2_5 ((uint32_t)0x00000020) /*!< ADC HT2 bit 5 */
#define ADC_HTR2_HT2_6 ((uint32_t)0x00000040) /*!< ADC HT2 bit 6 */
#define ADC_HTR2_HT2_7 ((uint32_t)0x00000080) /*!< ADC HT2 bit 7 */
#define ADC_HTR2_HT2_8 ((uint32_t)0x00000100) /*!< ADC HT2 bit 8 */
#define ADC_HTR2_HT2_9 ((uint32_t)0x00000200) /*!< ADC HT2 bit 9 */
#define ADC_HTR2_HT2_10 ((uint32_t)0x00000400) /*!< ADC HT2 bit 10 */
#define ADC_HTR2_HT2_11 ((uint32_t)0x00000800) /*!< ADC HT2 bit 11 */
#define ADC_HTR2_HT2_12 ((uint32_t)0x00001000) /*!< ADC HT2 bit 12 */
#define ADC_HTR2_HT2_13 ((uint32_t)0x00002000) /*!< ADC HT2 bit 13 */
#define ADC_HTR2_HT2_14 ((uint32_t)0x00004000) /*!< ADC HT2 bit 14 */
#define ADC_HTR2_HT2_15 ((uint32_t)0x00008000) /*!< ADC HT2 bit 15 */
#define ADC_HTR2_HT2_16 ((uint32_t)0x00010000) /*!< ADC HT2 bit 16 */
#define ADC_HTR2_HT2_17 ((uint32_t)0x00020000) /*!< ADC HT2 bit 17 */
#define ADC_HTR2_HT2_18 ((uint32_t)0x00040000) /*!< ADC HT2 bit 18 */
#define ADC_HTR2_HT2_19 ((uint32_t)0x00080000) /*!< ADC HT2 bit 19 */
#define ADC_HTR2_HT2_20 ((uint32_t)0x00100000) /*!< ADC HT2 bit 20 */
#define ADC_HTR2_HT2_21 ((uint32_t)0x00200000) /*!< ADC HT2 bit 21 */
#define ADC_HTR2_HT2_22 ((uint32_t)0x00400000) /*!< ADC HT2 bit 22 */
#define ADC_HTR2_HT2_23 ((uint32_t)0x00800000) /*!< ADC HT2 bit 23 */
#define ADC_HTR2_HT2_24 ((uint32_t)0x01000000) /*!< ADC HT2 bit 24 */
#define ADC_HTR2_HT2_25 ((uint32_t)0x020000000) /*!< ADC HT2 bit 25 */
/******************** Bit definition for ADC_LTR3 register ********************/
#define ADC_LTR3_LT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 lower threshold */
#define ADC_LTR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */
#define ADC_LTR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */
#define ADC_LTR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */
#define ADC_LTR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */
#define ADC_LTR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */
#define ADC_LTR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */
#define ADC_LTR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */
#define ADC_LTR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */
#define ADC_LTR3_LT3_8 ((uint32_t)0x00000100) /*!< ADC LT3 bit 8 */
#define ADC_LTR3_LT3_9 ((uint32_t)0x00000200) /*!< ADC LT3 bit 9 */
#define ADC_LTR3_LT3_10 ((uint32_t)0x00000400) /*!< ADC LT3 bit 10 */
#define ADC_LTR3_LT3_11 ((uint32_t)0x00000800) /*!< ADC LT3 bit 11 */
#define ADC_LTR3_LT3_12 ((uint32_t)0x00001000) /*!< ADC LT3 bit 12 */
#define ADC_LTR3_LT3_13 ((uint32_t)0x00002000) /*!< ADC LT3 bit 13 */
#define ADC_LTR3_LT3_14 ((uint32_t)0x00004000) /*!< ADC LT3 bit 14 */
#define ADC_LTR3_LT3_15 ((uint32_t)0x00008000) /*!< ADC LT3 bit 15 */
#define ADC_LTR3_LT3_16 ((uint32_t)0x00010000) /*!< ADC LT3 bit 16 */
#define ADC_LTR3_LT3_17 ((uint32_t)0x00020000) /*!< ADC LT3 bit 17 */
#define ADC_LTR3_LT3_18 ((uint32_t)0x00040000) /*!< ADC LT3 bit 18 */
#define ADC_LTR3_LT3_19 ((uint32_t)0x00080000) /*!< ADC LT3 bit 19 */
#define ADC_LTR3_LT3_20 ((uint32_t)0x00100000) /*!< ADC LT3 bit 20 */
#define ADC_LTR3_LT3_21 ((uint32_t)0x00200000) /*!< ADC LT3 bit 21 */
#define ADC_LTR3_LT3_22 ((uint32_t)0x00400000) /*!< ADC LT3 bit 22 */
#define ADC_LTR3_LT3_23 ((uint32_t)0x00800000) /*!< ADC LT3 bit 23 */
#define ADC_LTR3_LT3_24 ((uint32_t)0x01000000) /*!< ADC LT3 bit 24*/
#define ADC_LTR3_LT3_25 ((uint32_t)0x02000000) /*!< ADC LT3 bit 25 */
/******************** Bit definition for ADC_HTR3 register ********************/
#define ADC_HTR3_HT3 ((uint32_t) 0x03FFFFFF) /*!< ADC Analog watchdog 3 higher threshold */
#define ADC_HTR3_HT3_0 ((uint32_t)0x00000001) /*!< ADC HT3 bit 0 */
#define ADC_HTR3_HT3_1 ((uint32_t)0x00000002) /*!< ADC HT3 bit 1 */
#define ADC_HTR3_HT3_2 ((uint32_t)0x00000004) /*!< ADC HT3 bit 2 */
#define ADC_HTR3_HT3_3 ((uint32_t)0x00000008) /*!< ADC HT3 bit 3 */
#define ADC_HTR3_HT3_4 ((uint32_t)0x00000010) /*!< ADC HT3 bit 4 */
#define ADC_HTR3_HT3_5 ((uint32_t)0x00000020) /*!< ADC HT3 bit 5 */
#define ADC_HTR3_HT3_6 ((uint32_t)0x00000040) /*!< ADC HT3 bit 6 */
#define ADC_HTR3_HT3_7 ((uint32_t)0x00000080) /*!< ADC HT3 bit 7 */
#define ADC_HTR3_HT3_8 ((uint32_t)0x00000100) /*!< ADC HT3 bit 8 */
#define ADC_HTR3_HT3_9 ((uint32_t)0x00000200) /*!< ADC HT3 bit 9 */
#define ADC_HTR3_HT3_10 ((uint32_t)0x00000400) /*!< ADC HT3 bit 10 */
#define ADC_HTR3_HT3_11 ((uint32_t)0x00000800) /*!< ADC HT3 bit 11 */
#define ADC_HTR3_HT3_12 ((uint32_t)0x00001000) /*!< ADC HT3 bit 12 */
#define ADC_HTR3_HT3_13 ((uint32_t)0x00002000) /*!< ADC HT3 bit 13 */
#define ADC_HTR3_HT3_14 ((uint32_t)0x00004000) /*!< ADC HT3 bit 14 */
#define ADC_HTR3_HT3_15 ((uint32_t)0x00008000) /*!< ADC HT3 bit 15 */
#define ADC_HTR3_HT3_16 ((uint32_t)0x00010000) /*!< ADC HT3 bit 16 */
#define ADC_HTR3_HT3_17 ((uint32_t)0x00020000) /*!< ADC HT3 bit 17 */
#define ADC_HTR3_HT3_18 ((uint32_t)0x00040000) /*!< ADC HT3 bit 18 */
#define ADC_HTR3_HT3_19 ((uint32_t)0x00080000) /*!< ADC HT3 bit 19 */
#define ADC_HTR3_HT3_20 ((uint32_t)0x00100000) /*!< ADC HT3 bit 20 */
#define ADC_HTR3_HT3_21 ((uint32_t)0x00200000) /*!< ADC HT3 bit 21 */
#define ADC_HTR3_HT3_22 ((uint32_t)0x00400000) /*!< ADC HT3 bit 22 */
#define ADC_HTR3_HT3_23 ((uint32_t)0x00800000) /*!< ADC HT3 bit 23 */
#define ADC_HTR3_HT3_24 ((uint32_t)0x01000000) /*!< ADC HT3 bit 24 */
#define ADC_HTR3_HT3_25 ((uint32_t)0x02000000) /*!< ADC HT3 bit 25 */
/******************** Bit definition for ADC_SQR1 register ********************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */
#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */
#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */
#define ADC_SQR1_SQ1_Pos (6U)
#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */
#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
#define ADC_SQR1_SQ2_Pos (12U)
#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */
#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
#define ADC_SQR1_SQ3_Pos (18U)
#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */
#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
#define ADC_SQR1_SQ4_Pos (24U)
#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */
#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR2 register ********************/
#define ADC_SQR2_SQ5_Pos (0U)
#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */
#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
#define ADC_SQR2_SQ6_Pos (6U)
#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */
#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
#define ADC_SQR2_SQ7_Pos (12U)
#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */
#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
#define ADC_SQR2_SQ8_Pos (18U)
#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */
#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
#define ADC_SQR2_SQ9_Pos (24U)
#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */
#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR3 register ********************/
#define ADC_SQR3_SQ10_Pos (0U)
#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */
#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
#define ADC_SQR3_SQ11_Pos (6U)
#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */
#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
#define ADC_SQR3_SQ12_Pos (12U)
#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */
#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
#define ADC_SQR3_SQ13_Pos (18U)
#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */
#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
#define ADC_SQR3_SQ14_Pos (24U)
#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */
#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR4 register ********************/
#define ADC_SQR4_SQ15_Pos (0U)
#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */
#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
#define ADC_SQR4_SQ16_Pos (6U)
#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */
#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
/******************** Bit definition for ADC_DR register ********************/
#define ADC_DR_RDATA_Pos (0U)
#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */
#define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
#define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
#define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
#define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
#define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
#define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
#define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
#define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
#define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
#define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
#define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
#define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
#define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
#define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
#define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
#define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
#define ADC_DR_RDATA_16 (0x10000U << ADC_DR_RDATA_Pos) /*!< 0x00010000 */
#define ADC_DR_RDATA_17 (0x20000U << ADC_DR_RDATA_Pos) /*!< 0x00020000 */
#define ADC_DR_RDATA_18 (0x40000U << ADC_DR_RDATA_Pos) /*!< 0x00040000 */
#define ADC_DR_RDATA_19 (0x80000U << ADC_DR_RDATA_Pos) /*!< 0x00080000 */
#define ADC_DR_RDATA_20 (0x100000U << ADC_DR_RDATA_Pos) /*!< 0x00100000 */
#define ADC_DR_RDATA_21 (0x200000U << ADC_DR_RDATA_Pos) /*!< 0x00200000 */
#define ADC_DR_RDATA_22 (0x400000U << ADC_DR_RDATA_Pos) /*!< 0x00400000 */
#define ADC_DR_RDATA_23 (0x800000U << ADC_DR_RDATA_Pos) /*!< 0x00800000 */
#define ADC_DR_RDATA_24 (0x1000000U << ADC_DR_RDATA_Pos) /*!< 0x01000000 */
#define ADC_DR_RDATA_25 (0x2000000U << ADC_DR_RDATA_Pos) /*!< 0x02000000 */
#define ADC_DR_RDATA_26 (0x4000000U << ADC_DR_RDATA_Pos) /*!< 0x04000000 */
#define ADC_DR_RDATA_27 (0x8000000U << ADC_DR_RDATA_Pos) /*!< 0x08000000 */
#define ADC_DR_RDATA_28 (0x10000000U << ADC_DR_RDATA_Pos) /*!< 0x10000000 */
#define ADC_DR_RDATA_29 (0x20000000U << ADC_DR_RDATA_Pos) /*!< 0x20000000 */
#define ADC_DR_RDATA_30 (0x40000000U << ADC_DR_RDATA_Pos) /*!< 0x40000000 */
#define ADC_DR_RDATA_31 (0x80000000U << ADC_DR_RDATA_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_JSQR register ********************/
#define ADC_JSQR_JL_Pos (0U)
#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */
#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
#define ADC_JSQR_JEXTSEL_Pos (2U)
#define ADC_JSQR_JEXTSEL_Msk (0x1FU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */
#define ADC_JSQR_JEXTSEL_0 (0x01U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
#define ADC_JSQR_JEXTSEL_1 (0x02U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
#define ADC_JSQR_JEXTSEL_2 (0x04U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
#define ADC_JSQR_JEXTSEL_3 (0x08U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
#define ADC_JSQR_JEXTSEL_4 (0x10U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
#define ADC_JSQR_JEXTEN_Pos (7U)
#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */
#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
#define ADC_JSQR_JSQ1_Pos (9U)
#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */
#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
#define ADC_JSQR_JSQ2_Pos (15U)
#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */
#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */
#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */
#define ADC_JSQR_JSQ3_Pos (21U)
#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */
#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
#define ADC_JSQR_JSQ4_Pos (27U)
#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */
#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_OFR1 register ********************/
#define ADC_OFR1_OFFSET1_Pos (0U)
#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
#define ADC_OFR1_OFFSET1_0 (0x0000001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
#define ADC_OFR1_OFFSET1_1 (0x0000002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
#define ADC_OFR1_OFFSET1_2 (0x0000004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
#define ADC_OFR1_OFFSET1_3 (0x0000008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
#define ADC_OFR1_OFFSET1_4 (0x0000010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
#define ADC_OFR1_OFFSET1_5 (0x0000020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
#define ADC_OFR1_OFFSET1_6 (0x0000040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
#define ADC_OFR1_OFFSET1_7 (0x0000080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
#define ADC_OFR1_OFFSET1_8 (0x0000100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
#define ADC_OFR1_OFFSET1_9 (0x0000200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
#define ADC_OFR1_OFFSET1_10 (0x0000400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
#define ADC_OFR1_OFFSET1_11 (0x0000800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
#define ADC_OFR1_OFFSET1_12 (0x0001000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
#define ADC_OFR1_OFFSET1_13 (0x0002000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
#define ADC_OFR1_OFFSET1_14 (0x0004000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
#define ADC_OFR1_OFFSET1_15 (0x0008000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
#define ADC_OFR1_OFFSET1_16 (0x0010000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
#define ADC_OFR1_OFFSET1_17 (0x0020000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
#define ADC_OFR1_OFFSET1_18 (0x0040000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
#define ADC_OFR1_OFFSET1_19 (0x0080000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
#define ADC_OFR1_OFFSET1_20 (0x0100000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
#define ADC_OFR1_OFFSET1_21 (0x0200000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
#define ADC_OFR1_OFFSET1_22 (0x0400000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
#define ADC_OFR1_OFFSET1_23 (0x0800000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
#define ADC_OFR1_OFFSET1_24 (0x1000000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
#define ADC_OFR1_OFFSET1_25 (0x2000000U << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
#define ADC_OFR1_OFFSET1_CH_Pos (26U)
#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */
#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR1_SSATE_Pos (31U)
#define ADC_OFR1_SSATE_Msk (0x1U << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */
#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */
/******************** Bit definition for ADC_OFR2 register ********************/
#define ADC_OFR2_OFFSET2_Pos (0U)
#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
#define ADC_OFR2_OFFSET2_0 (0x0000001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
#define ADC_OFR2_OFFSET2_1 (0x0000002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
#define ADC_OFR2_OFFSET2_2 (0x0000004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
#define ADC_OFR2_OFFSET2_3 (0x0000008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
#define ADC_OFR2_OFFSET2_4 (0x0000010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
#define ADC_OFR2_OFFSET2_5 (0x0000020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
#define ADC_OFR2_OFFSET2_6 (0x0000040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
#define ADC_OFR2_OFFSET2_7 (0x0000080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
#define ADC_OFR2_OFFSET2_8 (0x0000100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
#define ADC_OFR2_OFFSET2_9 (0x0000200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
#define ADC_OFR2_OFFSET2_10 (0x0000400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
#define ADC_OFR2_OFFSET2_11 (0x0000800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
#define ADC_OFR2_OFFSET2_12 (0x0001000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
#define ADC_OFR2_OFFSET2_13 (0x0002000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
#define ADC_OFR2_OFFSET2_14 (0x0004000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
#define ADC_OFR2_OFFSET2_15 (0x0008000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
#define ADC_OFR2_OFFSET2_16 (0x0010000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
#define ADC_OFR2_OFFSET2_17 (0x0020000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
#define ADC_OFR2_OFFSET2_18 (0x0040000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
#define ADC_OFR2_OFFSET2_19 (0x0080000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
#define ADC_OFR2_OFFSET2_20 (0x0100000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
#define ADC_OFR2_OFFSET2_21 (0x0200000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
#define ADC_OFR2_OFFSET2_22 (0x0400000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
#define ADC_OFR2_OFFSET2_23 (0x0800000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
#define ADC_OFR2_OFFSET2_24 (0x1000000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
#define ADC_OFR2_OFFSET2_25 (0x2000000U << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
#define ADC_OFR2_OFFSET2_CH_Pos (26U)
#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */
#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR2_SSATE_Pos (31U)
#define ADC_OFR2_SSATE_Msk (0x1U << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */
#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */
/******************** Bit definition for ADC_OFR3 register ********************/
#define ADC_OFR3_OFFSET3_Pos (0U)
#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
#define ADC_OFR3_OFFSET3_0 (0x0000001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
#define ADC_OFR3_OFFSET3_1 (0x0000002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
#define ADC_OFR3_OFFSET3_2 (0x0000004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
#define ADC_OFR3_OFFSET3_3 (0x0000008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
#define ADC_OFR3_OFFSET3_4 (0x0000010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
#define ADC_OFR3_OFFSET3_5 (0x0000020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
#define ADC_OFR3_OFFSET3_6 (0x0000040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
#define ADC_OFR3_OFFSET3_7 (0x0000080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
#define ADC_OFR3_OFFSET3_8 (0x0000100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
#define ADC_OFR3_OFFSET3_9 (0x0000200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
#define ADC_OFR3_OFFSET3_10 (0x0000400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
#define ADC_OFR3_OFFSET3_11 (0x0000800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
#define ADC_OFR3_OFFSET3_12 (0x0001000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
#define ADC_OFR3_OFFSET3_13 (0x0002000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
#define ADC_OFR3_OFFSET3_14 (0x0004000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
#define ADC_OFR3_OFFSET3_15 (0x0008000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
#define ADC_OFR3_OFFSET3_16 (0x0010000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
#define ADC_OFR3_OFFSET3_17 (0x0020000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
#define ADC_OFR3_OFFSET3_18 (0x0040000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
#define ADC_OFR3_OFFSET3_19 (0x0080000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
#define ADC_OFR3_OFFSET3_20 (0x0100000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
#define ADC_OFR3_OFFSET3_21 (0x0200000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
#define ADC_OFR3_OFFSET3_22 (0x0400000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
#define ADC_OFR3_OFFSET3_23 (0x0800000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
#define ADC_OFR3_OFFSET3_24 (0x1000000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
#define ADC_OFR3_OFFSET3_25 (0x2000000U << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
#define ADC_OFR3_OFFSET3_CH_Pos (26U)
#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */
#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR3_SSATE_Pos (31U)
#define ADC_OFR3_SSATE_Msk (0x1U << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */
#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */
/******************** Bit definition for ADC_OFR4 register ********************/
#define ADC_OFR4_OFFSET4_Pos (0U)
#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
#define ADC_OFR4_OFFSET4_0 (0x0000001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
#define ADC_OFR4_OFFSET4_1 (0x0000002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
#define ADC_OFR4_OFFSET4_2 (0x0000004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
#define ADC_OFR4_OFFSET4_3 (0x0000008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
#define ADC_OFR4_OFFSET4_4 (0x0000010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
#define ADC_OFR4_OFFSET4_5 (0x0000020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
#define ADC_OFR4_OFFSET4_6 (0x0000040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
#define ADC_OFR4_OFFSET4_7 (0x0000080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
#define ADC_OFR4_OFFSET4_8 (0x0000100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
#define ADC_OFR4_OFFSET4_9 (0x0000200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
#define ADC_OFR4_OFFSET4_10 (0x0000400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
#define ADC_OFR4_OFFSET4_11 (0x0000800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
#define ADC_OFR4_OFFSET4_12 (0x0001000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
#define ADC_OFR4_OFFSET4_13 (0x0002000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
#define ADC_OFR4_OFFSET4_14 (0x0004000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
#define ADC_OFR4_OFFSET4_15 (0x0008000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
#define ADC_OFR4_OFFSET4_16 (0x0010000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
#define ADC_OFR4_OFFSET4_17 (0x0020000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
#define ADC_OFR4_OFFSET4_18 (0x0040000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
#define ADC_OFR4_OFFSET4_19 (0x0080000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
#define ADC_OFR4_OFFSET4_20 (0x0100000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
#define ADC_OFR4_OFFSET4_21 (0x0200000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
#define ADC_OFR4_OFFSET4_22 (0x0400000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
#define ADC_OFR4_OFFSET4_23 (0x0800000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
#define ADC_OFR4_OFFSET4_24 (0x1000000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
#define ADC_OFR4_OFFSET4_25 (0x2000000U << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
#define ADC_OFR4_OFFSET4_CH_Pos (26U)
#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */
#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR4_SSATE_Pos (31U)
#define ADC_OFR4_SSATE_Msk (0x1U << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */
#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */
/******************** Bit definition for ADC_JDR1 register ********************/
#define ADC_JDR1_JDATA_Pos (0U)
#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */
#define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
#define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
#define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
#define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
#define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
#define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
#define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
#define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
#define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
#define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
#define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
#define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
#define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
#define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
#define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
#define ADC_JDR1_JDATA_16 (0x10000U << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */
#define ADC_JDR1_JDATA_17 (0x20000U << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */
#define ADC_JDR1_JDATA_18 (0x40000U << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */
#define ADC_JDR1_JDATA_19 (0x80000U << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */
#define ADC_JDR1_JDATA_20 (0x100000U << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */
#define ADC_JDR1_JDATA_21 (0x200000U << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */
#define ADC_JDR1_JDATA_22 (0x400000U << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */
#define ADC_JDR1_JDATA_23 (0x800000U << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */
#define ADC_JDR1_JDATA_24 (0x1000000U << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */
#define ADC_JDR1_JDATA_25 (0x2000000U << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */
#define ADC_JDR1_JDATA_26 (0x4000000U << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */
#define ADC_JDR1_JDATA_27 (0x8000000U << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */
#define ADC_JDR1_JDATA_28 (0x10000000U << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */
#define ADC_JDR1_JDATA_29 (0x20000000U << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */
#define ADC_JDR1_JDATA_30 (0x40000000U << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */
#define ADC_JDR1_JDATA_31 (0x80000000U << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_JDR2 register ********************/
#define ADC_JDR2_JDATA_Pos (0U)
#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */
#define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
#define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
#define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
#define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
#define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
#define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
#define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
#define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
#define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
#define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
#define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
#define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
#define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
#define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
#define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
#define ADC_JDR2_JDATA_16 (0x10000U << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */
#define ADC_JDR2_JDATA_17 (0x20000U << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */
#define ADC_JDR2_JDATA_18 (0x40000U << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */
#define ADC_JDR2_JDATA_19 (0x80000U << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */
#define ADC_JDR2_JDATA_20 (0x100000U << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */
#define ADC_JDR2_JDATA_21 (0x200000U << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */
#define ADC_JDR2_JDATA_22 (0x400000U << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */
#define ADC_JDR2_JDATA_23 (0x800000U << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */
#define ADC_JDR2_JDATA_24 (0x1000000U << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */
#define ADC_JDR2_JDATA_25 (0x2000000U << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */
#define ADC_JDR2_JDATA_26 (0x4000000U << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */
#define ADC_JDR2_JDATA_27 (0x8000000U << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */
#define ADC_JDR2_JDATA_28 (0x10000000U << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */
#define ADC_JDR2_JDATA_29 (0x20000000U << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */
#define ADC_JDR2_JDATA_30 (0x40000000U << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */
#define ADC_JDR2_JDATA_31 (0x80000000U << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_JDR3 register ********************/
#define ADC_JDR3_JDATA_Pos (0U)
#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */
#define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
#define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
#define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
#define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
#define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
#define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
#define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
#define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
#define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
#define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
#define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
#define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
#define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
#define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
#define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
#define ADC_JDR3_JDATA_16 (0x10000U << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */
#define ADC_JDR3_JDATA_17 (0x20000U << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */
#define ADC_JDR3_JDATA_18 (0x40000U << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */
#define ADC_JDR3_JDATA_19 (0x80000U << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */
#define ADC_JDR3_JDATA_20 (0x100000U << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */
#define ADC_JDR3_JDATA_21 (0x200000U << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */
#define ADC_JDR3_JDATA_22 (0x400000U << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */
#define ADC_JDR3_JDATA_23 (0x800000U << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */
#define ADC_JDR3_JDATA_24 (0x1000000U << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */
#define ADC_JDR3_JDATA_25 (0x2000000U << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */
#define ADC_JDR3_JDATA_26 (0x4000000U << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */
#define ADC_JDR3_JDATA_27 (0x8000000U << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */
#define ADC_JDR3_JDATA_28 (0x10000000U << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */
#define ADC_JDR3_JDATA_29 (0x20000000U << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */
#define ADC_JDR3_JDATA_30 (0x40000000U << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */
#define ADC_JDR3_JDATA_31 (0x80000000U << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_JDR4 register ********************/
#define ADC_JDR4_JDATA_Pos (0U)
#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */
#define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
#define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
#define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
#define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
#define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
#define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
#define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
#define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
#define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
#define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
#define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
#define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
#define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
#define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
#define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
#define ADC_JDR4_JDATA_16 (0x10000U << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */
#define ADC_JDR4_JDATA_17 (0x20000U << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */
#define ADC_JDR4_JDATA_18 (0x40000U << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */
#define ADC_JDR4_JDATA_19 (0x80000U << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */
#define ADC_JDR4_JDATA_20 (0x100000U << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */
#define ADC_JDR4_JDATA_21 (0x200000U << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */
#define ADC_JDR4_JDATA_22 (0x400000U << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */
#define ADC_JDR4_JDATA_23 (0x800000U << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */
#define ADC_JDR4_JDATA_24 (0x1000000U << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */
#define ADC_JDR4_JDATA_25 (0x2000000U << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */
#define ADC_JDR4_JDATA_26 (0x4000000U << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */
#define ADC_JDR4_JDATA_27 (0x8000000U << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */
#define ADC_JDR4_JDATA_28 (0x10000000U << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */
#define ADC_JDR4_JDATA_29 (0x20000000U << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */
#define ADC_JDR4_JDATA_30 (0x40000000U << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */
#define ADC_JDR4_JDATA_31 (0x80000000U << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_AWD2CR register ********************/
#define ADC_AWD2CR_AWD2CH_Pos (0U)
#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */
#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
#define ADC_AWD2CR_AWD2CH_19 (0x80000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
/******************** Bit definition for ADC_AWD3CR register ********************/
#define ADC_AWD3CR_AWD3CH_Pos (0U)
#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 3 channel selection */
#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
#define ADC_AWD3CR_AWD3CH_19 (0x80000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
/******************** Bit definition for ADC_DIFSEL register ********************/
#define ADC_DIFSEL_DIFSEL_Pos (0U)
#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */
#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
#define ADC_DIFSEL_DIFSEL_19 (0x80000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */
/******************** Bit definition for ADC_CALFACT register ********************/
#define ADC_CALFACT_CALFACT_S_Pos (0U)
#define ADC_CALFACT_CALFACT_S_Msk (0x7FFU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */
#define ADC_CALFACT_CALFACT_S_0 (0x001U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
#define ADC_CALFACT_CALFACT_S_1 (0x002U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
#define ADC_CALFACT_CALFACT_S_2 (0x004U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
#define ADC_CALFACT_CALFACT_S_3 (0x008U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
#define ADC_CALFACT_CALFACT_S_4 (0x010U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
#define ADC_CALFACT_CALFACT_S_5 (0x020U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
#define ADC_CALFACT_CALFACT_S_6 (0x040U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
#define ADC_CALFACT_CALFACT_S_7 (0x080U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
#define ADC_CALFACT_CALFACT_S_8 (0x100U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
#define ADC_CALFACT_CALFACT_S_9 (0x200U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
#define ADC_CALFACT_CALFACT_S_10 (0x400U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
#define ADC_CALFACT_CALFACT_D_Pos (16U)
#define ADC_CALFACT_CALFACT_D_Msk (0x7FFU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */
#define ADC_CALFACT_CALFACT_D_0 (0x001U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
#define ADC_CALFACT_CALFACT_D_1 (0x002U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
#define ADC_CALFACT_CALFACT_D_2 (0x004U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
#define ADC_CALFACT_CALFACT_D_3 (0x008U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
#define ADC_CALFACT_CALFACT_D_4 (0x010U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
#define ADC_CALFACT_CALFACT_D_5 (0x020U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
#define ADC_CALFACT_CALFACT_D_6 (0x040U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
#define ADC_CALFACT_CALFACT_D_7 (0x080U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
#define ADC_CALFACT_CALFACT_D_8 (0x100U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
#define ADC_CALFACT_CALFACT_D_9 (0x200U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
#define ADC_CALFACT_CALFACT_D_10 (0x400U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
/******************** Bit definition for ADC_CALFACT2 register ********************/
#define ADC_CALFACT2_LINCALFACT_Pos (0U)
#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFU << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */
#define ADC_CALFACT2_LINCALFACT_0 (0x00000001U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
#define ADC_CALFACT2_LINCALFACT_1 (0x00000002U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
#define ADC_CALFACT2_LINCALFACT_2 (0x00000004U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
#define ADC_CALFACT2_LINCALFACT_3 (0x00000008U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
#define ADC_CALFACT2_LINCALFACT_4 (0x00000010U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
#define ADC_CALFACT2_LINCALFACT_5 (0x00000020U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
#define ADC_CALFACT2_LINCALFACT_6 (0x00000040U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
#define ADC_CALFACT2_LINCALFACT_7 (0x00000080U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
#define ADC_CALFACT2_LINCALFACT_8 (0x00000100U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
#define ADC_CALFACT2_LINCALFACT_9 (0x00000200U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
#define ADC_CALFACT2_LINCALFACT_10 (0x00000400U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
#define ADC_CALFACT2_LINCALFACT_11 (0x00000800U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
#define ADC_CALFACT2_LINCALFACT_12 (0x00001000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
#define ADC_CALFACT2_LINCALFACT_13 (0x00002000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
#define ADC_CALFACT2_LINCALFACT_14 (0x00004000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
#define ADC_CALFACT2_LINCALFACT_15 (0x00008000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
#define ADC_CALFACT2_LINCALFACT_16 (0x00010000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
#define ADC_CALFACT2_LINCALFACT_17 (0x00020000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
#define ADC_CALFACT2_LINCALFACT_18 (0x00040000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
#define ADC_CALFACT2_LINCALFACT_19 (0x00080000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
#define ADC_CALFACT2_LINCALFACT_20 (0x00100000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
#define ADC_CALFACT2_LINCALFACT_21 (0x00200000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
#define ADC_CALFACT2_LINCALFACT_22 (0x00400000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
#define ADC_CALFACT2_LINCALFACT_23 (0x00800000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
#define ADC_CALFACT2_LINCALFACT_24 (0x01000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
#define ADC_CALFACT2_LINCALFACT_25 (0x02000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
#define ADC_CALFACT2_LINCALFACT_26 (0x04000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
#define ADC_CALFACT2_LINCALFACT_27 (0x08000001U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000001 */
#define ADC_CALFACT2_LINCALFACT_28 (0x10000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
#define ADC_CALFACT2_LINCALFACT_29 (0x20000000U << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
/******************** Bit definition for ADC2_OR - Option Register ********************/
#define ADC2_OR_VDDCOREEN_Pos (0U)
#define ADC2_OR_VDDCOREEN_Msk (0x1U << ADC2_OR_VDDCOREEN_Pos) /*!< 0x00000001 */
#define ADC2_OR_VDDCOREEN ADC2_OR_VDDCOREEN_Msk /*!< ADC2 Option Register - VDDCORE enable bit */
/************************* ADC Common registers *****************************/
/******************** Bit definition for ADC_CSR register ********************/
#define ADC_CSR_ADRDY_MST_Pos (0U)
#define ADC_CSR_ADRDY_MST_Msk (0x1U << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
#define ADC_CSR_EOSMP_MST_Pos (1U)
#define ADC_CSR_EOSMP_MST_Msk (0x1U << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
#define ADC_CSR_EOC_MST_Pos (2U)
#define ADC_CSR_EOC_MST_Msk (0x1U << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
#define ADC_CSR_EOS_MST_Pos (3U)
#define ADC_CSR_EOS_MST_Msk (0x1U << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
#define ADC_CSR_OVR_MST_Pos (4U)
#define ADC_CSR_OVR_MST_Msk (0x1U << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */
#define ADC_CSR_JEOC_MST_Pos (5U)
#define ADC_CSR_JEOC_MST_Msk (0x1U << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
#define ADC_CSR_JEOS_MST_Pos (6U)
#define ADC_CSR_JEOS_MST_Msk (0x1U << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
#define ADC_CSR_AWD1_MST_Pos (7U)
#define ADC_CSR_AWD1_MST_Msk (0x1U << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
#define ADC_CSR_AWD2_MST_Pos (8U)
#define ADC_CSR_AWD2_MST_Msk (0x1U << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
#define ADC_CSR_AWD3_MST_Pos (9U)
#define ADC_CSR_AWD3_MST_Msk (0x1U << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
#define ADC_CSR_JQOVF_MST_Pos (10U)
#define ADC_CSR_JQOVF_MST_Msk (0x1U << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
#define ADC_CSR_ADRDY_SLV_Pos (16U)
#define ADC_CSR_ADRDY_SLV_Msk (0x1U << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
#define ADC_CSR_EOSMP_SLV_Pos (17U)
#define ADC_CSR_EOSMP_SLV_Msk (0x1U << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
#define ADC_CSR_EOC_SLV_Pos (18U)
#define ADC_CSR_EOC_SLV_Msk (0x1U << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
#define ADC_CSR_EOS_SLV_Pos (19U)
#define ADC_CSR_EOS_SLV_Msk (0x1U << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
#define ADC_CSR_OVR_SLV_Pos (20U)
#define ADC_CSR_OVR_SLV_Msk (0x1U << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
#define ADC_CSR_JEOC_SLV_Pos (21U)
#define ADC_CSR_JEOC_SLV_Msk (0x1U << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */
#define ADC_CSR_JEOS_SLV_Pos (22U)
#define ADC_CSR_JEOS_SLV_Msk (0x1U << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */
#define ADC_CSR_AWD1_SLV_Pos (23U)
#define ADC_CSR_AWD1_SLV_Msk (0x1U << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */
#define ADC_CSR_AWD2_SLV_Pos (24U)
#define ADC_CSR_AWD2_SLV_Msk (0x1U << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */
#define ADC_CSR_AWD3_SLV_Pos (25U)
#define ADC_CSR_AWD3_SLV_Msk (0x1U << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */
#define ADC_CSR_JQOVF_SLV_Pos (26U)
#define ADC_CSR_JQOVF_SLV_Msk (0x1U << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */
/******************** Bit definition for ADC_CCR register ********************/
#define ADC_CCR_DUAL_Pos (0U)
#define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */
#define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
#define ADC_CCR_DUAL_1 (0x02U << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
#define ADC_CCR_DUAL_2 (0x04U << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
#define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
#define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
#define ADC_CCR_DELAY_Pos (8U)
#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */
#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
#define ADC_CCR_DAMDF_Pos (14U)
#define ADC_CCR_DAMDF_Msk (0x3U << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */
#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */
#define ADC_CCR_DAMDF_0 (0x1U << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */
#define ADC_CCR_DAMDF_1 (0x2U << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */
#define ADC_CCR_CKMODE_Pos (16U)
#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */
#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
#define ADC_CCR_PRESC_Pos (18U)
#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */
#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
#define ADC_CCR_VREFEN_Pos (22U)
#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */
#define ADC_CCR_VSENSEEN_Pos (23U)
#define ADC_CCR_VSENSEEN_Msk (0x1U << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */
#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */
#define ADC_CCR_VBATEN_Pos (24U)
#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */
/******************** Bit definition for ADC_CDR register ********************/
#define ADC_CDR_RDATA_MST_Pos (0U)
#define ADC_CDR_RDATA_MST_Msk (0xFFFFU << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< Regular Data of the master ADC */
#define ADC_CDR_RDATA_MST_0 (0x0001U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */
#define ADC_CDR_RDATA_MST_1 (0x0002U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */
#define ADC_CDR_RDATA_MST_2 (0x0004U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */
#define ADC_CDR_RDATA_MST_3 (0x0008U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */
#define ADC_CDR_RDATA_MST_4 (0x0010U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */
#define ADC_CDR_RDATA_MST_5 (0x0020U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */
#define ADC_CDR_RDATA_MST_6 (0x0040U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */
#define ADC_CDR_RDATA_MST_7 (0x0080U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */
#define ADC_CDR_RDATA_MST_8 (0x0100U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */
#define ADC_CDR_RDATA_MST_9 (0x0200U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */
#define ADC_CDR_RDATA_MST_10 (0x0400U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */
#define ADC_CDR_RDATA_MST_11 (0x0800U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */
#define ADC_CDR_RDATA_MST_12 (0x1000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */
#define ADC_CDR_RDATA_MST_13 (0x2000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */
#define ADC_CDR_RDATA_MST_14 (0x4000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */
#define ADC_CDR_RDATA_MST_15 (0x8000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */
#define ADC_CDR_RDATA_SLV_Pos (16U)
#define ADC_CDR_RDATA_SLV_Msk (0xFFFFU << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< Regular Data of the master ADC */
#define ADC_CDR_RDATA_SLV_0 (0x0001U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */
#define ADC_CDR_RDATA_SLV_1 (0x0002U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */
#define ADC_CDR_RDATA_SLV_2 (0x0004U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */
#define ADC_CDR_RDATA_SLV_3 (0x0008U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */
#define ADC_CDR_RDATA_SLV_4 (0x0010U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */
#define ADC_CDR_RDATA_SLV_5 (0x0020U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */
#define ADC_CDR_RDATA_SLV_6 (0x0040U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */
#define ADC_CDR_RDATA_SLV_7 (0x0080U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */
#define ADC_CDR_RDATA_SLV_8 (0x0100U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */
#define ADC_CDR_RDATA_SLV_9 (0x0200U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */
#define ADC_CDR_RDATA_SLV_10 (0x0400U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */
#define ADC_CDR_RDATA_SLV_11 (0x0800U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */
#define ADC_CDR_RDATA_SLV_12 (0x1000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */
#define ADC_CDR_RDATA_SLV_13 (0x2000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */
#define ADC_CDR_RDATA_SLV_14 (0x4000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */
#define ADC_CDR_RDATA_SLV_15 (0x8000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_CDR2 register ********************/
#define ADC_CDR2_RDATA_ALT_Pos (0U)
#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFU << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular Data for dual Mode */
#define ADC_CDR2_RDATA_ALT_0 (0x00000001U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000001 */
#define ADC_CDR2_RDATA_ALT_1 (0x00000002U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000002 */
#define ADC_CDR2_RDATA_ALT_2 (0x00000004U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000004 */
#define ADC_CDR2_RDATA_ALT_3 (0x00000008U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000008 */
#define ADC_CDR2_RDATA_ALT_4 (0x00000010U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000010 */
#define ADC_CDR2_RDATA_ALT_5 (0x00000020U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000020 */
#define ADC_CDR2_RDATA_ALT_6 (0x00000040U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000040 */
#define ADC_CDR2_RDATA_ALT_7 (0x00000080U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000080 */
#define ADC_CDR2_RDATA_ALT_8 (0x00000100U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000100 */
#define ADC_CDR2_RDATA_ALT_9 (0x00000200U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000200 */
#define ADC_CDR2_RDATA_ALT_10 (0x00000400U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000400 */
#define ADC_CDR2_RDATA_ALT_11 (0x00000800U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00000800 */
#define ADC_CDR2_RDATA_ALT_12 (0x00001000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00001000 */
#define ADC_CDR2_RDATA_ALT_13 (0x00002000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00002000 */
#define ADC_CDR2_RDATA_ALT_14 (0x00004000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00004000 */
#define ADC_CDR2_RDATA_ALT_15 (0x00008000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00008000 */
#define ADC_CDR2_RDATA_ALT_16 (0x00010000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00010000 */
#define ADC_CDR2_RDATA_ALT_17 (0x00020000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00020000 */
#define ADC_CDR2_RDATA_ALT_18 (0x00040000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00040000 */
#define ADC_CDR2_RDATA_ALT_19 (0x00080000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00080000 */
#define ADC_CDR2_RDATA_ALT_20 (0x00100000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00100000 */
#define ADC_CDR2_RDATA_ALT_21 (0x00200000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00200000 */
#define ADC_CDR2_RDATA_ALT_22 (0x00400000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00400000 */
#define ADC_CDR2_RDATA_ALT_23 (0x00800000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x00800000 */
#define ADC_CDR2_RDATA_ALT_24 (0x01000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x01000000 */
#define ADC_CDR2_RDATA_ALT_25 (0x02000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x02000000 */
#define ADC_CDR2_RDATA_ALT_26 (0x04000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x04000000 */
#define ADC_CDR2_RDATA_ALT_27 (0x08000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x08000000 */
#define ADC_CDR2_RDATA_ALT_28 (0x10000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x10000000 */
#define ADC_CDR2_RDATA_ALT_29 (0x20000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x20000000 */
#define ADC_CDR2_RDATA_ALT_30 (0x40000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x40000000 */
#define ADC_CDR2_RDATA_ALT_31 (0x80000000U << ADC_CDR2_RDATA_ALT_Pos) /*!< 0x80000000 */
/******************************************************************************/
/* */
/* VREFBUF */
/* */
/******************************************************************************/
/******************* Bit definition for VREFBUF_CSR register ****************/
#define VREFBUF_CSR_ENVR_Pos (0U)
#define VREFBUF_CSR_ENVR_Msk (0x1U << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
#define VREFBUF_CSR_HIZ_Pos (1U)
#define VREFBUF_CSR_HIZ_Msk (0x1U << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
#define VREFBUF_CSR_VRR_Pos (3U)
#define VREFBUF_CSR_VRR_Msk (0x1U << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
#define VREFBUF_CSR_VRS_Pos (4U)
#define VREFBUF_CSR_VRS_Msk (0x7U << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
#define VREFBUF_CSR_VRS_OUT2_Msk (0x1U << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
#define VREFBUF_CSR_VRS_OUT3_Pos (5U)
#define VREFBUF_CSR_VRS_OUT3_Msk (0x1U << VREFBUF_CSR_VRS_OUT3_Pos) /*!< 0x00000020 */
#define VREFBUF_CSR_VRS_OUT3 VREFBUF_CSR_VRS_OUT3_Msk /*!<Voltage reference VREF_OUT3 */
#define VREFBUF_CSR_VRS_OUT4_Pos (4U)
#define VREFBUF_CSR_VRS_OUT4_Msk (0x3U << VREFBUF_CSR_VRS_OUT4_Pos) /*!< 0x00000030 */
#define VREFBUF_CSR_VRS_OUT4 VREFBUF_CSR_VRS_OUT4_Msk /*!<Voltage reference VREF_OUT4 */
/******************* Bit definition for VREFBUF_CCR register ****************/
#define VREFBUF_CCR_TRIM_Pos (0U)
#define VREFBUF_CCR_TRIM_Msk (0x3FU << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
/******************************************************************************/
/* */
/* Flexible Datarate Controller Area Network */
/* */
/******************************************************************************/
/*!<FDCAN control and status registers */
/***************** Bit definition for FDCAN_CREL register *******************/
#define FDCAN_CREL_DAY_Pos (0U)
#define FDCAN_CREL_DAY_Msk (0xFFU << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */
#define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */
#define FDCAN_CREL_MON_Pos (8U)
#define FDCAN_CREL_MON_Msk (0xFFU << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */
#define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */
#define FDCAN_CREL_YEAR_Pos (16U)
#define FDCAN_CREL_YEAR_Msk (0xFU << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */
#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */
#define FDCAN_CREL_SUBSTEP_Pos (20U)
#define FDCAN_CREL_SUBSTEP_Msk (0xFU << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
#define FDCAN_CREL_STEP_Pos (24U)
#define FDCAN_CREL_STEP_Msk (0xFU << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */
#define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */
#define FDCAN_CREL_REL_Pos (28U)
#define FDCAN_CREL_REL_Msk (0xFU << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */
#define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFU << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<TEndiannes Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
#define FDCAN_DBTP_DSJW_Msk (0xFU << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */
#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */
#define FDCAN_DBTP_DTSEG2_Pos (4U)
#define FDCAN_DBTP_DTSEG2_Msk (0xFU << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */
#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */
#define FDCAN_DBTP_DTSEG1_Pos (8U)
#define FDCAN_DBTP_DTSEG1_Msk (0x1FU << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */
#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */
#define FDCAN_DBTP_DBRP_Pos (16U)
#define FDCAN_DBTP_DBRP_Msk (0x1FU << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */
#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */
#define FDCAN_DBTP_TDC_Pos (23U)
#define FDCAN_DBTP_TDC_Msk (0x1U << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */
#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */
/***************** Bit definition for FDCAN_TEST register *******************/
#define FDCAN_TEST_LBCK_Pos (4U)
#define FDCAN_TEST_LBCK_Msk (0x1U << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */
#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */
#define FDCAN_TEST_TX_Pos (5U)
#define FDCAN_TEST_TX_Msk (0x3U << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */
#define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */
#define FDCAN_TEST_RX_Pos (7U)
#define FDCAN_TEST_RX_Msk (0x1U << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */
#define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */
/***************** Bit definition for FDCAN_RWD register ********************/
#define FDCAN_RWD_WDC_Pos (0U)
#define FDCAN_RWD_WDC_Msk (0xFFU << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */
#define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */
#define FDCAN_RWD_WDV_Pos (8U)
#define FDCAN_RWD_WDV_Msk (0xFFU << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */
#define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */
/***************** Bit definition for FDCAN_CCCR register ********************/
#define FDCAN_CCCR_INIT_Pos (0U)
#define FDCAN_CCCR_INIT_Msk (0x1U << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */
#define FDCAN_CCCR_CCE_Pos (1U)
#define FDCAN_CCCR_CCE_Msk (0x1U << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */
#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */
#define FDCAN_CCCR_ASM_Pos (2U)
#define FDCAN_CCCR_ASM_Msk (0x1U << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */
#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */
#define FDCAN_CCCR_CSA_Pos (3U)
#define FDCAN_CCCR_CSA_Msk (0x1U << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */
#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */
#define FDCAN_CCCR_CSR_Pos (4U)
#define FDCAN_CCCR_CSR_Msk (0x1U << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */
#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */
#define FDCAN_CCCR_MON_Pos (5U)
#define FDCAN_CCCR_MON_Msk (0x1U << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */
#define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */
#define FDCAN_CCCR_DAR_Pos (6U)
#define FDCAN_CCCR_DAR_Msk (0x1U << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */
#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */
#define FDCAN_CCCR_TEST_Pos (7U)
#define FDCAN_CCCR_TEST_Msk (0x1U << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */
#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */
#define FDCAN_CCCR_FDOE_Pos (8U)
#define FDCAN_CCCR_FDOE_Msk (0x1U << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */
#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */
#define FDCAN_CCCR_BRSE_Pos (9U)
#define FDCAN_CCCR_BRSE_Msk (0x1U << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */
#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */
#define FDCAN_CCCR_PXHD_Pos (12U)
#define FDCAN_CCCR_PXHD_Msk (0x1U << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */
#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */
#define FDCAN_CCCR_EFBI_Pos (13U)
#define FDCAN_CCCR_EFBI_Msk (0x1U << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */
#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */
#define FDCAN_CCCR_TXP_Pos (14U)
#define FDCAN_CCCR_TXP_Msk (0x1U << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */
#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */
#define FDCAN_CCCR_NISO_Pos (15U)
#define FDCAN_CCCR_NISO_Msk (0x1U << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */
#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */
/***************** Bit definition for FDCAN_NBTP register ********************/
#define FDCAN_NBTP_NTSEG2_Pos (0U)
#define FDCAN_NBTP_NTSEG2_Msk (0x7FU << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */
#define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */
#define FDCAN_NBTP_NTSEG1_Pos (8U)
#define FDCAN_NBTP_NTSEG1_Msk (0xFFU << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */
#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */
#define FDCAN_NBTP_NBRP_Pos (16U)
#define FDCAN_NBTP_NBRP_Msk (0x1FFU << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */
#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */
#define FDCAN_NBTP_NSJW_Pos (25U)
#define FDCAN_NBTP_NSJW_Msk (0x7FU << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */
#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */
/***************** Bit definition for FDCAN_TSCC register ********************/
#define FDCAN_TSCC_TSS_Pos (0U)
#define FDCAN_TSCC_TSS_Msk (0x3U << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */
#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */
#define FDCAN_TSCC_TCP_Pos (16U)
#define FDCAN_TSCC_TCP_Msk (0xFU << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */
#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */
/***************** Bit definition for FDCAN_TSCV register ********************/
#define FDCAN_TSCV_TSC_Pos (0U)
#define FDCAN_TSCV_TSC_Msk (0xFFFFU << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */
#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */
/***************** Bit definition for FDCAN_TOCC register ********************/
#define FDCAN_TOCC_ETOC_Pos (0U)
#define FDCAN_TOCC_ETOC_Msk (0x1U << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */
#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */
#define FDCAN_TOCC_TOS_Pos (1U)
#define FDCAN_TOCC_TOS_Msk (0x3U << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */
#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */
#define FDCAN_TOCC_TOP_Pos (16U)
#define FDCAN_TOCC_TOP_Msk (0xFFFFU << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */
#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */
/***************** Bit definition for FDCAN_TOCV register ********************/
#define FDCAN_TOCV_TOC_Pos (0U)
#define FDCAN_TOCV_TOC_Msk (0xFFFFU << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */
#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */
/***************** Bit definition for FDCAN_ECR register *********************/
#define FDCAN_ECR_TEC_Pos (0U)
#define FDCAN_ECR_TEC_Msk (0xFFU << FDCAN_ECR_TEC_Pos) /*!< 0x0000000F */
#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
#define FDCAN_ECR_REC_Pos (8U)
#define FDCAN_ECR_REC_Msk (0x7FU << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */
#define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */
#define FDCAN_ECR_RP_Pos (15U)
#define FDCAN_ECR_RP_Msk (0x1U << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */
#define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */
#define FDCAN_ECR_CEL_Pos (16U)
#define FDCAN_ECR_CEL_Msk (0xFFU << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */
#define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */
/***************** Bit definition for FDCAN_PSR register *********************/
#define FDCAN_PSR_LEC_Pos (0U)
#define FDCAN_PSR_LEC_Msk (0x7U << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */
#define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */
#define FDCAN_PSR_ACT_Pos (3U)
#define FDCAN_PSR_ACT_Msk (0x3U << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */
#define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */
#define FDCAN_PSR_EP_Pos (5U)
#define FDCAN_PSR_EP_Msk (0x1U << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */
#define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */
#define FDCAN_PSR_EW_Pos (6U)
#define FDCAN_PSR_EW_Msk (0x1U << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */
#define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */
#define FDCAN_PSR_BO_Pos (7U)
#define FDCAN_PSR_BO_Msk (0x1U << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */
#define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */
#define FDCAN_PSR_DLEC_Pos (8U)
#define FDCAN_PSR_DLEC_Msk (0x7U << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */
#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */
#define FDCAN_PSR_RESI_Pos (11U)
#define FDCAN_PSR_RESI_Msk (0x1U << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */
#define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */
#define FDCAN_PSR_RBRS_Pos (12U)
#define FDCAN_PSR_RBRS_Msk (0x1U << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */
#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */
#define FDCAN_PSR_REDL_Pos (13U)
#define FDCAN_PSR_REDL_Msk (0x1U << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */
#define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */
#define FDCAN_PSR_PXE_Pos (14U)
#define FDCAN_PSR_PXE_Msk (0x1U << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */
#define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */
#define FDCAN_PSR_TDCV_Pos (16U)
#define FDCAN_PSR_TDCV_Msk (0x7FU << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */
#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */
/***************** Bit definition for FDCAN_TDCR register ********************/
#define FDCAN_TDCR_TDCF_Pos (0U)
#define FDCAN_TDCR_TDCF_Msk (0x7FU << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */
#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */
#define FDCAN_TDCR_TDCO_Pos (8U)
#define FDCAN_TDCR_TDCO_Msk (0x7FU << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */
#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */
/***************** Bit definition for FDCAN_IR register **********************/
#define FDCAN_IR_RF0N_Pos (0U)
#define FDCAN_IR_RF0N_Msk (0x1U << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */
#define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */
#define FDCAN_IR_RF0W_Pos (1U)
#define FDCAN_IR_RF0W_Msk (0x1U << FDCAN_IR_RF0W_Pos) /*!< 0x00000002 */
#define FDCAN_IR_RF0W FDCAN_IR_RF0W_Msk /*!<Rx FIFO 0 Watermark Reached */
#define FDCAN_IR_RF0F_Pos (2U)
#define FDCAN_IR_RF0F_Msk (0x1U << FDCAN_IR_RF0F_Pos) /*!< 0x00000004 */
#define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */
#define FDCAN_IR_RF0L_Pos (3U)
#define FDCAN_IR_RF0L_Msk (0x1U << FDCAN_IR_RF0L_Pos) /*!< 0x00000008 */
#define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
#define FDCAN_IR_RF1N_Pos (4U)
#define FDCAN_IR_RF1N_Msk (0x1U << FDCAN_IR_RF1N_Pos) /*!< 0x00000010 */
#define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */
#define FDCAN_IR_RF1W_Pos (5U)
#define FDCAN_IR_RF1W_Msk (0x1U << FDCAN_IR_RF1W_Pos) /*!< 0x00000020 */
#define FDCAN_IR_RF1W FDCAN_IR_RF1W_Msk /*!<Rx FIFO 1 Watermark Reached */
#define FDCAN_IR_RF1F_Pos (6U)
#define FDCAN_IR_RF1F_Msk (0x1U << FDCAN_IR_RF1F_Pos) /*!< 0x00000040 */
#define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */
#define FDCAN_IR_RF1L_Pos (7U)
#define FDCAN_IR_RF1L_Msk (0x1U << FDCAN_IR_RF1L_Pos) /*!< 0x00000080 */
#define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
#define FDCAN_IR_HPM_Pos (8U)
#define FDCAN_IR_HPM_Msk (0x1U << FDCAN_IR_HPM_Pos) /*!< 0x00000100 */
#define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */
#define FDCAN_IR_TC_Pos (9U)
#define FDCAN_IR_TC_Msk (0x1U << FDCAN_IR_TC_Pos) /*!< 0x00000200 */
#define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */
#define FDCAN_IR_TCF_Pos (10U)
#define FDCAN_IR_TCF_Msk (0x1U << FDCAN_IR_TCF_Pos) /*!< 0x00000400 */
#define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */
#define FDCAN_IR_TFE_Pos (11U)
#define FDCAN_IR_TFE_Msk (0x1U << FDCAN_IR_TFE_Pos) /*!< 0x00000800 */
#define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */
#define FDCAN_IR_TEFN_Pos (12U)
#define FDCAN_IR_TEFN_Msk (0x1U << FDCAN_IR_TEFN_Pos) /*!< 0x00001000 */
#define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */
#define FDCAN_IR_TEFW_Pos (13U)
#define FDCAN_IR_TEFW_Msk (0x1U << FDCAN_IR_TEFW_Pos) /*!< 0x00002000 */
#define FDCAN_IR_TEFW FDCAN_IR_TEFW_Msk /*!<Tx Event FIFO Watermark Reached */
#define FDCAN_IR_TEFF_Pos (14U)
#define FDCAN_IR_TEFF_Msk (0x1U << FDCAN_IR_TEFF_Pos) /*!< 0x00004000 */
#define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */
#define FDCAN_IR_TEFL_Pos (15U)
#define FDCAN_IR_TEFL_Msk (0x1U << FDCAN_IR_TEFL_Pos) /*!< 0x00008000 */
#define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */
#define FDCAN_IR_TSW_Pos (16U)
#define FDCAN_IR_TSW_Msk (0x1U << FDCAN_IR_TSW_Pos) /*!< 0x00010000 */
#define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */
#define FDCAN_IR_MRAF_Pos (17U)
#define FDCAN_IR_MRAF_Msk (0x1U << FDCAN_IR_MRAF_Pos) /*!< 0x00020000 */
#define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */
#define FDCAN_IR_TOO_Pos (18U)
#define FDCAN_IR_TOO_Msk (0x1U << FDCAN_IR_TOO_Pos) /*!< 0x00040000 */
#define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */
#define FDCAN_IR_DRX_Pos (19U)
#define FDCAN_IR_DRX_Msk (0x1U << FDCAN_IR_DRX_Pos) /*!< 0x00080000 */
#define FDCAN_IR_DRX FDCAN_IR_DRX_Msk /*!<Message stored to Dedicated Rx Buffer */
#define FDCAN_IR_ELO_Pos (22U)
#define FDCAN_IR_ELO_Msk (0x1U << FDCAN_IR_ELO_Pos) /*!< 0x00400000 */
#define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */
#define FDCAN_IR_EP_Pos (23U)
#define FDCAN_IR_EP_Msk (0x1U << FDCAN_IR_EP_Pos) /*!< 0x00800000 */
#define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */
#define FDCAN_IR_EW_Pos (24U)
#define FDCAN_IR_EW_Msk (0x1U << FDCAN_IR_EW_Pos) /*!< 0x01000000 */
#define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */
#define FDCAN_IR_BO_Pos (25U)
#define FDCAN_IR_BO_Msk (0x1U << FDCAN_IR_BO_Pos) /*!< 0x02000000 */
#define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */
#define FDCAN_IR_WDI_Pos (26U)
#define FDCAN_IR_WDI_Msk (0x1U << FDCAN_IR_WDI_Pos) /*!< 0x04000000 */
#define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */
#define FDCAN_IR_PEA_Pos (27U)
#define FDCAN_IR_PEA_Msk (0x1U << FDCAN_IR_PEA_Pos) /*!< 0x08000000 */
#define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */
#define FDCAN_IR_PED_Pos (28U)
#define FDCAN_IR_PED_Msk (0x1U << FDCAN_IR_PED_Pos) /*!< 0x10000000 */
#define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */
#define FDCAN_IR_ARA_Pos (29U)
#define FDCAN_IR_ARA_Msk (0x1U << FDCAN_IR_ARA_Pos) /*!< 0x20000000 */
#define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */
/***************** Bit definition for FDCAN_IE register **********************/
#define FDCAN_IE_RF0NE_Pos (0U)
#define FDCAN_IE_RF0NE_Msk (0x1U << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */
#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */
#define FDCAN_IE_RF0WE_Pos (1U)
#define FDCAN_IE_RF0WE_Msk (0x1U << FDCAN_IE_RF0WE_Pos) /*!< 0x00000002 */
#define FDCAN_IE_RF0WE FDCAN_IE_RF0WE_Msk /*!<Rx FIFO 0 Watermark Reached Enable */
#define FDCAN_IE_RF0FE_Pos (2U)
#define FDCAN_IE_RF0FE_Msk (0x1U << FDCAN_IE_RF0FE_Pos) /*!< 0x00000004 */
#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */
#define FDCAN_IE_RF0LE_Pos (3U)
#define FDCAN_IE_RF0LE_Msk (0x1U << FDCAN_IE_RF0LE_Pos) /*!< 0x00000008 */
#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */
#define FDCAN_IE_RF1NE_Pos (4U)
#define FDCAN_IE_RF1NE_Msk (0x1U << FDCAN_IE_RF1NE_Pos) /*!< 0x00000010 */
#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */
#define FDCAN_IE_RF1WE_Pos (5U)
#define FDCAN_IE_RF1WE_Msk (0x1U << FDCAN_IE_RF1WE_Pos) /*!< 0x00000020 */
#define FDCAN_IE_RF1WE FDCAN_IE_RF1WE_Msk /*!<Rx FIFO 1 Watermark Reached Enable */
#define FDCAN_IE_RF1FE_Pos (6U)
#define FDCAN_IE_RF1FE_Msk (0x1U << FDCAN_IE_RF1FE_Pos) /*!< 0x00000040 */
#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */
#define FDCAN_IE_RF1LE_Pos (7U)
#define FDCAN_IE_RF1LE_Msk (0x1U << FDCAN_IE_RF1LE_Pos) /*!< 0x00000080 */
#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */
#define FDCAN_IE_HPME_Pos (8U)
#define FDCAN_IE_HPME_Msk (0x1U << FDCAN_IE_HPME_Pos) /*!< 0x00000100 */
#define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */
#define FDCAN_IE_TCE_Pos (9U)
#define FDCAN_IE_TCE_Msk (0x1U << FDCAN_IE_TCE_Pos) /*!< 0x00000200 */
#define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */
#define FDCAN_IE_TCFE_Pos (10U)
#define FDCAN_IE_TCFE_Msk (0x1U << FDCAN_IE_TCFE_Pos) /*!< 0x00000400 */
#define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable */
#define FDCAN_IE_TFEE_Pos (11U)
#define FDCAN_IE_TFEE_Msk (0x1U << FDCAN_IE_TFEE_Pos) /*!< 0x00000800 */
#define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */
#define FDCAN_IE_TEFNE_Pos (12U)
#define FDCAN_IE_TEFNE_Msk (0x1U << FDCAN_IE_TEFNE_Pos) /*!< 0x00001000 */
#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */
#define FDCAN_IE_TEFWE_Pos (13U)
#define FDCAN_IE_TEFWE_Msk (0x1U << FDCAN_IE_TEFWE_Pos) /*!< 0x00002000 */
#define FDCAN_IE_TEFWE FDCAN_IE_TEFWE_Msk /*!<Tx Event FIFO Watermark Reached Enable */
#define FDCAN_IE_TEFFE_Pos (14U)
#define FDCAN_IE_TEFFE_Msk (0x1U << FDCAN_IE_TEFFE_Pos) /*!< 0x00004000 */
#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */
#define FDCAN_IE_TEFLE_Pos (15U)
#define FDCAN_IE_TEFLE_Msk (0x1U << FDCAN_IE_TEFLE_Pos) /*!< 0x00008000 */
#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */
#define FDCAN_IE_TSWE_Pos (16U)
#define FDCAN_IE_TSWE_Msk (0x1U << FDCAN_IE_TSWE_Pos) /*!< 0x00010000 */
#define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */
#define FDCAN_IE_MRAFE_Pos (17U)
#define FDCAN_IE_MRAFE_Msk (0x1U << FDCAN_IE_MRAFE_Pos) /*!< 0x00020000 */
#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */
#define FDCAN_IE_TOOE_Pos (18U)
#define FDCAN_IE_TOOE_Msk (0x1U << FDCAN_IE_TOOE_Pos) /*!< 0x00040000 */
#define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */
#define FDCAN_IE_DRXE_Pos (19U)
#define FDCAN_IE_DRXE_Msk (0x1U << FDCAN_IE_DRXE_Pos) /*!< 0x00080000 */
#define FDCAN_IE_DRXE FDCAN_IE_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Enable */
#define FDCAN_IE_ELOE_Pos (22U)
#define FDCAN_IE_ELOE_Msk (0x1U << FDCAN_IE_ELOE_Pos) /*!< 0x00400000 */
#define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */
#define FDCAN_IE_EPE_Pos (23U)
#define FDCAN_IE_EPE_Msk (0x1U << FDCAN_IE_EPE_Pos) /*!< 0x00800000 */
#define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */
#define FDCAN_IE_EWE_Pos (24U)
#define FDCAN_IE_EWE_Msk (0x1U << FDCAN_IE_EWE_Pos) /*!< 0x01000000 */
#define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */
#define FDCAN_IE_BOE_Pos (25U)
#define FDCAN_IE_BOE_Msk (0x1U << FDCAN_IE_BOE_Pos) /*!< 0x02000000 */
#define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */
#define FDCAN_IE_WDIE_Pos (26U)
#define FDCAN_IE_WDIE_Msk (0x1U << FDCAN_IE_WDIE_Pos) /*!< 0x04000000 */
#define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */
#define FDCAN_IE_PEAE_Pos (27U)
#define FDCAN_IE_PEAE_Msk (0x1U << FDCAN_IE_PEAE_Pos) /*!< 0x08000000 */
#define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable */
#define FDCAN_IE_PEDE_Pos (28U)
#define FDCAN_IE_PEDE_Msk (0x1U << FDCAN_IE_PEDE_Pos) /*!< 0x10000000 */
#define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */
#define FDCAN_IE_ARAE_Pos (29U)
#define FDCAN_IE_ARAE_Msk (0x1U << FDCAN_IE_ARAE_Pos) /*!< 0x20000000 */
#define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */
/***************** Bit definition for FDCAN_ILS register **********************/
#define FDCAN_ILS_RF0NL_Pos (0U)
#define FDCAN_ILS_RF0NL_Msk (0x1U << FDCAN_ILS_RF0NL_Pos) /*!< 0x00000001 */
#define FDCAN_ILS_RF0NL FDCAN_ILS_RF0NL_Msk /*!<Rx FIFO 0 New Message Line */
#define FDCAN_ILS_RF0WL_Pos (1U)
#define FDCAN_ILS_RF0WL_Msk (0x1U << FDCAN_ILS_RF0WL_Pos) /*!< 0x00000002 */
#define FDCAN_ILS_RF0WL FDCAN_ILS_RF0WL_Msk /*!<Rx FIFO 0 Watermark Reached Line */
#define FDCAN_ILS_RF0FL_Pos (2U)
#define FDCAN_ILS_RF0FL_Msk (0x1U << FDCAN_ILS_RF0FL_Pos) /*!< 0x00000004 */
#define FDCAN_ILS_RF0FL FDCAN_ILS_RF0FL_Msk /*!<Rx FIFO 0 Full Line */
#define FDCAN_ILS_RF0LL_Pos (3U)
#define FDCAN_ILS_RF0LL_Msk (0x1U << FDCAN_ILS_RF0LL_Pos) /*!< 0x00000008 */
#define FDCAN_ILS_RF0LL FDCAN_ILS_RF0LL_Msk /*!<Rx FIFO 0 Message Lost Line */
#define FDCAN_ILS_RF1NL_Pos (4U)
#define FDCAN_ILS_RF1NL_Msk (0x1U << FDCAN_ILS_RF1NL_Pos) /*!< 0x00000010 */
#define FDCAN_ILS_RF1NL FDCAN_ILS_RF1NL_Msk /*!<Rx FIFO 1 New Message Line */
#define FDCAN_ILS_RF1WL_Pos (5U)
#define FDCAN_ILS_RF1WL_Msk (0x1U << FDCAN_ILS_RF1WL_Pos) /*!< 0x00000020 */
#define FDCAN_ILS_RF1WL FDCAN_ILS_RF1WL_Msk /*!<Rx FIFO 1 Watermark Reached Line */
#define FDCAN_ILS_RF1FL_Pos (6U)
#define FDCAN_ILS_RF1FL_Msk (0x1U << FDCAN_ILS_RF1FL_Pos) /*!< 0x00000040 */
#define FDCAN_ILS_RF1FL FDCAN_ILS_RF1FL_Msk /*!<Rx FIFO 1 Full Line */
#define FDCAN_ILS_RF1LL_Pos (7U)
#define FDCAN_ILS_RF1LL_Msk (0x1U << FDCAN_ILS_RF1LL_Pos) /*!< 0x00000080 */
#define FDCAN_ILS_RF1LL FDCAN_ILS_RF1LL_Msk /*!<Rx FIFO 1 Message Lost Line */
#define FDCAN_ILS_HPML_Pos (8U)
#define FDCAN_ILS_HPML_Msk (0x1U << FDCAN_ILS_HPML_Pos) /*!< 0x00000100 */
#define FDCAN_ILS_HPML FDCAN_ILS_HPML_Msk /*!<High Priority Message Line */
#define FDCAN_ILS_TCL_Pos (9U)
#define FDCAN_ILS_TCL_Msk (0x1U << FDCAN_ILS_TCL_Pos) /*!< 0x00000200 */
#define FDCAN_ILS_TCL FDCAN_ILS_TCL_Msk /*!<Transmission Completed Line */
#define FDCAN_ILS_TCFL_Pos (10U)
#define FDCAN_ILS_TCFL_Msk (0x1U << FDCAN_ILS_TCFL_Pos) /*!< 0x00000400 */
#define FDCAN_ILS_TCFL FDCAN_ILS_TCFL_Msk /*!<Transmission Cancellation Finished Line */
#define FDCAN_ILS_TFEL_Pos (11U)
#define FDCAN_ILS_TFEL_Msk (0x1U << FDCAN_ILS_TFEL_Pos) /*!< 0x00000800 */
#define FDCAN_ILS_TFEL FDCAN_ILS_TFEL_Msk /*!<Tx FIFO Empty Line */
#define FDCAN_ILS_TEFNL_Pos (12U)
#define FDCAN_ILS_TEFNL_Msk (0x1U << FDCAN_ILS_TEFNL_Pos) /*!< 0x00001000 */
#define FDCAN_ILS_TEFNL FDCAN_ILS_TEFNL_Msk /*!<Tx Event FIFO New Entry Line */
#define FDCAN_ILS_TEFWL_Pos (13U)
#define FDCAN_ILS_TEFWL_Msk (0x1U << FDCAN_ILS_TEFWL_Pos) /*!< 0x00002000 */
#define FDCAN_ILS_TEFWL FDCAN_ILS_TEFWL_Msk /*!<Tx Event FIFO Watermark Reached Line */
#define FDCAN_ILS_TEFFL_Pos (14U)
#define FDCAN_ILS_TEFFL_Msk (0x1U << FDCAN_ILS_TEFFL_Pos) /*!< 0x00004000 */
#define FDCAN_ILS_TEFFL FDCAN_ILS_TEFFL_Msk /*!<Tx Event FIFO Full Line */
#define FDCAN_ILS_TEFLL_Pos (15U)
#define FDCAN_ILS_TEFLL_Msk (0x1U << FDCAN_ILS_TEFLL_Pos) /*!< 0x00008000 */
#define FDCAN_ILS_TEFLL FDCAN_ILS_TEFLL_Msk /*!<Tx Event FIFO Element Lost Line */
#define FDCAN_ILS_TSWL_Pos (16U)
#define FDCAN_ILS_TSWL_Msk (0x1U << FDCAN_ILS_TSWL_Pos) /*!< 0x00010000 */
#define FDCAN_ILS_TSWL FDCAN_ILS_TSWL_Msk /*!<Timestamp Wraparound Line */
#define FDCAN_ILS_MRAFL_Pos (17U)
#define FDCAN_ILS_MRAFL_Msk (0x1U << FDCAN_ILS_MRAFL_Pos) /*!< 0x00020000 */
#define FDCAN_ILS_MRAFL FDCAN_ILS_MRAFL_Msk /*!<Message RAM Access Failure Line */
#define FDCAN_ILS_TOOL_Pos (18U)
#define FDCAN_ILS_TOOL_Msk (0x1U << FDCAN_ILS_TOOL_Pos) /*!< 0x00040000 */
#define FDCAN_ILS_TOOL FDCAN_ILS_TOOL_Msk /*!<Timeout Occurred Line */
#define FDCAN_ILS_DRXL_Pos (19U)
#define FDCAN_ILS_DRXL_Msk (0x1U << FDCAN_ILS_DRXL_Pos) /*!< 0x00080000 */
#define FDCAN_ILS_DRXL FDCAN_ILS_DRXL_Msk /*!<Message stored to Dedicated Rx Buffer Line */
#define FDCAN_ILS_ELOL_Pos (22U)
#define FDCAN_ILS_ELOL_Msk (0x1U << FDCAN_ILS_ELOL_Pos) /*!< 0x00400000 */
#define FDCAN_ILS_ELOL FDCAN_ILS_ELOL_Msk /*!<Error Logging Overflow Line */
#define FDCAN_ILS_EPL_Pos (23U)
#define FDCAN_ILS_EPL_Msk (0x1U << FDCAN_ILS_EPL_Pos) /*!< 0x00800000 */
#define FDCAN_ILS_EPL FDCAN_ILS_EPL_Msk /*!<Error Passive Line */
#define FDCAN_ILS_EWL_Pos (24U)
#define FDCAN_ILS_EWL_Msk (0x1U << FDCAN_ILS_EWL_Pos) /*!< 0x01000000 */
#define FDCAN_ILS_EWL FDCAN_ILS_EWL_Msk /*!<Warning Status Line */
#define FDCAN_ILS_BOL_Pos (25U)
#define FDCAN_ILS_BOL_Msk (0x1U << FDCAN_ILS_BOL_Pos) /*!< 0x02000000 */
#define FDCAN_ILS_BOL FDCAN_ILS_BOL_Msk /*!<Bus_Off Status Line */
#define FDCAN_ILS_WDIL_Pos (26U)
#define FDCAN_ILS_WDIL_Msk (0x1U << FDCAN_ILS_WDIL_Pos) /*!< 0x04000000 */
#define FDCAN_ILS_WDIL FDCAN_ILS_WDIL_Msk /*!<Watchdog Interrupt Line */
#define FDCAN_ILS_PEAL_Pos (27U)
#define FDCAN_ILS_PEAL_Msk (0x1U << FDCAN_ILS_PEAL_Pos) /*!< 0x08000000 */
#define FDCAN_ILS_PEAL FDCAN_ILS_PEAL_Msk /*!<Protocol Error in Arbitration Phase Line */
#define FDCAN_ILS_PEDL_Pos (28U)
#define FDCAN_ILS_PEDL_Msk (0x1U << FDCAN_ILS_PEDL_Pos) /*!< 0x10000000 */
#define FDCAN_ILS_PEDL FDCAN_ILS_PEDL_Msk /*!<Protocol Error in Data Phase Line */
#define FDCAN_ILS_ARAL_Pos (29U)
#define FDCAN_ILS_ARAL_Msk (0x1U << FDCAN_ILS_ARAL_Pos) /*!< 0x20000000 */
#define FDCAN_ILS_ARAL FDCAN_ILS_ARAL_Msk /*!<Access to Reserved Address Line */
/** @defgroup FDCAN_Interrupt_Group FDCAN interrupt group
* @{
*/
#define FDCAN_IT_GROUP_RX_FIFO0 FDCAN_ILS_RF0NL|FDCAN_ILS_RF0FL|FDCAN_ILS_RF0LL|FDCAN_ILS_RF0WL
/*!< RX FIFO 0 Interrupts Group:
RF0LL: Rx FIFO 0 Message Lost
RF0FL: Rx FIFO 0 is Full
RF0NL: Rx FIFO 0 Has New Message */
#define FDCAN_IT_GROUP_RX_FIFO1 FDCAN_ILS_RF1NL|FDCAN_ILS_RF1FL|FDCAN_ILS_RF1LL|FDCAN_ILS_RF1WL
/*!< RX FIFO 1 Interrupts Group:
RF1LL: Rx FIFO 1 Message Lost
RF1FL: Rx FIFO 1 is Full
RF1NL: Rx FIFO 1 Has New Message */
#define FDCAN_IT_GROUP_SMSG FDCAN_ILS_HPML|FDCAN_ILS_TCL|FDCAN_ILS_TCFL
/*!< Status Message Interrupts Group:
TCFL: Transmission Cancellation Finished
TCL: Transmission Completed
HPML: High Priority Message */
#define FDCAN_IT_GROUP_TX_FIFO_ERROR FDCAN_ILS_TFEL|FDCAN_ILS_TEFNL|FDCAN_ILS_TEFWL|FDCAN_ILS_TEFLL
/*!< TX FIFO Error Interrupts Group:
TEFLL: Tx Event FIFO Element Lost
TEFFL: Tx Event FIFO Full
TEFNL: Tx Event FIFO New Entry
TFEL: Tx FIFO Empty Interrupt Line */
#define FDCAN_IT_GROUP_MISC FDCAN_ILS_TSWL|FDCAN_ILS_MRAFL|FDCAN_ILS_TOOL|FDCAN_ILS_DRXL
/*!< Misc. Interrupts Group:
TOOL: Timeout Occurred
MRAFL: Message RAM Access Failure
TSWL: Timestamp Wraparound */
#define FDCAN_IT_GROUP_BIT_LINE_ERROR FDCAN_ILS_ELOL|FDCAN_ILS_EPL
/*!< Bit and Line Error Interrupts Group:
EPL: Error Passive
ELOL: Error Logging Overflow */
#define FDCAN_IT_GROUP_PROTOCOL_ERROR FDCAN_ILS_EWL|FDCAN_ILS_BOL|FDCAN_ILS_WDIL|FDCAN_ILS_PEAL|FDCAN_ILS_PEDL|FDCAN_ILS_ARAL
/*!< Protocol Error Group:
ARAL: Access to Reserved Address Line
PEDL: Protocol Error in Data Phase Line
PEAL: Protocol Error in Arbitration Phase Line
WDIL: Watchdog Interrupt Line
BOL: Bus_Off Status
EWL: Warning Status */
/**
* @}
*/
/***************** Bit definition for FDCAN_ILE register **********************/
#define FDCAN_ILE_EINT0_Pos (0U)
#define FDCAN_ILE_EINT0_Msk (0x1U << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */
#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */
#define FDCAN_ILE_EINT1_Pos (1U)
#define FDCAN_ILE_EINT1_Msk (0x1U << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */
#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */
/***************** Bit definition for FDCAN_GFC register **********************/
#define FDCAN_GFC_RRFE_Pos (0U)
#define FDCAN_GFC_RRFE_Msk (0x1U << FDCAN_GFC_RRFE_Pos) /*!< 0x00000001 */
#define FDCAN_GFC_RRFE FDCAN_GFC_RRFE_Msk /*!<Reject Remote Frames Extended */
#define FDCAN_GFC_RRFS_Pos (1U)
#define FDCAN_GFC_RRFS_Msk (0x1U << FDCAN_GFC_RRFS_Pos) /*!< 0x00000002 */
#define FDCAN_GFC_RRFS FDCAN_GFC_RRFS_Msk /*!<Reject Remote Frames Standard */
#define FDCAN_GFC_ANFE_Pos (2U)
#define FDCAN_GFC_ANFE_Msk (0x3U << FDCAN_GFC_ANFE_Pos) /*!< 0x0000000C */
#define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */
#define FDCAN_GFC_ANFS_Pos (4U)
#define FDCAN_GFC_ANFS_Msk (0x3U << FDCAN_GFC_ANFS_Pos) /*!< 0x00000030 */
#define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */
/***************** Bit definition for FDCAN_SIDFC register ********************/
#define FDCAN_SIDFC_FLSSA_Pos (2U)
#define FDCAN_SIDFC_FLSSA_Msk (0x3FFFU << FDCAN_SIDFC_FLSSA_Pos) /*!< 0x0000FFFC */
#define FDCAN_SIDFC_FLSSA FDCAN_SIDFC_FLSSA_Msk /*!<Filter List Standard Start Address */
#define FDCAN_SIDFC_LSS_Pos (16U)
#define FDCAN_SIDFC_LSS_Msk (0xFFU << FDCAN_SIDFC_LSS_Pos) /*!< 0x00FF0000 */
#define FDCAN_SIDFC_LSS FDCAN_SIDFC_LSS_Msk /*!<List Size Standard */
/***************** Bit definition for FDCAN_XIDFC register ********************/
#define FDCAN_XIDFC_FLESA_Pos (2U)
#define FDCAN_XIDFC_FLESA_Msk (0x3FFFU << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
#define FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_Msk /*!<Filter List Standard Start Address */
#define FDCAN_XIDFC_LSE_Pos (16U)
#define FDCAN_XIDFC_LSE_Msk (0xFFU << FDCAN_XIDFC_LSE_Pos) /*!< 0x00FF0000 */
#define FDCAN_XIDFC_LSE FDCAN_XIDFC_LSE_Msk /*!<List Size Extended */
/***************** Bit definition for FDCAN_XIDAM register ********************/
#define FDCAN_XIDAM_EIDM_Pos (0U)
#define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFU << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */
#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */
/***************** Bit definition for FDCAN_HPMS register *********************/
#define FDCAN_HPMS_BIDX_Pos (0U)
#define FDCAN_HPMS_BIDX_Msk (0x3FU << FDCAN_HPMS_BIDX_Pos) /*!< 0x0000003F */
#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */
#define FDCAN_HPMS_MSI_Pos (6U)
#define FDCAN_HPMS_MSI_Msk (0x3U << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */
#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */
#define FDCAN_HPMS_FIDX_Pos (8U)
#define FDCAN_HPMS_FIDX_Msk (0x7FU << FDCAN_HPMS_FIDX_Pos) /*!< 0x00007F00 */
#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */
#define FDCAN_HPMS_FLST_Pos (15U)
#define FDCAN_HPMS_FLST_Msk (0x1U << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */
#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */
/***************** Bit definition for FDCAN_NDAT1 register ********************/
#define FDCAN_NDAT1_ND0_Pos (0U)
#define FDCAN_NDAT1_ND0_Msk (0x1U << FDCAN_NDAT1_ND0_Pos) /*!< 0x00000001 */
#define FDCAN_NDAT1_ND0 FDCAN_NDAT1_ND0_Msk /*!<New Data flag of Rx Buffer 0 */
#define FDCAN_NDAT1_ND1_Pos (1U)
#define FDCAN_NDAT1_ND1_Msk (0x1U << FDCAN_NDAT1_ND1_Pos) /*!< 0x00000002 */
#define FDCAN_NDAT1_ND1 FDCAN_NDAT1_ND1_Msk /*!<New Data flag of Rx Buffer 1 */
#define FDCAN_NDAT1_ND2_Pos (2U)
#define FDCAN_NDAT1_ND2_Msk (0x1U << FDCAN_NDAT1_ND2_Pos) /*!< 0x00000004 */
#define FDCAN_NDAT1_ND2 FDCAN_NDAT1_ND2_Msk /*!<New Data flag of Rx Buffer 2 */
#define FDCAN_NDAT1_ND3_Pos (3U)
#define FDCAN_NDAT1_ND3_Msk (0x1U << FDCAN_NDAT1_ND3_Pos) /*!< 0x00000008 */
#define FDCAN_NDAT1_ND3 FDCAN_NDAT1_ND3_Msk /*!<New Data flag of Rx Buffer 3 */
#define FDCAN_NDAT1_ND4_Pos (4U)
#define FDCAN_NDAT1_ND4_Msk (0x1U << FDCAN_NDAT1_ND4_Pos) /*!< 0x00000010 */
#define FDCAN_NDAT1_ND4 FDCAN_NDAT1_ND4_Msk /*!<New Data flag of Rx Buffer 4 */
#define FDCAN_NDAT1_ND5_Pos (5U)
#define FDCAN_NDAT1_ND5_Msk (0x1U << FDCAN_NDAT1_ND5_Pos) /*!< 0x00000020 */
#define FDCAN_NDAT1_ND5 FDCAN_NDAT1_ND5_Msk /*!<New Data flag of Rx Buffer 5 */
#define FDCAN_NDAT1_ND6_Pos (6U)
#define FDCAN_NDAT1_ND6_Msk (0x1U << FDCAN_NDAT1_ND6_Pos) /*!< 0x00000040 */
#define FDCAN_NDAT1_ND6 FDCAN_NDAT1_ND6_Msk /*!<New Data flag of Rx Buffer 6 */
#define FDCAN_NDAT1_ND7_Pos (7U)
#define FDCAN_NDAT1_ND7_Msk (0x1U << FDCAN_NDAT1_ND7_Pos) /*!< 0x00000080 */
#define FDCAN_NDAT1_ND7 FDCAN_NDAT1_ND7_Msk /*!<New Data flag of Rx Buffer 7 */
#define FDCAN_NDAT1_ND8_Pos (8U)
#define FDCAN_NDAT1_ND8_Msk (0x1U << FDCAN_NDAT1_ND8_Pos) /*!< 0x00000100 */
#define FDCAN_NDAT1_ND8 FDCAN_NDAT1_ND8_Msk /*!<New Data flag of Rx Buffer 8 */
#define FDCAN_NDAT1_ND9_Pos (9U)
#define FDCAN_NDAT1_ND9_Msk (0x1U << FDCAN_NDAT1_ND9_Pos) /*!< 0x00000200 */
#define FDCAN_NDAT1_ND9 FDCAN_NDAT1_ND9_Msk /*!<New Data flag of Rx Buffer 9 */
#define FDCAN_NDAT1_ND10_Pos (10U)
#define FDCAN_NDAT1_ND10_Msk (0x1U << FDCAN_NDAT1_ND10_Pos) /*!< 0x00000400 */
#define FDCAN_NDAT1_ND10 FDCAN_NDAT1_ND10_Msk /*!<New Data flag of Rx Buffer 10 */
#define FDCAN_NDAT1_ND11_Pos (11U)
#define FDCAN_NDAT1_ND11_Msk (0x1U << FDCAN_NDAT1_ND11_Pos) /*!< 0x00000800 */
#define FDCAN_NDAT1_ND11 FDCAN_NDAT1_ND11_Msk /*!<New Data flag of Rx Buffer 11 */
#define FDCAN_NDAT1_ND12_Pos (12U)
#define FDCAN_NDAT1_ND12_Msk (0x1U << FDCAN_NDAT1_ND12_Pos) /*!< 0x00001000 */
#define FDCAN_NDAT1_ND12 FDCAN_NDAT1_ND12_Msk /*!<New Data flag of Rx Buffer 12 */
#define FDCAN_NDAT1_ND13_Pos (13U)
#define FDCAN_NDAT1_ND13_Msk (0x1U << FDCAN_NDAT1_ND13_Pos) /*!< 0x00002000 */
#define FDCAN_NDAT1_ND13 FDCAN_NDAT1_ND13_Msk /*!<New Data flag of Rx Buffer 13 */
#define FDCAN_NDAT1_ND14_Pos (14U)
#define FDCAN_NDAT1_ND14_Msk (0x1U << FDCAN_NDAT1_ND14_Pos) /*!< 0x00004000 */
#define FDCAN_NDAT1_ND14 FDCAN_NDAT1_ND14_Msk /*!<New Data flag of Rx Buffer 14 */
#define FDCAN_NDAT1_ND15_Pos (15U)
#define FDCAN_NDAT1_ND15_Msk (0x1U << FDCAN_NDAT1_ND15_Pos) /*!< 0x00008000 */
#define FDCAN_NDAT1_ND15 FDCAN_NDAT1_ND15_Msk /*!<New Data flag of Rx Buffer 15 */
#define FDCAN_NDAT1_ND16_Pos (16U)
#define FDCAN_NDAT1_ND16_Msk (0x1U << FDCAN_NDAT1_ND16_Pos) /*!< 0x00010000 */
#define FDCAN_NDAT1_ND16 FDCAN_NDAT1_ND16_Msk /*!<New Data flag of Rx Buffer 16 */
#define FDCAN_NDAT1_ND17_Pos (17U)
#define FDCAN_NDAT1_ND17_Msk (0x1U << FDCAN_NDAT1_ND17_Pos) /*!< 0x00020000 */
#define FDCAN_NDAT1_ND17 FDCAN_NDAT1_ND17_Msk /*!<New Data flag of Rx Buffer 17 */
#define FDCAN_NDAT1_ND18_Pos (18U)
#define FDCAN_NDAT1_ND18_Msk (0x1U << FDCAN_NDAT1_ND18_Pos) /*!< 0x00040000 */
#define FDCAN_NDAT1_ND18 FDCAN_NDAT1_ND18_Msk /*!<New Data flag of Rx Buffer 18 */
#define FDCAN_NDAT1_ND19_Pos (19U)
#define FDCAN_NDAT1_ND19_Msk (0x1U << FDCAN_NDAT1_ND19_Pos) /*!< 0x00080000 */
#define FDCAN_NDAT1_ND19 FDCAN_NDAT1_ND19_Msk /*!<New Data flag of Rx Buffer 19 */
#define FDCAN_NDAT1_ND20_Pos (20U)
#define FDCAN_NDAT1_ND20_Msk (0x1U << FDCAN_NDAT1_ND20_Pos) /*!< 0x00100000 */
#define FDCAN_NDAT1_ND20 FDCAN_NDAT1_ND20_Msk /*!<New Data flag of Rx Buffer 20 */
#define FDCAN_NDAT1_ND21_Pos (21U)
#define FDCAN_NDAT1_ND21_Msk (0x1U << FDCAN_NDAT1_ND21_Pos) /*!< 0x00200000 */
#define FDCAN_NDAT1_ND21 FDCAN_NDAT1_ND21_Msk /*!<New Data flag of Rx Buffer 21 */
#define FDCAN_NDAT1_ND22_Pos (22U)
#define FDCAN_NDAT1_ND22_Msk (0x1U << FDCAN_NDAT1_ND22_Pos) /*!< 0x00400000 */
#define FDCAN_NDAT1_ND22 FDCAN_NDAT1_ND22_Msk /*!<New Data flag of Rx Buffer 22 */
#define FDCAN_NDAT1_ND23_Pos (23U)
#define FDCAN_NDAT1_ND23_Msk (0x1U << FDCAN_NDAT1_ND23_Pos) /*!< 0x00800000 */
#define FDCAN_NDAT1_ND23 FDCAN_NDAT1_ND23_Msk /*!<New Data flag of Rx Buffer 23 */
#define FDCAN_NDAT1_ND24_Pos (24U)
#define FDCAN_NDAT1_ND24_Msk (0x1U << FDCAN_NDAT1_ND24_Pos) /*!< 0x01000000 */
#define FDCAN_NDAT1_ND24 FDCAN_NDAT1_ND24_Msk /*!<New Data flag of Rx Buffer 24 */
#define FDCAN_NDAT1_ND25_Pos (25U)
#define FDCAN_NDAT1_ND25_Msk (0x1U << FDCAN_NDAT1_ND25_Pos) /*!< 0x02000000 */
#define FDCAN_NDAT1_ND25 FDCAN_NDAT1_ND25_Msk /*!<New Data flag of Rx Buffer 25 */
#define FDCAN_NDAT1_ND26_Pos (26U)
#define FDCAN_NDAT1_ND26_Msk (0x1U << FDCAN_NDAT1_ND26_Pos) /*!< 0x04000000 */
#define FDCAN_NDAT1_ND26 FDCAN_NDAT1_ND26_Msk /*!<New Data flag of Rx Buffer 26 */
#define FDCAN_NDAT1_ND27_Pos (27U)
#define FDCAN_NDAT1_ND27_Msk (0x1U << FDCAN_NDAT1_ND27_Pos) /*!< 0x08000000 */
#define FDCAN_NDAT1_ND27 FDCAN_NDAT1_ND27_Msk /*!<New Data flag of Rx Buffer 27 */
#define FDCAN_NDAT1_ND28_Pos (28U)
#define FDCAN_NDAT1_ND28_Msk (0x1U << FDCAN_NDAT1_ND28_Pos) /*!< 0x10000000 */
#define FDCAN_NDAT1_ND28 FDCAN_NDAT1_ND28_Msk /*!<New Data flag of Rx Buffer 28 */
#define FDCAN_NDAT1_ND29_Pos (29U)
#define FDCAN_NDAT1_ND29_Msk (0x1U << FDCAN_NDAT1_ND29_Pos) /*!< 0x20000000 */
#define FDCAN_NDAT1_ND29 FDCAN_NDAT1_ND29_Msk /*!<New Data flag of Rx Buffer 29 */
#define FDCAN_NDAT1_ND30_Pos (30U)
#define FDCAN_NDAT1_ND30_Msk (0x1U << FDCAN_NDAT1_ND30_Pos) /*!< 0x40000000 */
#define FDCAN_NDAT1_ND30 FDCAN_NDAT1_ND30_Msk /*!<New Data flag of Rx Buffer 30 */
#define FDCAN_NDAT1_ND31_Pos (31U)
#define FDCAN_NDAT1_ND31_Msk (0x1U << FDCAN_NDAT1_ND31_Pos) /*!< 0x80000000 */
#define FDCAN_NDAT1_ND31 FDCAN_NDAT1_ND31_Msk /*!<New Data flag of Rx Buffer 31 */
/***************** Bit definition for FDCAN_NDAT2 register ********************/
#define FDCAN_NDAT2_ND32_Pos (0U)
#define FDCAN_NDAT2_ND32_Msk (0x1U << FDCAN_NDAT2_ND32_Pos) /*!< 0x00000001 */
#define FDCAN_NDAT2_ND32 FDCAN_NDAT2_ND32_Msk /*!<New Data flag of Rx Buffer 32 */
#define FDCAN_NDAT2_ND33_Pos (1U)
#define FDCAN_NDAT2_ND33_Msk (0x1U << FDCAN_NDAT2_ND33_Pos) /*!< 0x00000002 */
#define FDCAN_NDAT2_ND33 FDCAN_NDAT2_ND33_Msk /*!<New Data flag of Rx Buffer 33 */
#define FDCAN_NDAT2_ND34_Pos (2U)
#define FDCAN_NDAT2_ND34_Msk (0x1U << FDCAN_NDAT2_ND34_Pos) /*!< 0x00000004 */
#define FDCAN_NDAT2_ND34 FDCAN_NDAT2_ND34_Msk /*!<New Data flag of Rx Buffer 34 */
#define FDCAN_NDAT2_ND35_Pos (3U)
#define FDCAN_NDAT2_ND35_Msk (0x1U << FDCAN_NDAT2_ND35_Pos) /*!< 0x00000008 */
#define FDCAN_NDAT2_ND35 FDCAN_NDAT2_ND35_Msk /*!<New Data flag of Rx Buffer 35 */
#define FDCAN_NDAT2_ND36_Pos (4U)
#define FDCAN_NDAT2_ND36_Msk (0x1U << FDCAN_NDAT2_ND36_Pos) /*!< 0x00000010 */
#define FDCAN_NDAT2_ND36 FDCAN_NDAT2_ND36_Msk /*!<New Data flag of Rx Buffer 36 */
#define FDCAN_NDAT2_ND37_Pos (5U)
#define FDCAN_NDAT2_ND37_Msk (0x1U << FDCAN_NDAT2_ND37_Pos) /*!< 0x00000020 */
#define FDCAN_NDAT2_ND37 FDCAN_NDAT2_ND37_Msk /*!<New Data flag of Rx Buffer 37 */
#define FDCAN_NDAT2_ND38_Pos (6U)
#define FDCAN_NDAT2_ND38_Msk (0x1U << FDCAN_NDAT2_ND38_Pos) /*!< 0x00000040 */
#define FDCAN_NDAT2_ND38 FDCAN_NDAT2_ND38_Msk /*!<New Data flag of Rx Buffer 38 */
#define FDCAN_NDAT2_ND39_Pos (7U)
#define FDCAN_NDAT2_ND39_Msk (0x1U << FDCAN_NDAT2_ND39_Pos) /*!< 0x00000080 */
#define FDCAN_NDAT2_ND39 FDCAN_NDAT2_ND39_Msk /*!<New Data flag of Rx Buffer 39 */
#define FDCAN_NDAT2_ND40_Pos (8U)
#define FDCAN_NDAT2_ND40_Msk (0x1U << FDCAN_NDAT2_ND40_Pos) /*!< 0x00000100 */
#define FDCAN_NDAT2_ND40 FDCAN_NDAT2_ND40_Msk /*!<New Data flag of Rx Buffer 40 */
#define FDCAN_NDAT2_ND41_Pos (9U)
#define FDCAN_NDAT2_ND41_Msk (0x1U << FDCAN_NDAT2_ND41_Pos) /*!< 0x00000200 */
#define FDCAN_NDAT2_ND41 FDCAN_NDAT2_ND41_Msk /*!<New Data flag of Rx Buffer 41 */
#define FDCAN_NDAT2_ND42_Pos (10U)
#define FDCAN_NDAT2_ND42_Msk (0x1U << FDCAN_NDAT2_ND42_Pos) /*!< 0x00000400 */
#define FDCAN_NDAT2_ND42 FDCAN_NDAT2_ND42_Msk /*!<New Data flag of Rx Buffer 42 */
#define FDCAN_NDAT2_ND43_Pos (11U)
#define FDCAN_NDAT2_ND43_Msk (0x1U << FDCAN_NDAT2_ND43_Pos) /*!< 0x00000800 */
#define FDCAN_NDAT2_ND43 FDCAN_NDAT2_ND43_Msk /*!<New Data flag of Rx Buffer 43 */
#define FDCAN_NDAT2_ND44_Pos (12U)
#define FDCAN_NDAT2_ND44_Msk (0x1U << FDCAN_NDAT2_ND44_Pos) /*!< 0x00001000 */
#define FDCAN_NDAT2_ND44 FDCAN_NDAT2_ND44_Msk /*!<New Data flag of Rx Buffer 44 */
#define FDCAN_NDAT2_ND45_Pos (13U)
#define FDCAN_NDAT2_ND45_Msk (0x1U << FDCAN_NDAT2_ND45_Pos) /*!< 0x00002000 */
#define FDCAN_NDAT2_ND45 FDCAN_NDAT2_ND45_Msk /*!<New Data flag of Rx Buffer 45 */
#define FDCAN_NDAT2_ND46_Pos (14U)
#define FDCAN_NDAT2_ND46_Msk (0x1U << FDCAN_NDAT2_ND46_Pos) /*!< 0x00004000 */
#define FDCAN_NDAT2_ND46 FDCAN_NDAT2_ND46_Msk /*!<New Data flag of Rx Buffer 46 */
#define FDCAN_NDAT2_ND47_Pos (15U)
#define FDCAN_NDAT2_ND47_Msk (0x1U << FDCAN_NDAT2_ND47_Pos) /*!< 0x00008000 */
#define FDCAN_NDAT2_ND47 FDCAN_NDAT2_ND47_Msk /*!<New Data flag of Rx Buffer 47 */
#define FDCAN_NDAT2_ND48_Pos (16U)
#define FDCAN_NDAT2_ND48_Msk (0x1U << FDCAN_NDAT2_ND48_Pos) /*!< 0x00010000 */
#define FDCAN_NDAT2_ND48 FDCAN_NDAT2_ND48_Msk /*!<New Data flag of Rx Buffer 48 */
#define FDCAN_NDAT2_ND49_Pos (17U)
#define FDCAN_NDAT2_ND49_Msk (0x1U << FDCAN_NDAT2_ND49_Pos) /*!< 0x00020000 */
#define FDCAN_NDAT2_ND49 FDCAN_NDAT2_ND49_Msk /*!<New Data flag of Rx Buffer 49 */
#define FDCAN_NDAT2_ND50_Pos (18U)
#define FDCAN_NDAT2_ND50_Msk (0x1U << FDCAN_NDAT2_ND50_Pos) /*!< 0x00040000 */
#define FDCAN_NDAT2_ND50 FDCAN_NDAT2_ND50_Msk /*!<New Data flag of Rx Buffer 50 */
#define FDCAN_NDAT2_ND51_Pos (19U)
#define FDCAN_NDAT2_ND51_Msk (0x1U << FDCAN_NDAT2_ND51_Pos) /*!< 0x00080000 */
#define FDCAN_NDAT2_ND51 FDCAN_NDAT2_ND51_Msk /*!<New Data flag of Rx Buffer 51 */
#define FDCAN_NDAT2_ND52_Pos (20U)
#define FDCAN_NDAT2_ND52_Msk (0x1U << FDCAN_NDAT2_ND52_Pos) /*!< 0x00100000 */
#define FDCAN_NDAT2_ND52 FDCAN_NDAT2_ND52_Msk /*!<New Data flag of Rx Buffer 52 */
#define FDCAN_NDAT2_ND53_Pos (21U)
#define FDCAN_NDAT2_ND53_Msk (0x1U << FDCAN_NDAT2_ND53_Pos) /*!< 0x00200000 */
#define FDCAN_NDAT2_ND53 FDCAN_NDAT2_ND53_Msk /*!<New Data flag of Rx Buffer 53 */
#define FDCAN_NDAT2_ND54_Pos (22U)
#define FDCAN_NDAT2_ND54_Msk (0x1U << FDCAN_NDAT2_ND54_Pos) /*!< 0x00400000 */
#define FDCAN_NDAT2_ND54 FDCAN_NDAT2_ND54_Msk /*!<New Data flag of Rx Buffer 54 */
#define FDCAN_NDAT2_ND55_Pos (23U)
#define FDCAN_NDAT2_ND55_Msk (0x1U << FDCAN_NDAT2_ND55_Pos) /*!< 0x00800000 */
#define FDCAN_NDAT2_ND55 FDCAN_NDAT2_ND55_Msk /*!<New Data flag of Rx Buffer 55 */
#define FDCAN_NDAT2_ND56_Pos (24U)
#define FDCAN_NDAT2_ND56_Msk (0x1U << FDCAN_NDAT2_ND56_Pos) /*!< 0x01000000 */
#define FDCAN_NDAT2_ND56 FDCAN_NDAT2_ND56_Msk /*!<New Data flag of Rx Buffer 56 */
#define FDCAN_NDAT2_ND57_Pos (25U)
#define FDCAN_NDAT2_ND57_Msk (0x1U << FDCAN_NDAT2_ND57_Pos) /*!< 0x02000000 */
#define FDCAN_NDAT2_ND57 FDCAN_NDAT2_ND57_Msk /*!<New Data flag of Rx Buffer 57 */
#define FDCAN_NDAT2_ND58_Pos (26U)
#define FDCAN_NDAT2_ND58_Msk (0x1U << FDCAN_NDAT2_ND58_Pos) /*!< 0x04000000 */
#define FDCAN_NDAT2_ND58 FDCAN_NDAT2_ND58_Msk /*!<New Data flag of Rx Buffer 58 */
#define FDCAN_NDAT2_ND59_Pos (27U)
#define FDCAN_NDAT2_ND59_Msk (0x1U << FDCAN_NDAT2_ND59_Pos) /*!< 0x08000000 */
#define FDCAN_NDAT2_ND59 FDCAN_NDAT2_ND59_Msk /*!<New Data flag of Rx Buffer 59 */
#define FDCAN_NDAT2_ND60_Pos (28U)
#define FDCAN_NDAT2_ND60_Msk (0x1U << FDCAN_NDAT2_ND60_Pos) /*!< 0x10000000 */
#define FDCAN_NDAT2_ND60 FDCAN_NDAT2_ND60_Msk /*!<New Data flag of Rx Buffer 60 */
#define FDCAN_NDAT2_ND61_Pos (29U)
#define FDCAN_NDAT2_ND61_Msk (0x1U << FDCAN_NDAT2_ND61_Pos) /*!< 0x20000000 */
#define FDCAN_NDAT2_ND61 FDCAN_NDAT2_ND61_Msk /*!<New Data flag of Rx Buffer 61 */
#define FDCAN_NDAT2_ND62_Pos (30U)
#define FDCAN_NDAT2_ND62_Msk (0x1U << FDCAN_NDAT2_ND62_Pos) /*!< 0x40000000 */
#define FDCAN_NDAT2_ND62 FDCAN_NDAT2_ND62_Msk /*!<New Data flag of Rx Buffer 62 */
#define FDCAN_NDAT2_ND63_Pos (31U)
#define FDCAN_NDAT2_ND63_Msk (0x1U << FDCAN_NDAT2_ND63_Pos) /*!< 0x80000000 */
#define FDCAN_NDAT2_ND63 FDCAN_NDAT2_ND63_Msk /*!<New Data flag of Rx Buffer 63 */
/***************** Bit definition for FDCAN_RXF0C register ********************/
#define FDCAN_RXF0C_F0SA_Pos (2U)
#define FDCAN_RXF0C_F0SA_Msk (0x3FFFU << FDCAN_RXF0C_F0SA_Pos) /*!< 0x0000FFFC */
#define FDCAN_RXF0C_F0SA FDCAN_RXF0C_F0SA_Msk /*!<Rx FIFO 0 Start Address */
#define FDCAN_RXF0C_F0S_Pos (16U)
#define FDCAN_RXF0C_F0S_Msk (0x7FU << FDCAN_RXF0C_F0S_Pos) /*!< 0x007F0000 */
#define FDCAN_RXF0C_F0S FDCAN_RXF0C_F0S_Msk /*!<Number of Rx FIFO 0 elements */
#define FDCAN_RXF0C_F0WM_Pos (24U)
#define FDCAN_RXF0C_F0WM_Msk (0x7FU << FDCAN_RXF0C_F0WM_Pos) /*!< 0x7F000000 */
#define FDCAN_RXF0C_F0WM FDCAN_RXF0C_F0WM_Msk /*!<FIFO 0 Watermark */
#define FDCAN_RXF0C_F0OM_Pos (31U)
#define FDCAN_RXF0C_F0OM_Msk (0x1U << FDCAN_RXF0C_F0OM_Pos) /*!< 0x80000000 */
#define FDCAN_RXF0C_F0OM FDCAN_RXF0C_F0OM_Msk /*!<FIFO 0 Operation Mode */
/***************** Bit definition for FDCAN_RXF0S register ********************/
#define FDCAN_RXF0S_F0FL_Pos (0U)
#define FDCAN_RXF0S_F0FL_Msk (0x7FU << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000007F */
#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */
#define FDCAN_RXF0S_F0GI_Pos (8U)
#define FDCAN_RXF0S_F0GI_Msk (0x3FU << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00003F00 */
#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */
#define FDCAN_RXF0S_F0PI_Pos (16U)
#define FDCAN_RXF0S_F0PI_Msk (0x3FU << FDCAN_RXF0S_F0PI_Pos) /*!< 0x003F0000 */
#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */
#define FDCAN_RXF0S_F0F_Pos (24U)
#define FDCAN_RXF0S_F0F_Msk (0x1U << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */
#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */
#define FDCAN_RXF0S_RF0L_Pos (25U)
#define FDCAN_RXF0S_RF0L_Msk (0x1U << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */
#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
/***************** Bit definition for FDCAN_RXF0A register ********************/
#define FDCAN_RXF0A_F0AI_Pos (0U)
#define FDCAN_RXF0A_F0AI_Msk (0x3FU << FDCAN_RXF0A_F0AI_Pos) /*!< 0x0000003F */
#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */
/***************** Bit definition for FDCAN_RXBC register ********************/
#define FDCAN_RXBC_RBSA_Pos (2U)
#define FDCAN_RXBC_RBSA_Msk (0x3FFFU << FDCAN_RXBC_RBSA_Pos) /*!< 0x0000FFFC */
#define FDCAN_RXBC_RBSA FDCAN_RXBC_RBSA_Msk /*!<Rx Buffer Start Address */
/***************** Bit definition for FDCAN_RXF1C register ********************/
#define FDCAN_RXF1C_F1SA_Pos (2U)
#define FDCAN_RXF1C_F1SA_Msk (0x3FFFU << FDCAN_RXF1C_F1SA_Pos) /*!< 0x0000FFFC */
#define FDCAN_RXF1C_F1SA FDCAN_RXF1C_F1SA_Msk /*!<Rx FIFO 1 Start Address */
#define FDCAN_RXF1C_F1S_Pos (16U)
#define FDCAN_RXF1C_F1S_Msk (0x7FU << FDCAN_RXF1C_F1S_Pos) /*!< 0x007F0000 */
#define FDCAN_RXF1C_F1S FDCAN_RXF1C_F1S_Msk /*!<Number of Rx FIFO 1 elements */
#define FDCAN_RXF1C_F1WM_Pos (24U)
#define FDCAN_RXF1C_F1WM_Msk (0x7FU << FDCAN_RXF1C_F1WM_Pos) /*!< 0x7F000000 */
#define FDCAN_RXF1C_F1WM FDCAN_RXF1C_F1WM_Msk /*!<Rx FIFO 1 Watermark */
#define FDCAN_RXF1C_F1OM_Pos (31U)
#define FDCAN_RXF1C_F1OM_Msk (0x1U << FDCAN_RXF1C_F1OM_Pos) /*!< 0x80000000 */
#define FDCAN_RXF1C_F1OM FDCAN_RXF1C_F1OM_Msk /*!<FIFO 1 Operation Mode */
/***************** Bit definition for FDCAN_RXF1S register ********************/
#define FDCAN_RXF1S_F1FL_Pos (0U)
#define FDCAN_RXF1S_F1FL_Msk (0x7FU << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000007F */
#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */
#define FDCAN_RXF1S_F1GI_Pos (8U)
#define FDCAN_RXF1S_F1GI_Msk (0x3FU << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00003F00 */
#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */
#define FDCAN_RXF1S_F1PI_Pos (16U)
#define FDCAN_RXF1S_F1PI_Msk (0x3FU << FDCAN_RXF1S_F1PI_Pos) /*!< 0x003F0000 */
#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */
#define FDCAN_RXF1S_F1F_Pos (24U)
#define FDCAN_RXF1S_F1F_Msk (0x1U << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */
#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */
#define FDCAN_RXF1S_RF1L_Pos (25U)
#define FDCAN_RXF1S_RF1L_Msk (0x1U << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */
#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
#define FDCAN_RXF1S_DMS_Pos (30U)
#define FDCAN_RXF1S_DMS_Msk (0x3U << FDCAN_RXF1S_DMS_Pos) /*!< 0xC0000000 */
#define FDCAN_RXF1S_DMS FDCAN_RXF1S_DMS_Msk /*!<Debug Message Status */
/***************** Bit definition for FDCAN_RXF1A register ********************/
#define FDCAN_RXF1A_F1AI_Pos (0U)
#define FDCAN_RXF1A_F1AI_Msk (0x3FU << FDCAN_RXF1A_F1AI_Pos) /*!< 0x0000003F */
#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */
/***************** Bit definition for FDCAN_RXESC register ********************/
#define FDCAN_RXESC_F0DS_Pos (0U)
#define FDCAN_RXESC_F0DS_Msk (0x7U << FDCAN_RXESC_F0DS_Pos) /*!< 0x00000007 */
#define FDCAN_RXESC_F0DS FDCAN_RXESC_F0DS_Msk /*!<Rx FIFO 1 Data Field Size */
#define FDCAN_RXESC_F1DS_Pos (4U)
#define FDCAN_RXESC_F1DS_Msk (0x7U << FDCAN_RXESC_F1DS_Pos) /*!< 0x00000070 */
#define FDCAN_RXESC_F1DS FDCAN_RXESC_F1DS_Msk /*!<Rx FIFO 0 Data Field Size */
#define FDCAN_RXESC_RBDS_Pos (8U)
#define FDCAN_RXESC_RBDS_Msk (0x7U << FDCAN_RXESC_RBDS_Pos) /*!< 0x00000700 */
#define FDCAN_RXESC_RBDS FDCAN_RXESC_RBDS_Msk /*!<Rx Buffer Data Field Size */
/***************** Bit definition for FDCAN_TXBC register *********************/
#define FDCAN_TXBC_TBSA_Pos (2U)
#define FDCAN_TXBC_TBSA_Msk (0x3FFFU << FDCAN_TXBC_TBSA_Pos) /*!< 0x000000FC */
#define FDCAN_TXBC_TBSA FDCAN_TXBC_TBSA_Msk /*!<Tx Buffers Start Address */
#define FDCAN_TXBC_NDTB_Pos (16U)
#define FDCAN_TXBC_NDTB_Msk (0x3FU << FDCAN_TXBC_NDTB_Pos) /*!< 0x003F0000 */
#define FDCAN_TXBC_NDTB FDCAN_TXBC_NDTB_Msk /*!<Number of Dedicated Transmit Buffers */
#define FDCAN_TXBC_TFQS_Pos (24U)
#define FDCAN_TXBC_TFQS_Msk (0x3FU << FDCAN_TXBC_TFQS_Pos) /*!< 0x3F000000 */
#define FDCAN_TXBC_TFQS FDCAN_TXBC_TFQS_Msk /*!<Transmit FIFO/Queue Size */
#define FDCAN_TXBC_TFQM_Pos (30U)
#define FDCAN_TXBC_TFQM_Msk (0x1U << FDCAN_TXBC_TFQM_Pos) /*!< 0x40000000 */
#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */
/***************** Bit definition for FDCAN_TXFQS register *********************/
#define FDCAN_TXFQS_TFFL_Pos (0U)
#define FDCAN_TXFQS_TFFL_Msk (0x3FU << FDCAN_TXFQS_TFFL_Pos) /*!< 0x0000003F */
#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */
#define FDCAN_TXFQS_TFGI_Pos (8U)
#define FDCAN_TXFQS_TFGI_Msk (0x1FU << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00001F00 */
#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */
#define FDCAN_TXFQS_TFQPI_Pos (16U)
#define FDCAN_TXFQS_TFQPI_Msk (0x1FU << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x001F0000 */
#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */
#define FDCAN_TXFQS_TFQF_Pos (21U)
#define FDCAN_TXFQS_TFQF_Msk (0x1U << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */
#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */
/***************** Bit definition for FDCAN_TXESC register *********************/
#define FDCAN_TXESC_TBDS_Pos (0U)
#define FDCAN_TXESC_TBDS_Msk (0x7U << FDCAN_TXESC_TBDS_Pos) /*!< 0x00000007 */
#define FDCAN_TXESC_TBDS FDCAN_TXESC_TBDS_Msk /*!<Tx Buffer Data Field Size */
/***************** Bit definition for FDCAN_TXBRP register *********************/
#define FDCAN_TXBRP_TRP_Pos (0U)
#define FDCAN_TXBRP_TRP_Msk (0xFFFFFFFFU << FDCAN_TXBRP_TRP_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */
/***************** Bit definition for FDCAN_TXBAR register *********************/
#define FDCAN_TXBAR_AR_Pos (0U)
#define FDCAN_TXBAR_AR_Msk (0xFFFFFFFFU << FDCAN_TXBAR_AR_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */
/***************** Bit definition for FDCAN_TXBCR register *********************/
#define FDCAN_TXBCR_CR_Pos (0U)
#define FDCAN_TXBCR_CR_Msk (0xFFFFFFFFU << FDCAN_TXBCR_CR_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */
/***************** Bit definition for FDCAN_TXBTO register *********************/
#define FDCAN_TXBTO_TO_Pos (0U)
#define FDCAN_TXBTO_TO_Msk (0xFFFFFFFFU << FDCAN_TXBTO_TO_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */
/***************** Bit definition for FDCAN_TXBCF register *********************/
#define FDCAN_TXBCF_CF_Pos (0U)
#define FDCAN_TXBCF_CF_Msk (0xFFFFFFFFU << FDCAN_TXBCF_CF_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */
/***************** Bit definition for FDCAN_TXBTIE register ********************/
#define FDCAN_TXBTIE_TIE_Pos (0U)
#define FDCAN_TXBTIE_TIE_Msk (0xFFFFFFFFU << FDCAN_TXBTIE_TIE_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */
/***************** Bit definition for FDCAN_ TXBCIE register *******************/
#define FDCAN_TXBCIE_CF_Pos (0U)
#define FDCAN_TXBCIE_CF_Msk (0xFFFFFFFFU << FDCAN_TXBCIE_CF_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_TXBCIE_CF FDCAN_TXBCIE_CF_Msk /*!<Cancellation Finished Interrupt Enable */
/***************** Bit definition for FDCAN_TXEFC register *********************/
#define FDCAN_TXEFC_EFSA_Pos (2U)
#define FDCAN_TXEFC_EFSA_Msk (0x3FFFU << FDCAN_TXEFC_EFSA_Pos) /*!< 0x0000FFFC */
#define FDCAN_TXEFC_EFSA FDCAN_TXEFC_EFSA_Msk /*!<Event FIFO Start Address */
#define FDCAN_TXEFC_EFS_Pos (16U)
#define FDCAN_TXEFC_EFS_Msk (0x3FU << FDCAN_TXEFC_EFS_Pos) /*!< 0x003F0000 */
#define FDCAN_TXEFC_EFS FDCAN_TXEFC_EFS_Msk /*!<Event FIFO Size */
#define FDCAN_TXEFC_EFWM_Pos (24U)
#define FDCAN_TXEFC_EFWM_Msk (0x3FU << FDCAN_TXEFC_EFWM_Pos) /*!< 0x3F000000 */
#define FDCAN_TXEFC_EFWM FDCAN_TXEFC_EFWM_Msk /*!<Event FIFO Watermark */
/***************** Bit definition for FDCAN_TXEFS register *********************/
#define FDCAN_TXEFS_EFFL_Pos (0U)
#define FDCAN_TXEFS_EFFL_Msk (0x3FU << FDCAN_TXEFS_EFFL_Pos) /*!< 0x0000003F */
#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */
#define FDCAN_TXEFS_EFGI_Pos (8U)
#define FDCAN_TXEFS_EFGI_Msk (0x1FU << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00001F00 */
#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */
#define FDCAN_TXEFS_EFPI_Pos (16U)
#define FDCAN_TXEFS_EFPI_Msk (0x1FU << FDCAN_TXEFS_EFPI_Pos) /*!< 0x001F0000 */
#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */
#define FDCAN_TXEFS_EFF_Pos (24U)
#define FDCAN_TXEFS_EFF_Msk (0x1U << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */
#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */
#define FDCAN_TXEFS_TEFL_Pos (25U)
#define FDCAN_TXEFS_TEFL_Msk (0x1U << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */
#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */
/***************** Bit definition for FDCAN_TXEFA register *********************/
#define FDCAN_TXEFA_EFAI_Pos (0U)
#define FDCAN_TXEFA_EFAI_Msk (0x1FU << FDCAN_TXEFA_EFAI_Pos) /*!< 0x0000001F */
#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */
/***************** Bit definition for FDCAN_TTTMC register *********************/
#define FDCAN_TTTMC_TMSA_Pos (2U)
#define FDCAN_TTTMC_TMSA_Msk (0x3FFFU << FDCAN_TTTMC_TMSA_Pos) /*!< 0x0000FFFC */
#define FDCAN_TTTMC_TMSA FDCAN_TTTMC_TMSA_Msk /*!<Trigger Memory Start Address */
#define FDCAN_TTTMC_TME_Pos (16U)
#define FDCAN_TTTMC_TME_Msk (0x7FU << FDCAN_TTTMC_TME_Pos) /*!< 0x007F0000 */
#define FDCAN_TTTMC_TME FDCAN_TTTMC_TME_Msk /*!<Trigger Memory Elements */
/***************** Bit definition for FDCAN_TTRMC register *********************/
#define FDCAN_TTRMC_RID_Pos (0U)
#define FDCAN_TTRMC_RID_Msk (0x1FFFFFFFU << FDCAN_TTRMC_RID_Pos) /*!< 0x1FFFFFFF */
#define FDCAN_TTRMC_RID FDCAN_TTRMC_RID_Msk /*!<Reference Identifier */
#define FDCAN_TTRMC_XTD_Pos (30U)
#define FDCAN_TTRMC_XTD_Msk (0x1U << FDCAN_TTRMC_XTD_Pos) /*!< 0x40000000 */
#define FDCAN_TTRMC_XTD FDCAN_TTRMC_XTD_Msk /*!< Extended Identifier */
#define FDCAN_TTRMC_RMPS_Pos (31U)
#define FDCAN_TTRMC_RMPS_Msk (0x1U << FDCAN_TTRMC_RMPS_Pos) /*!< 0x80000000 */
#define FDCAN_TTRMC_RMPS FDCAN_TTRMC_RMPS_Msk /*!<Reference Message Payload Select */
/***************** Bit definition for FDCAN_TTOCF register *********************/
#define FDCAN_TTOCF_OM_Pos (0U)
#define FDCAN_TTOCF_OM_Msk (0x3U << FDCAN_TTOCF_OM_Pos) /*!< 0x00000003 */
#define FDCAN_TTOCF_OM FDCAN_TTOCF_OM_Msk /*!<Operation Mode */
#define FDCAN_TTOCF_GEN_Pos (3U)
#define FDCAN_TTOCF_GEN_Msk (0x1U << FDCAN_TTOCF_GEN_Pos) /*!< 0x00000008 */
#define FDCAN_TTOCF_GEN FDCAN_TTOCF_GEN_Msk /*!<Gap Enable */
#define FDCAN_TTOCF_TM_Pos (4U)
#define FDCAN_TTOCF_TM_Msk (0x1U << FDCAN_TTOCF_TM_Pos) /*!< 0x00000010 */
#define FDCAN_TTOCF_TM FDCAN_TTOCF_TM_Msk /*!<Time Master */
#define FDCAN_TTOCF_LDSDL_Pos (5U)
#define FDCAN_TTOCF_LDSDL_Msk (0x7U << FDCAN_TTOCF_LDSDL_Pos) /*!< 0x000000E0 */
#define FDCAN_TTOCF_LDSDL FDCAN_TTOCF_LDSDL_Msk /*!<LD of Synchronization Deviation Limit */
#define FDCAN_TTOCF_IRTO_Pos (8U)
#define FDCAN_TTOCF_IRTO_Msk (0x7FU << FDCAN_TTOCF_IRTO_Pos) /*!< 0x00007F00 */
#define FDCAN_TTOCF_IRTO FDCAN_TTOCF_IRTO_Msk /*!<Initial Reference Trigger Offset */
#define FDCAN_TTOCF_EECS_Pos (15U)
#define FDCAN_TTOCF_EECS_Msk (0x1U << FDCAN_TTOCF_EECS_Pos) /*!< 0x00008000 */
#define FDCAN_TTOCF_EECS FDCAN_TTOCF_EECS_Msk /*!<Enable External Clock Synchronization */
#define FDCAN_TTOCF_AWL_Pos (16U)
#define FDCAN_TTOCF_AWL_Msk (0xFFU << FDCAN_TTOCF_AWL_Pos) /*!< 0x00FF0000 */
#define FDCAN_TTOCF_AWL FDCAN_TTOCF_AWL_Msk /*!<Application Watchdog Limit */
#define FDCAN_TTOCF_EGTF_Pos (24U)
#define FDCAN_TTOCF_EGTF_Msk (0x1U << FDCAN_TTOCF_EGTF_Pos) /*!< 0x01000000 */
#define FDCAN_TTOCF_EGTF FDCAN_TTOCF_EGTF_Msk /*!<Enable Global Time Filtering */
#define FDCAN_TTOCF_ECC_Pos (25U)
#define FDCAN_TTOCF_ECC_Msk (0x1U << FDCAN_TTOCF_ECC_Pos) /*!< 0x02000000 */
#define FDCAN_TTOCF_ECC FDCAN_TTOCF_ECC_Msk /*!<Enable Clock Calibration */
#define FDCAN_TTOCF_EVTP_Pos (26U)
#define FDCAN_TTOCF_EVTP_Msk (0x1U << FDCAN_TTOCF_EVTP_Pos) /*!< 0x04000000 */
#define FDCAN_TTOCF_EVTP FDCAN_TTOCF_EVTP_Msk /*!<Event Trigger Polarity */
/***************** Bit definition for FDCAN_TTMLM register *********************/
#define FDCAN_TTMLM_CCM_Pos (0U)
#define FDCAN_TTMLM_CCM_Msk (0x3FU << FDCAN_TTMLM_CCM_Pos) /*!< 0x0000003F */
#define FDCAN_TTMLM_CCM FDCAN_TTMLM_CCM_Msk /*!<Cycle Count Max */
#define FDCAN_TTMLM_CSS_Pos (6U)
#define FDCAN_TTMLM_CSS_Msk (0x3U << FDCAN_TTMLM_CSS_Pos) /*!< 0x000000C0 */
#define FDCAN_TTMLM_CSS FDCAN_TTMLM_CSS_Msk /*!<Cycle Start Synchronization */
#define FDCAN_TTMLM_TXEW_Pos (8U)
#define FDCAN_TTMLM_TXEW_Msk (0xFU << FDCAN_TTMLM_TXEW_Pos) /*!< 0x00000F00 */
#define FDCAN_TTMLM_TXEW FDCAN_TTMLM_TXEW_Msk /*!<Tx Enable Window */
#define FDCAN_TTMLM_ENTT_Pos (16U)
#define FDCAN_TTMLM_ENTT_Msk (0xFFFU << FDCAN_TTMLM_ENTT_Pos) /*!< 0x0FFF0000 */
#define FDCAN_TTMLM_ENTT FDCAN_TTMLM_ENTT_Msk /*!<Expected Number of Tx Triggers */
/***************** Bit definition for FDCAN_TURCF register *********************/
#define FDCAN_TURCF_NCL_Pos (0U)
#define FDCAN_TURCF_NCL_Msk (0xFFFFU << FDCAN_TURCF_NCL_Pos) /*!< 0x0000FFFF */
#define FDCAN_TURCF_NCL FDCAN_TURCF_NCL_Msk /*!<Numerator Configuration Low */
#define FDCAN_TURCF_DC_Pos (16U)
#define FDCAN_TURCF_DC_Msk (0x3FFFU << FDCAN_TURCF_DC_Pos) /*!< 0x3FFF0000 */
#define FDCAN_TURCF_DC FDCAN_TURCF_DC_Msk /*!<Denominator Configuration */
#define FDCAN_TURCF_ELT_Pos (31U)
#define FDCAN_TURCF_ELT_Msk (0x1U << FDCAN_TURCF_ELT_Pos) /*!< 0x80000000 */
#define FDCAN_TURCF_ELT FDCAN_TURCF_ELT_Msk /*!<Enable Local Time */
/***************** Bit definition for FDCAN_TTOCN register ********************/
#define FDCAN_TTOCN_SGT_Pos (0U)
#define FDCAN_TTOCN_SGT_Msk (0x1U << FDCAN_TTOCN_SGT_Pos) /*!< 0x00000001 */
#define FDCAN_TTOCN_SGT FDCAN_TTOCN_SGT_Msk /*!<Set Global time */
#define FDCAN_TTOCN_ECS_Pos (1U)
#define FDCAN_TTOCN_ECS_Msk (0x1U << FDCAN_TTOCN_ECS_Pos) /*!< 0x00000002 */
#define FDCAN_TTOCN_ECS FDCAN_TTOCN_ECS_Msk /*!<External Clock Synchronization */
#define FDCAN_TTOCN_SWP_Pos (2U)
#define FDCAN_TTOCN_SWP_Msk (0x1U << FDCAN_TTOCN_SWP_Pos) /*!< 0x00000004 */
#define FDCAN_TTOCN_SWP FDCAN_TTOCN_SWP_Msk /*!<Stop Watch Polarity */
#define FDCAN_TTOCN_SWS_Pos (3U)
#define FDCAN_TTOCN_SWS_Msk (0x3U << FDCAN_TTOCN_SWS_Pos) /*!< 0x00000018 */
#define FDCAN_TTOCN_SWS FDCAN_TTOCN_SWS_Msk /*!<Stop Watch Source */
#define FDCAN_TTOCN_RTIE_Pos (5U)
#define FDCAN_TTOCN_RTIE_Msk (0x1U << FDCAN_TTOCN_RTIE_Pos) /*!< 0x00000020 */
#define FDCAN_TTOCN_RTIE FDCAN_TTOCN_RTIE_Msk /*!<Register Time Mark Interrupt Pulse Enable */
#define FDCAN_TTOCN_TMC_Pos (6U)
#define FDCAN_TTOCN_TMC_Msk (0x3U << FDCAN_TTOCN_TMC_Pos) /*!< 0x000000C0 */
#define FDCAN_TTOCN_TMC FDCAN_TTOCN_TMC_Msk /*!<Register Time Mark Compare */
#define FDCAN_TTOCN_TTIE_Pos (8U)
#define FDCAN_TTOCN_TTIE_Msk (0x1U << FDCAN_TTOCN_TTIE_Pos) /*!< 0x00000100 */
#define FDCAN_TTOCN_TTIE FDCAN_TTOCN_TTIE_Msk /*!<Trigger Time Mark Interrupt Pulse Enable */
#define FDCAN_TTOCN_GCS_Pos (9U)
#define FDCAN_TTOCN_GCS_Msk (0x1U << FDCAN_TTOCN_GCS_Pos) /*!< 0x00000200 */
#define FDCAN_TTOCN_GCS FDCAN_TTOCN_GCS_Msk /*!<Gap Control Select */
#define FDCAN_TTOCN_FGP_Pos (10U)
#define FDCAN_TTOCN_FGP_Msk (0x1U << FDCAN_TTOCN_FGP_Pos) /*!< 0x00000400 */
#define FDCAN_TTOCN_FGP FDCAN_TTOCN_FGP_Msk /*!<Finish Gap */
#define FDCAN_TTOCN_TMG_Pos (11U)
#define FDCAN_TTOCN_TMG_Msk (0x1U << FDCAN_TTOCN_TMG_Pos) /*!< 0x00000800 */
#define FDCAN_TTOCN_TMG FDCAN_TTOCN_TMG_Msk /*!<Time Mark Gap */
#define FDCAN_TTOCN_NIG_Pos (12U)
#define FDCAN_TTOCN_NIG_Msk (0x1U << FDCAN_TTOCN_NIG_Pos) /*!< 0x00001000 */
#define FDCAN_TTOCN_NIG FDCAN_TTOCN_NIG_Msk /*!<Next is Gap */
#define FDCAN_TTOCN_ESCN_Pos (13U)
#define FDCAN_TTOCN_ESCN_Msk (0x1U << FDCAN_TTOCN_ESCN_Pos) /*!< 0x00002000 */
#define FDCAN_TTOCN_ESCN FDCAN_TTOCN_ESCN_Msk /*!<External Synchronization Control */
#define FDCAN_TTOCN_LCKC_Pos (15U)
#define FDCAN_TTOCN_LCKC_Msk (0x1U << FDCAN_TTOCN_LCKC_Pos) /*!< 0x00008000 */
#define FDCAN_TTOCN_LCKC FDCAN_TTOCN_LCKC_Msk /*!<TT Operation Control Register Locked */
/***************** Bit definition for FDCAN_TTGTP register ********************/
#define FDCAN_TTGTP_TP_Pos (0U)
#define FDCAN_TTGTP_TP_Msk (0xFFFFU << FDCAN_TTGTP_TP_Pos) /*!< 0x0000FFFF */
#define FDCAN_TTGTP_TP FDCAN_TTGTP_TP_Msk /*!<Time Preset */
#define FDCAN_TTGTP_CTP_Pos (16U)
#define FDCAN_TTGTP_CTP_Msk (0xFFFFU << FDCAN_TTGTP_CTP_Pos) /*!< 0xFFFF0000 */
#define FDCAN_TTGTP_CTP FDCAN_TTGTP_CTP_Msk /*!<Cycle Time Target Phase */
/***************** Bit definition for FDCAN_TTTMK register ********************/
#define FDCAN_TTTMK_TM_Pos (0U)
#define FDCAN_TTTMK_TM_Msk (0xFFFFU << FDCAN_TTTMK_TM_Pos) /*!< 0x0000FFFF */
#define FDCAN_TTTMK_TM FDCAN_TTTMK_TM_Msk /*!<Time Mark */
#define FDCAN_TTTMK_TICC_Pos (16U)
#define FDCAN_TTTMK_TICC_Msk (0x7FU << FDCAN_TTTMK_TICC_Pos) /*!< 0x007F0000 */
#define FDCAN_TTTMK_TICC FDCAN_TTTMK_TICC_Msk /*!<Time Mark Cycle Code */
#define FDCAN_TTTMK_LCKM_Pos (31U)
#define FDCAN_TTTMK_LCKM_Msk (0x1U << FDCAN_TTTMK_LCKM_Pos) /*!< 0x80000000 */
#define FDCAN_TTTMK_LCKM FDCAN_TTTMK_LCKM_Msk /*!<TT Time Mark Register Locked */
/***************** Bit definition for FDCAN_TTIR register ********************/
#define FDCAN_TTIR_SBC_Pos (0U)
#define FDCAN_TTIR_SBC_Msk (0x1U << FDCAN_TTIR_SBC_Pos) /*!< 0x00000001 */
#define FDCAN_TTIR_SBC FDCAN_TTIR_SBC_Msk /*!<Start of Basic Cycle */
#define FDCAN_TTIR_SMC_Pos (1U)
#define FDCAN_TTIR_SMC_Msk (0x1U << FDCAN_TTIR_SMC_Pos) /*!< 0x00000002 */
#define FDCAN_TTIR_SMC FDCAN_TTIR_SMC_Msk /*!<Start of Matrix Cycle */
#define FDCAN_TTIR_CSM_Pos (2U)
#define FDCAN_TTIR_CSM_Msk (0x1U << FDCAN_TTIR_CSM_Pos) /*!< 0x00000004 */
#define FDCAN_TTIR_CSM FDCAN_TTIR_CSM_Msk /*!<Change of Synchronization Mode */
#define FDCAN_TTIR_SOG_Pos (3U)
#define FDCAN_TTIR_SOG_Msk (0x1U << FDCAN_TTIR_SOG_Pos) /*!< 0x00000008 */
#define FDCAN_TTIR_SOG FDCAN_TTIR_SOG_Msk /*!<Start of Gap */
#define FDCAN_TTIR_RTMI_Pos (4U)
#define FDCAN_TTIR_RTMI_Msk (0x1U << FDCAN_TTIR_RTMI_Pos) /*!< 0x00000010 */
#define FDCAN_TTIR_RTMI FDCAN_TTIR_RTMI_Msk /*!<Register Time Mark Interrupt */
#define FDCAN_TTIR_TTMI_Pos (5U)
#define FDCAN_TTIR_TTMI_Msk (0x1U << FDCAN_TTIR_TTMI_Pos) /*!< 0x00000020 */
#define FDCAN_TTIR_TTMI FDCAN_TTIR_TTMI_Msk /*!<Trigger Time Mark Event Internal */
#define FDCAN_TTIR_SWE_Pos (6U)
#define FDCAN_TTIR_SWE_Msk (0x1U << FDCAN_TTIR_SWE_Pos) /*!< 0x00000040 */
#define FDCAN_TTIR_SWE FDCAN_TTIR_SWE_Msk /*!<Stop Watch Event */
#define FDCAN_TTIR_GTW_Pos (7U)
#define FDCAN_TTIR_GTW_Msk (0x1U << FDCAN_TTIR_GTW_Pos) /*!< 0x00000080 */
#define FDCAN_TTIR_GTW FDCAN_TTIR_GTW_Msk /*!<Global Time Wrap */
#define FDCAN_TTIR_GTD_Pos (8U)
#define FDCAN_TTIR_GTD_Msk (0x1U << FDCAN_TTIR_GTD_Pos) /*!< 0x00000100 */
#define FDCAN_TTIR_GTD FDCAN_TTIR_GTD_Msk /*!<Global Time Discontinuity */
#define FDCAN_TTIR_GTE_Pos (9U)
#define FDCAN_TTIR_GTE_Msk (0x1U << FDCAN_TTIR_GTE_Pos) /*!< 0x00000200 */
#define FDCAN_TTIR_GTE FDCAN_TTIR_GTE_Msk /*!<Global Time Error */
#define FDCAN_TTIR_TXU_Pos (10U)
#define FDCAN_TTIR_TXU_Msk (0x1U << FDCAN_TTIR_TXU_Pos) /*!< 0x00000400 */
#define FDCAN_TTIR_TXU FDCAN_TTIR_TXU_Msk /*!<Tx Count Underflow */
#define FDCAN_TTIR_TXO_Pos (11U)
#define FDCAN_TTIR_TXO_Msk (0x1U << FDCAN_TTIR_TXO_Pos) /*!< 0x00000800 */
#define FDCAN_TTIR_TXO FDCAN_TTIR_TXO_Msk /*!<Tx Count Overflow */
#define FDCAN_TTIR_SE1_Pos (12U)
#define FDCAN_TTIR_SE1_Msk (0x1U << FDCAN_TTIR_SE1_Pos) /*!< 0x00001000 */
#define FDCAN_TTIR_SE1 FDCAN_TTIR_SE1_Msk /*!<Scheduling Error 1 */
#define FDCAN_TTIR_SE2_Pos (13U)
#define FDCAN_TTIR_SE2_Msk (0x1U << FDCAN_TTIR_SE2_Pos) /*!< 0x00002000 */
#define FDCAN_TTIR_SE2 FDCAN_TTIR_SE2_Msk /*!<Scheduling Error 2 */
#define FDCAN_TTIR_ELC_Pos (14U)
#define FDCAN_TTIR_ELC_Msk (0x1U << FDCAN_TTIR_ELC_Pos) /*!< 0x00004000 */
#define FDCAN_TTIR_ELC FDCAN_TTIR_ELC_Msk /*!<Error Level Changed */
#define FDCAN_TTIR_IWT_Pos (15U)
#define FDCAN_TTIR_IWT_Msk (0x1U << FDCAN_TTIR_IWT_Pos) /*!< 0x00008000 */
#define FDCAN_TTIR_IWT FDCAN_TTIR_IWT_Msk /*!<Initialization Watch Trigger */
#define FDCAN_TTIR_WT_Pos (16U)
#define FDCAN_TTIR_WT_Msk (0x1U << FDCAN_TTIR_WT_Pos) /*!< 0x00010000 */
#define FDCAN_TTIR_WT FDCAN_TTIR_WT_Msk /*!<Watch Trigger */
#define FDCAN_TTIR_AW_Pos (17U)
#define FDCAN_TTIR_AW_Msk (0x1U << FDCAN_TTIR_AW_Pos) /*!< 0x00020000 */
#define FDCAN_TTIR_AW FDCAN_TTIR_AW_Msk /*!<Application Watchdog */
#define FDCAN_TTIR_CER_Pos (18U)
#define FDCAN_TTIR_CER_Msk (0x1U << FDCAN_TTIR_CER_Pos) /*!< 0x00040000 */
#define FDCAN_TTIR_CER FDCAN_TTIR_CER_Msk /*!<Configuration Error */
/***************** Bit definition for FDCAN_TTIE register ********************/
#define FDCAN_TTIE_SBCE_Pos (0U)
#define FDCAN_TTIE_SBCE_Msk (0x1U << FDCAN_TTIE_SBCE_Pos) /*!< 0x00000001 */
#define FDCAN_TTIE_SBCE FDCAN_TTIE_SBCE_Msk /*!<Start of Basic Cycle Interrupt Enable */
#define FDCAN_TTIE_SMCE_Pos (1U)
#define FDCAN_TTIE_SMCE_Msk (0x1U << FDCAN_TTIE_SMCE_Pos) /*!< 0x00000002 */
#define FDCAN_TTIE_SMCE FDCAN_TTIE_SMCE_Msk /*!<Start of Matrix Cycle Interrupt Enable */
#define FDCAN_TTIE_CSME_Pos (2U)
#define FDCAN_TTIE_CSME_Msk (0x1U << FDCAN_TTIE_CSME_Pos) /*!< 0x00000004 */
#define FDCAN_TTIE_CSME FDCAN_TTIE_CSME_Msk /*!<Change of Synchronization Mode Interrupt Enable */
#define FDCAN_TTIE_SOGE_Pos (3U)
#define FDCAN_TTIE_SOGE_Msk (0x1U << FDCAN_TTIE_SOGE_Pos) /*!< 0x00000008 */
#define FDCAN_TTIE_SOGE FDCAN_TTIE_SOGE_Msk /*!<Start of Gap Interrupt Enable */
#define FDCAN_TTIE_RTMIE_Pos (4U)
#define FDCAN_TTIE_RTMIE_Msk (0x1U << FDCAN_TTIE_RTMIE_Pos) /*!< 0x00000010 */
#define FDCAN_TTIE_RTMIE FDCAN_TTIE_RTMIE_Msk /*!<Register Time Mark Interrupt Interrupt Enable */
#define FDCAN_TTIE_TTMIE_Pos (5U)
#define FDCAN_TTIE_TTMIE_Msk (0x1U << FDCAN_TTIE_TTMIE_Pos) /*!< 0x00000020 */
#define FDCAN_TTIE_TTMIE FDCAN_TTIE_TTMIE_Msk /*!<Trigger Time Mark Event Internal Interrupt Enable */
#define FDCAN_TTIE_SWEE_Pos (6U)
#define FDCAN_TTIE_SWEE_Msk (0x1U << FDCAN_TTIE_SWEE_Pos) /*!< 0x00000040 */
#define FDCAN_TTIE_SWEE FDCAN_TTIE_SWEE_Msk /*!<Stop Watch Event Interrupt Enable */
#define FDCAN_TTIE_GTWE_Pos (7U)
#define FDCAN_TTIE_GTWE_Msk (0x1U << FDCAN_TTIE_GTWE_Pos) /*!< 0x00000080 */
#define FDCAN_TTIE_GTWE FDCAN_TTIE_GTWE_Msk /*!<Global Time Wrap Interrupt Enable */
#define FDCAN_TTIE_GTDE_Pos (8U)
#define FDCAN_TTIE_GTDE_Msk (0x1U << FDCAN_TTIE_GTDE_Pos) /*!< 0x00000100 */
#define FDCAN_TTIE_GTDE FDCAN_TTIE_GTDE_Msk /*!<Global Time Discontinuity Interrupt Enable */
#define FDCAN_TTIE_GTEE_Pos (9U)
#define FDCAN_TTIE_GTEE_Msk (0x1U << FDCAN_TTIE_GTEE_Pos) /*!< 0x00000200 */
#define FDCAN_TTIE_GTEE FDCAN_TTIE_GTEE_Msk /*!<Global Time Error Interrupt Enable */
#define FDCAN_TTIE_TXUE_Pos (10U)
#define FDCAN_TTIE_TXUE_Msk (0x1U << FDCAN_TTIE_TXUE_Pos) /*!< 0x00000400 */
#define FDCAN_TTIE_TXUE FDCAN_TTIE_TXUE_Msk /*!<Tx Count Underflow Interrupt Enable */
#define FDCAN_TTIE_TXOE_Pos (11U)
#define FDCAN_TTIE_TXOE_Msk (0x1U << FDCAN_TTIE_TXOE_Pos) /*!< 0x00000800 */
#define FDCAN_TTIE_TXOE FDCAN_TTIE_TXOE_Msk /*!<Tx Count Overflow Interrupt Enable */
#define FDCAN_TTIE_SE1E_Pos (12U)
#define FDCAN_TTIE_SE1E_Msk (0x1U << FDCAN_TTIE_SE1E_Pos) /*!< 0x00001000 */
#define FDCAN_TTIE_SE1E FDCAN_TTIE_SE1E_Msk /*!<Scheduling Error 1 Interrupt Enable */
#define FDCAN_TTIE_SE2E_Pos (13U)
#define FDCAN_TTIE_SE2E_Msk (0x1U << FDCAN_TTIE_SE2E_Pos) /*!< 0x00002000 */
#define FDCAN_TTIE_SE2E FDCAN_TTIE_SE2E_Msk /*!<Scheduling Error 2 Interrupt Enable */
#define FDCAN_TTIE_ELCE_Pos (14U)
#define FDCAN_TTIE_ELCE_Msk (0x1U << FDCAN_TTIE_ELCE_Pos) /*!< 0x00004000 */
#define FDCAN_TTIE_ELCE FDCAN_TTIE_ELCE_Msk /*!<Error Level Changed Interrupt Enable */
#define FDCAN_TTIE_IWTE_Pos (15U)
#define FDCAN_TTIE_IWTE_Msk (0x1U << FDCAN_TTIE_IWTE_Pos) /*!< 0x00008000 */
#define FDCAN_TTIE_IWTE FDCAN_TTIE_IWTE_Msk /*!<Initialization Watch Trigger Interrupt Enable */
#define FDCAN_TTIE_WTE_Pos (16U)
#define FDCAN_TTIE_WTE_Msk (0x1U << FDCAN_TTIE_WTE_Pos) /*!< 0x00010000 */
#define FDCAN_TTIE_WTE FDCAN_TTIE_WTE_Msk /*!<Watch Trigger Interrupt Enable */
#define FDCAN_TTIE_AWE_Pos (17U)
#define FDCAN_TTIE_AWE_Msk (0x1U << FDCAN_TTIE_AWE_Pos) /*!< 0x00020000 */
#define FDCAN_TTIE_AWE FDCAN_TTIE_AWE_Msk /*!<Application Watchdog Interrupt Enable */
#define FDCAN_TTIE_CERE_Pos (18U)
#define FDCAN_TTIE_CERE_Msk (0x1U << FDCAN_TTIE_CERE_Pos) /*!< 0x00040000 */
#define FDCAN_TTIE_CERE FDCAN_TTIE_CERE_Msk /*!<Configuration Error Interrupt Enable */
/***************** Bit definition for FDCAN_TTILS register ********************/
#define FDCAN_TTILS_SBCS_Pos (0U)
#define FDCAN_TTILS_SBCS_Msk (0x1U << FDCAN_TTILS_SBCS_Pos) /*!< 0x00000001 */
#define FDCAN_TTILS_SBCS FDCAN_TTILS_SBCS_Msk /*!<Start of Basic Cycle Interrupt Line */
#define FDCAN_TTILS_SMCS_Pos (1U)
#define FDCAN_TTILS_SMCS_Msk (0x1U << FDCAN_TTILS_SMCS_Pos) /*!< 0x00000002 */
#define FDCAN_TTILS_SMCS FDCAN_TTILS_SMCS_Msk /*!<Start of Matrix Cycle Interrupt Line */
#define FDCAN_TTILS_CSMS_Pos (2U)
#define FDCAN_TTILS_CSMS_Msk (0x1U << FDCAN_TTILS_CSMS_Pos) /*!< 0x00000004 */
#define FDCAN_TTILS_CSMS FDCAN_TTILS_CSMS_Msk /*!<Change of Synchronization Mode Interrupt Line */
#define FDCAN_TTILS_SOGS_Pos (3U)
#define FDCAN_TTILS_SOGS_Msk (0x1U << FDCAN_TTILS_SOGS_Pos) /*!< 0x00000008 */
#define FDCAN_TTILS_SOGS FDCAN_TTILS_SOGS_Msk /*!<Start of Gap Interrupt Line */
#define FDCAN_TTILS_RTMIS_Pos (4U)
#define FDCAN_TTILS_RTMIS_Msk (0x1U << FDCAN_TTILS_RTMIS_Pos) /*!< 0x00000010 */
#define FDCAN_TTILS_RTMIS FDCAN_TTILS_RTMIS_Msk /*!<Register Time Mark Interrupt Interrupt Line */
#define FDCAN_TTILS_TTMIS_Pos (5U)
#define FDCAN_TTILS_TTMIS_Msk (0x1U << FDCAN_TTILS_TTMIS_Pos) /*!< 0x00000020 */
#define FDCAN_TTILS_TTMIS FDCAN_TTILS_TTMIS_Msk /*!<Trigger Time Mark Event Internal Interrupt Line */
#define FDCAN_TTILS_SWES_Pos (6U)
#define FDCAN_TTILS_SWES_Msk (0x1U << FDCAN_TTILS_SWES_Pos) /*!< 0x00000040 */
#define FDCAN_TTILS_SWES FDCAN_TTILS_SWES_Msk /*!<Stop Watch Event Interrupt Line */
#define FDCAN_TTILS_GTWS_Pos (7U)
#define FDCAN_TTILS_GTWS_Msk (0x1U << FDCAN_TTILS_GTWS_Pos) /*!< 0x00000080 */
#define FDCAN_TTILS_GTWS FDCAN_TTILS_GTWS_Msk /*!<Global Time Wrap Interrupt Line */
#define FDCAN_TTILS_GTDS_Pos (8U)
#define FDCAN_TTILS_GTDS_Msk (0x1U << FDCAN_TTILS_GTDS_Pos) /*!< 0x00000100 */
#define FDCAN_TTILS_GTDS FDCAN_TTILS_GTDS_Msk /*!<Global Time Discontinuity Interrupt Line */
#define FDCAN_TTILS_GTES_Pos (9U)
#define FDCAN_TTILS_GTES_Msk (0x1U << FDCAN_TTILS_GTES_Pos) /*!< 0x00000200 */
#define FDCAN_TTILS_GTES FDCAN_TTILS_GTES_Msk /*!<Global Time Error Interrupt Line */
#define FDCAN_TTILS_TXUS_Pos (10U)
#define FDCAN_TTILS_TXUS_Msk (0x1U << FDCAN_TTILS_TXUS_Pos) /*!< 0x00000400 */
#define FDCAN_TTILS_TXUS FDCAN_TTILS_TXUS_Msk /*!<Tx Count Underflow Interrupt Line */
#define FDCAN_TTILS_TXOS_Pos (11U)
#define FDCAN_TTILS_TXOS_Msk (0x1U << FDCAN_TTILS_TXOS_Pos) /*!< 0x00000800 */
#define FDCAN_TTILS_TXOS FDCAN_TTILS_TXOS_Msk /*!<Tx Count Overflow Interrupt Line */
#define FDCAN_TTILS_SE1S_Pos (12U)
#define FDCAN_TTILS_SE1S_Msk (0x1U << FDCAN_TTILS_SE1S_Pos) /*!< 0x00001000 */
#define FDCAN_TTILS_SE1S FDCAN_TTILS_SE1S_Msk /*!<Scheduling Error 1 Interrupt Line */
#define FDCAN_TTILS_SE2S_Pos (13U)
#define FDCAN_TTILS_SE2S_Msk (0x1U << FDCAN_TTILS_SE2S_Pos) /*!< 0x00002000 */
#define FDCAN_TTILS_SE2S FDCAN_TTILS_SE2S_Msk /*!<Scheduling Error 2 Interrupt Line */
#define FDCAN_TTILS_ELCS_Pos (14U)
#define FDCAN_TTILS_ELCS_Msk (0x1U << FDCAN_TTILS_ELCS_Pos) /*!< 0x00004000 */
#define FDCAN_TTILS_ELCS FDCAN_TTILS_ELCS_Msk /*!<Error Level Changed Interrupt Line */
#define FDCAN_TTILS_IWTS_Pos (15U)
#define FDCAN_TTILS_IWTS_Msk (0x1U << FDCAN_TTILS_IWTS_Pos) /*!< 0x00008000 */
#define FDCAN_TTILS_IWTS FDCAN_TTILS_IWTS_Msk /*!<Initialization Watch Trigger Interrupt Line */
#define FDCAN_TTILS_WTS_Pos (16U)
#define FDCAN_TTILS_WTS_Msk (0x1U << FDCAN_TTILS_WTS_Pos) /*!< 0x00010000 */
#define FDCAN_TTILS_WTS FDCAN_TTILS_WTS_Msk /*!<Watch Trigger Interrupt Line */
#define FDCAN_TTILS_AWS_Pos (17U)
#define FDCAN_TTILS_AWS_Msk (0x1U << FDCAN_TTILS_AWS_Pos) /*!< 0x00020000 */
#define FDCAN_TTILS_AWS FDCAN_TTILS_AWS_Msk /*!<Application Watchdog Interrupt Line */
#define FDCAN_TTILS_CERS_Pos (18U)
#define FDCAN_TTILS_CERS_Msk (0x1U << FDCAN_TTILS_CERS_Pos) /*!< 0x00040000 */
#define FDCAN_TTILS_CERS FDCAN_TTILS_CERS_Msk /*!<Configuration Error Interrupt Line */
/***************** Bit definition for FDCAN_TTOST register ********************/
#define FDCAN_TTOST_EL_Pos (0U)
#define FDCAN_TTOST_EL_Msk (0x3U << FDCAN_TTOST_EL_Pos) /*!< 0x00000003 */
#define FDCAN_TTOST_EL FDCAN_TTOST_EL_Msk /*!<Error Level */
#define FDCAN_TTOST_MS_Pos (2U)
#define FDCAN_TTOST_MS_Msk (0x3U << FDCAN_TTOST_MS_Pos) /*!< 0x0000000C */
#define FDCAN_TTOST_MS FDCAN_TTOST_MS_Msk /*!<Master State */
#define FDCAN_TTOST_SYS_Pos (4U)
#define FDCAN_TTOST_SYS_Msk (0x3U << FDCAN_TTOST_SYS_Pos) /*!< 0x00000030 */
#define FDCAN_TTOST_SYS FDCAN_TTOST_SYS_Msk /*!<Synchronization State */
#define FDCAN_TTOST_QGTP_Pos (6U)
#define FDCAN_TTOST_QGTP_Msk (0x1U << FDCAN_TTOST_QGTP_Pos) /*!< 0x00000040 */
#define FDCAN_TTOST_QGTP FDCAN_TTOST_QGTP_Msk /*!<Quality of Global Time Phase */
#define FDCAN_TTOST_QCS_Pos (7U)
#define FDCAN_TTOST_QCS_Msk (0x1U << FDCAN_TTOST_QCS_Pos) /*!< 0x00000080 */
#define FDCAN_TTOST_QCS FDCAN_TTOST_QCS_Msk /*!<Quality of Clock Speed */
#define FDCAN_TTOST_RTO_Pos (8U)
#define FDCAN_TTOST_RTO_Msk (0xFFU << FDCAN_TTOST_RTO_Pos) /*!< 0x0000FF00 */
#define FDCAN_TTOST_RTO FDCAN_TTOST_RTO_Msk /*!<Reference Trigger Offset */
#define FDCAN_TTOST_WGTD_Pos (22U)
#define FDCAN_TTOST_WGTD_Msk (0x1U << FDCAN_TTOST_WGTD_Pos) /*!< 0x00400000 */
#define FDCAN_TTOST_WGTD FDCAN_TTOST_WGTD_Msk /*!<Wait for Global Time Discontinuity */
#define FDCAN_TTOST_GFI_Pos (23U)
#define FDCAN_TTOST_GFI_Msk (0x1U << FDCAN_TTOST_GFI_Pos) /*!< 0x00800000 */
#define FDCAN_TTOST_GFI FDCAN_TTOST_GFI_Msk /*!<Gap Finished Indicator */
#define FDCAN_TTOST_TMP_Pos (24U)
#define FDCAN_TTOST_TMP_Msk (0x7U << FDCAN_TTOST_TMP_Pos) /*!< 0x07000000 */
#define FDCAN_TTOST_TMP FDCAN_TTOST_TMP_Msk /*!<Time Master Priority */
#define FDCAN_TTOST_GSI_Pos (27U)
#define FDCAN_TTOST_GSI_Msk (0x1U << FDCAN_TTOST_GSI_Pos) /*!< 0x08000000 */
#define FDCAN_TTOST_GSI FDCAN_TTOST_GSI_Msk /*!<Gap Started Indicator */
#define FDCAN_TTOST_WFE_Pos (28U)
#define FDCAN_TTOST_WFE_Msk (0x1U << FDCAN_TTOST_WFE_Pos) /*!< 0x10000000 */
#define FDCAN_TTOST_WFE FDCAN_TTOST_WFE_Msk /*!<Wait for Event */
#define FDCAN_TTOST_AWE_Pos (29U)
#define FDCAN_TTOST_AWE_Msk (0x1U << FDCAN_TTOST_AWE_Pos) /*!< 0x20000000 */
#define FDCAN_TTOST_AWE FDCAN_TTOST_AWE_Msk /*!<Application Watchdog Event */
#define FDCAN_TTOST_WECS_Pos (30U)
#define FDCAN_TTOST_WECS_Msk (0x1U << FDCAN_TTOST_WECS_Pos) /*!< 0x40000000 */
#define FDCAN_TTOST_WECS FDCAN_TTOST_WECS_Msk /*!<Wait for External Clock Synchronization */
#define FDCAN_TTOST_SPL_Pos (31U)
#define FDCAN_TTOST_SPL_Msk (0x1U << FDCAN_TTOST_SPL_Pos) /*!< 0x80000000 */
#define FDCAN_TTOST_SPL FDCAN_TTOST_SPL_Msk /*!<Schedule Phase Lock */
/***************** Bit definition for FDCAN_TURNA register ********************/
#define FDCAN_TURNA_NAV_Pos (0U)
#define FDCAN_TURNA_NAV_Msk (0x3FFFFU << FDCAN_TURNA_NAV_Pos) /*!< 0x0003FFFF */
#define FDCAN_TURNA_NAV FDCAN_TURNA_NAV_Msk /*!<Numerator Actual Value */
/***************** Bit definition for FDCAN_TTLGT register ********************/
#define FDCAN_TTLGT_LT_Pos (0U)
#define FDCAN_TTLGT_LT_Msk (0xFFFFU << FDCAN_TTLGT_LT_Pos) /*!< 0x0000FFFF */
#define FDCAN_TTLGT_LT FDCAN_TTLGT_LT_Msk /*!<Local Time */
#define FDCAN_TTLGT_GT_Pos (16U)
#define FDCAN_TTLGT_GT_Msk (0xFFFFU << FDCAN_TTLGT_GT_Pos) /*!< 0xFFFF0000 */
#define FDCAN_TTLGT_GT FDCAN_TTLGT_GT_Msk /*!<Global Time */
/***************** Bit definition for FDCAN_TTCTC register ********************/
#define FDCAN_TTCTC_CT_Pos (0U)
#define FDCAN_TTCTC_CT_Msk (0xFFFFU << FDCAN_TTCTC_CT_Pos) /*!< 0x0000FFFF */
#define FDCAN_TTCTC_CT FDCAN_TTCTC_CT_Msk /*!<Cycle Time */
#define FDCAN_TTCTC_CC_Pos (16U)
#define FDCAN_TTCTC_CC_Msk (0x3FU << FDCAN_TTCTC_CC_Pos) /*!< 0x003F0000 */
#define FDCAN_TTCTC_CC FDCAN_TTCTC_CC_Msk /*!<Cycle Count */
/***************** Bit definition for FDCAN_TTCPT register ********************/
#define FDCAN_TTCPT_CCV_Pos (0U)
#define FDCAN_TTCPT_CCV_Msk (0x3FU << FDCAN_TTCPT_CCV_Pos) /*!< 0x0000003F */
#define FDCAN_TTCPT_CCV FDCAN_TTCPT_CCV_Msk /*!<Cycle Count Value */
#define FDCAN_TTCPT_SWV_Pos (16U)
#define FDCAN_TTCPT_SWV_Msk (0xFFFFU << FDCAN_TTCPT_SWV_Pos) /*!< 0xFFFF0000 */
#define FDCAN_TTCPT_SWV FDCAN_TTCPT_SWV_Msk /*!<Stop Watch Value */
/***************** Bit definition for FDCAN_TTCSM register ********************/
#define FDCAN_TTCSM_CSM_Pos (0U)
#define FDCAN_TTCSM_CSM_Msk (0xFFFFU << FDCAN_TTCSM_CSM_Pos) /*!< 0x0000FFFF */
#define FDCAN_TTCSM_CSM FDCAN_TTCSM_CSM_Msk /*!<Cycle Sync Mark */
/***************** Bit definition for FDCAN_TTTS register *********************/
#define FDCAN_TTTS_SWTSEL_Pos (0U)
#define FDCAN_TTTS_SWTSEL_Msk (0x3U << FDCAN_TTTS_SWTSEL_Pos) /*!< 0x00000003 */
#define FDCAN_TTTS_SWTSEL FDCAN_TTTS_SWTSEL_Msk /*!<Stop watch trigger input selection */
#define FDCAN_TTTS_EVTSEL_Pos (4U)
#define FDCAN_TTTS_EVTSEL_Msk (0x3U << FDCAN_TTTS_EVTSEL_Pos) /*!< 0x00000030 */
#define FDCAN_TTTS_EVTSEL FDCAN_TTTS_EVTSEL_Msk /*!<Event trigger input selection */
/********************************************************************************/
/* */
/* FDCANCCU (Clock Calibration unit) */
/* */
/********************************************************************************/
/***************** Bit definition for FDCANCCU_CREL register ******************/
#define FDCANCCU_CREL_DAY_Pos (0U)
#define FDCANCCU_CREL_DAY_Msk (0xFFU << FDCANCCU_CREL_DAY_Pos) /*!< 0x000000FF */
#define FDCANCCU_CREL_DAY FDCANCCU_CREL_DAY_Msk /*!<Timestamp Day */
#define FDCANCCU_CREL_MON_Pos (8U)
#define FDCANCCU_CREL_MON_Msk (0xFFU << FDCANCCU_CREL_MON_Pos) /*!< 0x0000FF00 */
#define FDCANCCU_CREL_MON FDCANCCU_CREL_MON_Msk /*!<Timestamp Month */
#define FDCANCCU_CREL_YEAR_Pos (16U)
#define FDCANCCU_CREL_YEAR_Msk (0xFU << FDCANCCU_CREL_YEAR_Pos) /*!< 0x000F0000 */
#define FDCANCCU_CREL_YEAR FDCANCCU_CREL_YEAR_Msk /*!<Timestamp Year */
#define FDCANCCU_CREL_SUBSTEP_Pos (20U)
#define FDCANCCU_CREL_SUBSTEP_Msk (0xFU << FDCANCCU_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
#define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
#define FDCANCCU_CREL_STEP_Pos (24U)
#define FDCANCCU_CREL_STEP_Msk (0xFU << FDCANCCU_CREL_STEP_Pos) /*!< 0x0F000000 */
#define FDCANCCU_CREL_STEP FDCANCCU_CREL_STEP_Msk /*!<Step of Core release */
#define FDCANCCU_CREL_REL_Pos (28U)
#define FDCANCCU_CREL_REL_Msk (0xFU << FDCANCCU_CREL_REL_Pos) /*!< 0xF0000000 */
#define FDCANCCU_CREL_REL FDCANCCU_CREL_REL_Msk /*!<Core release */
/***************** Bit definition for FDCANCCU_CCFG register ******************/
#define FDCANCCU_CCFG_TQBT_Pos (0U)
#define FDCANCCU_CCFG_TQBT_Msk (0x1FU << FDCANCCU_CCFG_TQBT_Pos) /*!< 0x0000001F */
#define FDCANCCU_CCFG_TQBT FDCANCCU_CCFG_TQBT_Msk /*!<Time Quanta per Bit Time */
#define FDCANCCU_CCFG_BCC_Pos (6U)
#define FDCANCCU_CCFG_BCC_Msk (0x1U << FDCANCCU_CCFG_BCC_Pos) /*!< 0x00000040 */
#define FDCANCCU_CCFG_BCC FDCANCCU_CCFG_BCC_Msk /*!<Bypass Clock Calibration */
#define FDCANCCU_CCFG_CFL_Pos (7U)
#define FDCANCCU_CCFG_CFL_Msk (0x1U << FDCANCCU_CCFG_CFL_Pos) /*!< 0x00000080 */
#define FDCANCCU_CCFG_CFL FDCANCCU_CCFG_CFL_Msk /*!<Calibration Field Length */
#define FDCANCCU_CCFG_OCPM_Pos (8U)
#define FDCANCCU_CCFG_OCPM_Msk (0xFFU << FDCANCCU_CCFG_OCPM_Pos) /*!< 0x0000FF00 */
#define FDCANCCU_CCFG_OCPM FDCANCCU_CCFG_OCPM_Msk /*!<Oscillator Clock Periods Minimum */
#define FDCANCCU_CCFG_CDIV_Pos (16U)
#define FDCANCCU_CCFG_CDIV_Msk (0xFU << FDCANCCU_CCFG_CDIV_Pos) /*!< 0x000F0000 */
#define FDCANCCU_CCFG_CDIV FDCANCCU_CCFG_CDIV_Msk /*!<Clock Divider */
#define FDCANCCU_CCFG_SWR_Pos (31U)
#define FDCANCCU_CCFG_SWR_Msk (0x1U << FDCANCCU_CCFG_SWR_Pos) /*!< 0x80000000 */
#define FDCANCCU_CCFG_SWR FDCANCCU_CCFG_SWR_Msk /*!<Software Reset */
/***************** Bit definition for FDCANCCU_CSTAT register *****************/
#define FDCANCCU_CSTAT_OCPC_Pos (0U)
#define FDCANCCU_CSTAT_OCPC_Msk (0x3FFFFU << FDCANCCU_CSTAT_OCPC_Pos) /*!< 0x0003FFFF */
#define FDCANCCU_CSTAT_OCPC FDCANCCU_CSTAT_OCPC_Msk /*!<Oscillator Clock Period Counter */
#define FDCANCCU_CSTAT_TQC_Pos (18U)
#define FDCANCCU_CSTAT_TQC_Msk (0x7FFU << FDCANCCU_CSTAT_TQC_Pos) /*!< 0x1FFC0000 */
#define FDCANCCU_CSTAT_TQC FDCANCCU_CSTAT_TQC_Msk /*!<Time Quanta Counter */
#define FDCANCCU_CSTAT_CALS_Pos (30U)
#define FDCANCCU_CSTAT_CALS_Msk (0x3U << FDCANCCU_CSTAT_CALS_Pos) /*!< 0xC0000000 */
#define FDCANCCU_CSTAT_CALS FDCANCCU_CSTAT_CALS_Msk /*!<Calibration State */
/****************** Bit definition for FDCANCCU_CWD register ******************/
#define FDCANCCU_CWD_WDC_Pos (0U)
#define FDCANCCU_CWD_WDC_Msk (0xFFFFU << FDCANCCU_CWD_WDC_Pos) /*!< 0x0000FFFF */
#define FDCANCCU_CWD_WDC FDCANCCU_CWD_WDC_Msk /*!<Watchdog Configuration */
#define FDCANCCU_CWD_WDV_Pos (16U)
#define FDCANCCU_CWD_WDV_Msk (0xFFFFU << FDCANCCU_CWD_WDV_Pos) /*!< 0xFFFF0000 */
#define FDCANCCU_CWD_WDV FDCANCCU_CWD_WDV_Msk /*!<Watchdog Value */
/****************** Bit definition for FDCANCCU_IR register *******************/
#define FDCANCCU_IR_CWE_Pos (0U)
#define FDCANCCU_IR_CWE_Msk (0x1U << FDCANCCU_IR_CWE_Pos) /*!< 0x00000001 */
#define FDCANCCU_IR_CWE FDCANCCU_IR_CWE_Msk /*!<Calibration Watchdog Event */
#define FDCANCCU_IR_CSC_Pos (1U)
#define FDCANCCU_IR_CSC_Msk (0x1U << FDCANCCU_IR_CSC_Pos) /*!< 0x00000002 */
#define FDCANCCU_IR_CSC FDCANCCU_IR_CSC_Msk /*!<Calibration State Changed */
/****************** Bit definition for FDCANCCU_IE register *******************/
#define FDCANCCU_IE_CWEE_Pos (0U)
#define FDCANCCU_IE_CWEE_Msk (0x1U << FDCANCCU_IE_CWEE_Pos) /*!< 0x00000001 */
#define FDCANCCU_IE_CWEE FDCANCCU_IE_CWEE_Msk /*!<Calibration Watchdog Event Enable */
#define FDCANCCU_IE_CSCE_Pos (1U)
#define FDCANCCU_IE_CSCE_Msk (0x1U << FDCANCCU_IE_CSCE_Pos) /*!< 0x00000002 */
#define FDCANCCU_IE_CSCE FDCANCCU_IE_CSCE_Msk /*!<Calibration State Changed Enable */
/******************************************************************************/
/* */
/* HDMI-CEC (CEC) */
/* */
/******************************************************************************/
/******************* Bit definition for CEC_CR register *********************/
#define CEC_CR_CECEN_Pos (0U)
#define CEC_CR_CECEN_Msk (0x1U << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
#define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
#define CEC_CR_TXSOM_Pos (1U)
#define CEC_CR_TXSOM_Msk (0x1U << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
#define CEC_CR_TXEOM_Pos (2U)
#define CEC_CR_TXEOM_Msk (0x1U << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
/******************* Bit definition for CEC_CFGR register *******************/
#define CEC_CFGR_SFT_Pos (0U)
#define CEC_CFGR_SFT_Msk (0x7U << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
#define CEC_CFGR_RXTOL_Pos (3U)
#define CEC_CFGR_RXTOL_Msk (0x1U << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
#define CEC_CFGR_BRESTP_Pos (4U)
#define CEC_CFGR_BRESTP_Msk (0x1U << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
#define CEC_CFGR_BREGEN_Pos (5U)
#define CEC_CFGR_BREGEN_Msk (0x1U << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
#define CEC_CFGR_LBPEGEN_Pos (6U)
#define CEC_CFGR_LBPEGEN_Msk (0x1U << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error generation */
#define CEC_CFGR_SFTOPT_Pos (8U)
#define CEC_CFGR_SFTOPT_Msk (0x1U << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
#define CEC_CFGR_BRDNOGEN_Pos (7U)
#define CEC_CFGR_BRDNOGEN_Msk (0x1U << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No error generation */
#define CEC_CFGR_OAR_Pos (16U)
#define CEC_CFGR_OAR_Msk (0x7FFFU << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
#define CEC_CFGR_LSTN_Pos (31U)
#define CEC_CFGR_LSTN_Msk (0x1U << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
/******************* Bit definition for CEC_TXDR register *******************/
#define CEC_TXDR_TXD_Pos (0U)
#define CEC_TXDR_TXD_Msk (0xFFU << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
/******************* Bit definition for CEC_RXDR register *******************/
#define CEC_TXDR_RXD_Pos (0U)
#define CEC_TXDR_RXD_Msk (0xFFU << CEC_TXDR_RXD_Pos) /*!< 0x000000FF */
#define CEC_TXDR_RXD CEC_TXDR_RXD_Msk /*!< CEC Rx Data */
/******************* Bit definition for CEC_ISR register ********************/
#define CEC_ISR_RXBR_Pos (0U)
#define CEC_ISR_RXBR_Msk (0x1U << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
#define CEC_ISR_RXEND_Pos (1U)
#define CEC_ISR_RXEND_Msk (0x1U << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
#define CEC_ISR_RXOVR_Pos (2U)
#define CEC_ISR_RXOVR_Msk (0x1U << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
#define CEC_ISR_BRE_Pos (3U)
#define CEC_ISR_BRE_Msk (0x1U << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
#define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
#define CEC_ISR_SBPE_Pos (4U)
#define CEC_ISR_SBPE_Msk (0x1U << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
#define CEC_ISR_LBPE_Pos (5U)
#define CEC_ISR_LBPE_Msk (0x1U << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
#define CEC_ISR_RXACKE_Pos (6U)
#define CEC_ISR_RXACKE_Msk (0x1U << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
#define CEC_ISR_ARBLST_Pos (7U)
#define CEC_ISR_ARBLST_Msk (0x1U << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
#define CEC_ISR_TXBR_Pos (8U)
#define CEC_ISR_TXBR_Msk (0x1U << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
#define CEC_ISR_TXEND_Pos (9U)
#define CEC_ISR_TXEND_Msk (0x1U << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
#define CEC_ISR_TXUDR_Pos (10U)
#define CEC_ISR_TXUDR_Msk (0x1U << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
#define CEC_ISR_TXERR_Pos (11U)
#define CEC_ISR_TXERR_Msk (0x1U << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
#define CEC_ISR_TXACKE_Pos (12U)
#define CEC_ISR_TXACKE_Msk (0x1U << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
/******************* Bit definition for CEC_IER register ********************/
#define CEC_IER_RXBRIE_Pos (0U)
#define CEC_IER_RXBRIE_Msk (0x1U << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
#define CEC_IER_RXENDIE_Pos (1U)
#define CEC_IER_RXENDIE_Msk (0x1U << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
#define CEC_IER_RXOVRIE_Pos (2U)
#define CEC_IER_RXOVRIE_Msk (0x1U << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
#define CEC_IER_BREIE_Pos (3U)
#define CEC_IER_BREIE_Msk (0x1U << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
#define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
#define CEC_IER_SBPEIE_Pos (4U)
#define CEC_IER_SBPEIE_Msk (0x1U << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable */
#define CEC_IER_LBPEIE_Pos (5U)
#define CEC_IER_LBPEIE_Msk (0x1U << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
#define CEC_IER_RXACKEIE_Pos (6U)
#define CEC_IER_RXACKEIE_Msk (0x1U << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
#define CEC_IER_ARBLSTIE_Pos (7U)
#define CEC_IER_ARBLSTIE_Msk (0x1U << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
#define CEC_IER_TXBRIE_Pos (8U)
#define CEC_IER_TXBRIE_Msk (0x1U << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
#define CEC_IER_TXENDIE_Pos (9U)
#define CEC_IER_TXENDIE_Msk (0x1U << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
#define CEC_IER_TXUDRIE_Pos (10U)
#define CEC_IER_TXUDRIE_Msk (0x1U << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
#define CEC_IER_TXERRIE_Pos (11U)
#define CEC_IER_TXERRIE_Msk (0x1U << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
#define CEC_IER_TXACKEIE_Pos (12U)
#define CEC_IER_TXACKEIE_Msk (0x1U << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
/******************************************************************************/
/* */
/* CRC calculation unit */
/* */
/******************************************************************************/
/******************* Bit definition for CRC_DR register *********************/
#define CRC_DR_DR_Pos (0U)
#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFFFFFFFU << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET_Pos (0U)
#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
#define CRC_CR_POLYSIZE_Pos (3U)
#define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
#define CRC_CR_REV_IN_Pos (5U)
#define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
#define CRC_CR_REV_OUT_Pos (7U)
#define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
/******************* Bit definition for CRC_INIT register *******************/
#define CRC_INIT_INIT_Pos (0U)
#define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
/******************* Bit definition for CRC_POL register ********************/
#define CRC_POL_POL_Pos (0U)
#define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
/******************************************************************************/
/* */
/* CRS Clock Recovery System */
/******************************************************************************/
/******************* Bit definition for CRS_CR register *********************/
#define CRS_CR_SYNCOKIE_Pos (0U)
#define CRS_CR_SYNCOKIE_Msk (0x1U << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
#define CRS_CR_SYNCWARNIE_Pos (1U)
#define CRS_CR_SYNCWARNIE_Msk (0x1U << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
#define CRS_CR_ERRIE_Pos (2U)
#define CRS_CR_ERRIE_Msk (0x1U << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
#define CRS_CR_ESYNCIE_Pos (3U)
#define CRS_CR_ESYNCIE_Msk (0x1U << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
#define CRS_CR_CEN_Pos (5U)
#define CRS_CR_CEN_Msk (0x1U << CRS_CR_CEN_Pos) /*!< 0x00000020 */
#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
#define CRS_CR_AUTOTRIMEN_Pos (6U)
#define CRS_CR_AUTOTRIMEN_Msk (0x1U << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
#define CRS_CR_SWSYNC_Pos (7U)
#define CRS_CR_SWSYNC_Msk (0x1U << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
#define CRS_CR_TRIM_Pos (8U)
#define CRS_CR_TRIM_Msk (0x3FU << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
#define CRS_CFGR_RELOAD_Msk (0xFFFFU << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
#define CRS_CFGR_FELIM_Pos (16U)
#define CRS_CFGR_FELIM_Msk (0xFFU << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
#define CRS_CFGR_SYNCDIV_Pos (24U)
#define CRS_CFGR_SYNCDIV_Msk (0x7U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
#define CRS_CFGR_SYNCDIV_0 (0x1U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
#define CRS_CFGR_SYNCDIV_1 (0x2U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
#define CRS_CFGR_SYNCDIV_2 (0x4U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
#define CRS_CFGR_SYNCSRC_Pos (28U)
#define CRS_CFGR_SYNCSRC_Msk (0x3U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
#define CRS_CFGR_SYNCSRC_0 (0x1U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
#define CRS_CFGR_SYNCSRC_1 (0x2U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
#define CRS_CFGR_SYNCPOL_Pos (31U)
#define CRS_CFGR_SYNCPOL_Msk (0x1U << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
/******************* Bit definition for CRS_ISR register *********************/
#define CRS_ISR_SYNCOKF_Pos (0U)
#define CRS_ISR_SYNCOKF_Msk (0x1U << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
#define CRS_ISR_SYNCWARNF_Pos (1U)
#define CRS_ISR_SYNCWARNF_Msk (0x1U << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
#define CRS_ISR_ERRF_Pos (2U)
#define CRS_ISR_ERRF_Msk (0x1U << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
#define CRS_ISR_ESYNCF_Pos (3U)
#define CRS_ISR_ESYNCF_Msk (0x1U << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
#define CRS_ISR_SYNCERR_Pos (8U)
#define CRS_ISR_SYNCERR_Msk (0x1U << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
#define CRS_ISR_SYNCMISS_Pos (9U)
#define CRS_ISR_SYNCMISS_Msk (0x1U << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
#define CRS_ISR_TRIMOVF_Pos (10U)
#define CRS_ISR_TRIMOVF_Msk (0x1U << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
#define CRS_ISR_FEDIR_Pos (15U)
#define CRS_ISR_FEDIR_Msk (0x1U << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
#define CRS_ISR_FECAP_Pos (16U)
#define CRS_ISR_FECAP_Msk (0xFFFFU << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
/******************* Bit definition for CRS_ICR register *********************/
#define CRS_ICR_SYNCOKC_Pos (0U)
#define CRS_ICR_SYNCOKC_Msk (0x1U << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
#define CRS_ICR_SYNCWARNC_Pos (1U)
#define CRS_ICR_SYNCWARNC_Msk (0x1U << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
#define CRS_ICR_ERRC_Pos (2U)
#define CRS_ICR_ERRC_Msk (0x1U << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
#define CRS_ICR_ESYNCC_Pos (3U)
#define CRS_ICR_ESYNCC_Msk (0x1U << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
/******************************************************************************/
/* */
/* Crypto Processor */
/* */
/******************************************************************************/
/******************* Bits definition for CRYP_CR register ********************/
#define CRYP_CR_ALGODIR_Pos (2U)
#define CRYP_CR_ALGODIR_Msk (0x1U << CRYP_CR_ALGODIR_Pos) /*!< 0x00000004 */
#define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk
#define CRYP_CR_ALGOMODE_Pos (3U)
#define CRYP_CR_ALGOMODE_Msk (0x10007U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00080038 */
#define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk
#define CRYP_CR_ALGOMODE_0 (0x00001U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
#define CRYP_CR_ALGOMODE_1 (0x00002U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
#define CRYP_CR_ALGOMODE_2 (0x00004U << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1U << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
#define CRYP_CR_ALGOMODE_DES_ECB_Pos (4U)
#define CRYP_CR_ALGOMODE_DES_ECB_Msk (0x1U << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */
#define CRYP_CR_ALGOMODE_DES_ECB CRYP_CR_ALGOMODE_DES_ECB_Msk
#define CRYP_CR_ALGOMODE_DES_CBC_Pos (3U)
#define CRYP_CR_ALGOMODE_DES_CBC_Msk (0x3U << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */
#define CRYP_CR_ALGOMODE_DES_CBC CRYP_CR_ALGOMODE_DES_CBC_Msk
#define CRYP_CR_ALGOMODE_AES_ECB_Pos (5U)
#define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1U << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */
#define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk
#define CRYP_CR_ALGOMODE_AES_CBC_Pos (3U)
#define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5U << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */
#define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk
#define CRYP_CR_ALGOMODE_AES_CTR_Pos (4U)
#define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3U << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */
#define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk
#define CRYP_CR_ALGOMODE_AES_GCM_Pos (19U)
#define CRYP_CR_ALGOMODE_AES_GCM_Msk (0x1U << CRYP_CR_ALGOMODE_AES_GCM_Pos) /*!< 0x00080000 */
#define CRYP_CR_ALGOMODE_AES_GCM CRYP_CR_ALGOMODE_AES_GCM_Msk
#define CRYP_CR_ALGOMODE_AES_CCM_Pos (3U)
#define CRYP_CR_ALGOMODE_AES_CCM_Msk (0x10001U << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */
#define CRYP_CR_ALGOMODE_AES_CCM CRYP_CR_ALGOMODE_AES_CCM_Msk
#define CRYP_CR_ALGOMODE_AES_KEY_Pos (3U)
#define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7U << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */
#define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk
#define CRYP_CR_DATATYPE_Pos (6U)
#define CRYP_CR_DATATYPE_Msk (0x3U << CRYP_CR_DATATYPE_Pos) /*!< 0x000000C0 */
#define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk
#define CRYP_CR_DATATYPE_0 (0x1U << CRYP_CR_DATATYPE_Pos) /*!< 0x00000040 */
#define CRYP_CR_DATATYPE_1 (0x2U << CRYP_CR_DATATYPE_Pos) /*!< 0x00000080 */
#define CRYP_CR_KEYSIZE_Pos (8U)
#define CRYP_CR_KEYSIZE_Msk (0x3U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000300 */
#define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk
#define CRYP_CR_KEYSIZE_0 (0x1U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000100 */
#define CRYP_CR_KEYSIZE_1 (0x2U << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000200 */
#define CRYP_CR_FFLUSH_Pos (14U)
#define CRYP_CR_FFLUSH_Msk (0x1U << CRYP_CR_FFLUSH_Pos) /*!< 0x00004000 */
#define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk
#define CRYP_CR_CRYPEN_Pos (15U)
#define CRYP_CR_CRYPEN_Msk (0x1U << CRYP_CR_CRYPEN_Pos) /*!< 0x00008000 */
#define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk
#define CRYP_CR_GCM_CCMPH_Pos (16U)
#define CRYP_CR_GCM_CCMPH_Msk (0x3U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00030000 */
#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
#define CRYP_CR_GCM_CCMPH_0 (0x1U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
#define CRYP_CR_GCM_CCMPH_1 (0x2U << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
#define CRYP_CR_NPBLB_Pos (20U)
#define CRYP_CR_NPBLB_Msk (0xFU << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */
#define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk
/****************** Bits definition for CRYP_SR register *********************/
#define CRYP_SR_IFEM_Pos (0U)
#define CRYP_SR_IFEM_Msk (0x1U << CRYP_SR_IFEM_Pos) /*!< 0x00000001 */
#define CRYP_SR_IFEM CRYP_SR_IFEM_Msk
#define CRYP_SR_IFNF_Pos (1U)
#define CRYP_SR_IFNF_Msk (0x1U << CRYP_SR_IFNF_Pos) /*!< 0x00000002 */
#define CRYP_SR_IFNF CRYP_SR_IFNF_Msk
#define CRYP_SR_OFNE_Pos (2U)
#define CRYP_SR_OFNE_Msk (0x1U << CRYP_SR_OFNE_Pos) /*!< 0x00000004 */
#define CRYP_SR_OFNE CRYP_SR_OFNE_Msk
#define CRYP_SR_OFFU_Pos (3U)
#define CRYP_SR_OFFU_Msk (0x1U << CRYP_SR_OFFU_Pos) /*!< 0x00000008 */
#define CRYP_SR_OFFU CRYP_SR_OFFU_Msk
#define CRYP_SR_BUSY_Pos (4U)
#define CRYP_SR_BUSY_Msk (0x1U << CRYP_SR_BUSY_Pos) /*!< 0x00000010 */
#define CRYP_SR_BUSY CRYP_SR_BUSY_Msk
/****************** Bits definition for CRYP_DMACR register ******************/
#define CRYP_DMACR_DIEN_Pos (0U)
#define CRYP_DMACR_DIEN_Msk (0x1U << CRYP_DMACR_DIEN_Pos) /*!< 0x00000001 */
#define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk
#define CRYP_DMACR_DOEN_Pos (1U)
#define CRYP_DMACR_DOEN_Msk (0x1U << CRYP_DMACR_DOEN_Pos) /*!< 0x00000002 */
#define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk
/***************** Bits definition for CRYP_IMSCR register ******************/
#define CRYP_IMSCR_INIM_Pos (0U)
#define CRYP_IMSCR_INIM_Msk (0x1U << CRYP_IMSCR_INIM_Pos) /*!< 0x00000001 */
#define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk
#define CRYP_IMSCR_OUTIM_Pos (1U)
#define CRYP_IMSCR_OUTIM_Msk (0x1U << CRYP_IMSCR_OUTIM_Pos) /*!< 0x00000002 */
#define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk
/****************** Bits definition for CRYP_RISR register *******************/
#define CRYP_RISR_OUTRIS_Pos (0U)
#define CRYP_RISR_OUTRIS_Msk (0x1U << CRYP_RISR_OUTRIS_Pos) /*!< 0x00000001 */
#define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk
#define CRYP_RISR_INRIS_Pos (1U)
#define CRYP_RISR_INRIS_Msk (0x1U << CRYP_RISR_INRIS_Pos) /*!< 0x00000002 */
#define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk
/****************** Bits definition for CRYP_MISR register *******************/
#define CRYP_MISR_INMIS_Pos (0U)
#define CRYP_MISR_INMIS_Msk (0x1U << CRYP_MISR_INMIS_Pos) /*!< 0x00000001 */
#define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk
#define CRYP_MISR_OUTMIS_Pos (1U)
#define CRYP_MISR_OUTMIS_Msk (0x1U << CRYP_MISR_OUTMIS_Pos) /*!< 0x00000002 */
#define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk
/********************** Bit definition for CRYP_HWCFGR register ***************/
#define CRYP_HWCFGR_CFG1_Pos (0U)
#define CRYP_HWCFGR_CFG1_Msk (0xFU << CRYP_HWCFGR_CFG1_Pos) /*!< 0x0000000F */
#define CRYP_HWCFGR_CFG1 CRYP_HWCFGR_CFG1_Msk /*!< HW Generic 1 */
#define CRYP_HWCFGR_CFG2_Pos (4U)
#define CRYP_HWCFGR_CFG2_Msk (0xFU << CRYP_HWCFGR_CFG2_Pos) /*!< 0x000000F0 */
#define CRYP_HWCFGR_CFG2 CRYP_HWCFGR_CFG2_Msk /*!< HW Generic 2 */
#define CRYP_HWCFGR_CFG3_Pos (8U)
#define CRYP_HWCFGR_CFG3_Msk (0xFU << CRYP_HWCFGR_CFG3_Pos) /*!< 0x00000F00 */
#define CRYP_HWCFGR_CFG3 CRYP_HWCFGR_CFG3_Msk /*!< HW Generic 3 */
#define CRYP_HWCFGR_CFG4_Pos (12U)
#define CRYP_HWCFGR_CFG4_Msk (0xFU << CRYP_HWCFGR_CFG4_Pos) /*!< 0x0000F000 */
#define CRYP_HWCFGR_CFG4 CRYP_HWCFGR_CFG4_Msk /*!< HW Generic 4 */
/********************** Bit definition for CRYP_VERR register *****************/
#define CRYP_VERR_VER_Pos (0U)
#define CRYP_VERR_VER_Msk (0xFFU << CRYP_VERR_VER_Pos) /*!< 0x000000FF */
#define CRYP_VERR_VER CRYP_VERR_VER_Msk /*!< Revision number */
/********************** Bit definition for CRYP_IPIDR register ****************/
#define CRYP_IPIDR_IPID_Pos (0U)
#define CRYP_IPIDR_IPID_Msk (0xFFFFFFFFU << CRYP_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
#define CRYP_IPIDR_IPID CRYP_IPIDR_IPID_Msk /*!< IP Identification */
/********************** Bit definition for CRYP_SIDR register *****************/
#define CRYP_MID_MID_Pos (0U)
#define CRYP_MID_MID_Msk (0xFFFFFFFFU << CRYP_MID_MID_Pos) /*!< 0xFFFFFFFF */
#define CRYP_MID_MID CRYP_MID_MID_Msk /*!< IP size identification */
/******************************************************************************/
/* */
/* Digital to Analog Converter */
/* */
/******************************************************************************/
/******************** Bit definition for DAC_CR register ********************/
#define DAC_CR_EN1_Pos (0U)
#define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
#define DAC_CR_TEN1_Pos (1U)
#define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
#define DAC_CR_TSEL1_Pos (2U)
#define DAC_CR_TSEL1_Msk (0xFU << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
#define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
#define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
#define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
#define DAC_CR_TSEL1_3 (0x8U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
#define DAC_CR_WAVE1_Pos (6U)
#define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
#define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
#define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
#define DAC_CR_MAMP1_Pos (8U)
#define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
#define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
#define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
#define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
#define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
#define DAC_CR_DMAEN1_Pos (12U)
#define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
#define DAC_CR_DMAUDRIE1_Pos (13U)
#define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
#define DAC_CR_CEN1_Pos (14U)
#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
#define DAC_CR_HFSEL_Pos (15U)
#define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */
#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!<High frequency interface mode enable >*/
#define DAC_CR_EN2_Pos (16U)
#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
#define DAC_CR_TEN2_Pos (17U)
#define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
#define DAC_CR_TSEL2_Pos (18U)
#define DAC_CR_TSEL2_Msk (0xFU << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
#define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
#define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
#define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
#define DAC_CR_TSEL2_3 (0x8U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
#define DAC_CR_WAVE2_Pos (22U)
#define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
#define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
#define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
#define DAC_CR_MAMP2_Pos (24U)
#define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
#define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
#define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
#define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
#define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
#define DAC_CR_DMAEN2_Pos (28U)
#define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
#define DAC_CR_DMAUDRIE2_Pos (29U)
#define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
#define DAC_CR_CEN2_Pos (30U)
#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
/***************** Bit definition for DAC_SWTRIGR register ******************/
#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */
#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */
/***************** Bit definition for DAC_DHR12R1 register ******************/
#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12L1 register ******************/
#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8R1 register ******************/
#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
/***************** Bit definition for DAC_DHR12R2 register ******************/
#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12L2 register ******************/
#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8R2 register ******************/
#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
/***************** Bit definition for DAC_DHR12RD register ******************/
#define DAC_DHR12RD_DACC1DHR_Pos (0U)
#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
#define DAC_DHR12RD_DACC2DHR_Pos (16U)
#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12LD register ******************/
#define DAC_DHR12LD_DACC1DHR_Pos (4U)
#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
#define DAC_DHR12LD_DACC2DHR_Pos (20U)
#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8RD register ******************/
#define DAC_DHR8RD_DACC1DHR_Pos (0U)
#define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
#define DAC_DHR8RD_DACC2DHR_Pos (0U)
#define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
/******************* Bit definition for DAC_DOR1 register *******************/
#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */
/******************* Bit definition for DAC_DOR2 register *******************/
#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */
/******************** Bit definition for DAC_SR register ********************/
#define DAC_SR_DMAUDR1_Pos (13U)
#define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
#define DAC_SR_CAL_FLAG1_Pos (14U)
#define DAC_SR_CAL_FLAG1_Msk (0x1U << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
#define DAC_SR_BWST1_Pos (15U)
#define DAC_SR_BWST1_Msk (0x4001U << DAC_SR_BWST1_Pos) /*!< 0x20008000 */
#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
#define DAC_SR_DMAUDR2_Pos (29U)
#define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
#define DAC_SR_CAL_FLAG2_Pos (30U)
#define DAC_SR_CAL_FLAG2_Msk (0x1U << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
#define DAC_SR_BWST2_Pos (31U)
#define DAC_SR_BWST2_Msk (0x1U << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
/******************* Bit definition for DAC_CCR register ********************/
#define DAC_CCR_OTRIM1_Pos (0U)
#define DAC_CCR_OTRIM1_Msk (0x1FU << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
#define DAC_CCR_OTRIM2_Pos (16U)
#define DAC_CCR_OTRIM2_Msk (0x1FU << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
/******************* Bit definition for DAC_MCR register *******************/
#define DAC_MCR_MODE1_Pos (0U)
#define DAC_MCR_MODE1_Msk (0x7U << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
#define DAC_MCR_MODE1_0 (0x1U << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
#define DAC_MCR_MODE1_1 (0x2U << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
#define DAC_MCR_MODE1_2 (0x4U << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
#define DAC_MCR_MODE2_Pos (16U)
#define DAC_MCR_MODE2_Msk (0x7U << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
#define DAC_MCR_MODE2_0 (0x1U << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
#define DAC_MCR_MODE2_1 (0x2U << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
#define DAC_MCR_MODE2_2 (0x4U << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
/****************** Bit definition for DAC_SHSR1 register ******************/
#define DAC_SHSR1_TSAMPLE1_Pos (0U)
#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
/****************** Bit definition for DAC_SHSR2 register ******************/
#define DAC_SHSR1_TSAMPLE2_Pos (0U)
#define DAC_SHSR1_TSAMPLE2_Msk (0x3FFU << DAC_SHSR1_TSAMPLE2_Pos) /*!< 0x000003FF */
#define DAC_SHSR1_TSAMPLE2 DAC_SHSR1_TSAMPLE2_Msk /*!<DAC channel2 sample time */
/****************** Bit definition for DAC_SHHR register ******************/
#define DAC_SHHR_THOLD1_Pos (0U)
#define DAC_SHHR_THOLD1_Msk (0x3FFU << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
#define DAC_SHHR_THOLD2_Pos (16U)
#define DAC_SHHR_THOLD2_Msk (0x3FFU << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
/****************** Bit definition for DAC_SHRR register ******************/
#define DAC_SHRR_TREFRESH1_Pos (0U)
#define DAC_SHRR_TREFRESH1_Msk (0xFFU << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
#define DAC_SHRR_TREFRESH2_Pos (16U)
#define DAC_SHRR_TREFRESH2_Msk (0xFFU << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
/********************** Bit definition for DAC_HWCFGR0 register ***************/
#define DAC_HWCFGR0_DUAL_Pos (0U)
#define DAC_HWCFGR0_DUAL_Msk (0xFF << DAC_HWCFGR0_DUAL_Pos) /*!< 0x0000000F */
#define DAC_HWCFGR0_DUAL DAC_HWCFGR0_DUAL_Msk /*!< Dual DAC capability */
#define DAC_HWCFGR0_LFSR_Pos (4U)
#define DAC_HWCFGR0_LFSR_Msk (0xFU << DAC_HWCFGR0_LFSR_Pos) /*!< 0x000000F0 */
#define DAC_HWCFGR0_LFSR DAC_HWCFGR0_LFSR_Msk /*!< Pseudonoise wave generation capability */
#define DAC_HWCFGR0_TRIANGLE_Pos (8U)
#define DAC_HWCFGR0_TRIANGLE_Msk (0xFU << DAC_HWCFGR0_TRIANGLE_Pos) /*!< 0x00000F00 */
#define DAC_HWCFGR0_TRIANGLE DAC_HWCFGR0_TRIANGLE_Msk /*!< Triangle wave generation capability */
#define DAC_HWCFGR0_SAMPLE_Pos (12U)
#define DAC_HWCFGR0_SAMPLE_Msk (0xFU << DAC_HWCFGR0_SAMPLE_Pos) /*!< 0x0000F000 */
#define DAC_HWCFGR0_SAMPLE DAC_HWCFGR0_SAMPLE_Msk /*!< Sample and Hold mode capability */
#define DAC_HWCFGR0_OR_CFG_Pos (16U)
#define DAC_HWCFGR0_OR_CFG_Msk (0xFFU << DAC_HWCFGR0_OR_CFG_Pos) /*!< 0x00FF0000 */
#define DAC_HWCFGR0_OR_CFG DAC_HWCFGR0_OR_CFG_Msk /*!< option register bit width */
/******************** Bit definition for DAC_VERR register********************/
#define DAC_VERR_MINREV_Pos (0U)
#define DAC_VERR_MINREV_Msk (0xFU << DAC_VERR_MINREV_Pos) /*!< 0x0000000F */
#define DAC_VERR_MINREV DAC_VERR_MINREV_Msk /*!< MAJREV[3:0] bits (Minor revision) */
#define DAC_VERR_MAJREV_Pos (4U)
#define DAC_VERR_MAJREV_Msk (0xFU << DAC_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define DAC_VERR_MAJREV DAC_VERR_MAJREV_Msk /*!< MINREV[3:0] bits (Major revision) */
/********************** Bit definition for DAC_IPIDR register ****************/
#define DAC_IPIDR_IPID_Pos (0U)
#define DAC_IPIDR_IPID_Msk (0xFFFFFFFFU << DAC_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
#define DAC_IPIDR_IPID DAC_IPIDR_IPID_Msk /*!< IP Identification */
/********************** Bit definition for DAC_SIDR register *****************/
#define DAC_SIDR_SID_Pos (0U)
#define DAC_SIDR_SID_Msk (0xFFFFFFFFU << DAC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define DAC_SIDR_SID DAC_SIDR_SID_Msk /*!< IP size identification */
/******************************************************************************/
/* */
/* DBG */
/* */
/******************************************************************************/
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
#define DBGMCU_IDCODE_REV_ID_Pos (16U)
#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
/******************** Bit definition for DBGMCU_CR register *****************/
#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
#define DBGMCU_CR_DBG_STOP_Pos (1U)
#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
#define DBGMCU_CR_DBG_WDFZCTL_Pos (24U)
#define DBGMCU_CR_DBG_WDFZCTL_Msk (0x1U << DBGMCU_CR_DBG_WDFZCTL_Pos) /*!< 0x01000000 */
#define DBGMCU_CR_DBG_WDFZCTL DBGMCU_CR_DBG_WDFZCTL_Msk
#define DBGMCU_CR_DBG_TRGOEN_Pos (28U)
#define DBGMCU_CR_DBG_TRGOEN_Msk (0x1U << DBGMCU_CR_DBG_TRGOEN_Pos) /*!< 0x10000000 */
#define DBGMCU_CR_DBG_TRGOEN DBGMCU_CR_DBG_TRGOEN_Msk
/******************** Bit definition for APB4FZ register ************/
#define DBGMCU_APB4_FZ_DBG_IWDG2_STOP_Pos (2U)
#define DBGMCU_APB4_FZ_DBG_IWDG2_STOP_Msk (0x1U << DBGMCU_APB4_FZ_DBG_IWDG2_STOP_Pos) /*!< 0x00000004 */
#define DBGMCU_APB4_FZ_DBG_IWDG2_STOP DBGMCU_APB4_FZ_DBG_IWDG2_STOP_Msk
/******************** Bit definition for APB1FZ register ************/
#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos (9U)
#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos) /*!< 0x00000200 */
#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk
#define DBGMCU_APB1_FZ_DBG_WWDG1_STOP_Pos (10U)
#define DBGMCU_APB1_FZ_DBG_WWDG1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG1_STOP_Pos) /*!< 0x00000400 */
#define DBGMCU_APB1_FZ_DBG_WWDG1_STOP DBGMCU_APB1_FZ_DBG_WWDG1_STOP_Msk
#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (18U)
#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00040000 */
#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk
#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos (19U)
#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00080000 */
#define DBGMCU_APB1_FZ_DBG_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk
#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos (20U)
#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos) /*!< 0x00100000 */
#define DBGMCU_APB1_FZ_DBG_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk
#define DBGMCU_APB1_FZ_DBG_I2C5_STOP_Pos (21U)
#define DBGMCU_APB1_FZ_DBG_I2C5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C5_STOP_Pos) /*!< 0x00200000 */
#define DBGMCU_APB1_FZ_DBG_I2C5_STOP DBGMCU_APB1_FZ_DBG_I2C5_STOP_Msk
/******************** Bit definition for APB2FZ register ************/
#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
#define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (6U)
#define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00000040 */
#define DBGMCU_APB2_FZ_DBG_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk
#define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (7U)
#define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00000080 */
#define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk
#define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (8U)
#define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00000100 */
#define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk
#define DBGMCU_APB2_FZ_DBG_FDCAN_STOP_Pos (15U)
#define DBGMCU_APB2_FZ_DBG_FDCAN_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_FDCAN_STOP_Pos) /*!< 0x00008000 */
#define DBGMCU_APB2_FZ_DBG_FDCAN_STOP DBGMCU_APB2_FZ_DBG_FDCAN_STOP_Msk
/******************** Bit definition for APB3FZ register ************/
#define DBGMCU_APB3_FZ_DBG_LPTIM2_STOP_Pos (1U)
#define DBGMCU_APB3_FZ_DBG_LPTIM2_STOP_Msk (0x1U << DBGMCU_APB3_FZ_DBG_LPTIM2_STOP_Pos) /*!< 0x00000002 */
#define DBGMCU_APB3_FZ_DBG_LPTIM2_STOP DBGMCU_APB3_FZ_DBG_LPTIM2_STOP_Msk
#define DBGMCU_APB3_FZ_DBG_LPTIM3_STOP_Pos (2U)
#define DBGMCU_APB3_FZ_DBG_LPTIM3_STOP_Msk (0x1U << DBGMCU_APB3_FZ_DBG_LPTIM3_STOP_Pos) /*!< 0x00000004 */
#define DBGMCU_APB3_FZ_DBG_LPTIM3_STOP DBGMCU_APB3_FZ_DBG_LPTIM3_STOP_Msk
#define DBGMCU_APB3_FZ_DBG_LPTIM4_STOP_Pos (3U)
#define DBGMCU_APB3_FZ_DBG_LPTIM4_STOP_Msk (0x1U << DBGMCU_APB3_FZ_DBG_LPTIM4_STOP_Pos) /*!< 0x00000008 */
#define DBGMCU_APB3_FZ_DBG_LPTIM4_STOP DBGMCU_APB3_FZ_DBG_LPTIM4_STOP_Msk
#define DBGMCU_APB3_FZ_DBG_LPTIM5_STOP_Pos (4U)
#define DBGMCU_APB3_FZ_DBG_LPTIM5_STOP_Msk (0x1U << DBGMCU_APB3_FZ_DBG_LPTIM5_STOP_Pos) /*!< 0x00000010 */
#define DBGMCU_APB3_FZ_DBG_LPTIM5_STOP DBGMCU_APB3_FZ_DBG_LPTIM5_STOP_Msk
/******************** Bit definition for APB5FZ register ************/
#define DBGMCU_APB5_FZ_DBG_I2C4_STOP_Pos (2U)
#define DBGMCU_APB5_FZ_DBG_I2C4_STOP_Msk (0x1U << DBGMCU_APB5_FZ_DBG_I2C4_STOP_Pos) /*!< 0x00000004 */
#define DBGMCU_APB5_FZ_DBG_I2C4_STOP DBGMCU_APB5_FZ_DBG_I2C4_STOP_Msk
#define DBGMCU_APB5_FZ_DBG_IWDG1_STOP_Pos (3U)
#define DBGMCU_APB5_FZ_DBG_IWDG1_STOP_Msk (0x1U << DBGMCU_APB5_FZ_DBG_IWDG1_STOP_Pos) /*!< 0x00000008 */
#define DBGMCU_APB5_FZ_DBG_IWDG1_STOP DBGMCU_APB5_FZ_DBG_IWDG1_STOP_Msk
#define DBGMCU_APB5_FZ_DBG_RTC_STOP_Pos (4U)
#define DBGMCU_APB5_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB5_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000010 */
#define DBGMCU_APB5_FZ_DBG_RTC_STOP DBGMCU_APB5_FZ_DBG_RTC_STOP_Msk
#define DBGMCU_APB5_FZ_DBG_I2C6_STOP_Pos (9U)
#define DBGMCU_APB5_FZ_DBG_I2C6_STOP_Msk (0x1U << DBGMCU_APB5_FZ_DBG_I2C6_STOP_Pos) /*!< 0x00000200 */
#define DBGMCU_APB5_FZ_DBG_I2C6_STOP DBGMCU_APB5_FZ_DBG_I2C6_STOP_Msk
/******************************************************************************/
/* */
/* DCMI */
/* */
/******************************************************************************/
/******************** Bits definition for DCMI_CR register ******************/
#define DCMI_CR_CAPTURE_Pos (0U)
#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
#define DCMI_CR_CM_Pos (1U)
#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */
#define DCMI_CR_CM DCMI_CR_CM_Msk
#define DCMI_CR_CROP_Pos (2U)
#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
#define DCMI_CR_CROP DCMI_CR_CROP_Msk
#define DCMI_CR_JPEG_Pos (3U)
#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
#define DCMI_CR_ESS_Pos (4U)
#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
#define DCMI_CR_ESS DCMI_CR_ESS_Msk
#define DCMI_CR_PCKPOL_Pos (5U)
#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
#define DCMI_CR_HSPOL_Pos (6U)
#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
#define DCMI_CR_VSPOL_Pos (7U)
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
#define DCMI_CR_CRE_Pos (12U)
#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
#define DCMI_CR_CRE DCMI_CR_CRE_Msk
#define DCMI_CR_ENABLE_Pos (14U)
#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
#define DCMI_CR_BSM_Pos (16U)
#define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) /*!< 0x00030000 */
#define DCMI_CR_BSM DCMI_CR_BSM_Msk
#define DCMI_CR_BSM_0 (0x1U << DCMI_CR_BSM_Pos) /*!< 0x00010000 */
#define DCMI_CR_BSM_1 (0x2U << DCMI_CR_BSM_Pos) /*!< 0x00020000 */
#define DCMI_CR_OEBS_Pos (18U)
#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
#define DCMI_CR_LSM_Pos (19U)
#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
#define DCMI_CR_LSM DCMI_CR_LSM_Msk
#define DCMI_CR_OELS_Pos (20U)
#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
#define DCMI_CR_OELS DCMI_CR_OELS_Msk
/******************** Bits definition for DCMI_SR register ******************/
#define DCMI_SR_HSYNC_Pos (0U)
#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
#define DCMI_SR_VSYNC_Pos (1U)
#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
#define DCMI_SR_FNE_Pos (2U)
#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
#define DCMI_SR_FNE DCMI_SR_FNE_Msk
/******************** Bits definition for DCMI_RIS register ****************/
#define DCMI_RIS_FRAME_RIS_Pos (0U)
#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
#define DCMI_RIS_OVR_RIS_Pos (1U)
#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
#define DCMI_RIS_ERR_RIS_Pos (2U)
#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
#define DCMI_RIS_VSYNC_RIS_Pos (3U)
#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
#define DCMI_RIS_LINE_RIS_Pos (4U)
#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
/******************** Bits definition for DCMI_IER register *****************/
#define DCMI_IER_FRAME_IE_Pos (0U)
#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
#define DCMI_IER_OVR_IE_Pos (1U)
#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
#define DCMI_IER_ERR_IE_Pos (2U)
#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
#define DCMI_IER_VSYNC_IE_Pos (3U)
#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
#define DCMI_IER_LINE_IE_Pos (4U)
#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
/******************** Bits definition for DCMI_MIS register *****************/
#define DCMI_MIS_FRAME_MIS_Pos (0U)
#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
#define DCMI_MIS_OVR_MIS_Pos (1U)
#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
#define DCMI_MIS_ERR_MIS_Pos (2U)
#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
#define DCMI_MIS_VSYNC_MIS_Pos (3U)
#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
#define DCMI_MIS_LINE_MIS_Pos (4U)
#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
/******************** Bits definition for DCMI_ICR register *****************/
#define DCMI_ICR_FRAME_ISC_Pos (0U)
#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
#define DCMI_ICR_OVR_ISC_Pos (1U)
#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
#define DCMI_ICR_ERR_ISC_Pos (2U)
#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
#define DCMI_ICR_VSYNC_ISC_Pos (3U)
#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
#define DCMI_ICR_LINE_ISC_Pos (4U)
#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
/******************** Bits definition for DCMI_ESCR register ******************/
#define DCMI_ESCR_FSC_Pos (0U)
#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
#define DCMI_ESCR_LSC_Pos (8U)
#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
#define DCMI_ESCR_LEC_Pos (16U)
#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
#define DCMI_ESCR_FEC_Pos (24U)
#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
/******************** Bits definition for DCMI_ESUR register ******************/
#define DCMI_ESUR_FSU_Pos (0U)
#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
#define DCMI_ESUR_LSU_Pos (8U)
#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
#define DCMI_ESUR_LEU_Pos (16U)
#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
#define DCMI_ESUR_FEU_Pos (24U)
#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
/******************** Bits definition for DCMI_CWSTRT register ******************/
#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
#define DCMI_CWSTRT_VST_Pos (16U)
#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
/******************** Bits definition for DCMI_CWSIZE register ******************/
#define DCMI_CWSIZE_CAPCNT_Pos (0U)
#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
#define DCMI_CWSIZE_VLINE_Pos (16U)
#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
/******************** Bits definition for DCMI_DR register ******************/
#define DCMI_DR_BYTE0_Pos (0U)
#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
#define DCMI_DR_BYTE1_Pos (8U)
#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
#define DCMI_DR_BYTE2_Pos (16U)
#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
#define DCMI_DR_BYTE3_Pos (24U)
#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
/******************************************************************************/
/* */
/* Digital Filter for Sigma Delta Modulators */
/* */
/******************************************************************************/
/**************** DFSDM channel configuration registers ********************/
/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
#define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
#define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
#define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
#define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
#define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
#define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
#define DFSDM_CHCFGR1_CHEN_Pos (7U)
#define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
#define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
#define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
#define DFSDM_CHCFGR1_SITP_Pos (0U)
#define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
#define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
#define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos)/*!< 0xFFFFFF00 */
#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
/**************** Bit definition for DFSDM_CHAWSCDR register *****************/
#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
#define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
#define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
/**************** Bit definition for DFSDM_CHWDATR register *******************/
#define DFSDM_CHWDATR_WDATA_Pos (0U)
#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
/**************** Bit definition for DFSDM_CHDATINR register *****************/
#define DFSDM_CHDATINR_INDAT0_Pos (0U)
#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos)/*!< 0x0000FFFF */
#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
#define DFSDM_CHDATINR_INDAT1_Pos (16U)
#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos)/*!< 0xFFFF0000 */
#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
/**************** Bit definition for DFSDM_CHDLYR register *******************/
#define DFSDM_CHDLYR_PLSSKP_Pos (0U)
#define DFSDM_CHDLYR_PLSSKP_Msk (0x3FUL << DFSDM_CHDLYR_PLSSKP_Pos) /*!< 0x0000003F */
#define DFSDM_CHDLYR_PLSSKP DFSDM_CHDLYR_PLSSKP_Msk /*!< PLSSKP[5:0] Number of input serial samples that will be skipped */
/************************ DFSDM module registers ****************************/
/***************** Bit definition for DFSDM_FLTCR1 register *******************/
#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
#define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
#define DFSDM_FLTCR1_FAST_Pos (29U)
#define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
#define DFSDM_FLTCR1_RCH_Pos (24U)
#define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
#define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
#define DFSDM_FLTCR1_RSYNC_Pos (19U)
#define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
#define DFSDM_FLTCR1_RCONT_Pos (18U)
#define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
#define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
#define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
#define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
#define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
#define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001F00 */
#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
#define DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001000 */
#define DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000800 */
#define DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
#define DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
#define DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
#define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
#define DFSDM_FLTCR1_JSCAN_Pos (4U)
#define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
#define DFSDM_FLTCR1_JSYNC_Pos (3U)
#define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
#define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
#define DFSDM_FLTCR1_DFEN_Pos (0U)
#define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
/***************** Bit definition for DFSDM_FLTCR2 register *******************/
#define DFSDM_FLTCR2_AWDCH_Pos (16U)
#define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
#define DFSDM_FLTCR2_EXCH_Pos (8U)
#define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
#define DFSDM_FLTCR2_CKABIE_Pos (6U)
#define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
#define DFSDM_FLTCR2_SCDIE_Pos (5U)
#define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
#define DFSDM_FLTCR2_AWDIE_Pos (4U)
#define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
#define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
#define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
#define DFSDM_FLTCR2_REOCIE_Pos (1U)
#define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
#define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
/***************** Bit definition for DFSDM_FLTISR register *******************/
#define DFSDM_FLTISR_SCDF_Pos (24U)
#define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
#define DFSDM_FLTISR_CKABF_Pos (16U)
#define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
#define DFSDM_FLTISR_RCIP_Pos (14U)
#define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
#define DFSDM_FLTISR_JCIP_Pos (13U)
#define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
#define DFSDM_FLTISR_AWDF_Pos (4U)
#define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
#define DFSDM_FLTISR_ROVRF_Pos (3U)
#define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
#define DFSDM_FLTISR_JOVRF_Pos (2U)
#define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
#define DFSDM_FLTISR_REOCF_Pos (1U)
#define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
#define DFSDM_FLTISR_JEOCF_Pos (0U)
#define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
/***************** Bit definition for DFSDM_FLTICR register *******************/
#define DFSDM_FLTICR_CLRSCDF_Pos (24U)
#define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0xFF000000 */
#define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk /*!< CLRSCDF[7:0] Clear the short circuit detector flag */
#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
#define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
/**************** Bit definition for DFSDM_FLTJCHGR register ******************/
#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
/***************** Bit definition for DFSDM_FLTFCR register *******************/
#define DFSDM_FLTFCR_FORD_Pos (29U)
#define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
#define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
#define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
#define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
#define DFSDM_FLTFCR_FOSR_Pos (16U)
#define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
#define DFSDM_FLTFCR_IOSR_Pos (0U)
#define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
/*************** Bit definition for DFSDM_FLTJDATAR register *****************/
#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos)/*!< 0xFFFFFF00 */
#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
/*************** Bit definition for DFSDM_FLTRDATAR register *****************/
#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos)/*!< 0xFFFFFF00 */
#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
#define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
/*************** Bit definition for DFSDM_FLTAWHTR register ******************/
#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos)/*!< 0xFFFFFF00 */
#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
/*************** Bit definition for DFSDM_FLTAWLTR register ******************/
#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos)/*!< 0xFFFFFF00 */
#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWLT[23:0] Analog watchdog low threshold */
#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
/*************** Bit definition for DFSDM_FLTAWSR register *******************/
#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
/*************** Bit definition for DFSDM_FLTAWCFR register ******************/
#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos)/*!< 0x0000FF00 */
#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos)/*!< 0x000000FF */
#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
/*************** Bit definition for DFSDM_FLTEXMAX register ******************/
#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos)/*!< 0xFFFFFF00 */
#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
/*************** Bit definition for DFSDM_FLTEXMIN register ******************/
#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos)/*!< 0xFFFFFF00 */
#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
/*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos)/*!< 0xFFFFFFF0 */
#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
/********************** Bit definition for DFSDM_HWCFGR register ***************/
#define DFSDM_HWCFGR_NBT_Pos (0U)
#define DFSDM_HWCFGR_NBT_Msk (0xFFU << DFSDM_HWCFGR_NBT_Pos) /*!< 0x000000FF */
#define DFSDM_HWCFGR_NBT DFSDM_HWCFGR_NBT_Msk /*!< Number of implemented transceivers */
#define DFSDM_HWCFGR_NBF_Pos (8U)
#define DFSDM_HWCFGR_NBF_Msk (0xFFU << DFSDM_HWCFGR_NBF_Pos) /*!< 0x0000FF00 */
#define DFSDM_HWCFGR_NBF DFSDM_HWCFGR_NBF_Msk /*!< NNumber of implemented filters */
/********************** Bit definition for DFSDM_VERR register *****************/
#define DFSDM_VERR_MINREV_Pos (0U)
#define DFSDM_VERR_MINREV_Msk (0xFU << DFSDM_VERR_MINREV_Pos) /*!< 0x0000000F */
#define DFSDM_VERR_MINREV DFSDM_VERR_MINREV_Msk /*!< Minor Revision number */
#define DFSDM_VERR_MAJREV_Pos (4U)
#define DFSDM_VERR_MAJREV_Msk (0xFU << DFSDM_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define DFSDM_VERR_MAJREV DFSDM_VERR_MAJREV_Msk /*!< Major Revision number */
/********************** Bit definition for DFSDM_IPIDR register ****************/
#define DFSDM_IPIDR_IPID_Pos (0U)
#define DFSDM_IPIDR_IPID_Msk (0xFFFFFFFFU << DFSDM_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
#define DFSDM_IPIDR_IPID DFSDM_IPIDR_IPID_Msk /*!< IP Identification */
/********************** Bit definition for DFSDM_SIDR register *****************/
#define DFSDM_SIDR_SID_Pos (0U)
#define DFSDM_SIDR_SID_Msk (0xFFFFFFFFU << DFSDM_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define DFSDM_SIDR_SID DFSDM_SIDR_SID_Msk /*!< IP size identification */
/******************************************************************************/
/* */
/* Ethernet MAC Registers bits definitions */
/* */
/******************************************************************************/
/*************** Bit definition for ETH_MACCR register ***************/
#define ETH_MACCR_RE_Pos (0U)
#define ETH_MACCR_RE_Msk (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000001 */
#define ETH_MACCR_RE ETH_MACCR_RE_Msk /*!< Receiver Enable */
#define ETH_MACCR_TE_Pos (1U)
#define ETH_MACCR_TE_Msk (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000002 */
#define ETH_MACCR_TE ETH_MACCR_TE_Msk /*!< Transmitter Enable */
#define ETH_MACCR_PRELEN_Pos (2U)
#define ETH_MACCR_PRELEN_Msk (0x3U << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */
#define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /*!< Preamble Length for Transmit packets */
#define ETH_MACCR_PRELEN_0 (0x1U << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */
#define ETH_MACCR_PRELEN_1 (0x2U << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */
#define ETH_MACCR_DC_Pos (4U)
#define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
#define ETH_MACCR_DC ETH_MACCR_DC_Msk /*!< Deferral Check */
#define ETH_MACCR_BL_Pos (5U)
#define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
#define ETH_MACCR_BL ETH_MACCR_BL_Msk /*!< Back-Off Limit */
#define ETH_MACCR_BL_0 (0x1U << ETH_MACCR_BL_Pos) /*!< 0x00000020 */
#define ETH_MACCR_BL_1 (0x2U << ETH_MACCR_BL_Pos) /*!< 0x00000040 */
#define ETH_MACCR_DR_Pos (8U)
#define ETH_MACCR_DR_Msk (0x1U << ETH_MACCR_DR_Pos) /*!< 0x00000100 */
#define ETH_MACCR_DR ETH_MACCR_DR_Msk /*!< Disable Retry */
#define ETH_MACCR_DCRS_Pos (9U)
#define ETH_MACCR_DCRS_Msk (0x1U << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */
#define ETH_MACCR_DCRS ETH_MACCR_DCRS_Msk /*!< Disable Carrier Sense During Transmission */
#define ETH_MACCR_DO_Pos (10U)
#define ETH_MACCR_DO_Msk (0x1U << ETH_MACCR_DO_Pos) /*!< 0x00000400 */
#define ETH_MACCR_DO ETH_MACCR_DO_Msk /*!< Disable Receive Own */
#define ETH_MACCR_ECRSFD_Pos (11U)
#define ETH_MACCR_ECRSFD_Msk (0x1U << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */
#define ETH_MACCR_ECRSFD ETH_MACCR_ECRSFD_Msk /*!< Enable Carrier Sense Before Transmission in Full-Duplex Mode */
#define ETH_MACCR_LM_Pos (12U)
#define ETH_MACCR_LM_Msk (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
#define ETH_MACCR_LM ETH_MACCR_LM_Msk /*!< Loopback Mode */
#define ETH_MACCR_DM_Pos (13U)
#define ETH_MACCR_DM_Msk (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00002000 */
#define ETH_MACCR_DM ETH_MACCR_DM_Msk /*!< Duplex Mode */
#define ETH_MACCR_FES_Pos (14U)
#define ETH_MACCR_FES_Msk (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
#define ETH_MACCR_FES ETH_MACCR_FES_Msk /*!< MAC Speed */
#define ETH_MACCR_PS_Pos (15U)
#define ETH_MACCR_PS_Msk (0x1U << ETH_MACCR_PS_Pos) /*!< 0x00008000 */
#define ETH_MACCR_PS ETH_MACCR_PS_Msk /*!< Port Select */
#define ETH_MACCR_JE_Pos (16U)
#define ETH_MACCR_JE_Msk (0x1U << ETH_MACCR_JE_Pos) /*!< 0x00010000 */
#define ETH_MACCR_JE ETH_MACCR_JE_Msk /*!< Jumbo Packet Enable */
#define ETH_MACCR_JD_Pos (17U)
#define ETH_MACCR_JD_Msk (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00020000 */
#define ETH_MACCR_JD ETH_MACCR_JD_Msk /*!< Jabber Disable */
#define ETH_MACCR_BE_Pos (18U)
#define ETH_MACCR_BE_Msk (0x1U << ETH_MACCR_BE_Pos) /*!< 0x00040000 */
#define ETH_MACCR_BE ETH_MACCR_BE_Msk /*!< Packet Burst Enable */
#define ETH_MACCR_WD_Pos (19U)
#define ETH_MACCR_WD_Msk (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00080000 */
#define ETH_MACCR_WD ETH_MACCR_WD_Msk /*!< Watchdog Disable */
#define ETH_MACCR_ACS_Pos (20U)
#define ETH_MACCR_ACS_Msk (0x1U << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */
#define ETH_MACCR_ACS ETH_MACCR_ACS_Msk /*!< Automatic Pad or CRC Stripping */
#define ETH_MACCR_CST_Pos (21U)
#define ETH_MACCR_CST_Msk (0x1U << ETH_MACCR_CST_Pos) /*!< 0x00200000 */
#define ETH_MACCR_CST ETH_MACCR_CST_Msk /*!< CRC stripping for Type packets */
#define ETH_MACCR_S2KP_Pos (22U)
#define ETH_MACCR_S2KP_Msk (0x1U << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */
#define ETH_MACCR_S2KP ETH_MACCR_S2KP_Msk /*!< IEEE 802.3as Support for 2K Packets */
#define ETH_MACCR_GPSLCE_Pos (23U)
#define ETH_MACCR_GPSLCE_Msk (0x1U << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /*!< Giant Packet Size Limit Control Enable */
#define ETH_MACCR_IPG_Pos (24U)
#define ETH_MACCR_IPG_Msk (0x7U << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /*!< Inter-Packet Gap */
#define ETH_MACCR_IPG_0 (0x1U << ETH_MACCR_IPG_Pos) /*!< 0x01000000 */
#define ETH_MACCR_IPG_1 (0x2U << ETH_MACCR_IPG_Pos) /*!< 0x02000000 */
#define ETH_MACCR_IPG_2 (0x4U << ETH_MACCR_IPG_Pos) /*!< 0x04000000 */
#define ETH_MACCR_IPC_Pos (27U)
#define ETH_MACCR_IPC_Msk (0x1U << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */
#define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /*!< Checksum Offload */
#define ETH_MACCR_SARC_Pos (28U)
#define ETH_MACCR_SARC_Msk (0x7U << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /*!< Source Address Insertion or Replacement Control */
#define ETH_MACCR_SARC_0 (0x1U << ETH_MACCR_SARC_Pos) /*!< 0x10000000 */
#define ETH_MACCR_SARC_1 (0x2U << ETH_MACCR_SARC_Pos) /*!< 0x20000000 */
#define ETH_MACCR_SARC_2 (0x4U << ETH_MACCR_SARC_Pos) /*!< 0x40000000 */
#define ETH_MACCR_ARPEN_Pos (31U)
#define ETH_MACCR_ARPEN_Msk (0x1U << ETH_MACCR_ARPEN_Pos) /*!< 0x80000000 */
#define ETH_MACCR_ARPEN ETH_MACCR_ARPEN_Msk /*!< ARP Offload Enable */
/************** Bit definition for ETH_MACECR register ***************/
#define ETH_MACECR_GPSL_Pos (0U)
#define ETH_MACECR_GPSL_Msk (0x3FFFU << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */
#define ETH_MACECR_GPSL ETH_MACECR_GPSL_Msk /*!< Giant Packet Size Limit */
#define ETH_MACECR_GPSL_0 (0x1U << ETH_MACECR_GPSL_Pos) /*!< 0x00000001 */
#define ETH_MACECR_GPSL_1 (0x2U << ETH_MACECR_GPSL_Pos) /*!< 0x00000002 */
#define ETH_MACECR_GPSL_2 (0x4U << ETH_MACECR_GPSL_Pos) /*!< 0x00000004 */
#define ETH_MACECR_GPSL_3 (0x8U << ETH_MACECR_GPSL_Pos) /*!< 0x00000008 */
#define ETH_MACECR_GPSL_4 (0x10U << ETH_MACECR_GPSL_Pos) /*!< 0x00000010 */
#define ETH_MACECR_GPSL_5 (0x20U << ETH_MACECR_GPSL_Pos) /*!< 0x00000020 */
#define ETH_MACECR_GPSL_6 (0x40U << ETH_MACECR_GPSL_Pos) /*!< 0x00000040 */
#define ETH_MACECR_GPSL_7 (0x80U << ETH_MACECR_GPSL_Pos) /*!< 0x00000080 */
#define ETH_MACECR_GPSL_8 (0x100U << ETH_MACECR_GPSL_Pos) /*!< 0x00000100 */
#define ETH_MACECR_GPSL_9 (0x200U << ETH_MACECR_GPSL_Pos) /*!< 0x00000200 */
#define ETH_MACECR_GPSL_10 (0x400U << ETH_MACECR_GPSL_Pos) /*!< 0x00000400 */
#define ETH_MACECR_GPSL_11 (0x800U << ETH_MACECR_GPSL_Pos) /*!< 0x00000800 */
#define ETH_MACECR_GPSL_12 (0x1000U << ETH_MACECR_GPSL_Pos) /*!< 0x00001000 */
#define ETH_MACECR_GPSL_13 (0x2000U << ETH_MACECR_GPSL_Pos) /*!< 0x00002000 */
#define ETH_MACECR_DCRCC_Pos (16U)
#define ETH_MACECR_DCRCC_Msk (0x1U << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */
#define ETH_MACECR_DCRCC ETH_MACECR_DCRCC_Msk /*!< Disable CRC Checking for Received Packets */
#define ETH_MACECR_SPEN_Pos (17U)
#define ETH_MACECR_SPEN_Msk (0x1U << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */
#define ETH_MACECR_SPEN ETH_MACECR_SPEN_Msk /*!< Slow Protocol Detection Enable */
#define ETH_MACECR_USP_Pos (18U)
#define ETH_MACECR_USP_Msk (0x1U << ETH_MACECR_USP_Pos) /*!< 0x00040000 */
#define ETH_MACECR_USP ETH_MACECR_USP_Msk /*!< Unicast Slow Protocol Packet Detect */
#define ETH_MACECR_EIPGEN_Pos (24U)
#define ETH_MACECR_EIPGEN_Msk (0x1U << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */
#define ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk /*!< Extended Inter-Packet Gap Enable */
#define ETH_MACECR_EIPG_Pos (25U)
#define ETH_MACECR_EIPG_Msk (0x1FU << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */
#define ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk /*!< Extended Inter-Packet Gap */
#define ETH_MACECR_EIPG_0 (0x1U << ETH_MACECR_EIPG_Pos) /*!< 0x02000000 */
#define ETH_MACECR_EIPG_1 (0x2U << ETH_MACECR_EIPG_Pos) /*!< 0x04000000 */
#define ETH_MACECR_EIPG_2 (0x4U << ETH_MACECR_EIPG_Pos) /*!< 0x08000000 */
#define ETH_MACECR_EIPG_3 (0x8U << ETH_MACECR_EIPG_Pos) /*!< 0x10000000 */
#define ETH_MACECR_EIPG_4 (0x10U << ETH_MACECR_EIPG_Pos) /*!< 0x20000000 */
/************** Bit definition for ETH_MACPFR register ***************/
#define ETH_MACPFR_PR_Pos (0U)
#define ETH_MACPFR_PR_Msk (0x1U << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */
#define ETH_MACPFR_PR ETH_MACPFR_PR_Msk /*!< Promiscuous Mode */
#define ETH_MACPFR_HUC_Pos (1U)
#define ETH_MACPFR_HUC_Msk (0x1U << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */
#define ETH_MACPFR_HUC ETH_MACPFR_HUC_Msk /*!< Hash Unicast */
#define ETH_MACPFR_HMC_Pos (2U)
#define ETH_MACPFR_HMC_Msk (0x1U << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */
#define ETH_MACPFR_HMC ETH_MACPFR_HMC_Msk /*!< Hash Multicast */
#define ETH_MACPFR_DAIF_Pos (3U)
#define ETH_MACPFR_DAIF_Msk (0x1U << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */
#define ETH_MACPFR_DAIF ETH_MACPFR_DAIF_Msk /*!< DA Inverse Filtering */
#define ETH_MACPFR_PM_Pos (4U)
#define ETH_MACPFR_PM_Msk (0x1U << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */
#define ETH_MACPFR_PM ETH_MACPFR_PM_Msk /*!< Pass All Multicast */
#define ETH_MACPFR_DBF_Pos (5U)
#define ETH_MACPFR_DBF_Msk (0x1U << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */
#define ETH_MACPFR_DBF ETH_MACPFR_DBF_Msk /*!< Disable Broadcast Packets */
#define ETH_MACPFR_PCF_Pos (6U)
#define ETH_MACPFR_PCF_Msk (0x3U << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /*!< Pass Control Packets */
#define ETH_MACPFR_PCF_0 (0x1U << ETH_MACPFR_PCF_Pos) /*!< 0x00000040 */
#define ETH_MACPFR_PCF_1 (0x2U << ETH_MACPFR_PCF_Pos) /*!< 0x00000080 */
#define ETH_MACPFR_SAIF_Pos (8U)
#define ETH_MACPFR_SAIF_Msk (0x1U << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */
#define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /*!< SA Inverse Filtering */
#define ETH_MACPFR_SAF_Pos (9U)
#define ETH_MACPFR_SAF_Msk (0x1U << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */
#define ETH_MACPFR_SAF ETH_MACPFR_SAF_Msk /*!< Source Address Filter Enable */
#define ETH_MACPFR_HPF_Pos (10U)
#define ETH_MACPFR_HPF_Msk (0x1U << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */
#define ETH_MACPFR_HPF ETH_MACPFR_HPF_Msk /*!< Hash or Perfect Filter */
#define ETH_MACPFR_VTFE_Pos (16U)
#define ETH_MACPFR_VTFE_Msk (0x1U << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */
#define ETH_MACPFR_VTFE ETH_MACPFR_VTFE_Msk /*!< VLAN Tag Filter Enable */
#define ETH_MACPFR_IPFE_Pos (20U)
#define ETH_MACPFR_IPFE_Msk (0x1U << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */
#define ETH_MACPFR_IPFE ETH_MACPFR_IPFE_Msk /*!< Layer 3 and Layer 4 Filter Enable */
#define ETH_MACPFR_DNTU_Pos (21U)
#define ETH_MACPFR_DNTU_Msk (0x1U << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */
#define ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk /*!< Drop Non-TCP/UDP over IP Packets */
#define ETH_MACPFR_RA_Pos (31U)
#define ETH_MACPFR_RA_Msk (0x1U << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */
#define ETH_MACPFR_RA ETH_MACPFR_RA_Msk /*!< Receive All */
/************** Bit definition for ETH_MACWTR register ***************/
#define ETH_MACWTR_WTO_Pos (0U)
#define ETH_MACWTR_WTO_Msk (0xFU << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /*!< Watchdog Timeout */
#define ETH_MACWTR_WTO_0 (0x1U << ETH_MACWTR_WTO_Pos) /*!< 0x00000001 */
#define ETH_MACWTR_WTO_1 (0x2U << ETH_MACWTR_WTO_Pos) /*!< 0x00000002 */
#define ETH_MACWTR_WTO_2 (0x4U << ETH_MACWTR_WTO_Pos) /*!< 0x00000004 */
#define ETH_MACWTR_WTO_3 (0x8U << ETH_MACWTR_WTO_Pos) /*!< 0x00000008 */
#define ETH_MACWTR_PWE_Pos (8U)
#define ETH_MACWTR_PWE_Msk (0x1U << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */
#define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /*!< Programmable Watchdog Enable */
/************** Bit definition for ETH_MACHT0R register **************/
#define ETH_MACHT0R_HT31T0_Pos (0U)
#define ETH_MACHT0R_HT31T0_Msk (0xFFFFFFFFU << ETH_MACHT0R_HT31T0_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACHT0R_HT31T0 ETH_MACHT0R_HT31T0_Msk /*!< MAC Hash Table First 32 Bits */
#define ETH_MACHT0R_HT31T0_0 (0x1U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00000001 */
#define ETH_MACHT0R_HT31T0_1 (0x2U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00000002 */
#define ETH_MACHT0R_HT31T0_2 (0x4U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00000004 */
#define ETH_MACHT0R_HT31T0_3 (0x8U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00000008 */
#define ETH_MACHT0R_HT31T0_4 (0x10U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00000010 */
#define ETH_MACHT0R_HT31T0_5 (0x20U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00000020 */
#define ETH_MACHT0R_HT31T0_6 (0x40U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00000040 */
#define ETH_MACHT0R_HT31T0_7 (0x80U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00000080 */
#define ETH_MACHT0R_HT31T0_8 (0x100U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00000100 */
#define ETH_MACHT0R_HT31T0_9 (0x200U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00000200 */
#define ETH_MACHT0R_HT31T0_10 (0x400U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00000400 */
#define ETH_MACHT0R_HT31T0_11 (0x800U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00000800 */
#define ETH_MACHT0R_HT31T0_12 (0x1000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00001000 */
#define ETH_MACHT0R_HT31T0_13 (0x2000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00002000 */
#define ETH_MACHT0R_HT31T0_14 (0x4000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00004000 */
#define ETH_MACHT0R_HT31T0_15 (0x8000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00008000 */
#define ETH_MACHT0R_HT31T0_16 (0x10000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00010000 */
#define ETH_MACHT0R_HT31T0_17 (0x20000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00020000 */
#define ETH_MACHT0R_HT31T0_18 (0x40000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00040000 */
#define ETH_MACHT0R_HT31T0_19 (0x80000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00080000 */
#define ETH_MACHT0R_HT31T0_20 (0x100000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00100000 */
#define ETH_MACHT0R_HT31T0_21 (0x200000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00200000 */
#define ETH_MACHT0R_HT31T0_22 (0x400000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00400000 */
#define ETH_MACHT0R_HT31T0_23 (0x800000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x00800000 */
#define ETH_MACHT0R_HT31T0_24 (0x1000000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x01000000 */
#define ETH_MACHT0R_HT31T0_25 (0x2000000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x02000000 */
#define ETH_MACHT0R_HT31T0_26 (0x4000000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x04000000 */
#define ETH_MACHT0R_HT31T0_27 (0x8000000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x08000000 */
#define ETH_MACHT0R_HT31T0_28 (0x10000000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x10000000 */
#define ETH_MACHT0R_HT31T0_29 (0x20000000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x20000000 */
#define ETH_MACHT0R_HT31T0_30 (0x40000000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x40000000 */
#define ETH_MACHT0R_HT31T0_31 (0x80000000U << ETH_MACHT0R_HT31T0_Pos) /*!< 0x80000000 */
/************** Bit definition for ETH_MACHT1R register **************/
#define ETH_MACHT1R_HT63T32_Pos (0U)
#define ETH_MACHT1R_HT63T32_Msk (0xFFFFFFFFU << ETH_MACHT1R_HT63T32_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACHT1R_HT63T32 ETH_MACHT1R_HT63T32_Msk /*!< MAC Hash Table Second 32 Bits */
#define ETH_MACHT1R_HT63T32_0 (0x1U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00000001 */
#define ETH_MACHT1R_HT63T32_1 (0x2U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00000002 */
#define ETH_MACHT1R_HT63T32_2 (0x4U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00000004 */
#define ETH_MACHT1R_HT63T32_3 (0x8U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00000008 */
#define ETH_MACHT1R_HT63T32_4 (0x10U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00000010 */
#define ETH_MACHT1R_HT63T32_5 (0x20U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00000020 */
#define ETH_MACHT1R_HT63T32_6 (0x40U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00000040 */
#define ETH_MACHT1R_HT63T32_7 (0x80U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00000080 */
#define ETH_MACHT1R_HT63T32_8 (0x100U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00000100 */
#define ETH_MACHT1R_HT63T32_9 (0x200U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00000200 */
#define ETH_MACHT1R_HT63T32_10 (0x400U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00000400 */
#define ETH_MACHT1R_HT63T32_11 (0x800U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00000800 */
#define ETH_MACHT1R_HT63T32_12 (0x1000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00001000 */
#define ETH_MACHT1R_HT63T32_13 (0x2000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00002000 */
#define ETH_MACHT1R_HT63T32_14 (0x4000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00004000 */
#define ETH_MACHT1R_HT63T32_15 (0x8000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00008000 */
#define ETH_MACHT1R_HT63T32_16 (0x10000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00010000 */
#define ETH_MACHT1R_HT63T32_17 (0x20000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00020000 */
#define ETH_MACHT1R_HT63T32_18 (0x40000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00040000 */
#define ETH_MACHT1R_HT63T32_19 (0x80000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00080000 */
#define ETH_MACHT1R_HT63T32_20 (0x100000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00100000 */
#define ETH_MACHT1R_HT63T32_21 (0x200000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00200000 */
#define ETH_MACHT1R_HT63T32_22 (0x400000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00400000 */
#define ETH_MACHT1R_HT63T32_23 (0x800000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x00800000 */
#define ETH_MACHT1R_HT63T32_24 (0x1000000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x01000000 */
#define ETH_MACHT1R_HT63T32_25 (0x2000000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x02000000 */
#define ETH_MACHT1R_HT63T32_26 (0x4000000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x04000000 */
#define ETH_MACHT1R_HT63T32_27 (0x8000000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x08000000 */
#define ETH_MACHT1R_HT63T32_28 (0x10000000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x10000000 */
#define ETH_MACHT1R_HT63T32_29 (0x20000000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x20000000 */
#define ETH_MACHT1R_HT63T32_30 (0x40000000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x40000000 */
#define ETH_MACHT1R_HT63T32_31 (0x80000000U << ETH_MACHT1R_HT63T32_Pos) /*!< 0x80000000 */
/************** Bit definition for ETH_MACVTR register ***************/
#define ETH_MACVTR_VL_Pos (0U)
#define ETH_MACVTR_VL_Msk (0xFFFFU << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */
#define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /*!< VLAN Tag Identifier for Receive Packets */
#define ETH_MACVTR_VL_0 (0x1U << ETH_MACVTR_VL_Pos) /*!< 0x00000001 */
#define ETH_MACVTR_VL_1 (0x2U << ETH_MACVTR_VL_Pos) /*!< 0x00000002 */
#define ETH_MACVTR_VL_2 (0x4U << ETH_MACVTR_VL_Pos) /*!< 0x00000004 */
#define ETH_MACVTR_VL_3 (0x8U << ETH_MACVTR_VL_Pos) /*!< 0x00000008 */
#define ETH_MACVTR_VL_4 (0x10U << ETH_MACVTR_VL_Pos) /*!< 0x00000010 */
#define ETH_MACVTR_VL_5 (0x20U << ETH_MACVTR_VL_Pos) /*!< 0x00000020 */
#define ETH_MACVTR_VL_6 (0x40U << ETH_MACVTR_VL_Pos) /*!< 0x00000040 */
#define ETH_MACVTR_VL_7 (0x80U << ETH_MACVTR_VL_Pos) /*!< 0x00000080 */
#define ETH_MACVTR_VL_8 (0x100U << ETH_MACVTR_VL_Pos) /*!< 0x00000100 */
#define ETH_MACVTR_VL_9 (0x200U << ETH_MACVTR_VL_Pos) /*!< 0x00000200 */
#define ETH_MACVTR_VL_10 (0x400U << ETH_MACVTR_VL_Pos) /*!< 0x00000400 */
#define ETH_MACVTR_VL_11 (0x800U << ETH_MACVTR_VL_Pos) /*!< 0x00000800 */
#define ETH_MACVTR_VL_12 (0x1000U << ETH_MACVTR_VL_Pos) /*!< 0x00001000 */
#define ETH_MACVTR_VL_13 (0x2000U << ETH_MACVTR_VL_Pos) /*!< 0x00002000 */
#define ETH_MACVTR_VL_14 (0x4000U << ETH_MACVTR_VL_Pos) /*!< 0x00004000 */
#define ETH_MACVTR_VL_15 (0x8000U << ETH_MACVTR_VL_Pos) /*!< 0x00008000 */
#define ETH_MACVTR_ETV_Pos (16U)
#define ETH_MACVTR_ETV_Msk (0x1U << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */
#define ETH_MACVTR_ETV ETH_MACVTR_ETV_Msk /*!< Enable 12-Bit VLAN Tag Comparison */
#define ETH_MACVTR_VTIM_Pos (17U)
#define ETH_MACVTR_VTIM_Msk (0x1U << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */
#define ETH_MACVTR_VTIM ETH_MACVTR_VTIM_Msk /*!< VLAN Tag Inverse Match Enable */
#define ETH_MACVTR_ESVL_Pos (18U)
#define ETH_MACVTR_ESVL_Msk (0x1U << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */
#define ETH_MACVTR_ESVL ETH_MACVTR_ESVL_Msk /*!< Enable S-VLAN */
#define ETH_MACVTR_ERSVLM_Pos (19U)
#define ETH_MACVTR_ERSVLM_Msk (0x1U << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */
#define ETH_MACVTR_ERSVLM ETH_MACVTR_ERSVLM_Msk /*!< Enable Receive S-VLAN Match */
#define ETH_MACVTR_DOVLTC_Pos (20U)
#define ETH_MACVTR_DOVLTC_Msk (0x1U << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */
#define ETH_MACVTR_DOVLTC ETH_MACVTR_DOVLTC_Msk /*!< Disable VLAN Type Check */
#define ETH_MACVTR_EVLS_Pos (21U)
#define ETH_MACVTR_EVLS_Msk (0x3U << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /*!< Enable VLAN Tag Stripping on Receive */
#define ETH_MACVTR_EVLS_0 (0x1U << ETH_MACVTR_EVLS_Pos) /*!< 0x00200000 */
#define ETH_MACVTR_EVLS_1 (0x2U << ETH_MACVTR_EVLS_Pos) /*!< 0x00400000 */
#define ETH_MACVTR_EVLRXS_Pos (24U)
#define ETH_MACVTR_EVLRXS_Msk (0x1U << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */
#define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /*!< Enable VLAN Tag in Rx status */
#define ETH_MACVTR_VTHM_Pos (25U)
#define ETH_MACVTR_VTHM_Msk (0x1U << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */
#define ETH_MACVTR_VTHM ETH_MACVTR_VTHM_Msk /*!< VLAN Tag Hash Table Match Enable */
#define ETH_MACVTR_EDVLP_Pos (26U)
#define ETH_MACVTR_EDVLP_Msk (0x1U << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */
#define ETH_MACVTR_EDVLP ETH_MACVTR_EDVLP_Msk /*!< Enable Double VLAN Processing */
#define ETH_MACVTR_ERIVLT_Pos (27U)
#define ETH_MACVTR_ERIVLT_Msk (0x1U << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */
#define ETH_MACVTR_ERIVLT ETH_MACVTR_ERIVLT_Msk /*!< Enable Inner VLAN Tag */
#define ETH_MACVTR_EIVLS_Pos (28U)
#define ETH_MACVTR_EIVLS_Msk (0x3U << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /*!< Enable Inner VLAN Tag Stripping on Receive */
#define ETH_MACVTR_EIVLS_0 (0x1U << ETH_MACVTR_EIVLS_Pos) /*!< 0x10000000 */
#define ETH_MACVTR_EIVLS_1 (0x2U << ETH_MACVTR_EIVLS_Pos) /*!< 0x20000000 */
#define ETH_MACVTR_EIVLRXS_Pos (31U)
#define ETH_MACVTR_EIVLRXS_Msk (0x1U << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */
#define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /*!< Enable Inner VLAN Tag in Rx Status */
/************** Bit definition for ETH_MACVHTR register **************/
#define ETH_MACVHTR_VLHT_Pos (0U)
#define ETH_MACVHTR_VLHT_Msk (0xFFFFU << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */
#define ETH_MACVHTR_VLHT ETH_MACVHTR_VLHT_Msk /*!< VLAN Hash Table */
#define ETH_MACVHTR_VLHT_0 (0x1U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00000001 */
#define ETH_MACVHTR_VLHT_1 (0x2U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00000002 */
#define ETH_MACVHTR_VLHT_2 (0x4U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00000004 */
#define ETH_MACVHTR_VLHT_3 (0x8U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00000008 */
#define ETH_MACVHTR_VLHT_4 (0x10U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00000010 */
#define ETH_MACVHTR_VLHT_5 (0x20U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00000020 */
#define ETH_MACVHTR_VLHT_6 (0x40U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00000040 */
#define ETH_MACVHTR_VLHT_7 (0x80U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00000080 */
#define ETH_MACVHTR_VLHT_8 (0x100U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00000100 */
#define ETH_MACVHTR_VLHT_9 (0x200U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00000200 */
#define ETH_MACVHTR_VLHT_10 (0x400U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00000400 */
#define ETH_MACVHTR_VLHT_11 (0x800U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00000800 */
#define ETH_MACVHTR_VLHT_12 (0x1000U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00001000 */
#define ETH_MACVHTR_VLHT_13 (0x2000U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00002000 */
#define ETH_MACVHTR_VLHT_14 (0x4000U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00004000 */
#define ETH_MACVHTR_VLHT_15 (0x8000U << ETH_MACVHTR_VLHT_Pos) /*!< 0x00008000 */
/************** Bit definition for ETH_MACVIR register ***************/
#define ETH_MACVIR_VLT_Pos (0U)
#define ETH_MACVIR_VLT_Msk (0xFFFFU << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */
#define ETH_MACVIR_VLT ETH_MACVIR_VLT_Msk /*!< VLAN Tag for Transmit Packets */
#define ETH_MACVIR_VLT_0 (0x1U << ETH_MACVIR_VLT_Pos) /*!< 0x00000001 */
#define ETH_MACVIR_VLT_1 (0x2U << ETH_MACVIR_VLT_Pos) /*!< 0x00000002 */
#define ETH_MACVIR_VLT_2 (0x4U << ETH_MACVIR_VLT_Pos) /*!< 0x00000004 */
#define ETH_MACVIR_VLT_3 (0x8U << ETH_MACVIR_VLT_Pos) /*!< 0x00000008 */
#define ETH_MACVIR_VLT_4 (0x10U << ETH_MACVIR_VLT_Pos) /*!< 0x00000010 */
#define ETH_MACVIR_VLT_5 (0x20U << ETH_MACVIR_VLT_Pos) /*!< 0x00000020 */
#define ETH_MACVIR_VLT_6 (0x40U << ETH_MACVIR_VLT_Pos) /*!< 0x00000040 */
#define ETH_MACVIR_VLT_7 (0x80U << ETH_MACVIR_VLT_Pos) /*!< 0x00000080 */
#define ETH_MACVIR_VLT_8 (0x100U << ETH_MACVIR_VLT_Pos) /*!< 0x00000100 */
#define ETH_MACVIR_VLT_9 (0x200U << ETH_MACVIR_VLT_Pos) /*!< 0x00000200 */
#define ETH_MACVIR_VLT_10 (0x400U << ETH_MACVIR_VLT_Pos) /*!< 0x00000400 */
#define ETH_MACVIR_VLT_11 (0x800U << ETH_MACVIR_VLT_Pos) /*!< 0x00000800 */
#define ETH_MACVIR_VLT_12 (0x1000U << ETH_MACVIR_VLT_Pos) /*!< 0x00001000 */
#define ETH_MACVIR_VLT_13 (0x2000U << ETH_MACVIR_VLT_Pos) /*!< 0x00002000 */
#define ETH_MACVIR_VLT_14 (0x4000U << ETH_MACVIR_VLT_Pos) /*!< 0x00004000 */
#define ETH_MACVIR_VLT_15 (0x8000U << ETH_MACVIR_VLT_Pos) /*!< 0x00008000 */
#define ETH_MACVIR_VLC_Pos (16U)
#define ETH_MACVIR_VLC_Msk (0x3U << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */
#define ETH_MACVIR_VLC_0 (0x1U << ETH_MACVIR_VLC_Pos) /*!< 0x00010000 */
#define ETH_MACVIR_VLC_1 (0x2U << ETH_MACVIR_VLC_Pos) /*!< 0x00020000 */
#define ETH_MACVIR_VLP_Pos (18U)
#define ETH_MACVIR_VLP_Msk (0x1U << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */
#define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /*!< VLAN Priority Control */
#define ETH_MACVIR_CSVL_Pos (19U)
#define ETH_MACVIR_CSVL_Msk (0x1U << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */
#define ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk /*!< C-VLAN or S-VLAN */
#define ETH_MACVIR_VLTI_Pos (20U)
#define ETH_MACVIR_VLTI_Msk (0x1U << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */
#define ETH_MACVIR_VLTI ETH_MACVIR_VLTI_Msk /*!< VLAN Tag Input */
/************** Bit definition for ETH_MACIVIR register **************/
#define ETH_MACIVIR_VLT_Pos (0U)
#define ETH_MACIVIR_VLT_Msk (0xFFFFU << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */
#define ETH_MACIVIR_VLT ETH_MACIVIR_VLT_Msk /*!< VLAN Tag for Transmit Packets */
#define ETH_MACIVIR_VLT_0 (0x1U << ETH_MACIVIR_VLT_Pos) /*!< 0x00000001 */
#define ETH_MACIVIR_VLT_1 (0x2U << ETH_MACIVIR_VLT_Pos) /*!< 0x00000002 */
#define ETH_MACIVIR_VLT_2 (0x4U << ETH_MACIVIR_VLT_Pos) /*!< 0x00000004 */
#define ETH_MACIVIR_VLT_3 (0x8U << ETH_MACIVIR_VLT_Pos) /*!< 0x00000008 */
#define ETH_MACIVIR_VLT_4 (0x10U << ETH_MACIVIR_VLT_Pos) /*!< 0x00000010 */
#define ETH_MACIVIR_VLT_5 (0x20U << ETH_MACIVIR_VLT_Pos) /*!< 0x00000020 */
#define ETH_MACIVIR_VLT_6 (0x40U << ETH_MACIVIR_VLT_Pos) /*!< 0x00000040 */
#define ETH_MACIVIR_VLT_7 (0x80U << ETH_MACIVIR_VLT_Pos) /*!< 0x00000080 */
#define ETH_MACIVIR_VLT_8 (0x100U << ETH_MACIVIR_VLT_Pos) /*!< 0x00000100 */
#define ETH_MACIVIR_VLT_9 (0x200U << ETH_MACIVIR_VLT_Pos) /*!< 0x00000200 */
#define ETH_MACIVIR_VLT_10 (0x400U << ETH_MACIVIR_VLT_Pos) /*!< 0x00000400 */
#define ETH_MACIVIR_VLT_11 (0x800U << ETH_MACIVIR_VLT_Pos) /*!< 0x00000800 */
#define ETH_MACIVIR_VLT_12 (0x1000U << ETH_MACIVIR_VLT_Pos) /*!< 0x00001000 */
#define ETH_MACIVIR_VLT_13 (0x2000U << ETH_MACIVIR_VLT_Pos) /*!< 0x00002000 */
#define ETH_MACIVIR_VLT_14 (0x4000U << ETH_MACIVIR_VLT_Pos) /*!< 0x00004000 */
#define ETH_MACIVIR_VLT_15 (0x8000U << ETH_MACIVIR_VLT_Pos) /*!< 0x00008000 */
#define ETH_MACIVIR_VLC_Pos (16U)
#define ETH_MACIVIR_VLC_Msk (0x3U << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /*!< VLAN Tag Control in Transmit Packets */
#define ETH_MACIVIR_VLC_0 (0x1U << ETH_MACIVIR_VLC_Pos) /*!< 0x00010000 */
#define ETH_MACIVIR_VLC_1 (0x2U << ETH_MACIVIR_VLC_Pos) /*!< 0x00020000 */
#define ETH_MACIVIR_VLP_Pos (18U)
#define ETH_MACIVIR_VLP_Msk (0x1U << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */
#define ETH_MACIVIR_VLP ETH_MACIVIR_VLP_Msk /*!< VLAN Priority Control */
#define ETH_MACIVIR_CSVL_Pos (19U)
#define ETH_MACIVIR_CSVL_Msk (0x1U << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */
#define ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk /*!< C-VLAN or S-VLAN */
#define ETH_MACIVIR_VLTI_Pos (20U)
#define ETH_MACIVIR_VLTI_Msk (0x1U << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */
#define ETH_MACIVIR_VLTI ETH_MACIVIR_VLTI_Msk /*!< VLAN Tag Input */
/************ Bit definition for ETH_MACQ0TXFCR register *************/
#define ETH_MACQ0TXFCR_FCB_BPA_Pos (0U)
#define ETH_MACQ0TXFCR_FCB_BPA_Msk (0x1U << ETH_MACQ0TXFCR_FCB_BPA_Pos) /*!< 0x00000001 */
#define ETH_MACQ0TXFCR_FCB_BPA ETH_MACQ0TXFCR_FCB_BPA_Msk /*!< Flow Control Busy or Backpressure Activate */
#define ETH_MACQ0TXFCR_TFE_Pos (1U)
#define ETH_MACQ0TXFCR_TFE_Msk (0x1U << ETH_MACQ0TXFCR_TFE_Pos) /*!< 0x00000002 */
#define ETH_MACQ0TXFCR_TFE ETH_MACQ0TXFCR_TFE_Msk /*!< Transmit Flow Control Enable */
#define ETH_MACQ0TXFCR_PLT_Pos (4U)
#define ETH_MACQ0TXFCR_PLT_Msk (0x7U << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */
#define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /*!< Pause Low Threshold */
#define ETH_MACQ0TXFCR_PLT_0 (0x1U << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000010 */
#define ETH_MACQ0TXFCR_PLT_1 (0x2U << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000020 */
#define ETH_MACQ0TXFCR_PLT_2 (0x4U << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000040 */
#define ETH_MACQ0TXFCR_DZPQ_Pos (7U)
#define ETH_MACQ0TXFCR_DZPQ_Msk (0x1U << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */
#define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /*!< Disable Zero-Quanta Pause */
#define ETH_MACQ0TXFCR_PT_Pos (16U)
#define ETH_MACQ0TXFCR_PT_Msk (0xFFFFU << ETH_MACQ0TXFCR_PT_Pos) /*!< 0xFFFF0000 */
#define ETH_MACQ0TXFCR_PT ETH_MACQ0TXFCR_PT_Msk /*!< Pause Time */
#define ETH_MACQ0TXFCR_PT_0 (0x1U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x00010000 */
#define ETH_MACQ0TXFCR_PT_1 (0x2U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x00020000 */
#define ETH_MACQ0TXFCR_PT_2 (0x4U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x00040000 */
#define ETH_MACQ0TXFCR_PT_3 (0x8U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x00080000 */
#define ETH_MACQ0TXFCR_PT_4 (0x10U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x00100000 */
#define ETH_MACQ0TXFCR_PT_5 (0x20U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x00200000 */
#define ETH_MACQ0TXFCR_PT_6 (0x40U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x00400000 */
#define ETH_MACQ0TXFCR_PT_7 (0x80U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x00800000 */
#define ETH_MACQ0TXFCR_PT_8 (0x100U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x01000000 */
#define ETH_MACQ0TXFCR_PT_9 (0x200U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x02000000 */
#define ETH_MACQ0TXFCR_PT_10 (0x400U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x04000000 */
#define ETH_MACQ0TXFCR_PT_11 (0x800U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x08000000 */
#define ETH_MACQ0TXFCR_PT_12 (0x1000U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x10000000 */
#define ETH_MACQ0TXFCR_PT_13 (0x2000U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x20000000 */
#define ETH_MACQ0TXFCR_PT_14 (0x4000U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x40000000 */
#define ETH_MACQ0TXFCR_PT_15 (0x8000U << ETH_MACQ0TXFCR_PT_Pos) /*!< 0x80000000 */
/************* Bit definition for ETH_MACRXFCR register **************/
#define ETH_MACRXFCR_RFE_Pos (0U)
#define ETH_MACRXFCR_RFE_Msk (0x1U << ETH_MACRXFCR_RFE_Pos) /*!< 0x00000001 */
#define ETH_MACRXFCR_RFE ETH_MACRXFCR_RFE_Msk /*!< Receive Flow Control Enable */
#define ETH_MACRXFCR_UP_Pos (1U)
#define ETH_MACRXFCR_UP_Msk (0x1U << ETH_MACRXFCR_UP_Pos) /*!< 0x00000002 */
#define ETH_MACRXFCR_UP ETH_MACRXFCR_UP_Msk /*!< Unicast Pause Packet Detect */
/************* Bit definition for ETH_MACTXQPMR register *************/
#define ETH_MACTXQPMR_PSTQ0_Pos (0U)
#define ETH_MACTXQPMR_PSTQ0_Msk (0xFFU << ETH_MACTXQPMR_PSTQ0_Pos) /*!< 0x000000FF */
#define ETH_MACTXQPMR_PSTQ0 ETH_MACTXQPMR_PSTQ0_Msk /*!< Priorities Selected in Transmit Queue 0 */
#define ETH_MACTXQPMR_PSTQ0_0 (0x1U << ETH_MACTXQPMR_PSTQ0_Pos) /*!< 0x00000001 */
#define ETH_MACTXQPMR_PSTQ0_1 (0x2U << ETH_MACTXQPMR_PSTQ0_Pos) /*!< 0x00000002 */
#define ETH_MACTXQPMR_PSTQ0_2 (0x4U << ETH_MACTXQPMR_PSTQ0_Pos) /*!< 0x00000004 */
#define ETH_MACTXQPMR_PSTQ0_3 (0x8U << ETH_MACTXQPMR_PSTQ0_Pos) /*!< 0x00000008 */
#define ETH_MACTXQPMR_PSTQ0_4 (0x10U << ETH_MACTXQPMR_PSTQ0_Pos) /*!< 0x00000010 */
#define ETH_MACTXQPMR_PSTQ0_5 (0x20U << ETH_MACTXQPMR_PSTQ0_Pos) /*!< 0x00000020 */
#define ETH_MACTXQPMR_PSTQ0_6 (0x40U << ETH_MACTXQPMR_PSTQ0_Pos) /*!< 0x00000040 */
#define ETH_MACTXQPMR_PSTQ0_7 (0x80U << ETH_MACTXQPMR_PSTQ0_Pos) /*!< 0x00000080 */
#define ETH_MACTXQPMR_PSTQ1_Pos (8U)
#define ETH_MACTXQPMR_PSTQ1_Msk (0xFFU << ETH_MACTXQPMR_PSTQ1_Pos) /*!< 0x0000FF00 */
#define ETH_MACTXQPMR_PSTQ1 ETH_MACTXQPMR_PSTQ1_Msk /*!< Priorities Selected in Transmit Queue 1 */
#define ETH_MACTXQPMR_PSTQ1_0 (0x1U << ETH_MACTXQPMR_PSTQ1_Pos) /*!< 0x00000100 */
#define ETH_MACTXQPMR_PSTQ1_1 (0x2U << ETH_MACTXQPMR_PSTQ1_Pos) /*!< 0x00000200 */
#define ETH_MACTXQPMR_PSTQ1_2 (0x4U << ETH_MACTXQPMR_PSTQ1_Pos) /*!< 0x00000400 */
#define ETH_MACTXQPMR_PSTQ1_3 (0x8U << ETH_MACTXQPMR_PSTQ1_Pos) /*!< 0x00000800 */
#define ETH_MACTXQPMR_PSTQ1_4 (0x10U << ETH_MACTXQPMR_PSTQ1_Pos) /*!< 0x00001000 */
#define ETH_MACTXQPMR_PSTQ1_5 (0x20U << ETH_MACTXQPMR_PSTQ1_Pos) /*!< 0x00002000 */
#define ETH_MACTXQPMR_PSTQ1_6 (0x40U << ETH_MACTXQPMR_PSTQ1_Pos) /*!< 0x00004000 */
#define ETH_MACTXQPMR_PSTQ1_7 (0x80U << ETH_MACTXQPMR_PSTQ1_Pos) /*!< 0x00008000 */
/************* Bit definition for ETH_MACRXQC0R register *************/
#define ETH_MACRXQC0R_RXQ0EN_Pos (0U)
#define ETH_MACRXQC0R_RXQ0EN_Msk (0x3U << ETH_MACRXQC0R_RXQ0EN_Pos) /*!< 0x00000003 */
#define ETH_MACRXQC0R_RXQ0EN ETH_MACRXQC0R_RXQ0EN_Msk /*!< Receive Queue 0 Enable */
#define ETH_MACRXQC0R_RXQ0EN_0 (0x1U << ETH_MACRXQC0R_RXQ0EN_Pos) /*!< 0x00000001 */
#define ETH_MACRXQC0R_RXQ0EN_1 (0x2U << ETH_MACRXQC0R_RXQ0EN_Pos) /*!< 0x00000002 */
#define ETH_MACRXQC0R_RXQ1EN_Pos (2U)
#define ETH_MACRXQC0R_RXQ1EN_Msk (0x3U << ETH_MACRXQC0R_RXQ1EN_Pos) /*!< 0x0000000C */
#define ETH_MACRXQC0R_RXQ1EN ETH_MACRXQC0R_RXQ1EN_Msk /*!< Receive Queue 1 Enable */
#define ETH_MACRXQC0R_RXQ1EN_0 (0x1U << ETH_MACRXQC0R_RXQ1EN_Pos) /*!< 0x00000004 */
#define ETH_MACRXQC0R_RXQ1EN_1 (0x2U << ETH_MACRXQC0R_RXQ1EN_Pos) /*!< 0x00000008 */
/************* Bit definition for ETH_MACRXQC1R register *************/
#define ETH_MACRXQC1R_AVCPQ_Pos (0U)
#define ETH_MACRXQC1R_AVCPQ_Msk (0x7U << ETH_MACRXQC1R_AVCPQ_Pos) /*!< 0x00000007 */
#define ETH_MACRXQC1R_AVCPQ ETH_MACRXQC1R_AVCPQ_Msk /*!< AV Untagged Control Packets Queue */
#define ETH_MACRXQC1R_AVCPQ_0 (0x1U << ETH_MACRXQC1R_AVCPQ_Pos) /*!< 0x00000001 */
#define ETH_MACRXQC1R_AVCPQ_1 (0x2U << ETH_MACRXQC1R_AVCPQ_Pos) /*!< 0x00000002 */
#define ETH_MACRXQC1R_AVCPQ_2 (0x4U << ETH_MACRXQC1R_AVCPQ_Pos) /*!< 0x00000004 */
#define ETH_MACRXQC1R_AVPTPQ_Pos (4U)
#define ETH_MACRXQC1R_AVPTPQ_Msk (0x7U << ETH_MACRXQC1R_AVPTPQ_Pos) /*!< 0x00000070 */
#define ETH_MACRXQC1R_AVPTPQ ETH_MACRXQC1R_AVPTPQ_Msk /*!< AV PTP Packets Queue */
#define ETH_MACRXQC1R_AVPTPQ_0 (0x1U << ETH_MACRXQC1R_AVPTPQ_Pos) /*!< 0x00000010 */
#define ETH_MACRXQC1R_AVPTPQ_1 (0x2U << ETH_MACRXQC1R_AVPTPQ_Pos) /*!< 0x00000020 */
#define ETH_MACRXQC1R_AVPTPQ_2 (0x4U << ETH_MACRXQC1R_AVPTPQ_Pos) /*!< 0x00000040 */
#define ETH_MACRXQC1R_UPQ_Pos (12U)
#define ETH_MACRXQC1R_UPQ_Msk (0x7U << ETH_MACRXQC1R_UPQ_Pos) /*!< 0x00007000 */
#define ETH_MACRXQC1R_UPQ ETH_MACRXQC1R_UPQ_Msk /*!< Untagged Packet Queue */
#define ETH_MACRXQC1R_UPQ_0 (0x1U << ETH_MACRXQC1R_UPQ_Pos) /*!< 0x00001000 */
#define ETH_MACRXQC1R_UPQ_1 (0x2U << ETH_MACRXQC1R_UPQ_Pos) /*!< 0x00002000 */
#define ETH_MACRXQC1R_UPQ_2 (0x4U << ETH_MACRXQC1R_UPQ_Pos) /*!< 0x00004000 */
#define ETH_MACRXQC1R_MCBCQ_Pos (16U)
#define ETH_MACRXQC1R_MCBCQ_Msk (0x7U << ETH_MACRXQC1R_MCBCQ_Pos) /*!< 0x00070000 */
#define ETH_MACRXQC1R_MCBCQ ETH_MACRXQC1R_MCBCQ_Msk /*!< Multicast and Broadcast Queue */
#define ETH_MACRXQC1R_MCBCQ_0 (0x1U << ETH_MACRXQC1R_MCBCQ_Pos) /*!< 0x00010000 */
#define ETH_MACRXQC1R_MCBCQ_1 (0x2U << ETH_MACRXQC1R_MCBCQ_Pos) /*!< 0x00020000 */
#define ETH_MACRXQC1R_MCBCQ_2 (0x4U << ETH_MACRXQC1R_MCBCQ_Pos) /*!< 0x00040000 */
#define ETH_MACRXQC1R_MCBCQEN_Pos (20U)
#define ETH_MACRXQC1R_MCBCQEN_Msk (0x1U << ETH_MACRXQC1R_MCBCQEN_Pos) /*!< 0x00100000 */
#define ETH_MACRXQC1R_MCBCQEN ETH_MACRXQC1R_MCBCQEN_Msk /*!< Multicast and Broadcast Queue Enable */
#define ETH_MACRXQC1R_TACPQE_Pos (21U)
#define ETH_MACRXQC1R_TACPQE_Msk (0x1U << ETH_MACRXQC1R_TACPQE_Pos) /*!< 0x00200000 */
#define ETH_MACRXQC1R_TACPQE ETH_MACRXQC1R_TACPQE_Msk /*!< Tagged AV Control Packets Queuing Enable. */
/************* Bit definition for ETH_MACRXQC2R register *************/
#define ETH_MACRXQC2R_PSRQ0_Pos (0U)
#define ETH_MACRXQC2R_PSRQ0_Msk (0xFFU << ETH_MACRXQC2R_PSRQ0_Pos) /*!< 0x000000FF */
#define ETH_MACRXQC2R_PSRQ0 ETH_MACRXQC2R_PSRQ0_Msk /*!< Priorities Selected in the Receive Queue 0 */
#define ETH_MACRXQC2R_PSRQ0_0 (0x1U << ETH_MACRXQC2R_PSRQ0_Pos) /*!< 0x00000001 */
#define ETH_MACRXQC2R_PSRQ0_1 (0x2U << ETH_MACRXQC2R_PSRQ0_Pos) /*!< 0x00000002 */
#define ETH_MACRXQC2R_PSRQ0_2 (0x4U << ETH_MACRXQC2R_PSRQ0_Pos) /*!< 0x00000004 */
#define ETH_MACRXQC2R_PSRQ0_3 (0x8U << ETH_MACRXQC2R_PSRQ0_Pos) /*!< 0x00000008 */
#define ETH_MACRXQC2R_PSRQ0_4 (0x10U << ETH_MACRXQC2R_PSRQ0_Pos) /*!< 0x00000010 */
#define ETH_MACRXQC2R_PSRQ0_5 (0x20U << ETH_MACRXQC2R_PSRQ0_Pos) /*!< 0x00000020 */
#define ETH_MACRXQC2R_PSRQ0_6 (0x40U << ETH_MACRXQC2R_PSRQ0_Pos) /*!< 0x00000040 */
#define ETH_MACRXQC2R_PSRQ0_7 (0x80U << ETH_MACRXQC2R_PSRQ0_Pos) /*!< 0x00000080 */
#define ETH_MACRXQC2R_PSRQ1_Pos (8U)
#define ETH_MACRXQC2R_PSRQ1_Msk (0xFFU << ETH_MACRXQC2R_PSRQ1_Pos) /*!< 0x0000FF00 */
#define ETH_MACRXQC2R_PSRQ1 ETH_MACRXQC2R_PSRQ1_Msk /*!< Priorities Selected in the Receive Queue 1 */
#define ETH_MACRXQC2R_PSRQ1_0 (0x1U << ETH_MACRXQC2R_PSRQ1_Pos) /*!< 0x00000100 */
#define ETH_MACRXQC2R_PSRQ1_1 (0x2U << ETH_MACRXQC2R_PSRQ1_Pos) /*!< 0x00000200 */
#define ETH_MACRXQC2R_PSRQ1_2 (0x4U << ETH_MACRXQC2R_PSRQ1_Pos) /*!< 0x00000400 */
#define ETH_MACRXQC2R_PSRQ1_3 (0x8U << ETH_MACRXQC2R_PSRQ1_Pos) /*!< 0x00000800 */
#define ETH_MACRXQC2R_PSRQ1_4 (0x10U << ETH_MACRXQC2R_PSRQ1_Pos) /*!< 0x00001000 */
#define ETH_MACRXQC2R_PSRQ1_5 (0x20U << ETH_MACRXQC2R_PSRQ1_Pos) /*!< 0x00002000 */
#define ETH_MACRXQC2R_PSRQ1_6 (0x40U << ETH_MACRXQC2R_PSRQ1_Pos) /*!< 0x00004000 */
#define ETH_MACRXQC2R_PSRQ1_7 (0x80U << ETH_MACRXQC2R_PSRQ1_Pos) /*!< 0x00008000 */
/************** Bit definition for ETH_MACISR register ***************/
#define ETH_MACISR_RGSMIIIS_Pos (0U)
#define ETH_MACISR_RGSMIIIS_Msk (0x1U << ETH_MACISR_RGSMIIIS_Pos) /*!< 0x00000001 */
#define ETH_MACISR_RGSMIIIS ETH_MACISR_RGSMIIIS_Msk /*!< RGMII or SMII Interrupt Status */
#define ETH_MACISR_PHYIS_Pos (3U)
#define ETH_MACISR_PHYIS_Msk (0x1U << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */
#define ETH_MACISR_PHYIS ETH_MACISR_PHYIS_Msk /*!< PHY Interrupt */
#define ETH_MACISR_PMTIS_Pos (4U)
#define ETH_MACISR_PMTIS_Msk (0x1U << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */
#define ETH_MACISR_PMTIS ETH_MACISR_PMTIS_Msk /*!< PMT Interrupt Status */
#define ETH_MACISR_LPIIS_Pos (5U)
#define ETH_MACISR_LPIIS_Msk (0x1U << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */
#define ETH_MACISR_LPIIS ETH_MACISR_LPIIS_Msk /*!< LPI Interrupt Status */
#define ETH_MACISR_MMCIS_Pos (8U)
#define ETH_MACISR_MMCIS_Msk (0x1U << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */
#define ETH_MACISR_MMCIS ETH_MACISR_MMCIS_Msk /*!< MMC Interrupt Status */
#define ETH_MACISR_MMCRXIS_Pos (9U)
#define ETH_MACISR_MMCRXIS_Msk (0x1U << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */
#define ETH_MACISR_MMCRXIS ETH_MACISR_MMCRXIS_Msk /*!< MMC Receive Interrupt Status */
#define ETH_MACISR_MMCTXIS_Pos (10U)
#define ETH_MACISR_MMCTXIS_Msk (0x1U << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */
#define ETH_MACISR_MMCTXIS ETH_MACISR_MMCTXIS_Msk /*!< MMC Transmit Interrupt Status */
#define ETH_MACISR_TSIS_Pos (12U)
#define ETH_MACISR_TSIS_Msk (0x1U << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */
#define ETH_MACISR_TSIS ETH_MACISR_TSIS_Msk /*!< Timestamp Interrupt Status */
#define ETH_MACISR_TXSTSIS_Pos (13U)
#define ETH_MACISR_TXSTSIS_Msk (0x1U << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */
#define ETH_MACISR_TXSTSIS ETH_MACISR_TXSTSIS_Msk /*!< Transmit Status Interrupt */
#define ETH_MACISR_RXSTSIS_Pos (14U)
#define ETH_MACISR_RXSTSIS_Msk (0x1U << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */
#define ETH_MACISR_RXSTSIS ETH_MACISR_RXSTSIS_Msk /*!< Receive Status Interrupt */
/************** Bit definition for ETH_MACIER register ***************/
#define ETH_MACIER_RGSMIIIE_Pos (0U)
#define ETH_MACIER_RGSMIIIE_Msk (0x1U << ETH_MACIER_RGSMIIIE_Pos) /*!< 0x00000001 */
#define ETH_MACIER_RGSMIIIE ETH_MACIER_RGSMIIIE_Msk /*!< RGMII or SMII Interrupt Enable */
#define ETH_MACIER_PHYIE_Pos (3U)
#define ETH_MACIER_PHYIE_Msk (0x1U << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */
#define ETH_MACIER_PHYIE ETH_MACIER_PHYIE_Msk /*!< PHY Interrupt Enable */
#define ETH_MACIER_PMTIE_Pos (4U)
#define ETH_MACIER_PMTIE_Msk (0x1U << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */
#define ETH_MACIER_PMTIE ETH_MACIER_PMTIE_Msk /*!< PMT Interrupt Enable */
#define ETH_MACIER_LPIIE_Pos (5U)
#define ETH_MACIER_LPIIE_Msk (0x1U << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */
#define ETH_MACIER_LPIIE ETH_MACIER_LPIIE_Msk /*!< LPI Interrupt Enable */
#define ETH_MACIER_TSIE_Pos (12U)
#define ETH_MACIER_TSIE_Msk (0x1U << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */
#define ETH_MACIER_TSIE ETH_MACIER_TSIE_Msk /*!< Timestamp Interrupt Enable */
#define ETH_MACIER_TXSTSIE_Pos (13U)
#define ETH_MACIER_TXSTSIE_Msk (0x1U << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */
#define ETH_MACIER_TXSTSIE ETH_MACIER_TXSTSIE_Msk /*!< Transmit Status Interrupt Enable */
#define ETH_MACIER_RXSTSIE_Pos (14U)
#define ETH_MACIER_RXSTSIE_Msk (0x1U << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */
#define ETH_MACIER_RXSTSIE ETH_MACIER_RXSTSIE_Msk /*!< Receive Status Interrupt Enable */
/************* Bit definition for ETH_MACRXTXSR register *************/
#define ETH_MACRXTXSR_TJT_Pos (0U)
#define ETH_MACRXTXSR_TJT_Msk (0x1U << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */
#define ETH_MACRXTXSR_TJT ETH_MACRXTXSR_TJT_Msk /*!< Transmit Jabber Timeout */
#define ETH_MACRXTXSR_NCARR_Pos (1U)
#define ETH_MACRXTXSR_NCARR_Msk (0x1U << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */
#define ETH_MACRXTXSR_NCARR ETH_MACRXTXSR_NCARR_Msk /*!< No Carrier */
#define ETH_MACRXTXSR_LCARR_Pos (2U)
#define ETH_MACRXTXSR_LCARR_Msk (0x1U << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */
#define ETH_MACRXTXSR_LCARR ETH_MACRXTXSR_LCARR_Msk /*!< Loss of Carrier */
#define ETH_MACRXTXSR_EXDEF_Pos (3U)
#define ETH_MACRXTXSR_EXDEF_Msk (0x1U << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */
#define ETH_MACRXTXSR_EXDEF ETH_MACRXTXSR_EXDEF_Msk /*!< Excessive Deferral */
#define ETH_MACRXTXSR_LCOL_Pos (4U)
#define ETH_MACRXTXSR_LCOL_Msk (0x1U << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */
#define ETH_MACRXTXSR_LCOL ETH_MACRXTXSR_LCOL_Msk /*!< Late Collision */
#define ETH_MACRXTXSR_EXCOL_Pos (5U)
#define ETH_MACRXTXSR_EXCOL_Msk (0x1U << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */
#define ETH_MACRXTXSR_EXCOL ETH_MACRXTXSR_EXCOL_Msk /*!< Excessive Collisions */
#define ETH_MACRXTXSR_RWT_Pos (8U)
#define ETH_MACRXTXSR_RWT_Msk (0x1U << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */
#define ETH_MACRXTXSR_RWT ETH_MACRXTXSR_RWT_Msk /*!< Receive Watchdog Timeout */
/************** Bit definition for ETH_MACPCSR register **************/
#define ETH_MACPCSR_PWRDWN_Pos (0U)
#define ETH_MACPCSR_PWRDWN_Msk (0x1U << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */
#define ETH_MACPCSR_PWRDWN ETH_MACPCSR_PWRDWN_Msk /*!< Power Down */
#define ETH_MACPCSR_MGKPKTEN_Pos (1U)
#define ETH_MACPCSR_MGKPKTEN_Msk (0x1U << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */
#define ETH_MACPCSR_MGKPKTEN ETH_MACPCSR_MGKPKTEN_Msk /*!< Magic Packet Enable */
#define ETH_MACPCSR_RWKPKTEN_Pos (2U)
#define ETH_MACPCSR_RWKPKTEN_Msk (0x1U << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */
#define ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk /*!< Remote wakeup Packet Enable */
#define ETH_MACPCSR_MGKPRCVD_Pos (5U)
#define ETH_MACPCSR_MGKPRCVD_Msk (0x1U << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */
#define ETH_MACPCSR_MGKPRCVD ETH_MACPCSR_MGKPRCVD_Msk /*!< Magic Packet Received */
#define ETH_MACPCSR_RWKPRCVD_Pos (6U)
#define ETH_MACPCSR_RWKPRCVD_Msk (0x1U << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */
#define ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk /*!< Remote wakeup Packet Received */
#define ETH_MACPCSR_GLBLUCAST_Pos (9U)
#define ETH_MACPCSR_GLBLUCAST_Msk (0x1U << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */
#define ETH_MACPCSR_GLBLUCAST ETH_MACPCSR_GLBLUCAST_Msk /*!< Global Unicast */
#define ETH_MACPCSR_RWKPFE_Pos (10U)
#define ETH_MACPCSR_RWKPFE_Msk (0x1U << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */
#define ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk /*!< Remote wakeup Packet Forwarding Enable */
#define ETH_MACPCSR_RWKPTR_Pos (24U)
#define ETH_MACPCSR_RWKPTR_Msk (0x1FU << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */
#define ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk /*!< Remote wakeup FIFO Pointer */
#define ETH_MACPCSR_RWKPTR_0 (0x1U << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x01000000 */
#define ETH_MACPCSR_RWKPTR_1 (0x2U << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x02000000 */
#define ETH_MACPCSR_RWKPTR_2 (0x4U << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x04000000 */
#define ETH_MACPCSR_RWKPTR_3 (0x8U << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x08000000 */
#define ETH_MACPCSR_RWKPTR_4 (0x10U << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x10000000 */
#define ETH_MACPCSR_RWKFILTRST_Pos (31U)
#define ETH_MACPCSR_RWKFILTRST_Msk (0x1U << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */
#define ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk /*!< Remote wakeup Packet Filter Register Pointer Reset */
/************* Bit definition for ETH_MACRWKPFR register *************/
#define ETH_MACRWKPFR_MACRWKPFR_Pos (0U)
#define ETH_MACRWKPFR_MACRWKPFR_Msk (0xFFFFFFFFU << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACRWKPFR_MACRWKPFR ETH_MACRWKPFR_MACRWKPFR_Msk /*!< Remote wakeup packet filter */
#define ETH_MACRWKPFR_MACRWKPFR_0 (0x1U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00000001 */
#define ETH_MACRWKPFR_MACRWKPFR_1 (0x2U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00000002 */
#define ETH_MACRWKPFR_MACRWKPFR_2 (0x4U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00000004 */
#define ETH_MACRWKPFR_MACRWKPFR_3 (0x8U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00000008 */
#define ETH_MACRWKPFR_MACRWKPFR_4 (0x10U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00000010 */
#define ETH_MACRWKPFR_MACRWKPFR_5 (0x20U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00000020 */
#define ETH_MACRWKPFR_MACRWKPFR_6 (0x40U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00000040 */
#define ETH_MACRWKPFR_MACRWKPFR_7 (0x80U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00000080 */
#define ETH_MACRWKPFR_MACRWKPFR_8 (0x100U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00000100 */
#define ETH_MACRWKPFR_MACRWKPFR_9 (0x200U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00000200 */
#define ETH_MACRWKPFR_MACRWKPFR_10 (0x400U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00000400 */
#define ETH_MACRWKPFR_MACRWKPFR_11 (0x800U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00000800 */
#define ETH_MACRWKPFR_MACRWKPFR_12 (0x1000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00001000 */
#define ETH_MACRWKPFR_MACRWKPFR_13 (0x2000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00002000 */
#define ETH_MACRWKPFR_MACRWKPFR_14 (0x4000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00004000 */
#define ETH_MACRWKPFR_MACRWKPFR_15 (0x8000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00008000 */
#define ETH_MACRWKPFR_MACRWKPFR_16 (0x10000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00010000 */
#define ETH_MACRWKPFR_MACRWKPFR_17 (0x20000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00020000 */
#define ETH_MACRWKPFR_MACRWKPFR_18 (0x40000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00040000 */
#define ETH_MACRWKPFR_MACRWKPFR_19 (0x80000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00080000 */
#define ETH_MACRWKPFR_MACRWKPFR_20 (0x100000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00100000 */
#define ETH_MACRWKPFR_MACRWKPFR_21 (0x200000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00200000 */
#define ETH_MACRWKPFR_MACRWKPFR_22 (0x400000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00400000 */
#define ETH_MACRWKPFR_MACRWKPFR_23 (0x800000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x00800000 */
#define ETH_MACRWKPFR_MACRWKPFR_24 (0x1000000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x01000000 */
#define ETH_MACRWKPFR_MACRWKPFR_25 (0x2000000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x02000000 */
#define ETH_MACRWKPFR_MACRWKPFR_26 (0x4000000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x04000000 */
#define ETH_MACRWKPFR_MACRWKPFR_27 (0x8000000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x08000000 */
#define ETH_MACRWKPFR_MACRWKPFR_28 (0x10000000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x10000000 */
#define ETH_MACRWKPFR_MACRWKPFR_29 (0x20000000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x20000000 */
#define ETH_MACRWKPFR_MACRWKPFR_30 (0x40000000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x40000000 */
#define ETH_MACRWKPFR_MACRWKPFR_31 (0x80000000U << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0x80000000 */
/************** Bit definition for ETH_MACLCSR register **************/
#define ETH_MACLCSR_TLPIEN_Pos (0U)
#define ETH_MACLCSR_TLPIEN_Msk (0x1U << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */
#define ETH_MACLCSR_TLPIEN ETH_MACLCSR_TLPIEN_Msk /*!< Transmit LPI Entry */
#define ETH_MACLCSR_TLPIEX_Pos (1U)
#define ETH_MACLCSR_TLPIEX_Msk (0x1U << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */
#define ETH_MACLCSR_TLPIEX ETH_MACLCSR_TLPIEX_Msk /*!< Transmit LPI Exit */
#define ETH_MACLCSR_RLPIEN_Pos (2U)
#define ETH_MACLCSR_RLPIEN_Msk (0x1U << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */
#define ETH_MACLCSR_RLPIEN ETH_MACLCSR_RLPIEN_Msk /*!< Receive LPI Entry */
#define ETH_MACLCSR_RLPIEX_Pos (3U)
#define ETH_MACLCSR_RLPIEX_Msk (0x1U << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */
#define ETH_MACLCSR_RLPIEX ETH_MACLCSR_RLPIEX_Msk /*!< Receive LPI Exit */
#define ETH_MACLCSR_TLPIST_Pos (8U)
#define ETH_MACLCSR_TLPIST_Msk (0x1U << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */
#define ETH_MACLCSR_TLPIST ETH_MACLCSR_TLPIST_Msk /*!< Transmit LPI State */
#define ETH_MACLCSR_RLPIST_Pos (9U)
#define ETH_MACLCSR_RLPIST_Msk (0x1U << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */
#define ETH_MACLCSR_RLPIST ETH_MACLCSR_RLPIST_Msk /*!< Receive LPI State */
#define ETH_MACLCSR_LPIEN_Pos (16U)
#define ETH_MACLCSR_LPIEN_Msk (0x1U << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */
#define ETH_MACLCSR_LPIEN ETH_MACLCSR_LPIEN_Msk /*!< LPI Enable */
#define ETH_MACLCSR_PLS_Pos (17U)
#define ETH_MACLCSR_PLS_Msk (0x1U << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */
#define ETH_MACLCSR_PLS ETH_MACLCSR_PLS_Msk /*!< PHY Link Status */
#define ETH_MACLCSR_PLSEN_Pos (18U)
#define ETH_MACLCSR_PLSEN_Msk (0x1U << ETH_MACLCSR_PLSEN_Pos) /*!< 0x00040000 */
#define ETH_MACLCSR_PLSEN ETH_MACLCSR_PLSEN_Msk /*!< PHY Link Status Enable */
#define ETH_MACLCSR_LPITXA_Pos (19U)
#define ETH_MACLCSR_LPITXA_Msk (0x1U << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */
#define ETH_MACLCSR_LPITXA ETH_MACLCSR_LPITXA_Msk /*!< LPI Tx Automate */
#define ETH_MACLCSR_LPITE_Pos (20U)
#define ETH_MACLCSR_LPITE_Msk (0x1U << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */
#define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /*!< LPI Timer Enable */
/************** Bit definition for ETH_MACLTCR register **************/
#define ETH_MACLTCR_TWT_Pos (0U)
#define ETH_MACLTCR_TWT_Msk (0xFFFFU << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */
#define ETH_MACLTCR_TWT ETH_MACLTCR_TWT_Msk /*!< LPI TW Timer */
#define ETH_MACLTCR_TWT_0 (0x1U << ETH_MACLTCR_TWT_Pos) /*!< 0x00000001 */
#define ETH_MACLTCR_TWT_1 (0x2U << ETH_MACLTCR_TWT_Pos) /*!< 0x00000002 */
#define ETH_MACLTCR_TWT_2 (0x4U << ETH_MACLTCR_TWT_Pos) /*!< 0x00000004 */
#define ETH_MACLTCR_TWT_3 (0x8U << ETH_MACLTCR_TWT_Pos) /*!< 0x00000008 */
#define ETH_MACLTCR_TWT_4 (0x10U << ETH_MACLTCR_TWT_Pos) /*!< 0x00000010 */
#define ETH_MACLTCR_TWT_5 (0x20U << ETH_MACLTCR_TWT_Pos) /*!< 0x00000020 */
#define ETH_MACLTCR_TWT_6 (0x40U << ETH_MACLTCR_TWT_Pos) /*!< 0x00000040 */
#define ETH_MACLTCR_TWT_7 (0x80U << ETH_MACLTCR_TWT_Pos) /*!< 0x00000080 */
#define ETH_MACLTCR_TWT_8 (0x100U << ETH_MACLTCR_TWT_Pos) /*!< 0x00000100 */
#define ETH_MACLTCR_TWT_9 (0x200U << ETH_MACLTCR_TWT_Pos) /*!< 0x00000200 */
#define ETH_MACLTCR_TWT_10 (0x400U << ETH_MACLTCR_TWT_Pos) /*!< 0x00000400 */
#define ETH_MACLTCR_TWT_11 (0x800U << ETH_MACLTCR_TWT_Pos) /*!< 0x00000800 */
#define ETH_MACLTCR_TWT_12 (0x1000U << ETH_MACLTCR_TWT_Pos) /*!< 0x00001000 */
#define ETH_MACLTCR_TWT_13 (0x2000U << ETH_MACLTCR_TWT_Pos) /*!< 0x00002000 */
#define ETH_MACLTCR_TWT_14 (0x4000U << ETH_MACLTCR_TWT_Pos) /*!< 0x00004000 */
#define ETH_MACLTCR_TWT_15 (0x8000U << ETH_MACLTCR_TWT_Pos) /*!< 0x00008000 */
#define ETH_MACLTCR_LST_Pos (16U)
#define ETH_MACLTCR_LST_Msk (0x3FFU << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */
#define ETH_MACLTCR_LST ETH_MACLTCR_LST_Msk /*!< LPI LS Timer */
#define ETH_MACLTCR_LST_0 (0x1U << ETH_MACLTCR_LST_Pos) /*!< 0x00010000 */
#define ETH_MACLTCR_LST_1 (0x2U << ETH_MACLTCR_LST_Pos) /*!< 0x00020000 */
#define ETH_MACLTCR_LST_2 (0x4U << ETH_MACLTCR_LST_Pos) /*!< 0x00040000 */
#define ETH_MACLTCR_LST_3 (0x8U << ETH_MACLTCR_LST_Pos) /*!< 0x00080000 */
#define ETH_MACLTCR_LST_4 (0x10U << ETH_MACLTCR_LST_Pos) /*!< 0x00100000 */
#define ETH_MACLTCR_LST_5 (0x20U << ETH_MACLTCR_LST_Pos) /*!< 0x00200000 */
#define ETH_MACLTCR_LST_6 (0x40U << ETH_MACLTCR_LST_Pos) /*!< 0x00400000 */
#define ETH_MACLTCR_LST_7 (0x80U << ETH_MACLTCR_LST_Pos) /*!< 0x00800000 */
#define ETH_MACLTCR_LST_8 (0x100U << ETH_MACLTCR_LST_Pos) /*!< 0x01000000 */
#define ETH_MACLTCR_LST_9 (0x200U << ETH_MACLTCR_LST_Pos) /*!< 0x02000000 */
/************** Bit definition for ETH_MACLETR register **************/
#define ETH_MACLETR_LPIET_Pos (3U)
#define ETH_MACLETR_LPIET_Msk (0x1FFFFU << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFF8 */
#define ETH_MACLETR_LPIET ETH_MACLETR_LPIET_Msk /*!< LPI Entry Timer */
#define ETH_MACLETR_LPIET_0 (0x1U << ETH_MACLETR_LPIET_Pos) /*!< 0x00000008 */
#define ETH_MACLETR_LPIET_1 (0x2U << ETH_MACLETR_LPIET_Pos) /*!< 0x00000010 */
#define ETH_MACLETR_LPIET_2 (0x4U << ETH_MACLETR_LPIET_Pos) /*!< 0x00000020 */
#define ETH_MACLETR_LPIET_3 (0x8U << ETH_MACLETR_LPIET_Pos) /*!< 0x00000040 */
#define ETH_MACLETR_LPIET_4 (0x10U << ETH_MACLETR_LPIET_Pos) /*!< 0x00000080 */
#define ETH_MACLETR_LPIET_5 (0x20U << ETH_MACLETR_LPIET_Pos) /*!< 0x00000100 */
#define ETH_MACLETR_LPIET_6 (0x40U << ETH_MACLETR_LPIET_Pos) /*!< 0x00000200 */
#define ETH_MACLETR_LPIET_7 (0x80U << ETH_MACLETR_LPIET_Pos) /*!< 0x00000400 */
#define ETH_MACLETR_LPIET_8 (0x100U << ETH_MACLETR_LPIET_Pos) /*!< 0x00000800 */
#define ETH_MACLETR_LPIET_9 (0x200U << ETH_MACLETR_LPIET_Pos) /*!< 0x00001000 */
#define ETH_MACLETR_LPIET_10 (0x400U << ETH_MACLETR_LPIET_Pos) /*!< 0x00002000 */
#define ETH_MACLETR_LPIET_11 (0x800U << ETH_MACLETR_LPIET_Pos) /*!< 0x00004000 */
#define ETH_MACLETR_LPIET_12 (0x1000U << ETH_MACLETR_LPIET_Pos) /*!< 0x00008000 */
#define ETH_MACLETR_LPIET_13 (0x2000U << ETH_MACLETR_LPIET_Pos) /*!< 0x00010000 */
#define ETH_MACLETR_LPIET_14 (0x4000U << ETH_MACLETR_LPIET_Pos) /*!< 0x00020000 */
#define ETH_MACLETR_LPIET_15 (0x8000U << ETH_MACLETR_LPIET_Pos) /*!< 0x00040000 */
#define ETH_MACLETR_LPIET_16 (0x10000U << ETH_MACLETR_LPIET_Pos) /*!< 0x00080000 */
/************* Bit definition for ETH_MAC1USTCR register *************/
#define ETH_MAC1USTCR_TIC_1US_CNTR_Pos (0U)
#define ETH_MAC1USTCR_TIC_1US_CNTR_Msk (0xFFFU << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000FFF */
#define ETH_MAC1USTCR_TIC_1US_CNTR ETH_MAC1USTCR_TIC_1US_CNTR_Msk /*!< 1 µs tick Counter */
#define ETH_MAC1USTCR_TIC_1US_CNTR_0 (0x1U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000001 */
#define ETH_MAC1USTCR_TIC_1US_CNTR_1 (0x2U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000002 */
#define ETH_MAC1USTCR_TIC_1US_CNTR_2 (0x4U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000004 */
#define ETH_MAC1USTCR_TIC_1US_CNTR_3 (0x8U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000008 */
#define ETH_MAC1USTCR_TIC_1US_CNTR_4 (0x10U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000010 */
#define ETH_MAC1USTCR_TIC_1US_CNTR_5 (0x20U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000020 */
#define ETH_MAC1USTCR_TIC_1US_CNTR_6 (0x40U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000040 */
#define ETH_MAC1USTCR_TIC_1US_CNTR_7 (0x80U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000080 */
#define ETH_MAC1USTCR_TIC_1US_CNTR_8 (0x100U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000100 */
#define ETH_MAC1USTCR_TIC_1US_CNTR_9 (0x200U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000200 */
#define ETH_MAC1USTCR_TIC_1US_CNTR_10 (0x400U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000400 */
#define ETH_MAC1USTCR_TIC_1US_CNTR_11 (0x800U << ETH_MAC1USTCR_TIC_1US_CNTR_Pos) /*!< 0x00000800 */
/************* Bit definition for ETH_MACPHYCSR register *************/
#define ETH_MACPHYCSR_TC_Pos (0U)
#define ETH_MACPHYCSR_TC_Msk (0x1U << ETH_MACPHYCSR_TC_Pos) /*!< 0x00000001 */
#define ETH_MACPHYCSR_TC ETH_MACPHYCSR_TC_Msk /*!< Transmit Configuration in RGMII, SGMII, or SMII */
#define ETH_MACPHYCSR_LUD_Pos (1U)
#define ETH_MACPHYCSR_LUD_Msk (0x1U << ETH_MACPHYCSR_LUD_Pos) /*!< 0x00000002 */
#define ETH_MACPHYCSR_LUD ETH_MACPHYCSR_LUD_Msk /*!< Link Up or Down */
#define ETH_MACPHYCSR_LNKMOD_Pos (16U)
#define ETH_MACPHYCSR_LNKMOD_Msk (0x1U << ETH_MACPHYCSR_LNKMOD_Pos) /*!< 0x00010000 */
#define ETH_MACPHYCSR_LNKMOD ETH_MACPHYCSR_LNKMOD_Msk /*!< Link Mode */
#define ETH_MACPHYCSR_LNKSPEED_Pos (17U)
#define ETH_MACPHYCSR_LNKSPEED_Msk (0x3U << ETH_MACPHYCSR_LNKSPEED_Pos) /*!< 0x00060000 */
#define ETH_MACPHYCSR_LNKSPEED ETH_MACPHYCSR_LNKSPEED_Msk /*!< Link Speed */
#define ETH_MACPHYCSR_LNKSPEED_0 (0x1U << ETH_MACPHYCSR_LNKSPEED_Pos) /*!< 0x00020000 */
#define ETH_MACPHYCSR_LNKSPEED_1 (0x2U << ETH_MACPHYCSR_LNKSPEED_Pos) /*!< 0x00040000 */
#define ETH_MACPHYCSR_LNKSTS_Pos (19U)
#define ETH_MACPHYCSR_LNKSTS_Msk (0x1U << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */
#define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /*!< Link Status */
#define ETH_MACPHYCSR_JABTO_Pos (20U)
#define ETH_MACPHYCSR_JABTO_Msk (0x1U << ETH_MACPHYCSR_JABTO_Pos) /*!< 0x00100000 */
#define ETH_MACPHYCSR_JABTO ETH_MACPHYCSR_JABTO_Msk /*!< Jabber Timeout */
#define ETH_MACPHYCSR_FALSCARDET_Pos (21U)
#define ETH_MACPHYCSR_FALSCARDET_Msk (0x1U << ETH_MACPHYCSR_FALSCARDET_Pos) /*!< 0x00200000 */
#define ETH_MACPHYCSR_FALSCARDET ETH_MACPHYCSR_FALSCARDET_Msk /*!< False Carrier Detected */
/*************** Bit definition for ETH_MACVR register ***************/
#define ETH_MACVR_SNPSVER_Pos (0U)
#define ETH_MACVR_SNPSVER_Msk (0xFFU << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */
#define ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk /*!< IP version */
#define ETH_MACVR_SNPSVER_0 (0x1U << ETH_MACVR_SNPSVER_Pos) /*!< 0x00000001 */
#define ETH_MACVR_SNPSVER_1 (0x2U << ETH_MACVR_SNPSVER_Pos) /*!< 0x00000002 */
#define ETH_MACVR_SNPSVER_2 (0x4U << ETH_MACVR_SNPSVER_Pos) /*!< 0x00000004 */
#define ETH_MACVR_SNPSVER_3 (0x8U << ETH_MACVR_SNPSVER_Pos) /*!< 0x00000008 */
#define ETH_MACVR_SNPSVER_4 (0x10U << ETH_MACVR_SNPSVER_Pos) /*!< 0x00000010 */
#define ETH_MACVR_SNPSVER_5 (0x20U << ETH_MACVR_SNPSVER_Pos) /*!< 0x00000020 */
#define ETH_MACVR_SNPSVER_6 (0x40U << ETH_MACVR_SNPSVER_Pos) /*!< 0x00000040 */
#define ETH_MACVR_SNPSVER_7 (0x80U << ETH_MACVR_SNPSVER_Pos) /*!< 0x00000080 */
#define ETH_MACVR_USERVER_Pos (8U)
#define ETH_MACVR_USERVER_Msk (0xFFU << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */
#define ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk /*!< ST-defined version */
#define ETH_MACVR_USERVER_0 (0x1U << ETH_MACVR_USERVER_Pos) /*!< 0x00000100 */
#define ETH_MACVR_USERVER_1 (0x2U << ETH_MACVR_USERVER_Pos) /*!< 0x00000200 */
#define ETH_MACVR_USERVER_2 (0x4U << ETH_MACVR_USERVER_Pos) /*!< 0x00000400 */
#define ETH_MACVR_USERVER_3 (0x8U << ETH_MACVR_USERVER_Pos) /*!< 0x00000800 */
#define ETH_MACVR_USERVER_4 (0x10U << ETH_MACVR_USERVER_Pos) /*!< 0x00001000 */
#define ETH_MACVR_USERVER_5 (0x20U << ETH_MACVR_USERVER_Pos) /*!< 0x00002000 */
#define ETH_MACVR_USERVER_6 (0x40U << ETH_MACVR_USERVER_Pos) /*!< 0x00004000 */
#define ETH_MACVR_USERVER_7 (0x80U << ETH_MACVR_USERVER_Pos) /*!< 0x00008000 */
/*************** Bit definition for ETH_MACDR register ***************/
#define ETH_MACDR_RPESTS_Pos (0U)
#define ETH_MACDR_RPESTS_Msk (0x1U << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */
#define ETH_MACDR_RPESTS ETH_MACDR_RPESTS_Msk /*!< MAC GMII or MII Receive Protocol Engine Status */
#define ETH_MACDR_RFCFCSTS_Pos (1U)
#define ETH_MACDR_RFCFCSTS_Msk (0x3U << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */
#define ETH_MACDR_RFCFCSTS ETH_MACDR_RFCFCSTS_Msk /*!< MAC Receive Packet Controller FIFO Status */
#define ETH_MACDR_RFCFCSTS_0 (0x1U << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000002 */
#define ETH_MACDR_RFCFCSTS_1 (0x2U << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000004 */
#define ETH_MACDR_TPESTS_Pos (16U)
#define ETH_MACDR_TPESTS_Msk (0x1U << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */
#define ETH_MACDR_TPESTS ETH_MACDR_TPESTS_Msk /*!< MAC GMII or MII Transmit Protocol Engine Status */
#define ETH_MACDR_TFCSTS_Pos (17U)
#define ETH_MACDR_TFCSTS_Msk (0x3U << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /*!< MAC Transmit Packet Controller Status */
#define ETH_MACDR_TFCSTS_0 (0x1U << ETH_MACDR_TFCSTS_Pos) /*!< 0x00020000 */
#define ETH_MACDR_TFCSTS_1 (0x2U << ETH_MACDR_TFCSTS_Pos) /*!< 0x00040000 */
/************* Bit definition for ETH_MACHWF1R register **************/
#define ETH_MACHWF1R_RXFIFOSIZE_Pos (0U)
#define ETH_MACHWF1R_RXFIFOSIZE_Msk (0x1FU << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */
#define ETH_MACHWF1R_RXFIFOSIZE ETH_MACHWF1R_RXFIFOSIZE_Msk /*!< MTL Receive FIFO Size */
#define ETH_MACHWF1R_RXFIFOSIZE_0 (0x1U << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x00000001 */
#define ETH_MACHWF1R_RXFIFOSIZE_1 (0x2U << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x00000002 */
#define ETH_MACHWF1R_RXFIFOSIZE_2 (0x4U << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x00000004 */
#define ETH_MACHWF1R_RXFIFOSIZE_3 (0x8U << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x00000008 */
#define ETH_MACHWF1R_RXFIFOSIZE_4 (0x10U << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x00000010 */
#define ETH_MACHWF1R_TXFIFOSIZE_Pos (6U)
#define ETH_MACHWF1R_TXFIFOSIZE_Msk (0x1FU << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */
#define ETH_MACHWF1R_TXFIFOSIZE ETH_MACHWF1R_TXFIFOSIZE_Msk /*!< MTL Transmit FIFO Size */
#define ETH_MACHWF1R_TXFIFOSIZE_0 (0x1U << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x00000040 */
#define ETH_MACHWF1R_TXFIFOSIZE_1 (0x2U << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x00000080 */
#define ETH_MACHWF1R_TXFIFOSIZE_2 (0x4U << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x00000100 */
#define ETH_MACHWF1R_TXFIFOSIZE_3 (0x8U << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x00000200 */
#define ETH_MACHWF1R_TXFIFOSIZE_4 (0x10U << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x00000400 */
#define ETH_MACHWF1R_OSTEN_Pos (11U)
#define ETH_MACHWF1R_OSTEN_Msk (0x1U << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */
#define ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk /*!< One-Step Timestamping Enable */
#define ETH_MACHWF1R_PTOEN_Pos (12U)
#define ETH_MACHWF1R_PTOEN_Msk (0x1U << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */
#define ETH_MACHWF1R_PTOEN ETH_MACHWF1R_PTOEN_Msk /*!< PTP Offload Enable */
#define ETH_MACHWF1R_ADVTHWORD_Pos (13U)
#define ETH_MACHWF1R_ADVTHWORD_Msk (0x1U << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */
#define ETH_MACHWF1R_ADVTHWORD ETH_MACHWF1R_ADVTHWORD_Msk /*!< IEEE 1588 High Word Register Enable */
#define ETH_MACHWF1R_ADDR64_Pos (14U)
#define ETH_MACHWF1R_ADDR64_Msk (0x3U << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */
#define ETH_MACHWF1R_ADDR64 ETH_MACHWF1R_ADDR64_Msk /*!< Address width */
#define ETH_MACHWF1R_ADDR64_0 (0x1U << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */
#define ETH_MACHWF1R_ADDR64_1 (0x2U << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */
#define ETH_MACHWF1R_DCBEN_Pos (16U)
#define ETH_MACHWF1R_DCBEN_Msk (0x1U << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */
#define ETH_MACHWF1R_DCBEN ETH_MACHWF1R_DCBEN_Msk /*!< DCB Feature Enable */
#define ETH_MACHWF1R_SPHEN_Pos (17U)
#define ETH_MACHWF1R_SPHEN_Msk (0x1U << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */
#define ETH_MACHWF1R_SPHEN ETH_MACHWF1R_SPHEN_Msk /*!< Split Header Feature Enable */
#define ETH_MACHWF1R_TSOEN_Pos (18U)
#define ETH_MACHWF1R_TSOEN_Msk (0x1U << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */
#define ETH_MACHWF1R_TSOEN ETH_MACHWF1R_TSOEN_Msk /*!< TCP Segmentation Offload Enable */
#define ETH_MACHWF1R_DBGMEMA_Pos (19U)
#define ETH_MACHWF1R_DBGMEMA_Msk (0x1U << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */
#define ETH_MACHWF1R_DBGMEMA ETH_MACHWF1R_DBGMEMA_Msk /*!< DMA Debug Registers Enable */
#define ETH_MACHWF1R_AVSEL_Pos (20U)
#define ETH_MACHWF1R_AVSEL_Msk (0x1U << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */
#define ETH_MACHWF1R_AVSEL ETH_MACHWF1R_AVSEL_Msk /*!< AV Feature Enable */
#define ETH_MACHWF1R_HASHTBLSZ_Pos (24U)
#define ETH_MACHWF1R_HASHTBLSZ_Msk (0x3U << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */
#define ETH_MACHWF1R_HASHTBLSZ ETH_MACHWF1R_HASHTBLSZ_Msk /*!< Hash Table Size */
#define ETH_MACHWF1R_HASHTBLSZ_0 (0x1U << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x01000000 */
#define ETH_MACHWF1R_HASHTBLSZ_1 (0x2U << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x02000000 */
#define ETH_MACHWF1R_L3L4FNUM_Pos (27U)
#define ETH_MACHWF1R_L3L4FNUM_Msk (0xFU << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */
#define ETH_MACHWF1R_L3L4FNUM ETH_MACHWF1R_L3L4FNUM_Msk /*!< Total number of L3 or L4 Filters */
#define ETH_MACHWF1R_L3L4FNUM_0 (0x1U << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x08000000 */
#define ETH_MACHWF1R_L3L4FNUM_1 (0x2U << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x10000000 */
#define ETH_MACHWF1R_L3L4FNUM_2 (0x4U << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x20000000 */
#define ETH_MACHWF1R_L3L4FNUM_3 (0x8U << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x40000000 */
/************* Bit definition for ETH_MACHWF2R register **************/
#define ETH_MACHWF2R_RXQCNT_Pos (0U)
#define ETH_MACHWF2R_RXQCNT_Msk (0xFU << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */
#define ETH_MACHWF2R_RXQCNT ETH_MACHWF2R_RXQCNT_Msk /*!< Number of MTL Receive Queues */
#define ETH_MACHWF2R_RXQCNT_0 (0x1U << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x00000001 */
#define ETH_MACHWF2R_RXQCNT_1 (0x2U << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x00000002 */
#define ETH_MACHWF2R_RXQCNT_2 (0x4U << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x00000004 */
#define ETH_MACHWF2R_RXQCNT_3 (0x8U << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x00000008 */
#define ETH_MACHWF2R_TXQCNT_Pos (6U)
#define ETH_MACHWF2R_TXQCNT_Msk (0xFU << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */
#define ETH_MACHWF2R_TXQCNT ETH_MACHWF2R_TXQCNT_Msk /*!< Number of MTL Transmit Queues */
#define ETH_MACHWF2R_TXQCNT_0 (0x1U << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x00000040 */
#define ETH_MACHWF2R_TXQCNT_1 (0x2U << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x00000080 */
#define ETH_MACHWF2R_TXQCNT_2 (0x4U << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x00000100 */
#define ETH_MACHWF2R_TXQCNT_3 (0x8U << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x00000200 */
#define ETH_MACHWF2R_RXCHCNT_Pos (12U)
#define ETH_MACHWF2R_RXCHCNT_Msk (0xFU << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000F000 */
#define ETH_MACHWF2R_RXCHCNT ETH_MACHWF2R_RXCHCNT_Msk /*!< Number of DMA Receive Channels */
#define ETH_MACHWF2R_RXCHCNT_0 (0x1U << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x00001000 */
#define ETH_MACHWF2R_RXCHCNT_1 (0x2U << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x00002000 */
#define ETH_MACHWF2R_RXCHCNT_2 (0x4U << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x00004000 */
#define ETH_MACHWF2R_RXCHCNT_3 (0x8U << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x00008000 */
#define ETH_MACHWF2R_TXCHCNT_Pos (18U)
#define ETH_MACHWF2R_TXCHCNT_Msk (0xFU << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */
#define ETH_MACHWF2R_TXCHCNT ETH_MACHWF2R_TXCHCNT_Msk /*!< Number of DMA Transmit Channels */
#define ETH_MACHWF2R_TXCHCNT_0 (0x1U << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x00040000 */
#define ETH_MACHWF2R_TXCHCNT_1 (0x2U << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x00080000 */
#define ETH_MACHWF2R_TXCHCNT_2 (0x4U << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x00100000 */
#define ETH_MACHWF2R_TXCHCNT_3 (0x8U << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x00200000 */
#define ETH_MACHWF2R_PPSOUTNUM_Pos (24U)
#define ETH_MACHWF2R_PPSOUTNUM_Msk (0x7U << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */
#define ETH_MACHWF2R_PPSOUTNUM ETH_MACHWF2R_PPSOUTNUM_Msk /*!< Number of PPS Outputs */
#define ETH_MACHWF2R_PPSOUTNUM_0 (0x1U << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x01000000 */
#define ETH_MACHWF2R_PPSOUTNUM_1 (0x2U << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x02000000 */
#define ETH_MACHWF2R_PPSOUTNUM_2 (0x4U << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x04000000 */
#define ETH_MACHWF2R_AUXSNAPNUM_Pos (28U)
#define ETH_MACHWF2R_AUXSNAPNUM_Msk (0x7U << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */
#define ETH_MACHWF2R_AUXSNAPNUM ETH_MACHWF2R_AUXSNAPNUM_Msk /*!< Number of Auxiliary Snapshot Inputs */
#define ETH_MACHWF2R_AUXSNAPNUM_0 (0x1U << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x10000000 */
#define ETH_MACHWF2R_AUXSNAPNUM_1 (0x2U << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x20000000 */
#define ETH_MACHWF2R_AUXSNAPNUM_2 (0x4U << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x40000000 */
/************* Bit definition for ETH_MACMDIOAR register *************/
#define ETH_MACMDIOAR_GB_Pos (0U)
#define ETH_MACMDIOAR_GB_Msk (0x1U << ETH_MACMDIOAR_GB_Pos) /*!< 0x00000001 */
#define ETH_MACMDIOAR_GB ETH_MACMDIOAR_GB_Msk /*!< GMII Busy */
#define ETH_MACMDIOAR_C45E_Pos (1U)
#define ETH_MACMDIOAR_C45E_Msk (0x1U << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */
#define ETH_MACMDIOAR_C45E ETH_MACMDIOAR_C45E_Msk /*!< Clause 45 PHY Enable */
#define ETH_MACMDIOAR_GOC_Pos (2U)
#define ETH_MACMDIOAR_GOC_Msk (0x3U << ETH_MACMDIOAR_GOC_Pos) /*!< 0x0000000C */
#define ETH_MACMDIOAR_GOC ETH_MACMDIOAR_GOC_Msk /*!< GMII Operation Command */
#define ETH_MACMDIOAR_GOC_0 (0x1U << ETH_MACMDIOAR_GOC_Pos) /*!< 0x00000004 */
#define ETH_MACMDIOAR_GOC_1 (0x2U << ETH_MACMDIOAR_GOC_Pos) /*!< 0x00000008 */
#define ETH_MACMDIOAR_SKAP_Pos (4U)
#define ETH_MACMDIOAR_SKAP_Msk (0x1U << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */
#define ETH_MACMDIOAR_SKAP ETH_MACMDIOAR_SKAP_Msk /*!< Skip Address Packet */
#define ETH_MACMDIOAR_CR_Pos (8U)
#define ETH_MACMDIOAR_CR_Msk (0xFU << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /*!< CSR Clock Range */
#define ETH_MACMDIOAR_CR_0 (0x1U << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000100 */
#define ETH_MACMDIOAR_CR_1 (0x2U << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000200 */
#define ETH_MACMDIOAR_CR_2 (0x4U << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000400 */
#define ETH_MACMDIOAR_CR_3 (0x8U << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000800 */
#define ETH_MACMDIOAR_NTC_Pos (12U)
#define ETH_MACMDIOAR_NTC_Msk (0x7U << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */
#define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /*!< Number of Training Clocks */
#define ETH_MACMDIOAR_NTC_0 (0x1U << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00001000 */
#define ETH_MACMDIOAR_NTC_1 (0x2U << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00002000 */
#define ETH_MACMDIOAR_NTC_2 (0x4U << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00004000 */
#define ETH_MACMDIOAR_RDA_Pos (16U)
#define ETH_MACMDIOAR_RDA_Msk (0x1FU << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */
#define ETH_MACMDIOAR_RDA ETH_MACMDIOAR_RDA_Msk /*!< Register/Device Address */
#define ETH_MACMDIOAR_RDA_0 (0x1U << ETH_MACMDIOAR_RDA_Pos) /*!< 0x00010000 */
#define ETH_MACMDIOAR_RDA_1 (0x2U << ETH_MACMDIOAR_RDA_Pos) /*!< 0x00020000 */
#define ETH_MACMDIOAR_RDA_2 (0x4U << ETH_MACMDIOAR_RDA_Pos) /*!< 0x00040000 */
#define ETH_MACMDIOAR_RDA_3 (0x8U << ETH_MACMDIOAR_RDA_Pos) /*!< 0x00080000 */
#define ETH_MACMDIOAR_RDA_4 (0x10U << ETH_MACMDIOAR_RDA_Pos) /*!< 0x00100000 */
#define ETH_MACMDIOAR_PA_Pos (21U)
#define ETH_MACMDIOAR_PA_Msk (0x1FU << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */
#define ETH_MACMDIOAR_PA ETH_MACMDIOAR_PA_Msk /*!< Physical Layer Address */
#define ETH_MACMDIOAR_PA_0 (0x1U << ETH_MACMDIOAR_PA_Pos) /*!< 0x00200000 */
#define ETH_MACMDIOAR_PA_1 (0x2U << ETH_MACMDIOAR_PA_Pos) /*!< 0x00400000 */
#define ETH_MACMDIOAR_PA_2 (0x4U << ETH_MACMDIOAR_PA_Pos) /*!< 0x00800000 */
#define ETH_MACMDIOAR_PA_3 (0x8U << ETH_MACMDIOAR_PA_Pos) /*!< 0x01000000 */
#define ETH_MACMDIOAR_PA_4 (0x10U << ETH_MACMDIOAR_PA_Pos) /*!< 0x02000000 */
#define ETH_MACMDIOAR_BTB_Pos (26U)
#define ETH_MACMDIOAR_BTB_Msk (0x1U << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */
#define ETH_MACMDIOAR_BTB ETH_MACMDIOAR_BTB_Msk /*!< Back to Back transactions */
#define ETH_MACMDIOAR_PSE_Pos (27U)
#define ETH_MACMDIOAR_PSE_Msk (0x1U << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */
#define ETH_MACMDIOAR_PSE ETH_MACMDIOAR_PSE_Msk /*!< Preamble Suppression Enable */
/************* Bit definition for ETH_MACMDIODR register *************/
#define ETH_MACMDIODR_GD_Pos (0U)
#define ETH_MACMDIODR_GD_Msk (0xFFFFU << ETH_MACMDIODR_GD_Pos) /*!< 0x0000FFFF */
#define ETH_MACMDIODR_GD ETH_MACMDIODR_GD_Msk /*!< GMII Data */
#define ETH_MACMDIODR_GD_0 (0x1U << ETH_MACMDIODR_GD_Pos) /*!< 0x00000001 */
#define ETH_MACMDIODR_GD_1 (0x2U << ETH_MACMDIODR_GD_Pos) /*!< 0x00000002 */
#define ETH_MACMDIODR_GD_2 (0x4U << ETH_MACMDIODR_GD_Pos) /*!< 0x00000004 */
#define ETH_MACMDIODR_GD_3 (0x8U << ETH_MACMDIODR_GD_Pos) /*!< 0x00000008 */
#define ETH_MACMDIODR_GD_4 (0x10U << ETH_MACMDIODR_GD_Pos) /*!< 0x00000010 */
#define ETH_MACMDIODR_GD_5 (0x20U << ETH_MACMDIODR_GD_Pos) /*!< 0x00000020 */
#define ETH_MACMDIODR_GD_6 (0x40U << ETH_MACMDIODR_GD_Pos) /*!< 0x00000040 */
#define ETH_MACMDIODR_GD_7 (0x80U << ETH_MACMDIODR_GD_Pos) /*!< 0x00000080 */
#define ETH_MACMDIODR_GD_8 (0x100U << ETH_MACMDIODR_GD_Pos) /*!< 0x00000100 */
#define ETH_MACMDIODR_GD_9 (0x200U << ETH_MACMDIODR_GD_Pos) /*!< 0x00000200 */
#define ETH_MACMDIODR_GD_10 (0x400U << ETH_MACMDIODR_GD_Pos) /*!< 0x00000400 */
#define ETH_MACMDIODR_GD_11 (0x800U << ETH_MACMDIODR_GD_Pos) /*!< 0x00000800 */
#define ETH_MACMDIODR_GD_12 (0x1000U << ETH_MACMDIODR_GD_Pos) /*!< 0x00001000 */
#define ETH_MACMDIODR_GD_13 (0x2000U << ETH_MACMDIODR_GD_Pos) /*!< 0x00002000 */
#define ETH_MACMDIODR_GD_14 (0x4000U << ETH_MACMDIODR_GD_Pos) /*!< 0x00004000 */
#define ETH_MACMDIODR_GD_15 (0x8000U << ETH_MACMDIODR_GD_Pos) /*!< 0x00008000 */
#define ETH_MACMDIODR_RA_Pos (16U)
#define ETH_MACMDIODR_RA_Msk (0xFFFFU << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */
#define ETH_MACMDIODR_RA ETH_MACMDIODR_RA_Msk /*!< Register Address */
#define ETH_MACMDIODR_RA_0 (0x1U << ETH_MACMDIODR_RA_Pos) /*!< 0x00010000 */
#define ETH_MACMDIODR_RA_1 (0x2U << ETH_MACMDIODR_RA_Pos) /*!< 0x00020000 */
#define ETH_MACMDIODR_RA_2 (0x4U << ETH_MACMDIODR_RA_Pos) /*!< 0x00040000 */
#define ETH_MACMDIODR_RA_3 (0x8U << ETH_MACMDIODR_RA_Pos) /*!< 0x00080000 */
#define ETH_MACMDIODR_RA_4 (0x10U << ETH_MACMDIODR_RA_Pos) /*!< 0x00100000 */
#define ETH_MACMDIODR_RA_5 (0x20U << ETH_MACMDIODR_RA_Pos) /*!< 0x00200000 */
#define ETH_MACMDIODR_RA_6 (0x40U << ETH_MACMDIODR_RA_Pos) /*!< 0x00400000 */
#define ETH_MACMDIODR_RA_7 (0x80U << ETH_MACMDIODR_RA_Pos) /*!< 0x00800000 */
#define ETH_MACMDIODR_RA_8 (0x100U << ETH_MACMDIODR_RA_Pos) /*!< 0x01000000 */
#define ETH_MACMDIODR_RA_9 (0x200U << ETH_MACMDIODR_RA_Pos) /*!< 0x02000000 */
#define ETH_MACMDIODR_RA_10 (0x400U << ETH_MACMDIODR_RA_Pos) /*!< 0x04000000 */
#define ETH_MACMDIODR_RA_11 (0x800U << ETH_MACMDIODR_RA_Pos) /*!< 0x08000000 */
#define ETH_MACMDIODR_RA_12 (0x1000U << ETH_MACMDIODR_RA_Pos) /*!< 0x10000000 */
#define ETH_MACMDIODR_RA_13 (0x2000U << ETH_MACMDIODR_RA_Pos) /*!< 0x20000000 */
#define ETH_MACMDIODR_RA_14 (0x4000U << ETH_MACMDIODR_RA_Pos) /*!< 0x40000000 */
#define ETH_MACMDIODR_RA_15 (0x8000U << ETH_MACMDIODR_RA_Pos) /*!< 0x80000000 */
/************** Bit definition for ETH_MACA0HR register **************/
#define ETH_MACA0HR_ADDRHI_Pos (0U)
#define ETH_MACA0HR_ADDRHI_Msk (0xFFFFU << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */
#define ETH_MACA0HR_ADDRHI ETH_MACA0HR_ADDRHI_Msk /*!< MAC Address0[47:32] */
#define ETH_MACA0HR_ADDRHI_0 (0x1U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00000001 */
#define ETH_MACA0HR_ADDRHI_1 (0x2U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00000002 */
#define ETH_MACA0HR_ADDRHI_2 (0x4U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00000004 */
#define ETH_MACA0HR_ADDRHI_3 (0x8U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00000008 */
#define ETH_MACA0HR_ADDRHI_4 (0x10U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00000010 */
#define ETH_MACA0HR_ADDRHI_5 (0x20U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00000020 */
#define ETH_MACA0HR_ADDRHI_6 (0x40U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00000040 */
#define ETH_MACA0HR_ADDRHI_7 (0x80U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00000080 */
#define ETH_MACA0HR_ADDRHI_8 (0x100U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00000100 */
#define ETH_MACA0HR_ADDRHI_9 (0x200U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00000200 */
#define ETH_MACA0HR_ADDRHI_10 (0x400U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00000400 */
#define ETH_MACA0HR_ADDRHI_11 (0x800U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00000800 */
#define ETH_MACA0HR_ADDRHI_12 (0x1000U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00001000 */
#define ETH_MACA0HR_ADDRHI_13 (0x2000U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00002000 */
#define ETH_MACA0HR_ADDRHI_14 (0x4000U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00004000 */
#define ETH_MACA0HR_ADDRHI_15 (0x8000U << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x00008000 */
#define ETH_MACA0HR_AE_Pos (31U)
#define ETH_MACA0HR_AE_Msk (0x1U << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */
#define ETH_MACA0HR_AE ETH_MACA0HR_AE_Msk /*!< Address Enable */
/************** Bit definition for ETH_MACA0LR register **************/
#define ETH_MACA0LR_ADDRLO_Pos (0U)
#define ETH_MACA0LR_ADDRLO_Msk (0xFFFFFFFFU << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACA0LR_ADDRLO ETH_MACA0LR_ADDRLO_Msk /*!< MAC Address x [31:0] (x = 0 to 3) */
#define ETH_MACA0LR_ADDRLO_0 (0x1U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00000001 */
#define ETH_MACA0LR_ADDRLO_1 (0x2U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00000002 */
#define ETH_MACA0LR_ADDRLO_2 (0x4U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00000004 */
#define ETH_MACA0LR_ADDRLO_3 (0x8U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00000008 */
#define ETH_MACA0LR_ADDRLO_4 (0x10U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00000010 */
#define ETH_MACA0LR_ADDRLO_5 (0x20U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00000020 */
#define ETH_MACA0LR_ADDRLO_6 (0x40U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00000040 */
#define ETH_MACA0LR_ADDRLO_7 (0x80U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00000080 */
#define ETH_MACA0LR_ADDRLO_8 (0x100U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00000100 */
#define ETH_MACA0LR_ADDRLO_9 (0x200U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00000200 */
#define ETH_MACA0LR_ADDRLO_10 (0x400U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00000400 */
#define ETH_MACA0LR_ADDRLO_11 (0x800U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00000800 */
#define ETH_MACA0LR_ADDRLO_12 (0x1000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00001000 */
#define ETH_MACA0LR_ADDRLO_13 (0x2000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00002000 */
#define ETH_MACA0LR_ADDRLO_14 (0x4000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00004000 */
#define ETH_MACA0LR_ADDRLO_15 (0x8000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00008000 */
#define ETH_MACA0LR_ADDRLO_16 (0x10000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00010000 */
#define ETH_MACA0LR_ADDRLO_17 (0x20000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00020000 */
#define ETH_MACA0LR_ADDRLO_18 (0x40000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00040000 */
#define ETH_MACA0LR_ADDRLO_19 (0x80000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00080000 */
#define ETH_MACA0LR_ADDRLO_20 (0x100000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00100000 */
#define ETH_MACA0LR_ADDRLO_21 (0x200000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00200000 */
#define ETH_MACA0LR_ADDRLO_22 (0x400000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00400000 */
#define ETH_MACA0LR_ADDRLO_23 (0x800000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x00800000 */
#define ETH_MACA0LR_ADDRLO_24 (0x1000000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x01000000 */
#define ETH_MACA0LR_ADDRLO_25 (0x2000000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x02000000 */
#define ETH_MACA0LR_ADDRLO_26 (0x4000000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x04000000 */
#define ETH_MACA0LR_ADDRLO_27 (0x8000000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x08000000 */
#define ETH_MACA0LR_ADDRLO_28 (0x10000000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x10000000 */
#define ETH_MACA0LR_ADDRLO_29 (0x20000000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x20000000 */
#define ETH_MACA0LR_ADDRLO_30 (0x40000000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x40000000 */
#define ETH_MACA0LR_ADDRLO_31 (0x80000000U << ETH_MACA0LR_ADDRLO_Pos) /*!< 0x80000000 */
/************** Bit definition for ETH_MACA1HR register **************/
#define ETH_MACA1HR_ADDRHI_Pos (0U)
#define ETH_MACA1HR_ADDRHI_Msk (0xFFFFU << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */
#define ETH_MACA1HR_ADDRHI ETH_MACA1HR_ADDRHI_Msk /*!< MAC Address1 [47:32] */
#define ETH_MACA1HR_ADDRHI_0 (0x1U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00000001 */
#define ETH_MACA1HR_ADDRHI_1 (0x2U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00000002 */
#define ETH_MACA1HR_ADDRHI_2 (0x4U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00000004 */
#define ETH_MACA1HR_ADDRHI_3 (0x8U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00000008 */
#define ETH_MACA1HR_ADDRHI_4 (0x10U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00000010 */
#define ETH_MACA1HR_ADDRHI_5 (0x20U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00000020 */
#define ETH_MACA1HR_ADDRHI_6 (0x40U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00000040 */
#define ETH_MACA1HR_ADDRHI_7 (0x80U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00000080 */
#define ETH_MACA1HR_ADDRHI_8 (0x100U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00000100 */
#define ETH_MACA1HR_ADDRHI_9 (0x200U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00000200 */
#define ETH_MACA1HR_ADDRHI_10 (0x400U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00000400 */
#define ETH_MACA1HR_ADDRHI_11 (0x800U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00000800 */
#define ETH_MACA1HR_ADDRHI_12 (0x1000U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00001000 */
#define ETH_MACA1HR_ADDRHI_13 (0x2000U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00002000 */
#define ETH_MACA1HR_ADDRHI_14 (0x4000U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00004000 */
#define ETH_MACA1HR_ADDRHI_15 (0x8000U << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x00008000 */
#define ETH_MACA1HR_MBC_Pos (24U)
#define ETH_MACA1HR_MBC_Msk (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /*!< Mask Byte Control */
#define ETH_MACA1HR_MBC_0 (0x1U << ETH_MACA1HR_MBC_Pos) /*!< 0x01000000 */
#define ETH_MACA1HR_MBC_1 (0x2U << ETH_MACA1HR_MBC_Pos) /*!< 0x02000000 */
#define ETH_MACA1HR_MBC_2 (0x4U << ETH_MACA1HR_MBC_Pos) /*!< 0x04000000 */
#define ETH_MACA1HR_MBC_3 (0x8U << ETH_MACA1HR_MBC_Pos) /*!< 0x08000000 */
#define ETH_MACA1HR_MBC_4 (0x10U << ETH_MACA1HR_MBC_Pos) /*!< 0x10000000 */
#define ETH_MACA1HR_MBC_5 (0x20U << ETH_MACA1HR_MBC_Pos) /*!< 0x20000000 */
#define ETH_MACA1HR_SA_Pos (30U)
#define ETH_MACA1HR_SA_Msk (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /*!< Source Address */
#define ETH_MACA1HR_AE_Pos (31U)
#define ETH_MACA1HR_AE_Msk (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /*!< Address Enable */
/************** Bit definition for ETH_MACA1LR register **************/
#define ETH_MACA1LR_ADDRLO_Pos (0U)
#define ETH_MACA1LR_ADDRLO_Msk (0xFFFFFFFFU << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACA1LR_ADDRLO ETH_MACA1LR_ADDRLO_Msk /*!< MAC Address x [31:0] (x = 0 to 3) */
#define ETH_MACA1LR_ADDRLO_0 (0x1U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00000001 */
#define ETH_MACA1LR_ADDRLO_1 (0x2U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00000002 */
#define ETH_MACA1LR_ADDRLO_2 (0x4U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00000004 */
#define ETH_MACA1LR_ADDRLO_3 (0x8U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00000008 */
#define ETH_MACA1LR_ADDRLO_4 (0x10U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00000010 */
#define ETH_MACA1LR_ADDRLO_5 (0x20U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00000020 */
#define ETH_MACA1LR_ADDRLO_6 (0x40U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00000040 */
#define ETH_MACA1LR_ADDRLO_7 (0x80U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00000080 */
#define ETH_MACA1LR_ADDRLO_8 (0x100U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00000100 */
#define ETH_MACA1LR_ADDRLO_9 (0x200U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00000200 */
#define ETH_MACA1LR_ADDRLO_10 (0x400U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00000400 */
#define ETH_MACA1LR_ADDRLO_11 (0x800U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00000800 */
#define ETH_MACA1LR_ADDRLO_12 (0x1000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00001000 */
#define ETH_MACA1LR_ADDRLO_13 (0x2000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00002000 */
#define ETH_MACA1LR_ADDRLO_14 (0x4000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00004000 */
#define ETH_MACA1LR_ADDRLO_15 (0x8000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00008000 */
#define ETH_MACA1LR_ADDRLO_16 (0x10000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00010000 */
#define ETH_MACA1LR_ADDRLO_17 (0x20000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00020000 */
#define ETH_MACA1LR_ADDRLO_18 (0x40000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00040000 */
#define ETH_MACA1LR_ADDRLO_19 (0x80000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00080000 */
#define ETH_MACA1LR_ADDRLO_20 (0x100000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00100000 */
#define ETH_MACA1LR_ADDRLO_21 (0x200000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00200000 */
#define ETH_MACA1LR_ADDRLO_22 (0x400000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00400000 */
#define ETH_MACA1LR_ADDRLO_23 (0x800000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x00800000 */
#define ETH_MACA1LR_ADDRLO_24 (0x1000000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x01000000 */
#define ETH_MACA1LR_ADDRLO_25 (0x2000000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x02000000 */
#define ETH_MACA1LR_ADDRLO_26 (0x4000000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x04000000 */
#define ETH_MACA1LR_ADDRLO_27 (0x8000000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x08000000 */
#define ETH_MACA1LR_ADDRLO_28 (0x10000000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x10000000 */
#define ETH_MACA1LR_ADDRLO_29 (0x20000000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x20000000 */
#define ETH_MACA1LR_ADDRLO_30 (0x40000000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x40000000 */
#define ETH_MACA1LR_ADDRLO_31 (0x80000000U << ETH_MACA1LR_ADDRLO_Pos) /*!< 0x80000000 */
/************** Bit definition for ETH_MACA2HR register **************/
#define ETH_MACA2HR_ADDRHI_Pos (0U)
#define ETH_MACA2HR_ADDRHI_Msk (0xFFFFU << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */
#define ETH_MACA2HR_ADDRHI ETH_MACA2HR_ADDRHI_Msk /*!< MAC Address1 [47:32] */
#define ETH_MACA2HR_ADDRHI_0 (0x1U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00000001 */
#define ETH_MACA2HR_ADDRHI_1 (0x2U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00000002 */
#define ETH_MACA2HR_ADDRHI_2 (0x4U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00000004 */
#define ETH_MACA2HR_ADDRHI_3 (0x8U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00000008 */
#define ETH_MACA2HR_ADDRHI_4 (0x10U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00000010 */
#define ETH_MACA2HR_ADDRHI_5 (0x20U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00000020 */
#define ETH_MACA2HR_ADDRHI_6 (0x40U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00000040 */
#define ETH_MACA2HR_ADDRHI_7 (0x80U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00000080 */
#define ETH_MACA2HR_ADDRHI_8 (0x100U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00000100 */
#define ETH_MACA2HR_ADDRHI_9 (0x200U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00000200 */
#define ETH_MACA2HR_ADDRHI_10 (0x400U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00000400 */
#define ETH_MACA2HR_ADDRHI_11 (0x800U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00000800 */
#define ETH_MACA2HR_ADDRHI_12 (0x1000U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00001000 */
#define ETH_MACA2HR_ADDRHI_13 (0x2000U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00002000 */
#define ETH_MACA2HR_ADDRHI_14 (0x4000U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00004000 */
#define ETH_MACA2HR_ADDRHI_15 (0x8000U << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x00008000 */
#define ETH_MACA2HR_MBC_Pos (24U)
#define ETH_MACA2HR_MBC_Msk (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /*!< Mask Byte Control */
#define ETH_MACA2HR_MBC_0 (0x1U << ETH_MACA2HR_MBC_Pos) /*!< 0x01000000 */
#define ETH_MACA2HR_MBC_1 (0x2U << ETH_MACA2HR_MBC_Pos) /*!< 0x02000000 */
#define ETH_MACA2HR_MBC_2 (0x4U << ETH_MACA2HR_MBC_Pos) /*!< 0x04000000 */
#define ETH_MACA2HR_MBC_3 (0x8U << ETH_MACA2HR_MBC_Pos) /*!< 0x08000000 */
#define ETH_MACA2HR_MBC_4 (0x10U << ETH_MACA2HR_MBC_Pos) /*!< 0x10000000 */
#define ETH_MACA2HR_MBC_5 (0x20U << ETH_MACA2HR_MBC_Pos) /*!< 0x20000000 */
#define ETH_MACA2HR_SA_Pos (30U)
#define ETH_MACA2HR_SA_Msk (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /*!< Source Address */
#define ETH_MACA2HR_AE_Pos (31U)
#define ETH_MACA2HR_AE_Msk (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /*!< Address Enable */
/************** Bit definition for ETH_MACA2LR register **************/
#define ETH_MACA2LR_ADDRLO_Pos (0U)
#define ETH_MACA2LR_ADDRLO_Msk (0xFFFFFFFFU << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACA2LR_ADDRLO ETH_MACA2LR_ADDRLO_Msk /*!< MAC Address x [31:0] (x = 0 to 3) */
#define ETH_MACA2LR_ADDRLO_0 (0x1U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00000001 */
#define ETH_MACA2LR_ADDRLO_1 (0x2U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00000002 */
#define ETH_MACA2LR_ADDRLO_2 (0x4U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00000004 */
#define ETH_MACA2LR_ADDRLO_3 (0x8U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00000008 */
#define ETH_MACA2LR_ADDRLO_4 (0x10U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00000010 */
#define ETH_MACA2LR_ADDRLO_5 (0x20U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00000020 */
#define ETH_MACA2LR_ADDRLO_6 (0x40U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00000040 */
#define ETH_MACA2LR_ADDRLO_7 (0x80U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00000080 */
#define ETH_MACA2LR_ADDRLO_8 (0x100U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00000100 */
#define ETH_MACA2LR_ADDRLO_9 (0x200U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00000200 */
#define ETH_MACA2LR_ADDRLO_10 (0x400U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00000400 */
#define ETH_MACA2LR_ADDRLO_11 (0x800U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00000800 */
#define ETH_MACA2LR_ADDRLO_12 (0x1000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00001000 */
#define ETH_MACA2LR_ADDRLO_13 (0x2000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00002000 */
#define ETH_MACA2LR_ADDRLO_14 (0x4000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00004000 */
#define ETH_MACA2LR_ADDRLO_15 (0x8000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00008000 */
#define ETH_MACA2LR_ADDRLO_16 (0x10000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00010000 */
#define ETH_MACA2LR_ADDRLO_17 (0x20000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00020000 */
#define ETH_MACA2LR_ADDRLO_18 (0x40000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00040000 */
#define ETH_MACA2LR_ADDRLO_19 (0x80000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00080000 */
#define ETH_MACA2LR_ADDRLO_20 (0x100000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00100000 */
#define ETH_MACA2LR_ADDRLO_21 (0x200000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00200000 */
#define ETH_MACA2LR_ADDRLO_22 (0x400000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00400000 */
#define ETH_MACA2LR_ADDRLO_23 (0x800000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x00800000 */
#define ETH_MACA2LR_ADDRLO_24 (0x1000000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x01000000 */
#define ETH_MACA2LR_ADDRLO_25 (0x2000000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x02000000 */
#define ETH_MACA2LR_ADDRLO_26 (0x4000000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x04000000 */
#define ETH_MACA2LR_ADDRLO_27 (0x8000000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x08000000 */
#define ETH_MACA2LR_ADDRLO_28 (0x10000000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x10000000 */
#define ETH_MACA2LR_ADDRLO_29 (0x20000000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x20000000 */
#define ETH_MACA2LR_ADDRLO_30 (0x40000000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x40000000 */
#define ETH_MACA2LR_ADDRLO_31 (0x80000000U << ETH_MACA2LR_ADDRLO_Pos) /*!< 0x80000000 */
/************** Bit definition for ETH_MACA3HR register **************/
#define ETH_MACA3HR_ADDRHI_Pos (0U)
#define ETH_MACA3HR_ADDRHI_Msk (0xFFFFU << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */
#define ETH_MACA3HR_ADDRHI ETH_MACA3HR_ADDRHI_Msk /*!< MAC Address1 [47:32] */
#define ETH_MACA3HR_ADDRHI_0 (0x1U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00000001 */
#define ETH_MACA3HR_ADDRHI_1 (0x2U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00000002 */
#define ETH_MACA3HR_ADDRHI_2 (0x4U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00000004 */
#define ETH_MACA3HR_ADDRHI_3 (0x8U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00000008 */
#define ETH_MACA3HR_ADDRHI_4 (0x10U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00000010 */
#define ETH_MACA3HR_ADDRHI_5 (0x20U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00000020 */
#define ETH_MACA3HR_ADDRHI_6 (0x40U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00000040 */
#define ETH_MACA3HR_ADDRHI_7 (0x80U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00000080 */
#define ETH_MACA3HR_ADDRHI_8 (0x100U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00000100 */
#define ETH_MACA3HR_ADDRHI_9 (0x200U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00000200 */
#define ETH_MACA3HR_ADDRHI_10 (0x400U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00000400 */
#define ETH_MACA3HR_ADDRHI_11 (0x800U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00000800 */
#define ETH_MACA3HR_ADDRHI_12 (0x1000U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00001000 */
#define ETH_MACA3HR_ADDRHI_13 (0x2000U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00002000 */
#define ETH_MACA3HR_ADDRHI_14 (0x4000U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00004000 */
#define ETH_MACA3HR_ADDRHI_15 (0x8000U << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x00008000 */
#define ETH_MACA3HR_MBC_Pos (24U)
#define ETH_MACA3HR_MBC_Msk (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /*!< Mask Byte Control */
#define ETH_MACA3HR_MBC_0 (0x1U << ETH_MACA3HR_MBC_Pos) /*!< 0x01000000 */
#define ETH_MACA3HR_MBC_1 (0x2U << ETH_MACA3HR_MBC_Pos) /*!< 0x02000000 */
#define ETH_MACA3HR_MBC_2 (0x4U << ETH_MACA3HR_MBC_Pos) /*!< 0x04000000 */
#define ETH_MACA3HR_MBC_3 (0x8U << ETH_MACA3HR_MBC_Pos) /*!< 0x08000000 */
#define ETH_MACA3HR_MBC_4 (0x10U << ETH_MACA3HR_MBC_Pos) /*!< 0x10000000 */
#define ETH_MACA3HR_MBC_5 (0x20U << ETH_MACA3HR_MBC_Pos) /*!< 0x20000000 */
#define ETH_MACA3HR_SA_Pos (30U)
#define ETH_MACA3HR_SA_Msk (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /*!< Source Address */
#define ETH_MACA3HR_AE_Pos (31U)
#define ETH_MACA3HR_AE_Msk (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /*!< Address Enable */
/************** Bit definition for ETH_MACA3LR register **************/
#define ETH_MACA3LR_ADDRLO_Pos (0U)
#define ETH_MACA3LR_ADDRLO_Msk (0xFFFFFFFFU << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACA3LR_ADDRLO ETH_MACA3LR_ADDRLO_Msk /*!< MAC Address x [31:0] (x = 0 to 3) */
#define ETH_MACA3LR_ADDRLO_0 (0x1U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00000001 */
#define ETH_MACA3LR_ADDRLO_1 (0x2U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00000002 */
#define ETH_MACA3LR_ADDRLO_2 (0x4U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00000004 */
#define ETH_MACA3LR_ADDRLO_3 (0x8U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00000008 */
#define ETH_MACA3LR_ADDRLO_4 (0x10U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00000010 */
#define ETH_MACA3LR_ADDRLO_5 (0x20U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00000020 */
#define ETH_MACA3LR_ADDRLO_6 (0x40U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00000040 */
#define ETH_MACA3LR_ADDRLO_7 (0x80U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00000080 */
#define ETH_MACA3LR_ADDRLO_8 (0x100U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00000100 */
#define ETH_MACA3LR_ADDRLO_9 (0x200U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00000200 */
#define ETH_MACA3LR_ADDRLO_10 (0x400U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00000400 */
#define ETH_MACA3LR_ADDRLO_11 (0x800U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00000800 */
#define ETH_MACA3LR_ADDRLO_12 (0x1000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00001000 */
#define ETH_MACA3LR_ADDRLO_13 (0x2000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00002000 */
#define ETH_MACA3LR_ADDRLO_14 (0x4000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00004000 */
#define ETH_MACA3LR_ADDRLO_15 (0x8000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00008000 */
#define ETH_MACA3LR_ADDRLO_16 (0x10000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00010000 */
#define ETH_MACA3LR_ADDRLO_17 (0x20000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00020000 */
#define ETH_MACA3LR_ADDRLO_18 (0x40000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00040000 */
#define ETH_MACA3LR_ADDRLO_19 (0x80000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00080000 */
#define ETH_MACA3LR_ADDRLO_20 (0x100000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00100000 */
#define ETH_MACA3LR_ADDRLO_21 (0x200000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00200000 */
#define ETH_MACA3LR_ADDRLO_22 (0x400000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00400000 */
#define ETH_MACA3LR_ADDRLO_23 (0x800000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x00800000 */
#define ETH_MACA3LR_ADDRLO_24 (0x1000000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x01000000 */
#define ETH_MACA3LR_ADDRLO_25 (0x2000000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x02000000 */
#define ETH_MACA3LR_ADDRLO_26 (0x4000000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x04000000 */
#define ETH_MACA3LR_ADDRLO_27 (0x8000000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x08000000 */
#define ETH_MACA3LR_ADDRLO_28 (0x10000000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x10000000 */
#define ETH_MACA3LR_ADDRLO_29 (0x20000000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x20000000 */
#define ETH_MACA3LR_ADDRLO_30 (0x40000000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x40000000 */
#define ETH_MACA3LR_ADDRLO_31 (0x80000000U << ETH_MACA3LR_ADDRLO_Pos) /*!< 0x80000000 */
/************ Bit definition for ETH_MMC_CONTROL register ************/
#define ETH_MMCCR_CNTRST_Pos (0U)
#define ETH_MMCCR_CNTRST_Msk (0x1U << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */
#define ETH_MMCCR_CNTRST ETH_MMCCR_CNTRST_Msk /*!< Counters Reset */
#define ETH_MMCCR_CNTSTOPRO_Pos (1U)
#define ETH_MMCCR_CNTSTOPRO_Msk (0x1U << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */
#define ETH_MMCCR_CNTSTOPRO ETH_MMCCR_CNTSTOPRO_Msk /*!< Counter Stop Rollover */
#define ETH_MMCCR_RSTONRD_Pos (2U)
#define ETH_MMCCR_RSTONRD_Msk (0x1U << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */
#define ETH_MMCCR_RSTONRD ETH_MMCCR_RSTONRD_Msk /*!< Reset on Read */
#define ETH_MMCCR_CNTFREEZ_Pos (3U)
#define ETH_MMCCR_CNTFREEZ_Msk (0x1U << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */
#define ETH_MMCCR_CNTFREEZ ETH_MMCCR_CNTFREEZ_Msk /*!< MMC Counter Freeze */
#define ETH_MMCCR_CNTPRST_Pos (4U)
#define ETH_MMCCR_CNTPRST_Msk (0x1U << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */
#define ETH_MMCCR_CNTPRST ETH_MMCCR_CNTPRST_Msk /*!< Counters Preset */
#define ETH_MMCCR_CNTPRSTLVL_Pos (5U)
#define ETH_MMCCR_CNTPRSTLVL_Msk (0x1U << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */
#define ETH_MMCCR_CNTPRSTLVL ETH_MMCCR_CNTPRSTLVL_Msk /*!< Full-Half Preset */
#define ETH_MMCCR_UCDBC_Pos (8U)
#define ETH_MMCCR_UCDBC_Msk (0x1U << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */
#define ETH_MMCCR_UCDBC ETH_MMCCR_UCDBC_Msk /*!< Update MMC Counters for Dropped Broadcast Packets */
/*********** Bit definition for ETH_MMC_RX_INTERRUPT register ************/
#define ETH_MMCRXIR_RXCRCERPIS_Pos (5U)
#define ETH_MMCRXIR_RXCRCERPIS_Msk (0x1U << ETH_MMCRXIR_RXCRCERPIS_Pos) /*!< 0x00000020 */
#define ETH_MMCRXIR_RXCRCERPIS ETH_MMCRXIR_RXCRCERPIS_Msk /*!< MMC Receive CRC Error Packet Counter Interrupt Status */
#define ETH_MMCRXIR_RXALGNERPIS_Pos (6U)
#define ETH_MMCRXIR_RXALGNERPIS_Msk (0x1U << ETH_MMCRXIR_RXALGNERPIS_Pos) /*!< 0x00000040 */
#define ETH_MMCRXIR_RXALGNERPIS ETH_MMCRXIR_RXALGNERPIS_Msk /*!< MMC Receive Alignment Error Packet Counter Interrupt Status */
#define ETH_MMCRXIR_RXUCGPIS_Pos (17U)
#define ETH_MMCRXIR_RXUCGPIS_Msk (0x1U << ETH_MMCRXIR_RXUCGPIS_Pos) /*!< 0x00020000 */
#define ETH_MMCRXIR_RXUCGPIS ETH_MMCRXIR_RXUCGPIS_Msk /*!< MMC Receive Unicast Good Packet Counter Interrupt Status */
#define ETH_MMCRXIR_RXLPIUSCIS_Pos (26U)
#define ETH_MMCRXIR_RXLPIUSCIS_Msk (0x1U << ETH_MMCRXIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */
#define ETH_MMCRXIR_RXLPIUSCIS ETH_MMCRXIR_RXLPIUSCIS_Msk /*!< MMC Receive LPI microsecond counter interrupt status */
#define ETH_MMCRXIR_RXLPITRCIS_Pos (27U)
#define ETH_MMCRXIR_RXLPITRCIS_Msk (0x1U << ETH_MMCRXIR_RXLPITRCIS_Pos) /*!< 0x08000000 */
#define ETH_MMCRXIR_RXLPITRCIS ETH_MMCRXIR_RXLPITRCIS_Msk /*!< MMC Receive LPI transition counter interrupt status */
/*********** Bit definition for ETH_MMC_TX_INTERRUPT register ************/
#define ETH_MMCTXIR_TXSCOLGPIS_Pos (14U)
#define ETH_MMCTXIR_TXSCOLGPIS_Msk (0x1U << ETH_MMCTXIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */
#define ETH_MMCTXIR_TXSCOLGPIS ETH_MMCTXIR_TXSCOLGPIS_Msk /*!< MMC Transmit Single Collision Good Packet Counter Interrupt Status */
#define ETH_MMCTXIR_TXMCOLGPIS_Pos (15U)
#define ETH_MMCTXIR_TXMCOLGPIS_Msk (0x1U << ETH_MMCTXIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */
#define ETH_MMCTXIR_TXMCOLGPIS ETH_MMCTXIR_TXMCOLGPIS_Msk /*!< MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
#define ETH_MMCTXIR_TXGPKTIS_Pos (21U)
#define ETH_MMCTXIR_TXGPKTIS_Msk (0x1U << ETH_MMCTXIR_TXGPKTIS_Pos) /*!< 0x00200000 */
#define ETH_MMCTXIR_TXGPKTIS ETH_MMCTXIR_TXGPKTIS_Msk /*!< MMC Transmit Good Packet Counter Interrupt Status */
#define ETH_MMCTXIR_TXLPIUSCIS_Pos (26U)
#define ETH_MMCTXIR_TXLPIUSCIS_Msk (0x1U << ETH_MMCTXIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */
#define ETH_MMCTXIR_TXLPIUSCIS ETH_MMCTXIR_TXLPIUSCIS_Msk /*!< MMC Transmit LPI microsecond counter interrupt status */
#define ETH_MMCTXIR_TXLPITRCIS_Pos (27U)
#define ETH_MMCTXIR_TXLPITRCIS_Msk (0x1U << ETH_MMCTXIR_TXLPITRCIS_Pos) /*!< 0x08000000 */
#define ETH_MMCTXIR_TXLPITRCIS ETH_MMCTXIR_TXLPITRCIS_Msk /*!< MMC Transmit LPI transition counter interrupt status */
/********** Bit definition for ETH_MMC_RX_INTERRUPT_MASK register ***********/
#define ETH_MMCRXIMR_RXCRCERPIM_Pos (5U)
#define ETH_MMCRXIMR_RXCRCERPIM_Msk (0x1U << ETH_MMCRXIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */
#define ETH_MMCRXIMR_RXCRCERPIM ETH_MMCRXIMR_RXCRCERPIM_Msk /*!< MMC Receive CRC Error Packet Counter Interrupt Mask */
#define ETH_MMCRXIMR_RXALGNERPIM_Pos (6U)
#define ETH_MMCRXIMR_RXALGNERPIM_Msk (0x1U << ETH_MMCRXIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */
#define ETH_MMCRXIMR_RXALGNERPIM ETH_MMCRXIMR_RXALGNERPIM_Msk /*!< MMC Receive Alignment Error Packet Counter Interrupt Mask */
#define ETH_MMCRXIMR_RXUCGPIM_Pos (17U)
#define ETH_MMCRXIMR_RXUCGPIM_Msk (0x1U << ETH_MMCRXIMR_RXUCGPIM_Pos) /*!< 0x00020000 */
#define ETH_MMCRXIMR_RXUCGPIM ETH_MMCRXIMR_RXUCGPIM_Msk /*!< MMC Receive Unicast Good Packet Counter Interrupt Mask */
#define ETH_MMCRXIMR_RXLPIUSCIM_Pos (26U)
#define ETH_MMCRXIMR_RXLPIUSCIM_Msk (0x1U << ETH_MMCRXIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */
#define ETH_MMCRXIMR_RXLPIUSCIM ETH_MMCRXIMR_RXLPIUSCIM_Msk /*!< MMC Receive LPI microsecond counter interrupt Mask */
#define ETH_MMCRXIMR_RXLPITRCIM_Pos (27U)
#define ETH_MMCRXIMR_RXLPITRCIM_Msk (0x1U << ETH_MMCRXIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */
#define ETH_MMCRXIMR_RXLPITRCIM ETH_MMCRXIMR_RXLPITRCIM_Msk /*!< MMC Receive LPI transition counter interrupt Mask */
/********** Bit definition for ETH_MMC_TX_INTERRUPT_MASK register ***********/
#define ETH_MMCTXIMR_TXSCOLGPIM_Pos (14U)
#define ETH_MMCTXIMR_TXSCOLGPIM_Msk (0x1U << ETH_MMCTXIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */
#define ETH_MMCTXIMR_TXSCOLGPIM ETH_MMCTXIMR_TXSCOLGPIM_Msk /*!< MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
#define ETH_MMCTXIMR_TXMCOLGPIM_Pos (15U)
#define ETH_MMCTXIMR_TXMCOLGPIM_Msk (0x1U << ETH_MMCTXIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */
#define ETH_MMCTXIMR_TXMCOLGPIM ETH_MMCTXIMR_TXMCOLGPIM_Msk /*!< MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
#define ETH_MMCTXIMR_TXGPKTIM_Pos (21U)
#define ETH_MMCTXIMR_TXGPKTIM_Msk (0x1U << ETH_MMCTXIMR_TXGPKTIM_Pos) /*!< 0x00200000 */
#define ETH_MMCTXIMR_TXGPKTIM ETH_MMCTXIMR_TXGPKTIM_Msk /*!< MMC Transmit Good Packet Counter Interrupt Mask */
#define ETH_MMCTXIMR_TXLPIUSCIM_Pos (26U)
#define ETH_MMCTXIMR_TXLPIUSCIM_Msk (0x1U << ETH_MMCTXIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */
#define ETH_MMCTXIMR_TXLPIUSCIM ETH_MMCTXIMR_TXLPIUSCIM_Msk /*!< MMC Transmit LPI microsecond counter interrupt Mask */
#define ETH_MMCTXIMR_TXLPITRCIM_Pos (27U)
#define ETH_MMCTXIMR_TXLPITRCIM_Msk (0x1U << ETH_MMCTXIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */
#define ETH_MMCTXIMR_TXLPITRCIM ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk /*!< MMC Transmit LPI transition counter interrupt Mask */
/*********** Bit definition for ETH_MMC_TX_SINGLE_COLLISION_GOOD_PACKETS register ************/
#define ETH_MMCTXSCGPR_TXSNGLCOLG_Pos (0U)
#define ETH_MMCTXSCGPR_TXSNGLCOLG_Msk (0xFFFFFFFFU << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCTXSCGPR_TXSNGLCOLG ETH_MMCTXSCGPR_TXSNGLCOLG_Msk /*!< Tx Single Collision Good Packets */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_0 (0x1U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00000001 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_1 (0x2U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00000002 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_2 (0x4U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00000004 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_3 (0x8U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00000008 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_4 (0x10U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00000010 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_5 (0x20U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00000020 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_6 (0x40U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00000040 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_7 (0x80U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00000080 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_8 (0x100U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00000100 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_9 (0x200U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00000200 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_10 (0x400U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00000400 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_11 (0x800U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00000800 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_12 (0x1000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00001000 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_13 (0x2000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00002000 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_14 (0x4000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00004000 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_15 (0x8000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00008000 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_16 (0x10000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00010000 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_17 (0x20000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00020000 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_18 (0x40000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00040000 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_19 (0x80000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00080000 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_20 (0x100000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00100000 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_21 (0x200000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00200000 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_22 (0x400000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00400000 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_23 (0x800000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x00800000 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_24 (0x1000000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x01000000 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_25 (0x2000000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x02000000 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_26 (0x4000000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x04000000 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_27 (0x8000000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x08000000 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_28 (0x10000000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x10000000 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_29 (0x20000000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x20000000 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_30 (0x40000000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x40000000 */
#define ETH_MMCTXSCGPR_TXSNGLCOLG_31 (0x80000000U << ETH_MMCTXSCGPR_TXSNGLCOLG_Pos) /*!< 0x80000000 */
/*********** Bit definition for ETH_MMC_TX_MULTIPLE_COLLISION_GOOD_PACKETS register ************/
#define ETH_MMCTXMCGPR_TXMULTCOLG_Pos (0U)
#define ETH_MMCTXMCGPR_TXMULTCOLG_Msk (0xFFFFFFFFU << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCTXMCGPR_TXMULTCOLG ETH_MMCTXMCGPR_TXMULTCOLG_Msk /*!< Tx Multiple Collision Good Packets */
#define ETH_MMCTXMCGPR_TXMULTCOLG_0 (0x1U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00000001 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_1 (0x2U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00000002 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_2 (0x4U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00000004 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_3 (0x8U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00000008 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_4 (0x10U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00000010 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_5 (0x20U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00000020 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_6 (0x40U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00000040 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_7 (0x80U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00000080 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_8 (0x100U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00000100 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_9 (0x200U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00000200 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_10 (0x400U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00000400 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_11 (0x800U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00000800 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_12 (0x1000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00001000 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_13 (0x2000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00002000 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_14 (0x4000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00004000 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_15 (0x8000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00008000 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_16 (0x10000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00010000 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_17 (0x20000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00020000 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_18 (0x40000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00040000 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_19 (0x80000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00080000 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_20 (0x100000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00100000 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_21 (0x200000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00200000 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_22 (0x400000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00400000 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_23 (0x800000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x00800000 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_24 (0x1000000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x01000000 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_25 (0x2000000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x02000000 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_26 (0x4000000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x04000000 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_27 (0x8000000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x08000000 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_28 (0x10000000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x10000000 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_29 (0x20000000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x20000000 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_30 (0x40000000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x40000000 */
#define ETH_MMCTXMCGPR_TXMULTCOLG_31 (0x80000000U << ETH_MMCTXMCGPR_TXMULTCOLG_Pos) /*!< 0x80000000 */
/************ Bit definition for ETH_MMC_TX_PACKET_COUNT_GOOD register *************/
#define ETH_MMCTXPCGR_TXPKTG_Pos (0U)
#define ETH_MMCTXPCGR_TXPKTG_Msk (0xFFFFFFFFU << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCTXPCGR_TXPKTG ETH_MMCTXPCGR_TXPKTG_Msk /*!< Tx Packet Count Good */
#define ETH_MMCTXPCGR_TXPKTG_0 (0x1U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00000001 */
#define ETH_MMCTXPCGR_TXPKTG_1 (0x2U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00000002 */
#define ETH_MMCTXPCGR_TXPKTG_2 (0x4U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00000004 */
#define ETH_MMCTXPCGR_TXPKTG_3 (0x8U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00000008 */
#define ETH_MMCTXPCGR_TXPKTG_4 (0x10U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00000010 */
#define ETH_MMCTXPCGR_TXPKTG_5 (0x20U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00000020 */
#define ETH_MMCTXPCGR_TXPKTG_6 (0x40U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00000040 */
#define ETH_MMCTXPCGR_TXPKTG_7 (0x80U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00000080 */
#define ETH_MMCTXPCGR_TXPKTG_8 (0x100U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00000100 */
#define ETH_MMCTXPCGR_TXPKTG_9 (0x200U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00000200 */
#define ETH_MMCTXPCGR_TXPKTG_10 (0x400U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00000400 */
#define ETH_MMCTXPCGR_TXPKTG_11 (0x800U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00000800 */
#define ETH_MMCTXPCGR_TXPKTG_12 (0x1000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00001000 */
#define ETH_MMCTXPCGR_TXPKTG_13 (0x2000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00002000 */
#define ETH_MMCTXPCGR_TXPKTG_14 (0x4000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00004000 */
#define ETH_MMCTXPCGR_TXPKTG_15 (0x8000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00008000 */
#define ETH_MMCTXPCGR_TXPKTG_16 (0x10000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00010000 */
#define ETH_MMCTXPCGR_TXPKTG_17 (0x20000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00020000 */
#define ETH_MMCTXPCGR_TXPKTG_18 (0x40000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00040000 */
#define ETH_MMCTXPCGR_TXPKTG_19 (0x80000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00080000 */
#define ETH_MMCTXPCGR_TXPKTG_20 (0x100000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00100000 */
#define ETH_MMCTXPCGR_TXPKTG_21 (0x200000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00200000 */
#define ETH_MMCTXPCGR_TXPKTG_22 (0x400000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00400000 */
#define ETH_MMCTXPCGR_TXPKTG_23 (0x800000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x00800000 */
#define ETH_MMCTXPCGR_TXPKTG_24 (0x1000000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x01000000 */
#define ETH_MMCTXPCGR_TXPKTG_25 (0x2000000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x02000000 */
#define ETH_MMCTXPCGR_TXPKTG_26 (0x4000000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x04000000 */
#define ETH_MMCTXPCGR_TXPKTG_27 (0x8000000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x08000000 */
#define ETH_MMCTXPCGR_TXPKTG_28 (0x10000000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x10000000 */
#define ETH_MMCTXPCGR_TXPKTG_29 (0x20000000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x20000000 */
#define ETH_MMCTXPCGR_TXPKTG_30 (0x40000000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x40000000 */
#define ETH_MMCTXPCGR_TXPKTG_31 (0x80000000U << ETH_MMCTXPCGR_TXPKTG_Pos) /*!< 0x80000000 */
/*********** Bit definition for ETH_MMC_RX_CRC_ERROR_PACKETS register ***********/
#define ETH_MMCRXCRCEPR_RXCRCERR_Pos (0U)
#define ETH_MMCRXCRCEPR_RXCRCERR_Msk (0xFFFFFFFFU << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCRXCRCEPR_RXCRCERR ETH_MMCRXCRCEPR_RXCRCERR_Msk /*!< Rx CRC Error Packets */
#define ETH_MMCRXCRCEPR_RXCRCERR_0 (0x1U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00000001 */
#define ETH_MMCRXCRCEPR_RXCRCERR_1 (0x2U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00000002 */
#define ETH_MMCRXCRCEPR_RXCRCERR_2 (0x4U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00000004 */
#define ETH_MMCRXCRCEPR_RXCRCERR_3 (0x8U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00000008 */
#define ETH_MMCRXCRCEPR_RXCRCERR_4 (0x10U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00000010 */
#define ETH_MMCRXCRCEPR_RXCRCERR_5 (0x20U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00000020 */
#define ETH_MMCRXCRCEPR_RXCRCERR_6 (0x40U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00000040 */
#define ETH_MMCRXCRCEPR_RXCRCERR_7 (0x80U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00000080 */
#define ETH_MMCRXCRCEPR_RXCRCERR_8 (0x100U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00000100 */
#define ETH_MMCRXCRCEPR_RXCRCERR_9 (0x200U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00000200 */
#define ETH_MMCRXCRCEPR_RXCRCERR_10 (0x400U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00000400 */
#define ETH_MMCRXCRCEPR_RXCRCERR_11 (0x800U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00000800 */
#define ETH_MMCRXCRCEPR_RXCRCERR_12 (0x1000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00001000 */
#define ETH_MMCRXCRCEPR_RXCRCERR_13 (0x2000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00002000 */
#define ETH_MMCRXCRCEPR_RXCRCERR_14 (0x4000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00004000 */
#define ETH_MMCRXCRCEPR_RXCRCERR_15 (0x8000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00008000 */
#define ETH_MMCRXCRCEPR_RXCRCERR_16 (0x10000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00010000 */
#define ETH_MMCRXCRCEPR_RXCRCERR_17 (0x20000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00020000 */
#define ETH_MMCRXCRCEPR_RXCRCERR_18 (0x40000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00040000 */
#define ETH_MMCRXCRCEPR_RXCRCERR_19 (0x80000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00080000 */
#define ETH_MMCRXCRCEPR_RXCRCERR_20 (0x100000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00100000 */
#define ETH_MMCRXCRCEPR_RXCRCERR_21 (0x200000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00200000 */
#define ETH_MMCRXCRCEPR_RXCRCERR_22 (0x400000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00400000 */
#define ETH_MMCRXCRCEPR_RXCRCERR_23 (0x800000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x00800000 */
#define ETH_MMCRXCRCEPR_RXCRCERR_24 (0x1000000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x01000000 */
#define ETH_MMCRXCRCEPR_RXCRCERR_25 (0x2000000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x02000000 */
#define ETH_MMCRXCRCEPR_RXCRCERR_26 (0x4000000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x04000000 */
#define ETH_MMCRXCRCEPR_RXCRCERR_27 (0x8000000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x08000000 */
#define ETH_MMCRXCRCEPR_RXCRCERR_28 (0x10000000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x10000000 */
#define ETH_MMCRXCRCEPR_RXCRCERR_29 (0x20000000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x20000000 */
#define ETH_MMCRXCRCEPR_RXCRCERR_30 (0x40000000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x40000000 */
#define ETH_MMCRXCRCEPR_RXCRCERR_31 (0x80000000U << ETH_MMCRXCRCEPR_RXCRCERR_Pos) /*!< 0x80000000 */
/*********** Bit definition for ETH_MMC_RX_ALIGNMENT_ERROR_PACKETS register ***********/
#define ETH_MMCRXAEPR_RXALGNERR_Pos (0U)
#define ETH_MMCRXAEPR_RXALGNERR_Msk (0xFFFFFFFFU << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCRXAEPR_RXALGNERR ETH_MMCRXAEPR_RXALGNERR_Msk /*!< Rx Alignment Error Packets */
#define ETH_MMCRXAEPR_RXALGNERR_0 (0x1U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00000001 */
#define ETH_MMCRXAEPR_RXALGNERR_1 (0x2U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00000002 */
#define ETH_MMCRXAEPR_RXALGNERR_2 (0x4U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00000004 */
#define ETH_MMCRXAEPR_RXALGNERR_3 (0x8U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00000008 */
#define ETH_MMCRXAEPR_RXALGNERR_4 (0x10U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00000010 */
#define ETH_MMCRXAEPR_RXALGNERR_5 (0x20U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00000020 */
#define ETH_MMCRXAEPR_RXALGNERR_6 (0x40U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00000040 */
#define ETH_MMCRXAEPR_RXALGNERR_7 (0x80U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00000080 */
#define ETH_MMCRXAEPR_RXALGNERR_8 (0x100U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00000100 */
#define ETH_MMCRXAEPR_RXALGNERR_9 (0x200U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00000200 */
#define ETH_MMCRXAEPR_RXALGNERR_10 (0x400U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00000400 */
#define ETH_MMCRXAEPR_RXALGNERR_11 (0x800U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00000800 */
#define ETH_MMCRXAEPR_RXALGNERR_12 (0x1000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00001000 */
#define ETH_MMCRXAEPR_RXALGNERR_13 (0x2000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00002000 */
#define ETH_MMCRXAEPR_RXALGNERR_14 (0x4000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00004000 */
#define ETH_MMCRXAEPR_RXALGNERR_15 (0x8000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00008000 */
#define ETH_MMCRXAEPR_RXALGNERR_16 (0x10000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00010000 */
#define ETH_MMCRXAEPR_RXALGNERR_17 (0x20000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00020000 */
#define ETH_MMCRXAEPR_RXALGNERR_18 (0x40000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00040000 */
#define ETH_MMCRXAEPR_RXALGNERR_19 (0x80000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00080000 */
#define ETH_MMCRXAEPR_RXALGNERR_20 (0x100000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00100000 */
#define ETH_MMCRXAEPR_RXALGNERR_21 (0x200000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00200000 */
#define ETH_MMCRXAEPR_RXALGNERR_22 (0x400000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00400000 */
#define ETH_MMCRXAEPR_RXALGNERR_23 (0x800000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x00800000 */
#define ETH_MMCRXAEPR_RXALGNERR_24 (0x1000000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x01000000 */
#define ETH_MMCRXAEPR_RXALGNERR_25 (0x2000000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x02000000 */
#define ETH_MMCRXAEPR_RXALGNERR_26 (0x4000000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x04000000 */
#define ETH_MMCRXAEPR_RXALGNERR_27 (0x8000000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x08000000 */
#define ETH_MMCRXAEPR_RXALGNERR_28 (0x10000000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x10000000 */
#define ETH_MMCRXAEPR_RXALGNERR_29 (0x20000000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x20000000 */
#define ETH_MMCRXAEPR_RXALGNERR_30 (0x40000000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x40000000 */
#define ETH_MMCRXAEPR_RXALGNERR_31 (0x80000000U << ETH_MMCRXAEPR_RXALGNERR_Pos) /*!< 0x80000000 */
/*********** Bit definition for ETH_MMC_RX_UNICAST_PACKETS_GOOD register ************/
#define ETH_MMCRXUPGR_RXUCASTG_Pos (0U)
#define ETH_MMCRXUPGR_RXUCASTG_Msk (0xFFFFFFFFU << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCRXUPGR_RXUCASTG ETH_MMCRXUPGR_RXUCASTG_Msk /*!< Rx Unicast Packets Good */
#define ETH_MMCRXUPGR_RXUCASTG_0 (0x1U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00000001 */
#define ETH_MMCRXUPGR_RXUCASTG_1 (0x2U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00000002 */
#define ETH_MMCRXUPGR_RXUCASTG_2 (0x4U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00000004 */
#define ETH_MMCRXUPGR_RXUCASTG_3 (0x8U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00000008 */
#define ETH_MMCRXUPGR_RXUCASTG_4 (0x10U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00000010 */
#define ETH_MMCRXUPGR_RXUCASTG_5 (0x20U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00000020 */
#define ETH_MMCRXUPGR_RXUCASTG_6 (0x40U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00000040 */
#define ETH_MMCRXUPGR_RXUCASTG_7 (0x80U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00000080 */
#define ETH_MMCRXUPGR_RXUCASTG_8 (0x100U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00000100 */
#define ETH_MMCRXUPGR_RXUCASTG_9 (0x200U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00000200 */
#define ETH_MMCRXUPGR_RXUCASTG_10 (0x400U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00000400 */
#define ETH_MMCRXUPGR_RXUCASTG_11 (0x800U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00000800 */
#define ETH_MMCRXUPGR_RXUCASTG_12 (0x1000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00001000 */
#define ETH_MMCRXUPGR_RXUCASTG_13 (0x2000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00002000 */
#define ETH_MMCRXUPGR_RXUCASTG_14 (0x4000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00004000 */
#define ETH_MMCRXUPGR_RXUCASTG_15 (0x8000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00008000 */
#define ETH_MMCRXUPGR_RXUCASTG_16 (0x10000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00010000 */
#define ETH_MMCRXUPGR_RXUCASTG_17 (0x20000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00020000 */
#define ETH_MMCRXUPGR_RXUCASTG_18 (0x40000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00040000 */
#define ETH_MMCRXUPGR_RXUCASTG_19 (0x80000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00080000 */
#define ETH_MMCRXUPGR_RXUCASTG_20 (0x100000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00100000 */
#define ETH_MMCRXUPGR_RXUCASTG_21 (0x200000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00200000 */
#define ETH_MMCRXUPGR_RXUCASTG_22 (0x400000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00400000 */
#define ETH_MMCRXUPGR_RXUCASTG_23 (0x800000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x00800000 */
#define ETH_MMCRXUPGR_RXUCASTG_24 (0x1000000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x01000000 */
#define ETH_MMCRXUPGR_RXUCASTG_25 (0x2000000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x02000000 */
#define ETH_MMCRXUPGR_RXUCASTG_26 (0x4000000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x04000000 */
#define ETH_MMCRXUPGR_RXUCASTG_27 (0x8000000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x08000000 */
#define ETH_MMCRXUPGR_RXUCASTG_28 (0x10000000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x10000000 */
#define ETH_MMCRXUPGR_RXUCASTG_29 (0x20000000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x20000000 */
#define ETH_MMCRXUPGR_RXUCASTG_30 (0x40000000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x40000000 */
#define ETH_MMCRXUPGR_RXUCASTG_31 (0x80000000U << ETH_MMCRXUPGR_RXUCASTG_Pos) /*!< 0x80000000 */
/************* Bit definition for ETH_MMC_TX_LPI_USEC_CNTR register *************/
#define ETH_MMCTXLPIMSTR_TXLPIUSC_Pos (0U)
#define ETH_MMCTXLPIMSTR_TXLPIUSC_Msk (0xFFFFFFFFU << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCTXLPIMSTR_TXLPIUSC ETH_MMCTXLPIMSTR_TXLPIUSC_Msk /*!< Tx LPI Microseconds Counter */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_0 (0x1U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00000001 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_1 (0x2U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00000002 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_2 (0x4U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00000004 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_3 (0x8U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00000008 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_4 (0x10U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00000010 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_5 (0x20U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00000020 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_6 (0x40U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00000040 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_7 (0x80U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00000080 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_8 (0x100U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00000100 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_9 (0x200U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00000200 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_10 (0x400U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00000400 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_11 (0x800U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00000800 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_12 (0x1000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00001000 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_13 (0x2000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00002000 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_14 (0x4000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00004000 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_15 (0x8000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00008000 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_16 (0x10000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00010000 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_17 (0x20000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00020000 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_18 (0x40000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00040000 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_19 (0x80000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00080000 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_20 (0x100000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00100000 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_21 (0x200000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00200000 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_22 (0x400000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00400000 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_23 (0x800000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x00800000 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_24 (0x1000000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x01000000 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_25 (0x2000000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x02000000 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_26 (0x4000000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x04000000 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_27 (0x8000000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x08000000 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_28 (0x10000000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x10000000 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_29 (0x20000000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x20000000 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_30 (0x40000000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x40000000 */
#define ETH_MMCTXLPIMSTR_TXLPIUSC_31 (0x80000000U << ETH_MMCTXLPIMSTR_TXLPIUSC_Pos) /*!< 0x80000000 */
/************* Bit definition for ETH_MMC_TX_LPI_TRAN_CNTR register *************/
#define ETH_MMCTXLPITCR_TXLPITRC_Pos (0U)
#define ETH_MMCTXLPITCR_TXLPITRC_Msk (0xFFFFFFFFU << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCTXLPITCR_TXLPITRC ETH_MMCTXLPITCR_TXLPITRC_Msk /*!< Tx LPI Transition counter */
#define ETH_MMCTXLPITCR_TXLPITRC_0 (0x1U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00000001 */
#define ETH_MMCTXLPITCR_TXLPITRC_1 (0x2U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00000002 */
#define ETH_MMCTXLPITCR_TXLPITRC_2 (0x4U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00000004 */
#define ETH_MMCTXLPITCR_TXLPITRC_3 (0x8U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00000008 */
#define ETH_MMCTXLPITCR_TXLPITRC_4 (0x10U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00000010 */
#define ETH_MMCTXLPITCR_TXLPITRC_5 (0x20U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00000020 */
#define ETH_MMCTXLPITCR_TXLPITRC_6 (0x40U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00000040 */
#define ETH_MMCTXLPITCR_TXLPITRC_7 (0x80U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00000080 */
#define ETH_MMCTXLPITCR_TXLPITRC_8 (0x100U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00000100 */
#define ETH_MMCTXLPITCR_TXLPITRC_9 (0x200U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00000200 */
#define ETH_MMCTXLPITCR_TXLPITRC_10 (0x400U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00000400 */
#define ETH_MMCTXLPITCR_TXLPITRC_11 (0x800U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00000800 */
#define ETH_MMCTXLPITCR_TXLPITRC_12 (0x1000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00001000 */
#define ETH_MMCTXLPITCR_TXLPITRC_13 (0x2000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00002000 */
#define ETH_MMCTXLPITCR_TXLPITRC_14 (0x4000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00004000 */
#define ETH_MMCTXLPITCR_TXLPITRC_15 (0x8000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00008000 */
#define ETH_MMCTXLPITCR_TXLPITRC_16 (0x10000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00010000 */
#define ETH_MMCTXLPITCR_TXLPITRC_17 (0x20000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00020000 */
#define ETH_MMCTXLPITCR_TXLPITRC_18 (0x40000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00040000 */
#define ETH_MMCTXLPITCR_TXLPITRC_19 (0x80000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00080000 */
#define ETH_MMCTXLPITCR_TXLPITRC_20 (0x100000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00100000 */
#define ETH_MMCTXLPITCR_TXLPITRC_21 (0x200000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00200000 */
#define ETH_MMCTXLPITCR_TXLPITRC_22 (0x400000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00400000 */
#define ETH_MMCTXLPITCR_TXLPITRC_23 (0x800000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x00800000 */
#define ETH_MMCTXLPITCR_TXLPITRC_24 (0x1000000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x01000000 */
#define ETH_MMCTXLPITCR_TXLPITRC_25 (0x2000000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x02000000 */
#define ETH_MMCTXLPITCR_TXLPITRC_26 (0x4000000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x04000000 */
#define ETH_MMCTXLPITCR_TXLPITRC_27 (0x8000000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x08000000 */
#define ETH_MMCTXLPITCR_TXLPITRC_28 (0x10000000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x10000000 */
#define ETH_MMCTXLPITCR_TXLPITRC_29 (0x20000000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x20000000 */
#define ETH_MMCTXLPITCR_TXLPITRC_30 (0x40000000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x40000000 */
#define ETH_MMCTXLPITCR_TXLPITRC_31 (0x80000000U << ETH_MMCTXLPITCR_TXLPITRC_Pos) /*!< 0x80000000 */
/************* Bit definition for ETH_MMC_RX_LPI_USEC_CNTR register *************/
#define ETH_MMCRXLPIMSTR_RXLPIUSC_Pos (0U)
#define ETH_MMCRXLPIMSTR_RXLPIUSC_Msk (0xFFFFFFFFU << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCRXLPIMSTR_RXLPIUSC ETH_MMCRXLPIMSTR_RXLPIUSC_Msk /*!< Rx LPI Microseconds Counter */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_0 (0x1U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00000001 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_1 (0x2U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00000002 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_2 (0x4U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00000004 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_3 (0x8U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00000008 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_4 (0x10U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00000010 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_5 (0x20U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00000020 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_6 (0x40U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00000040 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_7 (0x80U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00000080 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_8 (0x100U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00000100 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_9 (0x200U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00000200 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_10 (0x400U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00000400 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_11 (0x800U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00000800 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_12 (0x1000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00001000 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_13 (0x2000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00002000 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_14 (0x4000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00004000 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_15 (0x8000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00008000 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_16 (0x10000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00010000 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_17 (0x20000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00020000 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_18 (0x40000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00040000 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_19 (0x80000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00080000 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_20 (0x100000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00100000 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_21 (0x200000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00200000 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_22 (0x400000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00400000 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_23 (0x800000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x00800000 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_24 (0x1000000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x01000000 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_25 (0x2000000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x02000000 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_26 (0x4000000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x04000000 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_27 (0x8000000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x08000000 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_28 (0x10000000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x10000000 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_29 (0x20000000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x20000000 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_30 (0x40000000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x40000000 */
#define ETH_MMCRXLPIMSTR_RXLPIUSC_31 (0x80000000U << ETH_MMCRXLPIMSTR_RXLPIUSC_Pos) /*!< 0x80000000 */
/************* Bit definition for ETH_MMC_RX_LPI_TRAN_CNTR register *************/
#define ETH_MMCRXLPITCR_RXLPITRC_Pos (0U)
#define ETH_MMCRXLPITCR_RXLPITRC_Msk (0xFFFFFFFFU << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCRXLPITCR_RXLPITRC ETH_MMCRXLPITCR_RXLPITRC_Msk /*!< Rx LPI Transition counter */
#define ETH_MMCRXLPITCR_RXLPITRC_0 (0x1U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00000001 */
#define ETH_MMCRXLPITCR_RXLPITRC_1 (0x2U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00000002 */
#define ETH_MMCRXLPITCR_RXLPITRC_2 (0x4U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00000004 */
#define ETH_MMCRXLPITCR_RXLPITRC_3 (0x8U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00000008 */
#define ETH_MMCRXLPITCR_RXLPITRC_4 (0x10U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00000010 */
#define ETH_MMCRXLPITCR_RXLPITRC_5 (0x20U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00000020 */
#define ETH_MMCRXLPITCR_RXLPITRC_6 (0x40U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00000040 */
#define ETH_MMCRXLPITCR_RXLPITRC_7 (0x80U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00000080 */
#define ETH_MMCRXLPITCR_RXLPITRC_8 (0x100U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00000100 */
#define ETH_MMCRXLPITCR_RXLPITRC_9 (0x200U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00000200 */
#define ETH_MMCRXLPITCR_RXLPITRC_10 (0x400U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00000400 */
#define ETH_MMCRXLPITCR_RXLPITRC_11 (0x800U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00000800 */
#define ETH_MMCRXLPITCR_RXLPITRC_12 (0x1000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00001000 */
#define ETH_MMCRXLPITCR_RXLPITRC_13 (0x2000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00002000 */
#define ETH_MMCRXLPITCR_RXLPITRC_14 (0x4000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00004000 */
#define ETH_MMCRXLPITCR_RXLPITRC_15 (0x8000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00008000 */
#define ETH_MMCRXLPITCR_RXLPITRC_16 (0x10000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00010000 */
#define ETH_MMCRXLPITCR_RXLPITRC_17 (0x20000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00020000 */
#define ETH_MMCRXLPITCR_RXLPITRC_18 (0x40000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00040000 */
#define ETH_MMCRXLPITCR_RXLPITRC_19 (0x80000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00080000 */
#define ETH_MMCRXLPITCR_RXLPITRC_20 (0x100000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00100000 */
#define ETH_MMCRXLPITCR_RXLPITRC_21 (0x200000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00200000 */
#define ETH_MMCRXLPITCR_RXLPITRC_22 (0x400000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00400000 */
#define ETH_MMCRXLPITCR_RXLPITRC_23 (0x800000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x00800000 */
#define ETH_MMCRXLPITCR_RXLPITRC_24 (0x1000000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x01000000 */
#define ETH_MMCRXLPITCR_RXLPITRC_25 (0x2000000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x02000000 */
#define ETH_MMCRXLPITCR_RXLPITRC_26 (0x4000000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x04000000 */
#define ETH_MMCRXLPITCR_RXLPITRC_27 (0x8000000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x08000000 */
#define ETH_MMCRXLPITCR_RXLPITRC_28 (0x10000000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x10000000 */
#define ETH_MMCRXLPITCR_RXLPITRC_29 (0x20000000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x20000000 */
#define ETH_MMCRXLPITCR_RXLPITRC_30 (0x40000000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x40000000 */
#define ETH_MMCRXLPITCR_RXLPITRC_31 (0x80000000U << ETH_MMCRXLPITCR_RXLPITRC_Pos) /*!< 0x80000000 */
/************ Bit definition for ETH_MACL3L4C0R register *************/
#define ETH_MACL3L4C0R_L3PEN0_Pos (0U)
#define ETH_MACL3L4C0R_L3PEN0_Msk (0x1U << ETH_MACL3L4C0R_L3PEN0_Pos) /*!< 0x00000001 */
#define ETH_MACL3L4C0R_L3PEN0 ETH_MACL3L4C0R_L3PEN0_Msk /*!< Layer 3 Protocol Enable */
#define ETH_MACL3L4C0R_L3SAM0_Pos (2U)
#define ETH_MACL3L4C0R_L3SAM0_Msk (0x1U << ETH_MACL3L4C0R_L3SAM0_Pos) /*!< 0x00000004 */
#define ETH_MACL3L4C0R_L3SAM0 ETH_MACL3L4C0R_L3SAM0_Msk /*!< Layer 3 IP SA Match Enable */
#define ETH_MACL3L4C0R_L3SAIM0_Pos (3U)
#define ETH_MACL3L4C0R_L3SAIM0_Msk (0x1U << ETH_MACL3L4C0R_L3SAIM0_Pos) /*!< 0x00000008 */
#define ETH_MACL3L4C0R_L3SAIM0 ETH_MACL3L4C0R_L3SAIM0_Msk /*!< Layer 3 IP SA Inverse Match Enable */
#define ETH_MACL3L4C0R_L3DAM0_Pos (4U)
#define ETH_MACL3L4C0R_L3DAM0_Msk (0x1U << ETH_MACL3L4C0R_L3DAM0_Pos) /*!< 0x00000010 */
#define ETH_MACL3L4C0R_L3DAM0 ETH_MACL3L4C0R_L3DAM0_Msk /*!< Layer 3 IP DA Match Enable */
#define ETH_MACL3L4C0R_L3DAIM0_Pos (5U)
#define ETH_MACL3L4C0R_L3DAIM0_Msk (0x1U << ETH_MACL3L4C0R_L3DAIM0_Pos) /*!< 0x00000020 */
#define ETH_MACL3L4C0R_L3DAIM0 ETH_MACL3L4C0R_L3DAIM0_Msk /*!< Layer 3 IP DA Inverse Match Enable */
#define ETH_MACL3L4C0R_L3HSBM0_Pos (6U)
#define ETH_MACL3L4C0R_L3HSBM0_Msk (0x1FU << ETH_MACL3L4C0R_L3HSBM0_Pos) /*!< 0x000007C0 */
#define ETH_MACL3L4C0R_L3HSBM0 ETH_MACL3L4C0R_L3HSBM0_Msk /*!< Layer 3 IP SA Higher Bits Match */
#define ETH_MACL3L4C0R_L3HSBM0_0 (0x1U << ETH_MACL3L4C0R_L3HSBM0_Pos) /*!< 0x00000040 */
#define ETH_MACL3L4C0R_L3HSBM0_1 (0x2U << ETH_MACL3L4C0R_L3HSBM0_Pos) /*!< 0x00000080 */
#define ETH_MACL3L4C0R_L3HSBM0_2 (0x4U << ETH_MACL3L4C0R_L3HSBM0_Pos) /*!< 0x00000100 */
#define ETH_MACL3L4C0R_L3HSBM0_3 (0x8U << ETH_MACL3L4C0R_L3HSBM0_Pos) /*!< 0x00000200 */
#define ETH_MACL3L4C0R_L3HSBM0_4 (0x10U << ETH_MACL3L4C0R_L3HSBM0_Pos) /*!< 0x00000400 */
#define ETH_MACL3L4C0R_L3HDBM0_Pos (11U)
#define ETH_MACL3L4C0R_L3HDBM0_Msk (0x1FU << ETH_MACL3L4C0R_L3HDBM0_Pos) /*!< 0x0000F800 */
#define ETH_MACL3L4C0R_L3HDBM0 ETH_MACL3L4C0R_L3HDBM0_Msk /*!< Layer 3 IP DA Higher Bits Match */
#define ETH_MACL3L4C0R_L3HDBM0_0 (0x1U << ETH_MACL3L4C0R_L3HDBM0_Pos) /*!< 0x00000800 */
#define ETH_MACL3L4C0R_L3HDBM0_1 (0x2U << ETH_MACL3L4C0R_L3HDBM0_Pos) /*!< 0x00001000 */
#define ETH_MACL3L4C0R_L3HDBM0_2 (0x4U << ETH_MACL3L4C0R_L3HDBM0_Pos) /*!< 0x00002000 */
#define ETH_MACL3L4C0R_L3HDBM0_3 (0x8U << ETH_MACL3L4C0R_L3HDBM0_Pos) /*!< 0x00004000 */
#define ETH_MACL3L4C0R_L3HDBM0_4 (0x10U << ETH_MACL3L4C0R_L3HDBM0_Pos) /*!< 0x00008000 */
#define ETH_MACL3L4C0R_L4PEN0_Pos (16U)
#define ETH_MACL3L4C0R_L4PEN0_Msk (0x1U << ETH_MACL3L4C0R_L4PEN0_Pos) /*!< 0x00010000 */
#define ETH_MACL3L4C0R_L4PEN0 ETH_MACL3L4C0R_L4PEN0_Msk /*!< Layer 4 Protocol Enable */
#define ETH_MACL3L4C0R_L4SPM0_Pos (18U)
#define ETH_MACL3L4C0R_L4SPM0_Msk (0x1U << ETH_MACL3L4C0R_L4SPM0_Pos) /*!< 0x00040000 */
#define ETH_MACL3L4C0R_L4SPM0 ETH_MACL3L4C0R_L4SPM0_Msk /*!< Layer 4 Source Port Match Enable */
#define ETH_MACL3L4C0R_L4SPIM0_Pos (19U)
#define ETH_MACL3L4C0R_L4SPIM0_Msk (0x1U << ETH_MACL3L4C0R_L4SPIM0_Pos) /*!< 0x00080000 */
#define ETH_MACL3L4C0R_L4SPIM0 ETH_MACL3L4C0R_L4SPIM0_Msk /*!< Layer 4 Source Port Inverse Match Enable */
#define ETH_MACL3L4C0R_L4DPM0_Pos (20U)
#define ETH_MACL3L4C0R_L4DPM0_Msk (0x1U << ETH_MACL3L4C0R_L4DPM0_Pos) /*!< 0x00100000 */
#define ETH_MACL3L4C0R_L4DPM0 ETH_MACL3L4C0R_L4DPM0_Msk /*!< Layer 4 Destination Port Match Enable */
#define ETH_MACL3L4C0R_L4DPIM0_Pos (21U)
#define ETH_MACL3L4C0R_L4DPIM0_Msk (0x1U << ETH_MACL3L4C0R_L4DPIM0_Pos) /*!< 0x00200000 */
#define ETH_MACL3L4C0R_L4DPIM0 ETH_MACL3L4C0R_L4DPIM0_Msk /*!< Layer 4 Destination Port Inverse Match Enable */
/************* Bit definition for ETH_MACL4A0R register **************/
#define ETH_MACL4A0R_L4SP0_Pos (0U)
#define ETH_MACL4A0R_L4SP0_Msk (0xFFFFU << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x0000FFFF */
#define ETH_MACL4A0R_L4SP0 ETH_MACL4A0R_L4SP0_Msk /*!< Layer 4 Source Port Number Field */
#define ETH_MACL4A0R_L4SP0_0 (0x1U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00000001 */
#define ETH_MACL4A0R_L4SP0_1 (0x2U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00000002 */
#define ETH_MACL4A0R_L4SP0_2 (0x4U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00000004 */
#define ETH_MACL4A0R_L4SP0_3 (0x8U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00000008 */
#define ETH_MACL4A0R_L4SP0_4 (0x10U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00000010 */
#define ETH_MACL4A0R_L4SP0_5 (0x20U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00000020 */
#define ETH_MACL4A0R_L4SP0_6 (0x40U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00000040 */
#define ETH_MACL4A0R_L4SP0_7 (0x80U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00000080 */
#define ETH_MACL4A0R_L4SP0_8 (0x100U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00000100 */
#define ETH_MACL4A0R_L4SP0_9 (0x200U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00000200 */
#define ETH_MACL4A0R_L4SP0_10 (0x400U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00000400 */
#define ETH_MACL4A0R_L4SP0_11 (0x800U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00000800 */
#define ETH_MACL4A0R_L4SP0_12 (0x1000U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00001000 */
#define ETH_MACL4A0R_L4SP0_13 (0x2000U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00002000 */
#define ETH_MACL4A0R_L4SP0_14 (0x4000U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00004000 */
#define ETH_MACL4A0R_L4SP0_15 (0x8000U << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x00008000 */
#define ETH_MACL4A0R_L4DP0_Pos (16U)
#define ETH_MACL4A0R_L4DP0_Msk (0xFFFFU << ETH_MACL4A0R_L4DP0_Pos) /*!< 0xFFFF0000 */
#define ETH_MACL4A0R_L4DP0 ETH_MACL4A0R_L4DP0_Msk /*!< Layer 4 Destination Port Number Field */
#define ETH_MACL4A0R_L4DP0_0 (0x1U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x00010000 */
#define ETH_MACL4A0R_L4DP0_1 (0x2U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x00020000 */
#define ETH_MACL4A0R_L4DP0_2 (0x4U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x00040000 */
#define ETH_MACL4A0R_L4DP0_3 (0x8U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x00080000 */
#define ETH_MACL4A0R_L4DP0_4 (0x10U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x00100000 */
#define ETH_MACL4A0R_L4DP0_5 (0x20U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x00200000 */
#define ETH_MACL4A0R_L4DP0_6 (0x40U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x00400000 */
#define ETH_MACL4A0R_L4DP0_7 (0x80U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x00800000 */
#define ETH_MACL4A0R_L4DP0_8 (0x100U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x01000000 */
#define ETH_MACL4A0R_L4DP0_9 (0x200U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x02000000 */
#define ETH_MACL4A0R_L4DP0_10 (0x400U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x04000000 */
#define ETH_MACL4A0R_L4DP0_11 (0x800U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x08000000 */
#define ETH_MACL4A0R_L4DP0_12 (0x1000U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x10000000 */
#define ETH_MACL4A0R_L4DP0_13 (0x2000U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x20000000 */
#define ETH_MACL4A0R_L4DP0_14 (0x4000U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x40000000 */
#define ETH_MACL4A0R_L4DP0_15 (0x8000U << ETH_MACL4A0R_L4DP0_Pos) /*!< 0x80000000 */
/************* Bit definition for ETH_MACL3A00R register *************/
#define ETH_MACL3A00R_L3A00_Pos (0U)
#define ETH_MACL3A00R_L3A00_Msk (0xFFFFFFFFU << ETH_MACL3A00R_L3A00_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACL3A00R_L3A00 ETH_MACL3A00R_L3A00_Msk /*!< Layer 3 Address 0 Field */
#define ETH_MACL3A00R_L3A00_0 (0x1U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00000001 */
#define ETH_MACL3A00R_L3A00_1 (0x2U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00000002 */
#define ETH_MACL3A00R_L3A00_2 (0x4U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00000004 */
#define ETH_MACL3A00R_L3A00_3 (0x8U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00000008 */
#define ETH_MACL3A00R_L3A00_4 (0x10U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00000010 */
#define ETH_MACL3A00R_L3A00_5 (0x20U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00000020 */
#define ETH_MACL3A00R_L3A00_6 (0x40U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00000040 */
#define ETH_MACL3A00R_L3A00_7 (0x80U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00000080 */
#define ETH_MACL3A00R_L3A00_8 (0x100U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00000100 */
#define ETH_MACL3A00R_L3A00_9 (0x200U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00000200 */
#define ETH_MACL3A00R_L3A00_10 (0x400U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00000400 */
#define ETH_MACL3A00R_L3A00_11 (0x800U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00000800 */
#define ETH_MACL3A00R_L3A00_12 (0x1000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00001000 */
#define ETH_MACL3A00R_L3A00_13 (0x2000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00002000 */
#define ETH_MACL3A00R_L3A00_14 (0x4000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00004000 */
#define ETH_MACL3A00R_L3A00_15 (0x8000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00008000 */
#define ETH_MACL3A00R_L3A00_16 (0x10000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00010000 */
#define ETH_MACL3A00R_L3A00_17 (0x20000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00020000 */
#define ETH_MACL3A00R_L3A00_18 (0x40000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00040000 */
#define ETH_MACL3A00R_L3A00_19 (0x80000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00080000 */
#define ETH_MACL3A00R_L3A00_20 (0x100000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00100000 */
#define ETH_MACL3A00R_L3A00_21 (0x200000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00200000 */
#define ETH_MACL3A00R_L3A00_22 (0x400000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00400000 */
#define ETH_MACL3A00R_L3A00_23 (0x800000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x00800000 */
#define ETH_MACL3A00R_L3A00_24 (0x1000000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x01000000 */
#define ETH_MACL3A00R_L3A00_25 (0x2000000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x02000000 */
#define ETH_MACL3A00R_L3A00_26 (0x4000000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x04000000 */
#define ETH_MACL3A00R_L3A00_27 (0x8000000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x08000000 */
#define ETH_MACL3A00R_L3A00_28 (0x10000000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x10000000 */
#define ETH_MACL3A00R_L3A00_29 (0x20000000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x20000000 */
#define ETH_MACL3A00R_L3A00_30 (0x40000000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x40000000 */
#define ETH_MACL3A00R_L3A00_31 (0x80000000U << ETH_MACL3A00R_L3A00_Pos) /*!< 0x80000000 */
/************* Bit definition for ETH_MACL3A10R register *************/
#define ETH_MACL3A10R_L3A10_Pos (0U)
#define ETH_MACL3A10R_L3A10_Msk (0xFFFFFFFFU << ETH_MACL3A10R_L3A10_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACL3A10R_L3A10 ETH_MACL3A10R_L3A10_Msk /*!< Layer 3 Address 1 Field */
#define ETH_MACL3A10R_L3A10_0 (0x1U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00000001 */
#define ETH_MACL3A10R_L3A10_1 (0x2U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00000002 */
#define ETH_MACL3A10R_L3A10_2 (0x4U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00000004 */
#define ETH_MACL3A10R_L3A10_3 (0x8U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00000008 */
#define ETH_MACL3A10R_L3A10_4 (0x10U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00000010 */
#define ETH_MACL3A10R_L3A10_5 (0x20U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00000020 */
#define ETH_MACL3A10R_L3A10_6 (0x40U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00000040 */
#define ETH_MACL3A10R_L3A10_7 (0x80U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00000080 */
#define ETH_MACL3A10R_L3A10_8 (0x100U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00000100 */
#define ETH_MACL3A10R_L3A10_9 (0x200U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00000200 */
#define ETH_MACL3A10R_L3A10_10 (0x400U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00000400 */
#define ETH_MACL3A10R_L3A10_11 (0x800U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00000800 */
#define ETH_MACL3A10R_L3A10_12 (0x1000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00001000 */
#define ETH_MACL3A10R_L3A10_13 (0x2000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00002000 */
#define ETH_MACL3A10R_L3A10_14 (0x4000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00004000 */
#define ETH_MACL3A10R_L3A10_15 (0x8000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00008000 */
#define ETH_MACL3A10R_L3A10_16 (0x10000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00010000 */
#define ETH_MACL3A10R_L3A10_17 (0x20000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00020000 */
#define ETH_MACL3A10R_L3A10_18 (0x40000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00040000 */
#define ETH_MACL3A10R_L3A10_19 (0x80000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00080000 */
#define ETH_MACL3A10R_L3A10_20 (0x100000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00100000 */
#define ETH_MACL3A10R_L3A10_21 (0x200000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00200000 */
#define ETH_MACL3A10R_L3A10_22 (0x400000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00400000 */
#define ETH_MACL3A10R_L3A10_23 (0x800000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x00800000 */
#define ETH_MACL3A10R_L3A10_24 (0x1000000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x01000000 */
#define ETH_MACL3A10R_L3A10_25 (0x2000000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x02000000 */
#define ETH_MACL3A10R_L3A10_26 (0x4000000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x04000000 */
#define ETH_MACL3A10R_L3A10_27 (0x8000000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x08000000 */
#define ETH_MACL3A10R_L3A10_28 (0x10000000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x10000000 */
#define ETH_MACL3A10R_L3A10_29 (0x20000000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x20000000 */
#define ETH_MACL3A10R_L3A10_30 (0x40000000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x40000000 */
#define ETH_MACL3A10R_L3A10_31 (0x80000000U << ETH_MACL3A10R_L3A10_Pos) /*!< 0x80000000 */
/************* Bit definition for ETH_MACL3A20 register **************/
#define ETH_MACL3A20_L3A20_Pos (0U)
#define ETH_MACL3A20_L3A20_Msk (0xFFFFFFFFU << ETH_MACL3A20_L3A20_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACL3A20_L3A20 ETH_MACL3A20_L3A20_Msk /*!< Layer 3 Address 2 Field */
#define ETH_MACL3A20_L3A20_0 (0x1U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00000001 */
#define ETH_MACL3A20_L3A20_1 (0x2U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00000002 */
#define ETH_MACL3A20_L3A20_2 (0x4U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00000004 */
#define ETH_MACL3A20_L3A20_3 (0x8U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00000008 */
#define ETH_MACL3A20_L3A20_4 (0x10U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00000010 */
#define ETH_MACL3A20_L3A20_5 (0x20U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00000020 */
#define ETH_MACL3A20_L3A20_6 (0x40U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00000040 */
#define ETH_MACL3A20_L3A20_7 (0x80U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00000080 */
#define ETH_MACL3A20_L3A20_8 (0x100U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00000100 */
#define ETH_MACL3A20_L3A20_9 (0x200U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00000200 */
#define ETH_MACL3A20_L3A20_10 (0x400U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00000400 */
#define ETH_MACL3A20_L3A20_11 (0x800U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00000800 */
#define ETH_MACL3A20_L3A20_12 (0x1000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00001000 */
#define ETH_MACL3A20_L3A20_13 (0x2000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00002000 */
#define ETH_MACL3A20_L3A20_14 (0x4000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00004000 */
#define ETH_MACL3A20_L3A20_15 (0x8000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00008000 */
#define ETH_MACL3A20_L3A20_16 (0x10000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00010000 */
#define ETH_MACL3A20_L3A20_17 (0x20000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00020000 */
#define ETH_MACL3A20_L3A20_18 (0x40000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00040000 */
#define ETH_MACL3A20_L3A20_19 (0x80000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00080000 */
#define ETH_MACL3A20_L3A20_20 (0x100000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00100000 */
#define ETH_MACL3A20_L3A20_21 (0x200000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00200000 */
#define ETH_MACL3A20_L3A20_22 (0x400000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00400000 */
#define ETH_MACL3A20_L3A20_23 (0x800000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x00800000 */
#define ETH_MACL3A20_L3A20_24 (0x1000000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x01000000 */
#define ETH_MACL3A20_L3A20_25 (0x2000000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x02000000 */
#define ETH_MACL3A20_L3A20_26 (0x4000000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x04000000 */
#define ETH_MACL3A20_L3A20_27 (0x8000000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x08000000 */
#define ETH_MACL3A20_L3A20_28 (0x10000000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x10000000 */
#define ETH_MACL3A20_L3A20_29 (0x20000000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x20000000 */
#define ETH_MACL3A20_L3A20_30 (0x40000000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x40000000 */
#define ETH_MACL3A20_L3A20_31 (0x80000000U << ETH_MACL3A20_L3A20_Pos) /*!< 0x80000000 */
/************* Bit definition for ETH_MACL3A30 register **************/
#define ETH_MACL3A30_L3A30_Pos (0U)
#define ETH_MACL3A30_L3A30_Msk (0xFFFFFFFFU << ETH_MACL3A30_L3A30_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACL3A30_L3A30 ETH_MACL3A30_L3A30_Msk /*!< Layer 3 Address 3 Field */
#define ETH_MACL3A30_L3A30_0 (0x1U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00000001 */
#define ETH_MACL3A30_L3A30_1 (0x2U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00000002 */
#define ETH_MACL3A30_L3A30_2 (0x4U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00000004 */
#define ETH_MACL3A30_L3A30_3 (0x8U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00000008 */
#define ETH_MACL3A30_L3A30_4 (0x10U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00000010 */
#define ETH_MACL3A30_L3A30_5 (0x20U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00000020 */
#define ETH_MACL3A30_L3A30_6 (0x40U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00000040 */
#define ETH_MACL3A30_L3A30_7 (0x80U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00000080 */
#define ETH_MACL3A30_L3A30_8 (0x100U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00000100 */
#define ETH_MACL3A30_L3A30_9 (0x200U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00000200 */
#define ETH_MACL3A30_L3A30_10 (0x400U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00000400 */
#define ETH_MACL3A30_L3A30_11 (0x800U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00000800 */
#define ETH_MACL3A30_L3A30_12 (0x1000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00001000 */
#define ETH_MACL3A30_L3A30_13 (0x2000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00002000 */
#define ETH_MACL3A30_L3A30_14 (0x4000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00004000 */
#define ETH_MACL3A30_L3A30_15 (0x8000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00008000 */
#define ETH_MACL3A30_L3A30_16 (0x10000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00010000 */
#define ETH_MACL3A30_L3A30_17 (0x20000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00020000 */
#define ETH_MACL3A30_L3A30_18 (0x40000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00040000 */
#define ETH_MACL3A30_L3A30_19 (0x80000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00080000 */
#define ETH_MACL3A30_L3A30_20 (0x100000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00100000 */
#define ETH_MACL3A30_L3A30_21 (0x200000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00200000 */
#define ETH_MACL3A30_L3A30_22 (0x400000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00400000 */
#define ETH_MACL3A30_L3A30_23 (0x800000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x00800000 */
#define ETH_MACL3A30_L3A30_24 (0x1000000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x01000000 */
#define ETH_MACL3A30_L3A30_25 (0x2000000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x02000000 */
#define ETH_MACL3A30_L3A30_26 (0x4000000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x04000000 */
#define ETH_MACL3A30_L3A30_27 (0x8000000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x08000000 */
#define ETH_MACL3A30_L3A30_28 (0x10000000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x10000000 */
#define ETH_MACL3A30_L3A30_29 (0x20000000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x20000000 */
#define ETH_MACL3A30_L3A30_30 (0x40000000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x40000000 */
#define ETH_MACL3A30_L3A30_31 (0x80000000U << ETH_MACL3A30_L3A30_Pos) /*!< 0x80000000 */
/************ Bit definition for ETH_MACL3L4C1R register *************/
#define ETH_MACL3L4C1R_L3PEN1_Pos (0U)
#define ETH_MACL3L4C1R_L3PEN1_Msk (0x1U << ETH_MACL3L4C1R_L3PEN1_Pos) /*!< 0x00000001 */
#define ETH_MACL3L4C1R_L3PEN1 ETH_MACL3L4C1R_L3PEN1_Msk /*!< Layer 3 Protocol Enable */
#define ETH_MACL3L4C1R_L3SAM1_Pos (2U)
#define ETH_MACL3L4C1R_L3SAM1_Msk (0x1U << ETH_MACL3L4C1R_L3SAM1_Pos) /*!< 0x00000004 */
#define ETH_MACL3L4C1R_L3SAM1 ETH_MACL3L4C1R_L3SAM1_Msk /*!< Layer 3 IP SA Match Enable */
#define ETH_MACL3L4C1R_L3SAIM1_Pos (3U)
#define ETH_MACL3L4C1R_L3SAIM1_Msk (0x1U << ETH_MACL3L4C1R_L3SAIM1_Pos) /*!< 0x00000008 */
#define ETH_MACL3L4C1R_L3SAIM1 ETH_MACL3L4C1R_L3SAIM1_Msk /*!< Layer 3 IP SA Inverse Match Enable */
#define ETH_MACL3L4C1R_L3DAM1_Pos (4U)
#define ETH_MACL3L4C1R_L3DAM1_Msk (0x1U << ETH_MACL3L4C1R_L3DAM1_Pos) /*!< 0x00000010 */
#define ETH_MACL3L4C1R_L3DAM1 ETH_MACL3L4C1R_L3DAM1_Msk /*!< Layer 3 IP DA Match Enable */
#define ETH_MACL3L4C1R_L3DAIM1_Pos (5U)
#define ETH_MACL3L4C1R_L3DAIM1_Msk (0x1U << ETH_MACL3L4C1R_L3DAIM1_Pos) /*!< 0x00000020 */
#define ETH_MACL3L4C1R_L3DAIM1 ETH_MACL3L4C1R_L3DAIM1_Msk /*!< Layer 3 IP DA Inverse Match Enable */
#define ETH_MACL3L4C1R_L3HSBM1_Pos (6U)
#define ETH_MACL3L4C1R_L3HSBM1_Msk (0x1FU << ETH_MACL3L4C1R_L3HSBM1_Pos) /*!< 0x000007C0 */
#define ETH_MACL3L4C1R_L3HSBM1 ETH_MACL3L4C1R_L3HSBM1_Msk /*!< Layer 3 IP SA Higher Bits Match */
#define ETH_MACL3L4C1R_L3HSBM1_0 (0x1U << ETH_MACL3L4C1R_L3HSBM1_Pos) /*!< 0x00000040 */
#define ETH_MACL3L4C1R_L3HSBM1_1 (0x2U << ETH_MACL3L4C1R_L3HSBM1_Pos) /*!< 0x00000080 */
#define ETH_MACL3L4C1R_L3HSBM1_2 (0x4U << ETH_MACL3L4C1R_L3HSBM1_Pos) /*!< 0x00000100 */
#define ETH_MACL3L4C1R_L3HSBM1_3 (0x8U << ETH_MACL3L4C1R_L3HSBM1_Pos) /*!< 0x00000200 */
#define ETH_MACL3L4C1R_L3HSBM1_4 (0x10U << ETH_MACL3L4C1R_L3HSBM1_Pos) /*!< 0x00000400 */
#define ETH_MACL3L4C1R_L3HDBM1_Pos (11U)
#define ETH_MACL3L4C1R_L3HDBM1_Msk (0x1FU << ETH_MACL3L4C1R_L3HDBM1_Pos) /*!< 0x0000F800 */
#define ETH_MACL3L4C1R_L3HDBM1 ETH_MACL3L4C1R_L3HDBM1_Msk /*!< Layer 3 IP DA Higher Bits Match */
#define ETH_MACL3L4C1R_L3HDBM1_0 (0x1U << ETH_MACL3L4C1R_L3HDBM1_Pos) /*!< 0x00000800 */
#define ETH_MACL3L4C1R_L3HDBM1_1 (0x2U << ETH_MACL3L4C1R_L3HDBM1_Pos) /*!< 0x00001000 */
#define ETH_MACL3L4C1R_L3HDBM1_2 (0x4U << ETH_MACL3L4C1R_L3HDBM1_Pos) /*!< 0x00002000 */
#define ETH_MACL3L4C1R_L3HDBM1_3 (0x8U << ETH_MACL3L4C1R_L3HDBM1_Pos) /*!< 0x00004000 */
#define ETH_MACL3L4C1R_L3HDBM1_4 (0x10U << ETH_MACL3L4C1R_L3HDBM1_Pos) /*!< 0x00008000 */
#define ETH_MACL3L4C1R_L4PEN1_Pos (16U)
#define ETH_MACL3L4C1R_L4PEN1_Msk (0x1U << ETH_MACL3L4C1R_L4PEN1_Pos) /*!< 0x00010000 */
#define ETH_MACL3L4C1R_L4PEN1 ETH_MACL3L4C1R_L4PEN1_Msk /*!< Layer 4 Protocol Enable */
#define ETH_MACL3L4C1R_L4SPM1_Pos (18U)
#define ETH_MACL3L4C1R_L4SPM1_Msk (0x1U << ETH_MACL3L4C1R_L4SPM1_Pos) /*!< 0x00040000 */
#define ETH_MACL3L4C1R_L4SPM1 ETH_MACL3L4C1R_L4SPM1_Msk /*!< Layer 4 Source Port Match Enable */
#define ETH_MACL3L4C1R_L4SPIM1_Pos (19U)
#define ETH_MACL3L4C1R_L4SPIM1_Msk (0x1U << ETH_MACL3L4C1R_L4SPIM1_Pos) /*!< 0x00080000 */
#define ETH_MACL3L4C1R_L4SPIM1 ETH_MACL3L4C1R_L4SPIM1_Msk /*!< Layer 4 Source Port Inverse Match Enable */
#define ETH_MACL3L4C1R_L4DPM1_Pos (20U)
#define ETH_MACL3L4C1R_L4DPM1_Msk (0x1U << ETH_MACL3L4C1R_L4DPM1_Pos) /*!< 0x00100000 */
#define ETH_MACL3L4C1R_L4DPM1 ETH_MACL3L4C1R_L4DPM1_Msk /*!< Layer 4 Destination Port Match Enable */
#define ETH_MACL3L4C1R_L4DPIM1_Pos (21U)
#define ETH_MACL3L4C1R_L4DPIM1_Msk (0x1U << ETH_MACL3L4C1R_L4DPIM1_Pos) /*!< 0x00200000 */
#define ETH_MACL3L4C1R_L4DPIM1 ETH_MACL3L4C1R_L4DPIM1_Msk /*!< Layer 4 Destination Port Inverse Match Enable */
/************* Bit definition for ETH_MACL4A1R register **************/
#define ETH_MACL4A1R_L4SP1_Pos (0U)
#define ETH_MACL4A1R_L4SP1_Msk (0xFFFFU << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x0000FFFF */
#define ETH_MACL4A1R_L4SP1 ETH_MACL4A1R_L4SP1_Msk /*!< Layer 4 Source Port Number Field */
#define ETH_MACL4A1R_L4SP1_0 (0x1U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00000001 */
#define ETH_MACL4A1R_L4SP1_1 (0x2U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00000002 */
#define ETH_MACL4A1R_L4SP1_2 (0x4U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00000004 */
#define ETH_MACL4A1R_L4SP1_3 (0x8U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00000008 */
#define ETH_MACL4A1R_L4SP1_4 (0x10U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00000010 */
#define ETH_MACL4A1R_L4SP1_5 (0x20U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00000020 */
#define ETH_MACL4A1R_L4SP1_6 (0x40U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00000040 */
#define ETH_MACL4A1R_L4SP1_7 (0x80U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00000080 */
#define ETH_MACL4A1R_L4SP1_8 (0x100U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00000100 */
#define ETH_MACL4A1R_L4SP1_9 (0x200U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00000200 */
#define ETH_MACL4A1R_L4SP1_10 (0x400U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00000400 */
#define ETH_MACL4A1R_L4SP1_11 (0x800U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00000800 */
#define ETH_MACL4A1R_L4SP1_12 (0x1000U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00001000 */
#define ETH_MACL4A1R_L4SP1_13 (0x2000U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00002000 */
#define ETH_MACL4A1R_L4SP1_14 (0x4000U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00004000 */
#define ETH_MACL4A1R_L4SP1_15 (0x8000U << ETH_MACL4A1R_L4SP1_Pos) /*!< 0x00008000 */
#define ETH_MACL4A1R_L4DP1_Pos (16U)
#define ETH_MACL4A1R_L4DP1_Msk (0xFFFFU << ETH_MACL4A1R_L4DP1_Pos) /*!< 0xFFFF0000 */
#define ETH_MACL4A1R_L4DP1 ETH_MACL4A1R_L4DP1_Msk /*!< Layer 4 Destination Port Number Field */
#define ETH_MACL4A1R_L4DP1_0 (0x1U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x00010000 */
#define ETH_MACL4A1R_L4DP1_1 (0x2U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x00020000 */
#define ETH_MACL4A1R_L4DP1_2 (0x4U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x00040000 */
#define ETH_MACL4A1R_L4DP1_3 (0x8U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x00080000 */
#define ETH_MACL4A1R_L4DP1_4 (0x10U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x00100000 */
#define ETH_MACL4A1R_L4DP1_5 (0x20U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x00200000 */
#define ETH_MACL4A1R_L4DP1_6 (0x40U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x00400000 */
#define ETH_MACL4A1R_L4DP1_7 (0x80U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x00800000 */
#define ETH_MACL4A1R_L4DP1_8 (0x100U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x01000000 */
#define ETH_MACL4A1R_L4DP1_9 (0x200U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x02000000 */
#define ETH_MACL4A1R_L4DP1_10 (0x400U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x04000000 */
#define ETH_MACL4A1R_L4DP1_11 (0x800U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x08000000 */
#define ETH_MACL4A1R_L4DP1_12 (0x1000U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x10000000 */
#define ETH_MACL4A1R_L4DP1_13 (0x2000U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x20000000 */
#define ETH_MACL4A1R_L4DP1_14 (0x4000U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x40000000 */
#define ETH_MACL4A1R_L4DP1_15 (0x8000U << ETH_MACL4A1R_L4DP1_Pos) /*!< 0x80000000 */
/************* Bit definition for ETH_MACL3A01R register *************/
#define ETH_MACL3A01R_L3A01_Pos (0U)
#define ETH_MACL3A01R_L3A01_Msk (0xFFFFFFFFU << ETH_MACL3A01R_L3A01_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACL3A01R_L3A01 ETH_MACL3A01R_L3A01_Msk /*!< Layer 3 Address 0 Field */
#define ETH_MACL3A01R_L3A01_0 (0x1U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00000001 */
#define ETH_MACL3A01R_L3A01_1 (0x2U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00000002 */
#define ETH_MACL3A01R_L3A01_2 (0x4U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00000004 */
#define ETH_MACL3A01R_L3A01_3 (0x8U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00000008 */
#define ETH_MACL3A01R_L3A01_4 (0x10U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00000010 */
#define ETH_MACL3A01R_L3A01_5 (0x20U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00000020 */
#define ETH_MACL3A01R_L3A01_6 (0x40U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00000040 */
#define ETH_MACL3A01R_L3A01_7 (0x80U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00000080 */
#define ETH_MACL3A01R_L3A01_8 (0x100U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00000100 */
#define ETH_MACL3A01R_L3A01_9 (0x200U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00000200 */
#define ETH_MACL3A01R_L3A01_10 (0x400U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00000400 */
#define ETH_MACL3A01R_L3A01_11 (0x800U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00000800 */
#define ETH_MACL3A01R_L3A01_12 (0x1000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00001000 */
#define ETH_MACL3A01R_L3A01_13 (0x2000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00002000 */
#define ETH_MACL3A01R_L3A01_14 (0x4000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00004000 */
#define ETH_MACL3A01R_L3A01_15 (0x8000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00008000 */
#define ETH_MACL3A01R_L3A01_16 (0x10000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00010000 */
#define ETH_MACL3A01R_L3A01_17 (0x20000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00020000 */
#define ETH_MACL3A01R_L3A01_18 (0x40000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00040000 */
#define ETH_MACL3A01R_L3A01_19 (0x80000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00080000 */
#define ETH_MACL3A01R_L3A01_20 (0x100000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00100000 */
#define ETH_MACL3A01R_L3A01_21 (0x200000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00200000 */
#define ETH_MACL3A01R_L3A01_22 (0x400000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00400000 */
#define ETH_MACL3A01R_L3A01_23 (0x800000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x00800000 */
#define ETH_MACL3A01R_L3A01_24 (0x1000000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x01000000 */
#define ETH_MACL3A01R_L3A01_25 (0x2000000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x02000000 */
#define ETH_MACL3A01R_L3A01_26 (0x4000000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x04000000 */
#define ETH_MACL3A01R_L3A01_27 (0x8000000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x08000000 */
#define ETH_MACL3A01R_L3A01_28 (0x10000000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x10000000 */
#define ETH_MACL3A01R_L3A01_29 (0x20000000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x20000000 */
#define ETH_MACL3A01R_L3A01_30 (0x40000000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x40000000 */
#define ETH_MACL3A01R_L3A01_31 (0x80000000U << ETH_MACL3A01R_L3A01_Pos) /*!< 0x80000000 */
/************* Bit definition for ETH_MACL3A11R register *************/
#define ETH_MACL3A11R_L3A11_Pos (0U)
#define ETH_MACL3A11R_L3A11_Msk (0xFFFFFFFFU << ETH_MACL3A11R_L3A11_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACL3A11R_L3A11 ETH_MACL3A11R_L3A11_Msk /*!< Layer 3 Address 1 Field */
#define ETH_MACL3A11R_L3A11_0 (0x1U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00000001 */
#define ETH_MACL3A11R_L3A11_1 (0x2U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00000002 */
#define ETH_MACL3A11R_L3A11_2 (0x4U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00000004 */
#define ETH_MACL3A11R_L3A11_3 (0x8U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00000008 */
#define ETH_MACL3A11R_L3A11_4 (0x10U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00000010 */
#define ETH_MACL3A11R_L3A11_5 (0x20U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00000020 */
#define ETH_MACL3A11R_L3A11_6 (0x40U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00000040 */
#define ETH_MACL3A11R_L3A11_7 (0x80U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00000080 */
#define ETH_MACL3A11R_L3A11_8 (0x100U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00000100 */
#define ETH_MACL3A11R_L3A11_9 (0x200U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00000200 */
#define ETH_MACL3A11R_L3A11_10 (0x400U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00000400 */
#define ETH_MACL3A11R_L3A11_11 (0x800U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00000800 */
#define ETH_MACL3A11R_L3A11_12 (0x1000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00001000 */
#define ETH_MACL3A11R_L3A11_13 (0x2000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00002000 */
#define ETH_MACL3A11R_L3A11_14 (0x4000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00004000 */
#define ETH_MACL3A11R_L3A11_15 (0x8000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00008000 */
#define ETH_MACL3A11R_L3A11_16 (0x10000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00010000 */
#define ETH_MACL3A11R_L3A11_17 (0x20000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00020000 */
#define ETH_MACL3A11R_L3A11_18 (0x40000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00040000 */
#define ETH_MACL3A11R_L3A11_19 (0x80000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00080000 */
#define ETH_MACL3A11R_L3A11_20 (0x100000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00100000 */
#define ETH_MACL3A11R_L3A11_21 (0x200000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00200000 */
#define ETH_MACL3A11R_L3A11_22 (0x400000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00400000 */
#define ETH_MACL3A11R_L3A11_23 (0x800000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x00800000 */
#define ETH_MACL3A11R_L3A11_24 (0x1000000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x01000000 */
#define ETH_MACL3A11R_L3A11_25 (0x2000000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x02000000 */
#define ETH_MACL3A11R_L3A11_26 (0x4000000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x04000000 */
#define ETH_MACL3A11R_L3A11_27 (0x8000000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x08000000 */
#define ETH_MACL3A11R_L3A11_28 (0x10000000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x10000000 */
#define ETH_MACL3A11R_L3A11_29 (0x20000000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x20000000 */
#define ETH_MACL3A11R_L3A11_30 (0x40000000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x40000000 */
#define ETH_MACL3A11R_L3A11_31 (0x80000000U << ETH_MACL3A11R_L3A11_Pos) /*!< 0x80000000 */
/************* Bit definition for ETH_MACL3A21R register *************/
#define ETH_MACL3A21R_L3A21_Pos (0U)
#define ETH_MACL3A21R_L3A21_Msk (0xFFFFFFFFU << ETH_MACL3A21R_L3A21_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACL3A21R_L3A21 ETH_MACL3A21R_L3A21_Msk /*!< Layer 3 Address 2 Field */
#define ETH_MACL3A21R_L3A21_0 (0x1U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00000001 */
#define ETH_MACL3A21R_L3A21_1 (0x2U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00000002 */
#define ETH_MACL3A21R_L3A21_2 (0x4U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00000004 */
#define ETH_MACL3A21R_L3A21_3 (0x8U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00000008 */
#define ETH_MACL3A21R_L3A21_4 (0x10U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00000010 */
#define ETH_MACL3A21R_L3A21_5 (0x20U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00000020 */
#define ETH_MACL3A21R_L3A21_6 (0x40U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00000040 */
#define ETH_MACL3A21R_L3A21_7 (0x80U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00000080 */
#define ETH_MACL3A21R_L3A21_8 (0x100U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00000100 */
#define ETH_MACL3A21R_L3A21_9 (0x200U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00000200 */
#define ETH_MACL3A21R_L3A21_10 (0x400U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00000400 */
#define ETH_MACL3A21R_L3A21_11 (0x800U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00000800 */
#define ETH_MACL3A21R_L3A21_12 (0x1000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00001000 */
#define ETH_MACL3A21R_L3A21_13 (0x2000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00002000 */
#define ETH_MACL3A21R_L3A21_14 (0x4000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00004000 */
#define ETH_MACL3A21R_L3A21_15 (0x8000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00008000 */
#define ETH_MACL3A21R_L3A21_16 (0x10000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00010000 */
#define ETH_MACL3A21R_L3A21_17 (0x20000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00020000 */
#define ETH_MACL3A21R_L3A21_18 (0x40000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00040000 */
#define ETH_MACL3A21R_L3A21_19 (0x80000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00080000 */
#define ETH_MACL3A21R_L3A21_20 (0x100000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00100000 */
#define ETH_MACL3A21R_L3A21_21 (0x200000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00200000 */
#define ETH_MACL3A21R_L3A21_22 (0x400000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00400000 */
#define ETH_MACL3A21R_L3A21_23 (0x800000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x00800000 */
#define ETH_MACL3A21R_L3A21_24 (0x1000000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x01000000 */
#define ETH_MACL3A21R_L3A21_25 (0x2000000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x02000000 */
#define ETH_MACL3A21R_L3A21_26 (0x4000000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x04000000 */
#define ETH_MACL3A21R_L3A21_27 (0x8000000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x08000000 */
#define ETH_MACL3A21R_L3A21_28 (0x10000000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x10000000 */
#define ETH_MACL3A21R_L3A21_29 (0x20000000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x20000000 */
#define ETH_MACL3A21R_L3A21_30 (0x40000000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x40000000 */
#define ETH_MACL3A21R_L3A21_31 (0x80000000U << ETH_MACL3A21R_L3A21_Pos) /*!< 0x80000000 */
/************* Bit definition for ETH_MACL3A31R register *************/
#define ETH_MACL3A31R_L3A31_Pos (0U)
#define ETH_MACL3A31R_L3A31_Msk (0xFFFFFFFFU << ETH_MACL3A31R_L3A31_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACL3A31R_L3A31 ETH_MACL3A31R_L3A31_Msk /*!< Layer 3 Address 3 Field */
#define ETH_MACL3A31R_L3A31_0 (0x1U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00000001 */
#define ETH_MACL3A31R_L3A31_1 (0x2U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00000002 */
#define ETH_MACL3A31R_L3A31_2 (0x4U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00000004 */
#define ETH_MACL3A31R_L3A31_3 (0x8U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00000008 */
#define ETH_MACL3A31R_L3A31_4 (0x10U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00000010 */
#define ETH_MACL3A31R_L3A31_5 (0x20U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00000020 */
#define ETH_MACL3A31R_L3A31_6 (0x40U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00000040 */
#define ETH_MACL3A31R_L3A31_7 (0x80U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00000080 */
#define ETH_MACL3A31R_L3A31_8 (0x100U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00000100 */
#define ETH_MACL3A31R_L3A31_9 (0x200U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00000200 */
#define ETH_MACL3A31R_L3A31_10 (0x400U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00000400 */
#define ETH_MACL3A31R_L3A31_11 (0x800U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00000800 */
#define ETH_MACL3A31R_L3A31_12 (0x1000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00001000 */
#define ETH_MACL3A31R_L3A31_13 (0x2000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00002000 */
#define ETH_MACL3A31R_L3A31_14 (0x4000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00004000 */
#define ETH_MACL3A31R_L3A31_15 (0x8000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00008000 */
#define ETH_MACL3A31R_L3A31_16 (0x10000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00010000 */
#define ETH_MACL3A31R_L3A31_17 (0x20000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00020000 */
#define ETH_MACL3A31R_L3A31_18 (0x40000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00040000 */
#define ETH_MACL3A31R_L3A31_19 (0x80000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00080000 */
#define ETH_MACL3A31R_L3A31_20 (0x100000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00100000 */
#define ETH_MACL3A31R_L3A31_21 (0x200000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00200000 */
#define ETH_MACL3A31R_L3A31_22 (0x400000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00400000 */
#define ETH_MACL3A31R_L3A31_23 (0x800000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x00800000 */
#define ETH_MACL3A31R_L3A31_24 (0x1000000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x01000000 */
#define ETH_MACL3A31R_L3A31_25 (0x2000000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x02000000 */
#define ETH_MACL3A31R_L3A31_26 (0x4000000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x04000000 */
#define ETH_MACL3A31R_L3A31_27 (0x8000000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x08000000 */
#define ETH_MACL3A31R_L3A31_28 (0x10000000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x10000000 */
#define ETH_MACL3A31R_L3A31_29 (0x20000000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x20000000 */
#define ETH_MACL3A31R_L3A31_30 (0x40000000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x40000000 */
#define ETH_MACL3A31R_L3A31_31 (0x80000000U << ETH_MACL3A31R_L3A31_Pos) /*!< 0x80000000 */
/************* Bit definition for ETH_MACARPAR register **************/
#define ETH_MACARPAR_ARPPA_Pos (0U)
#define ETH_MACARPAR_ARPPA_Msk (0xFFFFFFFFU << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACARPAR_ARPPA ETH_MACARPAR_ARPPA_Msk /*!< ARP Protocol Address */
#define ETH_MACARPAR_ARPPA_0 (0x1U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00000001 */
#define ETH_MACARPAR_ARPPA_1 (0x2U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00000002 */
#define ETH_MACARPAR_ARPPA_2 (0x4U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00000004 */
#define ETH_MACARPAR_ARPPA_3 (0x8U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00000008 */
#define ETH_MACARPAR_ARPPA_4 (0x10U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00000010 */
#define ETH_MACARPAR_ARPPA_5 (0x20U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00000020 */
#define ETH_MACARPAR_ARPPA_6 (0x40U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00000040 */
#define ETH_MACARPAR_ARPPA_7 (0x80U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00000080 */
#define ETH_MACARPAR_ARPPA_8 (0x100U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00000100 */
#define ETH_MACARPAR_ARPPA_9 (0x200U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00000200 */
#define ETH_MACARPAR_ARPPA_10 (0x400U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00000400 */
#define ETH_MACARPAR_ARPPA_11 (0x800U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00000800 */
#define ETH_MACARPAR_ARPPA_12 (0x1000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00001000 */
#define ETH_MACARPAR_ARPPA_13 (0x2000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00002000 */
#define ETH_MACARPAR_ARPPA_14 (0x4000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00004000 */
#define ETH_MACARPAR_ARPPA_15 (0x8000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00008000 */
#define ETH_MACARPAR_ARPPA_16 (0x10000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00010000 */
#define ETH_MACARPAR_ARPPA_17 (0x20000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00020000 */
#define ETH_MACARPAR_ARPPA_18 (0x40000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00040000 */
#define ETH_MACARPAR_ARPPA_19 (0x80000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00080000 */
#define ETH_MACARPAR_ARPPA_20 (0x100000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00100000 */
#define ETH_MACARPAR_ARPPA_21 (0x200000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00200000 */
#define ETH_MACARPAR_ARPPA_22 (0x400000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00400000 */
#define ETH_MACARPAR_ARPPA_23 (0x800000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x00800000 */
#define ETH_MACARPAR_ARPPA_24 (0x1000000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x01000000 */
#define ETH_MACARPAR_ARPPA_25 (0x2000000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x02000000 */
#define ETH_MACARPAR_ARPPA_26 (0x4000000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x04000000 */
#define ETH_MACARPAR_ARPPA_27 (0x8000000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x08000000 */
#define ETH_MACARPAR_ARPPA_28 (0x10000000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x10000000 */
#define ETH_MACARPAR_ARPPA_29 (0x20000000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x20000000 */
#define ETH_MACARPAR_ARPPA_30 (0x40000000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x40000000 */
#define ETH_MACARPAR_ARPPA_31 (0x80000000U << ETH_MACARPAR_ARPPA_Pos) /*!< 0x80000000 */
/************** Bit definition for ETH_MACTSCR register **************/
#define ETH_MACTSCR_TSENA_Pos (0U)
#define ETH_MACTSCR_TSENA_Msk (0x1U << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */
#define ETH_MACTSCR_TSENA ETH_MACTSCR_TSENA_Msk /*!< Enable Timestamp */
#define ETH_MACTSCR_TSCFUPDT_Pos (1U)
#define ETH_MACTSCR_TSCFUPDT_Msk (0x1U << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */
#define ETH_MACTSCR_TSCFUPDT ETH_MACTSCR_TSCFUPDT_Msk /*!< Fine or Coarse Timestamp Update */
#define ETH_MACTSCR_TSINIT_Pos (2U)
#define ETH_MACTSCR_TSINIT_Msk (0x1U << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */
#define ETH_MACTSCR_TSINIT ETH_MACTSCR_TSINIT_Msk /*!< Initialize Timestamp */
#define ETH_MACTSCR_TSUPDT_Pos (3U)
#define ETH_MACTSCR_TSUPDT_Msk (0x1U << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */
#define ETH_MACTSCR_TSUPDT ETH_MACTSCR_TSUPDT_Msk /*!< Update Timestamp */
#define ETH_MACTSCR_TSADDREG_Pos (5U)
#define ETH_MACTSCR_TSADDREG_Msk (0x1U << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */
#define ETH_MACTSCR_TSADDREG ETH_MACTSCR_TSADDREG_Msk /*!< Update Addend Register */
#define ETH_MACTSCR_TSENALL_Pos (8U)
#define ETH_MACTSCR_TSENALL_Msk (0x1U << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */
#define ETH_MACTSCR_TSENALL ETH_MACTSCR_TSENALL_Msk /*!< Enable Timestamp for All Packets */
#define ETH_MACTSCR_TSCTRLSSR_Pos (9U)
#define ETH_MACTSCR_TSCTRLSSR_Msk (0x1U << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */
#define ETH_MACTSCR_TSCTRLSSR ETH_MACTSCR_TSCTRLSSR_Msk /*!< Timestamp Digital or Binary Rollover Control */
#define ETH_MACTSCR_TSVER2ENA_Pos (10U)
#define ETH_MACTSCR_TSVER2ENA_Msk (0x1U << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */
#define ETH_MACTSCR_TSVER2ENA ETH_MACTSCR_TSVER2ENA_Msk /*!< Enable PTP Packet Processing for Version 2 Format */
#define ETH_MACTSCR_TSIPENA_Pos (11U)
#define ETH_MACTSCR_TSIPENA_Msk (0x1U << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */
#define ETH_MACTSCR_TSIPENA ETH_MACTSCR_TSIPENA_Msk /*!< Enable Processing of PTP over Ethernet Packets */
#define ETH_MACTSCR_TSIPV6ENA_Pos (12U)
#define ETH_MACTSCR_TSIPV6ENA_Msk (0x1U << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */
#define ETH_MACTSCR_TSIPV6ENA ETH_MACTSCR_TSIPV6ENA_Msk /*!< Enable Processing of PTP Packets Sent over IPv6-UDP */
#define ETH_MACTSCR_TSIPV4ENA_Pos (13U)
#define ETH_MACTSCR_TSIPV4ENA_Msk (0x1U << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */
#define ETH_MACTSCR_TSIPV4ENA ETH_MACTSCR_TSIPV4ENA_Msk /*!< Enable Processing of PTP Packets Sent over IPv4-UDP */
#define ETH_MACTSCR_TSEVNTENA_Pos (14U)
#define ETH_MACTSCR_TSEVNTENA_Msk (0x1U << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */
#define ETH_MACTSCR_TSEVNTENA ETH_MACTSCR_TSEVNTENA_Msk /*!< Enable Timestamp Snapshot for Event Messages */
#define ETH_MACTSCR_TSMSTRENA_Pos (15U)
#define ETH_MACTSCR_TSMSTRENA_Msk (0x1U << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */
#define ETH_MACTSCR_TSMSTRENA ETH_MACTSCR_TSMSTRENA_Msk /*!< Enable Snapshot for Messages Relevant to Master */
#define ETH_MACTSCR_SNAPTYPSEL_Pos (16U)
#define ETH_MACTSCR_SNAPTYPSEL_Msk (0x3U << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */
#define ETH_MACTSCR_SNAPTYPSEL ETH_MACTSCR_SNAPTYPSEL_Msk /*!< Select PTP packets for Taking Snapshots */
#define ETH_MACTSCR_SNAPTYPSEL_0 (0x1U << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00010000 */
#define ETH_MACTSCR_SNAPTYPSEL_1 (0x2U << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00020000 */
#define ETH_MACTSCR_TSENMACADDR_Pos (18U)
#define ETH_MACTSCR_TSENMACADDR_Msk (0x1U << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */
#define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /*!< Enable MAC Address for PTP Packet Filtering */
#define ETH_MACTSCR_CSC_Pos (19U)
#define ETH_MACTSCR_CSC_Msk (0x1U << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */
#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */
#define ETH_MACTSCR_TXTSSTSM_Pos (24U)
#define ETH_MACTSCR_TXTSSTSM_Msk (0x1U << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */
#define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /*!< Transmit Timestamp Status Mode */
#define ETH_MACTSCR_AV8021ASMEN_Pos (28U)
#define ETH_MACTSCR_AV8021ASMEN_Msk (0x1U << ETH_MACTSCR_AV8021ASMEN_Pos) /*!< 0x10000000 */
#define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /*!< AV 802.1AS Mode Enable */
/************** Bit definition for ETH_MACSSIR register **************/
#define ETH_MACSSIR_SNSINC_Pos (8U)
#define ETH_MACSSIR_SNSINC_Msk (0xFFU << ETH_MACSSIR_SNSINC_Pos) /*!< 0x0000FF00 */
#define ETH_MACSSIR_SNSINC ETH_MACSSIR_SNSINC_Msk /*!< Sub-nanosecond Increment Value */
#define ETH_MACSSIR_SNSINC_0 (0x1U << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000100 */
#define ETH_MACSSIR_SNSINC_1 (0x2U << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000200 */
#define ETH_MACSSIR_SNSINC_2 (0x4U << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000400 */
#define ETH_MACSSIR_SNSINC_3 (0x8U << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00000800 */
#define ETH_MACSSIR_SNSINC_4 (0x10U << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00001000 */
#define ETH_MACSSIR_SNSINC_5 (0x20U << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00002000 */
#define ETH_MACSSIR_SNSINC_6 (0x40U << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00004000 */
#define ETH_MACSSIR_SNSINC_7 (0x80U << ETH_MACSSIR_SNSINC_Pos) /*!< 0x00008000 */
#define ETH_MACSSIR_SSINC_Pos (16U)
#define ETH_MACSSIR_SSINC_Msk (0xFFU << ETH_MACSSIR_SSINC_Pos) /*!< 0x00FF0000 */
#define ETH_MACSSIR_SSINC ETH_MACSSIR_SSINC_Msk /*!< Sub-second Increment Value */
#define ETH_MACSSIR_SSINC_0 (0x1U << ETH_MACSSIR_SSINC_Pos) /*!< 0x00010000 */
#define ETH_MACSSIR_SSINC_1 (0x2U << ETH_MACSSIR_SSINC_Pos) /*!< 0x00020000 */
#define ETH_MACSSIR_SSINC_2 (0x4U << ETH_MACSSIR_SSINC_Pos) /*!< 0x00040000 */
#define ETH_MACSSIR_SSINC_3 (0x8U << ETH_MACSSIR_SSINC_Pos) /*!< 0x00080000 */
#define ETH_MACSSIR_SSINC_4 (0x10U << ETH_MACSSIR_SSINC_Pos) /*!< 0x00100000 */
#define ETH_MACSSIR_SSINC_5 (0x20U << ETH_MACSSIR_SSINC_Pos) /*!< 0x00200000 */
#define ETH_MACSSIR_SSINC_6 (0x40U << ETH_MACSSIR_SSINC_Pos) /*!< 0x00400000 */
#define ETH_MACSSIR_SSINC_7 (0x80U << ETH_MACSSIR_SSINC_Pos) /*!< 0x00800000 */
/************** Bit definition for ETH_MACSTSR register **************/
#define ETH_MACSTSR_TSS_Pos (0U)
#define ETH_MACSTSR_TSS_Msk (0xFFFFFFFFU << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACSTSR_TSS ETH_MACSTSR_TSS_Msk /*!< Timestamp Second */
#define ETH_MACSTSR_TSS_0 (0x1U << ETH_MACSTSR_TSS_Pos) /*!< 0x00000001 */
#define ETH_MACSTSR_TSS_1 (0x2U << ETH_MACSTSR_TSS_Pos) /*!< 0x00000002 */
#define ETH_MACSTSR_TSS_2 (0x4U << ETH_MACSTSR_TSS_Pos) /*!< 0x00000004 */
#define ETH_MACSTSR_TSS_3 (0x8U << ETH_MACSTSR_TSS_Pos) /*!< 0x00000008 */
#define ETH_MACSTSR_TSS_4 (0x10U << ETH_MACSTSR_TSS_Pos) /*!< 0x00000010 */
#define ETH_MACSTSR_TSS_5 (0x20U << ETH_MACSTSR_TSS_Pos) /*!< 0x00000020 */
#define ETH_MACSTSR_TSS_6 (0x40U << ETH_MACSTSR_TSS_Pos) /*!< 0x00000040 */
#define ETH_MACSTSR_TSS_7 (0x80U << ETH_MACSTSR_TSS_Pos) /*!< 0x00000080 */
#define ETH_MACSTSR_TSS_8 (0x100U << ETH_MACSTSR_TSS_Pos) /*!< 0x00000100 */
#define ETH_MACSTSR_TSS_9 (0x200U << ETH_MACSTSR_TSS_Pos) /*!< 0x00000200 */
#define ETH_MACSTSR_TSS_10 (0x400U << ETH_MACSTSR_TSS_Pos) /*!< 0x00000400 */
#define ETH_MACSTSR_TSS_11 (0x800U << ETH_MACSTSR_TSS_Pos) /*!< 0x00000800 */
#define ETH_MACSTSR_TSS_12 (0x1000U << ETH_MACSTSR_TSS_Pos) /*!< 0x00001000 */
#define ETH_MACSTSR_TSS_13 (0x2000U << ETH_MACSTSR_TSS_Pos) /*!< 0x00002000 */
#define ETH_MACSTSR_TSS_14 (0x4000U << ETH_MACSTSR_TSS_Pos) /*!< 0x00004000 */
#define ETH_MACSTSR_TSS_15 (0x8000U << ETH_MACSTSR_TSS_Pos) /*!< 0x00008000 */
#define ETH_MACSTSR_TSS_16 (0x10000U << ETH_MACSTSR_TSS_Pos) /*!< 0x00010000 */
#define ETH_MACSTSR_TSS_17 (0x20000U << ETH_MACSTSR_TSS_Pos) /*!< 0x00020000 */
#define ETH_MACSTSR_TSS_18 (0x40000U << ETH_MACSTSR_TSS_Pos) /*!< 0x00040000 */
#define ETH_MACSTSR_TSS_19 (0x80000U << ETH_MACSTSR_TSS_Pos) /*!< 0x00080000 */
#define ETH_MACSTSR_TSS_20 (0x100000U << ETH_MACSTSR_TSS_Pos) /*!< 0x00100000 */
#define ETH_MACSTSR_TSS_21 (0x200000U << ETH_MACSTSR_TSS_Pos) /*!< 0x00200000 */
#define ETH_MACSTSR_TSS_22 (0x400000U << ETH_MACSTSR_TSS_Pos) /*!< 0x00400000 */
#define ETH_MACSTSR_TSS_23 (0x800000U << ETH_MACSTSR_TSS_Pos) /*!< 0x00800000 */
#define ETH_MACSTSR_TSS_24 (0x1000000U << ETH_MACSTSR_TSS_Pos) /*!< 0x01000000 */
#define ETH_MACSTSR_TSS_25 (0x2000000U << ETH_MACSTSR_TSS_Pos) /*!< 0x02000000 */
#define ETH_MACSTSR_TSS_26 (0x4000000U << ETH_MACSTSR_TSS_Pos) /*!< 0x04000000 */
#define ETH_MACSTSR_TSS_27 (0x8000000U << ETH_MACSTSR_TSS_Pos) /*!< 0x08000000 */
#define ETH_MACSTSR_TSS_28 (0x10000000U << ETH_MACSTSR_TSS_Pos) /*!< 0x10000000 */
#define ETH_MACSTSR_TSS_29 (0x20000000U << ETH_MACSTSR_TSS_Pos) /*!< 0x20000000 */
#define ETH_MACSTSR_TSS_30 (0x40000000U << ETH_MACSTSR_TSS_Pos) /*!< 0x40000000 */
#define ETH_MACSTSR_TSS_31 (0x80000000U << ETH_MACSTSR_TSS_Pos) /*!< 0x80000000 */
/************** Bit definition for ETH_MACSTNR register **************/
#define ETH_MACSTNR_TSSS_Pos (0U)
#define ETH_MACSTNR_TSSS_Msk (0x7FFFFFFFU << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */
#define ETH_MACSTNR_TSSS ETH_MACSTNR_TSSS_Msk /*!< Timestamp Sub-seconds */
#define ETH_MACSTNR_TSSS_0 (0x1U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00000001 */
#define ETH_MACSTNR_TSSS_1 (0x2U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00000002 */
#define ETH_MACSTNR_TSSS_2 (0x4U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00000004 */
#define ETH_MACSTNR_TSSS_3 (0x8U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00000008 */
#define ETH_MACSTNR_TSSS_4 (0x10U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00000010 */
#define ETH_MACSTNR_TSSS_5 (0x20U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00000020 */
#define ETH_MACSTNR_TSSS_6 (0x40U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00000040 */
#define ETH_MACSTNR_TSSS_7 (0x80U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00000080 */
#define ETH_MACSTNR_TSSS_8 (0x100U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00000100 */
#define ETH_MACSTNR_TSSS_9 (0x200U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00000200 */
#define ETH_MACSTNR_TSSS_10 (0x400U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00000400 */
#define ETH_MACSTNR_TSSS_11 (0x800U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00000800 */
#define ETH_MACSTNR_TSSS_12 (0x1000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00001000 */
#define ETH_MACSTNR_TSSS_13 (0x2000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00002000 */
#define ETH_MACSTNR_TSSS_14 (0x4000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00004000 */
#define ETH_MACSTNR_TSSS_15 (0x8000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00008000 */
#define ETH_MACSTNR_TSSS_16 (0x10000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00010000 */
#define ETH_MACSTNR_TSSS_17 (0x20000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00020000 */
#define ETH_MACSTNR_TSSS_18 (0x40000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00040000 */
#define ETH_MACSTNR_TSSS_19 (0x80000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00080000 */
#define ETH_MACSTNR_TSSS_20 (0x100000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00100000 */
#define ETH_MACSTNR_TSSS_21 (0x200000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00200000 */
#define ETH_MACSTNR_TSSS_22 (0x400000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00400000 */
#define ETH_MACSTNR_TSSS_23 (0x800000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x00800000 */
#define ETH_MACSTNR_TSSS_24 (0x1000000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x01000000 */
#define ETH_MACSTNR_TSSS_25 (0x2000000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x02000000 */
#define ETH_MACSTNR_TSSS_26 (0x4000000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x04000000 */
#define ETH_MACSTNR_TSSS_27 (0x8000000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x08000000 */
#define ETH_MACSTNR_TSSS_28 (0x10000000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x10000000 */
#define ETH_MACSTNR_TSSS_29 (0x20000000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x20000000 */
#define ETH_MACSTNR_TSSS_30 (0x40000000U << ETH_MACSTNR_TSSS_Pos) /*!< 0x40000000 */
/************* Bit definition for ETH_MACSTSUR register **************/
#define ETH_MACSTSUR_TSS_Pos (0U)
#define ETH_MACSTSUR_TSS_Msk (0xFFFFFFFFU << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACSTSUR_TSS ETH_MACSTSUR_TSS_Msk /*!< Timestamp Seconds */
#define ETH_MACSTSUR_TSS_0 (0x1U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00000001 */
#define ETH_MACSTSUR_TSS_1 (0x2U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00000002 */
#define ETH_MACSTSUR_TSS_2 (0x4U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00000004 */
#define ETH_MACSTSUR_TSS_3 (0x8U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00000008 */
#define ETH_MACSTSUR_TSS_4 (0x10U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00000010 */
#define ETH_MACSTSUR_TSS_5 (0x20U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00000020 */
#define ETH_MACSTSUR_TSS_6 (0x40U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00000040 */
#define ETH_MACSTSUR_TSS_7 (0x80U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00000080 */
#define ETH_MACSTSUR_TSS_8 (0x100U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00000100 */
#define ETH_MACSTSUR_TSS_9 (0x200U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00000200 */
#define ETH_MACSTSUR_TSS_10 (0x400U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00000400 */
#define ETH_MACSTSUR_TSS_11 (0x800U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00000800 */
#define ETH_MACSTSUR_TSS_12 (0x1000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00001000 */
#define ETH_MACSTSUR_TSS_13 (0x2000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00002000 */
#define ETH_MACSTSUR_TSS_14 (0x4000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00004000 */
#define ETH_MACSTSUR_TSS_15 (0x8000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00008000 */
#define ETH_MACSTSUR_TSS_16 (0x10000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00010000 */
#define ETH_MACSTSUR_TSS_17 (0x20000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00020000 */
#define ETH_MACSTSUR_TSS_18 (0x40000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00040000 */
#define ETH_MACSTSUR_TSS_19 (0x80000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00080000 */
#define ETH_MACSTSUR_TSS_20 (0x100000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00100000 */
#define ETH_MACSTSUR_TSS_21 (0x200000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00200000 */
#define ETH_MACSTSUR_TSS_22 (0x400000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00400000 */
#define ETH_MACSTSUR_TSS_23 (0x800000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x00800000 */
#define ETH_MACSTSUR_TSS_24 (0x1000000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x01000000 */
#define ETH_MACSTSUR_TSS_25 (0x2000000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x02000000 */
#define ETH_MACSTSUR_TSS_26 (0x4000000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x04000000 */
#define ETH_MACSTSUR_TSS_27 (0x8000000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x08000000 */
#define ETH_MACSTSUR_TSS_28 (0x10000000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x10000000 */
#define ETH_MACSTSUR_TSS_29 (0x20000000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x20000000 */
#define ETH_MACSTSUR_TSS_30 (0x40000000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x40000000 */
#define ETH_MACSTSUR_TSS_31 (0x80000000U << ETH_MACSTSUR_TSS_Pos) /*!< 0x80000000 */
/************* Bit definition for ETH_MACSTNUR register **************/
#define ETH_MACSTNUR_TSSS_Pos (0U)
#define ETH_MACSTNUR_TSSS_Msk (0x7FFFFFFFU << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */
#define ETH_MACSTNUR_TSSS ETH_MACSTNUR_TSSS_Msk /*!< Timestamp Sub-seconds */
#define ETH_MACSTNUR_TSSS_0 (0x1U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00000001 */
#define ETH_MACSTNUR_TSSS_1 (0x2U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00000002 */
#define ETH_MACSTNUR_TSSS_2 (0x4U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00000004 */
#define ETH_MACSTNUR_TSSS_3 (0x8U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00000008 */
#define ETH_MACSTNUR_TSSS_4 (0x10U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00000010 */
#define ETH_MACSTNUR_TSSS_5 (0x20U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00000020 */
#define ETH_MACSTNUR_TSSS_6 (0x40U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00000040 */
#define ETH_MACSTNUR_TSSS_7 (0x80U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00000080 */
#define ETH_MACSTNUR_TSSS_8 (0x100U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00000100 */
#define ETH_MACSTNUR_TSSS_9 (0x200U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00000200 */
#define ETH_MACSTNUR_TSSS_10 (0x400U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00000400 */
#define ETH_MACSTNUR_TSSS_11 (0x800U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00000800 */
#define ETH_MACSTNUR_TSSS_12 (0x1000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00001000 */
#define ETH_MACSTNUR_TSSS_13 (0x2000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00002000 */
#define ETH_MACSTNUR_TSSS_14 (0x4000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00004000 */
#define ETH_MACSTNUR_TSSS_15 (0x8000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00008000 */
#define ETH_MACSTNUR_TSSS_16 (0x10000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00010000 */
#define ETH_MACSTNUR_TSSS_17 (0x20000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00020000 */
#define ETH_MACSTNUR_TSSS_18 (0x40000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00040000 */
#define ETH_MACSTNUR_TSSS_19 (0x80000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00080000 */
#define ETH_MACSTNUR_TSSS_20 (0x100000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00100000 */
#define ETH_MACSTNUR_TSSS_21 (0x200000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00200000 */
#define ETH_MACSTNUR_TSSS_22 (0x400000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00400000 */
#define ETH_MACSTNUR_TSSS_23 (0x800000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x00800000 */
#define ETH_MACSTNUR_TSSS_24 (0x1000000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x01000000 */
#define ETH_MACSTNUR_TSSS_25 (0x2000000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x02000000 */
#define ETH_MACSTNUR_TSSS_26 (0x4000000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x04000000 */
#define ETH_MACSTNUR_TSSS_27 (0x8000000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x08000000 */
#define ETH_MACSTNUR_TSSS_28 (0x10000000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x10000000 */
#define ETH_MACSTNUR_TSSS_29 (0x20000000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x20000000 */
#define ETH_MACSTNUR_TSSS_30 (0x40000000U << ETH_MACSTNUR_TSSS_Pos) /*!< 0x40000000 */
#define ETH_MACSTNUR_ADDSUB_Pos (31U)
#define ETH_MACSTNUR_ADDSUB_Msk (0x1U << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */
#define ETH_MACSTNUR_ADDSUB ETH_MACSTNUR_ADDSUB_Msk /*!< Add or Subtract Time */
/************** Bit definition for ETH_MACTSAR register **************/
#define ETH_MACTSAR_TSAR_Pos (0U)
#define ETH_MACTSAR_TSAR_Msk (0xFFFFFFFFU << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACTSAR_TSAR ETH_MACTSAR_TSAR_Msk /*!< Timestamp Addend Register */
#define ETH_MACTSAR_TSAR_0 (0x1U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00000001 */
#define ETH_MACTSAR_TSAR_1 (0x2U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00000002 */
#define ETH_MACTSAR_TSAR_2 (0x4U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00000004 */
#define ETH_MACTSAR_TSAR_3 (0x8U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00000008 */
#define ETH_MACTSAR_TSAR_4 (0x10U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00000010 */
#define ETH_MACTSAR_TSAR_5 (0x20U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00000020 */
#define ETH_MACTSAR_TSAR_6 (0x40U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00000040 */
#define ETH_MACTSAR_TSAR_7 (0x80U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00000080 */
#define ETH_MACTSAR_TSAR_8 (0x100U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00000100 */
#define ETH_MACTSAR_TSAR_9 (0x200U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00000200 */
#define ETH_MACTSAR_TSAR_10 (0x400U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00000400 */
#define ETH_MACTSAR_TSAR_11 (0x800U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00000800 */
#define ETH_MACTSAR_TSAR_12 (0x1000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00001000 */
#define ETH_MACTSAR_TSAR_13 (0x2000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00002000 */
#define ETH_MACTSAR_TSAR_14 (0x4000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00004000 */
#define ETH_MACTSAR_TSAR_15 (0x8000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00008000 */
#define ETH_MACTSAR_TSAR_16 (0x10000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00010000 */
#define ETH_MACTSAR_TSAR_17 (0x20000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00020000 */
#define ETH_MACTSAR_TSAR_18 (0x40000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00040000 */
#define ETH_MACTSAR_TSAR_19 (0x80000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00080000 */
#define ETH_MACTSAR_TSAR_20 (0x100000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00100000 */
#define ETH_MACTSAR_TSAR_21 (0x200000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00200000 */
#define ETH_MACTSAR_TSAR_22 (0x400000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00400000 */
#define ETH_MACTSAR_TSAR_23 (0x800000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x00800000 */
#define ETH_MACTSAR_TSAR_24 (0x1000000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x01000000 */
#define ETH_MACTSAR_TSAR_25 (0x2000000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x02000000 */
#define ETH_MACTSAR_TSAR_26 (0x4000000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x04000000 */
#define ETH_MACTSAR_TSAR_27 (0x8000000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x08000000 */
#define ETH_MACTSAR_TSAR_28 (0x10000000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x10000000 */
#define ETH_MACTSAR_TSAR_29 (0x20000000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x20000000 */
#define ETH_MACTSAR_TSAR_30 (0x40000000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x40000000 */
#define ETH_MACTSAR_TSAR_31 (0x80000000U << ETH_MACTSAR_TSAR_Pos) /*!< 0x80000000 */
/************** Bit definition for ETH_MACTSSR register **************/
#define ETH_MACTSSR_TSSOVF_Pos (0U)
#define ETH_MACTSSR_TSSOVF_Msk (0x1U << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */
#define ETH_MACTSSR_TSSOVF ETH_MACTSSR_TSSOVF_Msk /*!< Timestamp Seconds Overflow */
#define ETH_MACTSSR_TSTARGT0_Pos (1U)
#define ETH_MACTSSR_TSTARGT0_Msk (0x1U << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */
#define ETH_MACTSSR_TSTARGT0 ETH_MACTSSR_TSTARGT0_Msk /*!< Timestamp Target Time Reached */
#define ETH_MACTSSR_AUXTSTRIG_Pos (2U)
#define ETH_MACTSSR_AUXTSTRIG_Msk (0x1U << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */
#define ETH_MACTSSR_AUXTSTRIG ETH_MACTSSR_AUXTSTRIG_Msk /*!< Auxiliary Timestamp Trigger Snapshot */
#define ETH_MACTSSR_TSTRGTERR0_Pos (3U)
#define ETH_MACTSSR_TSTRGTERR0_Msk (0x1U << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */
#define ETH_MACTSSR_TSTRGTERR0 ETH_MACTSSR_TSTRGTERR0_Msk /*!< Timestamp Target Time Error */
#define ETH_MACTSSR_TXTSSIS_Pos (15U)
#define ETH_MACTSSR_TXTSSIS_Msk (0x1U << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */
#define ETH_MACTSSR_TXTSSIS ETH_MACTSSR_TXTSSIS_Msk /*!< Tx Timestamp Status Interrupt Status */
#define ETH_MACTSSR_ATSSTN_Pos (16U)
#define ETH_MACTSSR_ATSSTN_Msk (0xFU << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */
#define ETH_MACTSSR_ATSSTN ETH_MACTSSR_ATSSTN_Msk /*!< Auxiliary Timestamp Snapshot Trigger Identifier */
#define ETH_MACTSSR_ATSSTN_0 (0x1U << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x00010000 */
#define ETH_MACTSSR_ATSSTN_1 (0x2U << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x00020000 */
#define ETH_MACTSSR_ATSSTN_2 (0x4U << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x00040000 */
#define ETH_MACTSSR_ATSSTN_3 (0x8U << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x00080000 */
#define ETH_MACTSSR_ATSSTM_Pos (24U)
#define ETH_MACTSSR_ATSSTM_Msk (0x1U << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */
#define ETH_MACTSSR_ATSSTM ETH_MACTSSR_ATSSTM_Msk /*!< Auxiliary Timestamp Snapshot Trigger Missed */
#define ETH_MACTSSR_ATSNS_Pos (25U)
#define ETH_MACTSSR_ATSNS_Msk (0x1FU << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */
#define ETH_MACTSSR_ATSNS ETH_MACTSSR_ATSNS_Msk /*!< Number of Auxiliary Timestamp Snapshots */
#define ETH_MACTSSR_ATSNS_0 (0x1U << ETH_MACTSSR_ATSNS_Pos) /*!< 0x02000000 */
#define ETH_MACTSSR_ATSNS_1 (0x2U << ETH_MACTSSR_ATSNS_Pos) /*!< 0x04000000 */
#define ETH_MACTSSR_ATSNS_2 (0x4U << ETH_MACTSSR_ATSNS_Pos) /*!< 0x08000000 */
#define ETH_MACTSSR_ATSNS_3 (0x8U << ETH_MACTSSR_ATSNS_Pos) /*!< 0x10000000 */
#define ETH_MACTSSR_ATSNS_4 (0x10U << ETH_MACTSSR_ATSNS_Pos) /*!< 0x20000000 */
/************ Bit definition for ETH_MACTXTSSNR register *************/
#define ETH_MACTXTSSNR_TXTSSLO_Pos (0U)
#define ETH_MACTXTSSNR_TXTSSLO_Msk (0x7FFFFFFFU << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */
#define ETH_MACTXTSSNR_TXTSSLO ETH_MACTXTSSNR_TXTSSLO_Msk /*!< Transmit Timestamp Status Low */
#define ETH_MACTXTSSNR_TXTSSLO_0 (0x1U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00000001 */
#define ETH_MACTXTSSNR_TXTSSLO_1 (0x2U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00000002 */
#define ETH_MACTXTSSNR_TXTSSLO_2 (0x4U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00000004 */
#define ETH_MACTXTSSNR_TXTSSLO_3 (0x8U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00000008 */
#define ETH_MACTXTSSNR_TXTSSLO_4 (0x10U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00000010 */
#define ETH_MACTXTSSNR_TXTSSLO_5 (0x20U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00000020 */
#define ETH_MACTXTSSNR_TXTSSLO_6 (0x40U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00000040 */
#define ETH_MACTXTSSNR_TXTSSLO_7 (0x80U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00000080 */
#define ETH_MACTXTSSNR_TXTSSLO_8 (0x100U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00000100 */
#define ETH_MACTXTSSNR_TXTSSLO_9 (0x200U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00000200 */
#define ETH_MACTXTSSNR_TXTSSLO_10 (0x400U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00000400 */
#define ETH_MACTXTSSNR_TXTSSLO_11 (0x800U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00000800 */
#define ETH_MACTXTSSNR_TXTSSLO_12 (0x1000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00001000 */
#define ETH_MACTXTSSNR_TXTSSLO_13 (0x2000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00002000 */
#define ETH_MACTXTSSNR_TXTSSLO_14 (0x4000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00004000 */
#define ETH_MACTXTSSNR_TXTSSLO_15 (0x8000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00008000 */
#define ETH_MACTXTSSNR_TXTSSLO_16 (0x10000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00010000 */
#define ETH_MACTXTSSNR_TXTSSLO_17 (0x20000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00020000 */
#define ETH_MACTXTSSNR_TXTSSLO_18 (0x40000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00040000 */
#define ETH_MACTXTSSNR_TXTSSLO_19 (0x80000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00080000 */
#define ETH_MACTXTSSNR_TXTSSLO_20 (0x100000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00100000 */
#define ETH_MACTXTSSNR_TXTSSLO_21 (0x200000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00200000 */
#define ETH_MACTXTSSNR_TXTSSLO_22 (0x400000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00400000 */
#define ETH_MACTXTSSNR_TXTSSLO_23 (0x800000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x00800000 */
#define ETH_MACTXTSSNR_TXTSSLO_24 (0x1000000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x01000000 */
#define ETH_MACTXTSSNR_TXTSSLO_25 (0x2000000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x02000000 */
#define ETH_MACTXTSSNR_TXTSSLO_26 (0x4000000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x04000000 */
#define ETH_MACTXTSSNR_TXTSSLO_27 (0x8000000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x08000000 */
#define ETH_MACTXTSSNR_TXTSSLO_28 (0x10000000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x10000000 */
#define ETH_MACTXTSSNR_TXTSSLO_29 (0x20000000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x20000000 */
#define ETH_MACTXTSSNR_TXTSSLO_30 (0x40000000U << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x40000000 */
#define ETH_MACTXTSSNR_TXTSSMIS_Pos (31U)
#define ETH_MACTXTSSNR_TXTSSMIS_Msk (0x1U << ETH_MACTXTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */
#define ETH_MACTXTSSNR_TXTSSMIS ETH_MACTXTSSNR_TXTSSMIS_Msk /*!< Transmit Timestamp Status Missed */
/************ Bit definition for ETH_MACTXTSSSR register *************/
#define ETH_MACTXTSSSR_TXTSSHI_Pos (0U)
#define ETH_MACTXTSSSR_TXTSSHI_Msk (0xFFFFFFFFU << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACTXTSSSR_TXTSSHI ETH_MACTXTSSSR_TXTSSHI_Msk /*!< Transmit Timestamp Status High */
#define ETH_MACTXTSSSR_TXTSSHI_0 (0x1U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00000001 */
#define ETH_MACTXTSSSR_TXTSSHI_1 (0x2U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00000002 */
#define ETH_MACTXTSSSR_TXTSSHI_2 (0x4U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00000004 */
#define ETH_MACTXTSSSR_TXTSSHI_3 (0x8U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00000008 */
#define ETH_MACTXTSSSR_TXTSSHI_4 (0x10U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00000010 */
#define ETH_MACTXTSSSR_TXTSSHI_5 (0x20U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00000020 */
#define ETH_MACTXTSSSR_TXTSSHI_6 (0x40U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00000040 */
#define ETH_MACTXTSSSR_TXTSSHI_7 (0x80U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00000080 */
#define ETH_MACTXTSSSR_TXTSSHI_8 (0x100U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00000100 */
#define ETH_MACTXTSSSR_TXTSSHI_9 (0x200U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00000200 */
#define ETH_MACTXTSSSR_TXTSSHI_10 (0x400U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00000400 */
#define ETH_MACTXTSSSR_TXTSSHI_11 (0x800U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00000800 */
#define ETH_MACTXTSSSR_TXTSSHI_12 (0x1000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00001000 */
#define ETH_MACTXTSSSR_TXTSSHI_13 (0x2000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00002000 */
#define ETH_MACTXTSSSR_TXTSSHI_14 (0x4000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00004000 */
#define ETH_MACTXTSSSR_TXTSSHI_15 (0x8000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00008000 */
#define ETH_MACTXTSSSR_TXTSSHI_16 (0x10000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00010000 */
#define ETH_MACTXTSSSR_TXTSSHI_17 (0x20000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00020000 */
#define ETH_MACTXTSSSR_TXTSSHI_18 (0x40000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00040000 */
#define ETH_MACTXTSSSR_TXTSSHI_19 (0x80000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00080000 */
#define ETH_MACTXTSSSR_TXTSSHI_20 (0x100000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00100000 */
#define ETH_MACTXTSSSR_TXTSSHI_21 (0x200000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00200000 */
#define ETH_MACTXTSSSR_TXTSSHI_22 (0x400000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00400000 */
#define ETH_MACTXTSSSR_TXTSSHI_23 (0x800000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x00800000 */
#define ETH_MACTXTSSSR_TXTSSHI_24 (0x1000000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x01000000 */
#define ETH_MACTXTSSSR_TXTSSHI_25 (0x2000000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x02000000 */
#define ETH_MACTXTSSSR_TXTSSHI_26 (0x4000000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x04000000 */
#define ETH_MACTXTSSSR_TXTSSHI_27 (0x8000000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x08000000 */
#define ETH_MACTXTSSSR_TXTSSHI_28 (0x10000000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x10000000 */
#define ETH_MACTXTSSSR_TXTSSHI_29 (0x20000000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x20000000 */
#define ETH_MACTXTSSSR_TXTSSHI_30 (0x40000000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x40000000 */
#define ETH_MACTXTSSSR_TXTSSHI_31 (0x80000000U << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0x80000000 */
/************** Bit definition for ETH_MACACR register ***************/
#define ETH_MACACR_ATSFC_Pos (0U)
#define ETH_MACACR_ATSFC_Msk (0x1U << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */
#define ETH_MACACR_ATSFC ETH_MACACR_ATSFC_Msk /*!< Auxiliary Snapshot FIFO Clear */
#define ETH_MACACR_ATSEN0_Pos (4U)
#define ETH_MACACR_ATSEN0_Msk (0x1U << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */
#define ETH_MACACR_ATSEN0 ETH_MACACR_ATSEN0_Msk /*!< Auxiliary Snapshot 0 Enable */
#define ETH_MACACR_ATSEN1_Pos (5U)
#define ETH_MACACR_ATSEN1_Msk (0x1U << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */
#define ETH_MACACR_ATSEN1 ETH_MACACR_ATSEN1_Msk /*!< Auxiliary Snapshot 1 Enable */
#define ETH_MACACR_ATSEN2_Pos (6U)
#define ETH_MACACR_ATSEN2_Msk (0x1U << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */
#define ETH_MACACR_ATSEN2 ETH_MACACR_ATSEN2_Msk /*!< Auxiliary Snapshot 2 Enable */
#define ETH_MACACR_ATSEN3_Pos (7U)
#define ETH_MACACR_ATSEN3_Msk (0x1U << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */
#define ETH_MACACR_ATSEN3 ETH_MACACR_ATSEN3_Msk /*!< Auxiliary Snapshot 3 Enable */
/************* Bit definition for ETH_MACATSNR register **************/
#define ETH_MACATSNR_AUXTSLO_Pos (0U)
#define ETH_MACATSNR_AUXTSLO_Msk (0x7FFFFFFFU << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */
#define ETH_MACATSNR_AUXTSLO ETH_MACATSNR_AUXTSLO_Msk /*!< Auxiliary Timestamp */
#define ETH_MACATSNR_AUXTSLO_0 (0x1U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00000001 */
#define ETH_MACATSNR_AUXTSLO_1 (0x2U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00000002 */
#define ETH_MACATSNR_AUXTSLO_2 (0x4U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00000004 */
#define ETH_MACATSNR_AUXTSLO_3 (0x8U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00000008 */
#define ETH_MACATSNR_AUXTSLO_4 (0x10U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00000010 */
#define ETH_MACATSNR_AUXTSLO_5 (0x20U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00000020 */
#define ETH_MACATSNR_AUXTSLO_6 (0x40U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00000040 */
#define ETH_MACATSNR_AUXTSLO_7 (0x80U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00000080 */
#define ETH_MACATSNR_AUXTSLO_8 (0x100U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00000100 */
#define ETH_MACATSNR_AUXTSLO_9 (0x200U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00000200 */
#define ETH_MACATSNR_AUXTSLO_10 (0x400U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00000400 */
#define ETH_MACATSNR_AUXTSLO_11 (0x800U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00000800 */
#define ETH_MACATSNR_AUXTSLO_12 (0x1000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00001000 */
#define ETH_MACATSNR_AUXTSLO_13 (0x2000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00002000 */
#define ETH_MACATSNR_AUXTSLO_14 (0x4000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00004000 */
#define ETH_MACATSNR_AUXTSLO_15 (0x8000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00008000 */
#define ETH_MACATSNR_AUXTSLO_16 (0x10000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00010000 */
#define ETH_MACATSNR_AUXTSLO_17 (0x20000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00020000 */
#define ETH_MACATSNR_AUXTSLO_18 (0x40000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00040000 */
#define ETH_MACATSNR_AUXTSLO_19 (0x80000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00080000 */
#define ETH_MACATSNR_AUXTSLO_20 (0x100000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00100000 */
#define ETH_MACATSNR_AUXTSLO_21 (0x200000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00200000 */
#define ETH_MACATSNR_AUXTSLO_22 (0x400000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00400000 */
#define ETH_MACATSNR_AUXTSLO_23 (0x800000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x00800000 */
#define ETH_MACATSNR_AUXTSLO_24 (0x1000000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x01000000 */
#define ETH_MACATSNR_AUXTSLO_25 (0x2000000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x02000000 */
#define ETH_MACATSNR_AUXTSLO_26 (0x4000000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x04000000 */
#define ETH_MACATSNR_AUXTSLO_27 (0x8000000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x08000000 */
#define ETH_MACATSNR_AUXTSLO_28 (0x10000000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x10000000 */
#define ETH_MACATSNR_AUXTSLO_29 (0x20000000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x20000000 */
#define ETH_MACATSNR_AUXTSLO_30 (0x40000000U << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x40000000 */
/************* Bit definition for ETH_MACATSSR register **************/
#define ETH_MACATSSR_AUXTSHI_Pos (0U)
#define ETH_MACATSSR_AUXTSHI_Msk (0xFFFFFFFFU << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACATSSR_AUXTSHI ETH_MACATSSR_AUXTSHI_Msk /*!< Auxiliary Timestamp */
#define ETH_MACATSSR_AUXTSHI_0 (0x1U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00000001 */
#define ETH_MACATSSR_AUXTSHI_1 (0x2U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00000002 */
#define ETH_MACATSSR_AUXTSHI_2 (0x4U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00000004 */
#define ETH_MACATSSR_AUXTSHI_3 (0x8U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00000008 */
#define ETH_MACATSSR_AUXTSHI_4 (0x10U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00000010 */
#define ETH_MACATSSR_AUXTSHI_5 (0x20U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00000020 */
#define ETH_MACATSSR_AUXTSHI_6 (0x40U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00000040 */
#define ETH_MACATSSR_AUXTSHI_7 (0x80U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00000080 */
#define ETH_MACATSSR_AUXTSHI_8 (0x100U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00000100 */
#define ETH_MACATSSR_AUXTSHI_9 (0x200U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00000200 */
#define ETH_MACATSSR_AUXTSHI_10 (0x400U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00000400 */
#define ETH_MACATSSR_AUXTSHI_11 (0x800U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00000800 */
#define ETH_MACATSSR_AUXTSHI_12 (0x1000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00001000 */
#define ETH_MACATSSR_AUXTSHI_13 (0x2000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00002000 */
#define ETH_MACATSSR_AUXTSHI_14 (0x4000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00004000 */
#define ETH_MACATSSR_AUXTSHI_15 (0x8000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00008000 */
#define ETH_MACATSSR_AUXTSHI_16 (0x10000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00010000 */
#define ETH_MACATSSR_AUXTSHI_17 (0x20000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00020000 */
#define ETH_MACATSSR_AUXTSHI_18 (0x40000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00040000 */
#define ETH_MACATSSR_AUXTSHI_19 (0x80000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00080000 */
#define ETH_MACATSSR_AUXTSHI_20 (0x100000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00100000 */
#define ETH_MACATSSR_AUXTSHI_21 (0x200000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00200000 */
#define ETH_MACATSSR_AUXTSHI_22 (0x400000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00400000 */
#define ETH_MACATSSR_AUXTSHI_23 (0x800000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x00800000 */
#define ETH_MACATSSR_AUXTSHI_24 (0x1000000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x01000000 */
#define ETH_MACATSSR_AUXTSHI_25 (0x2000000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x02000000 */
#define ETH_MACATSSR_AUXTSHI_26 (0x4000000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x04000000 */
#define ETH_MACATSSR_AUXTSHI_27 (0x8000000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x08000000 */
#define ETH_MACATSSR_AUXTSHI_28 (0x10000000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x10000000 */
#define ETH_MACATSSR_AUXTSHI_29 (0x20000000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x20000000 */
#define ETH_MACATSSR_AUXTSHI_30 (0x40000000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x40000000 */
#define ETH_MACATSSR_AUXTSHI_31 (0x80000000U << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0x80000000 */
/************* Bit definition for ETH_MACTSIACR register *************/
#define ETH_MACTSIACR_OSTIAC_Pos (0U)
#define ETH_MACTSIACR_OSTIAC_Msk (0xFFFFFFFFU << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACTSIACR_OSTIAC ETH_MACTSIACR_OSTIAC_Msk /*!< One-Step Timestamp Ingress Asymmetry Correction */
#define ETH_MACTSIACR_OSTIAC_0 (0x1U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00000001 */
#define ETH_MACTSIACR_OSTIAC_1 (0x2U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00000002 */
#define ETH_MACTSIACR_OSTIAC_2 (0x4U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00000004 */
#define ETH_MACTSIACR_OSTIAC_3 (0x8U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00000008 */
#define ETH_MACTSIACR_OSTIAC_4 (0x10U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00000010 */
#define ETH_MACTSIACR_OSTIAC_5 (0x20U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00000020 */
#define ETH_MACTSIACR_OSTIAC_6 (0x40U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00000040 */
#define ETH_MACTSIACR_OSTIAC_7 (0x80U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00000080 */
#define ETH_MACTSIACR_OSTIAC_8 (0x100U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00000100 */
#define ETH_MACTSIACR_OSTIAC_9 (0x200U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00000200 */
#define ETH_MACTSIACR_OSTIAC_10 (0x400U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00000400 */
#define ETH_MACTSIACR_OSTIAC_11 (0x800U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00000800 */
#define ETH_MACTSIACR_OSTIAC_12 (0x1000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00001000 */
#define ETH_MACTSIACR_OSTIAC_13 (0x2000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00002000 */
#define ETH_MACTSIACR_OSTIAC_14 (0x4000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00004000 */
#define ETH_MACTSIACR_OSTIAC_15 (0x8000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00008000 */
#define ETH_MACTSIACR_OSTIAC_16 (0x10000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00010000 */
#define ETH_MACTSIACR_OSTIAC_17 (0x20000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00020000 */
#define ETH_MACTSIACR_OSTIAC_18 (0x40000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00040000 */
#define ETH_MACTSIACR_OSTIAC_19 (0x80000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00080000 */
#define ETH_MACTSIACR_OSTIAC_20 (0x100000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00100000 */
#define ETH_MACTSIACR_OSTIAC_21 (0x200000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00200000 */
#define ETH_MACTSIACR_OSTIAC_22 (0x400000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00400000 */
#define ETH_MACTSIACR_OSTIAC_23 (0x800000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x00800000 */
#define ETH_MACTSIACR_OSTIAC_24 (0x1000000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x01000000 */
#define ETH_MACTSIACR_OSTIAC_25 (0x2000000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x02000000 */
#define ETH_MACTSIACR_OSTIAC_26 (0x4000000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x04000000 */
#define ETH_MACTSIACR_OSTIAC_27 (0x8000000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x08000000 */
#define ETH_MACTSIACR_OSTIAC_28 (0x10000000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x10000000 */
#define ETH_MACTSIACR_OSTIAC_29 (0x20000000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x20000000 */
#define ETH_MACTSIACR_OSTIAC_30 (0x40000000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x40000000 */
#define ETH_MACTSIACR_OSTIAC_31 (0x80000000U << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0x80000000 */
/************* Bit definition for ETH_MACTSEACR register *************/
#define ETH_MACTSEACR_OSTEAC_Pos (0U)
#define ETH_MACTSEACR_OSTEAC_Msk (0xFFFFFFFFU << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACTSEACR_OSTEAC ETH_MACTSEACR_OSTEAC_Msk /*!< One-Step Timestamp Egress Asymmetry Correction */
#define ETH_MACTSEACR_OSTEAC_0 (0x1U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00000001 */
#define ETH_MACTSEACR_OSTEAC_1 (0x2U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00000002 */
#define ETH_MACTSEACR_OSTEAC_2 (0x4U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00000004 */
#define ETH_MACTSEACR_OSTEAC_3 (0x8U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00000008 */
#define ETH_MACTSEACR_OSTEAC_4 (0x10U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00000010 */
#define ETH_MACTSEACR_OSTEAC_5 (0x20U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00000020 */
#define ETH_MACTSEACR_OSTEAC_6 (0x40U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00000040 */
#define ETH_MACTSEACR_OSTEAC_7 (0x80U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00000080 */
#define ETH_MACTSEACR_OSTEAC_8 (0x100U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00000100 */
#define ETH_MACTSEACR_OSTEAC_9 (0x200U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00000200 */
#define ETH_MACTSEACR_OSTEAC_10 (0x400U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00000400 */
#define ETH_MACTSEACR_OSTEAC_11 (0x800U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00000800 */
#define ETH_MACTSEACR_OSTEAC_12 (0x1000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00001000 */
#define ETH_MACTSEACR_OSTEAC_13 (0x2000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00002000 */
#define ETH_MACTSEACR_OSTEAC_14 (0x4000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00004000 */
#define ETH_MACTSEACR_OSTEAC_15 (0x8000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00008000 */
#define ETH_MACTSEACR_OSTEAC_16 (0x10000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00010000 */
#define ETH_MACTSEACR_OSTEAC_17 (0x20000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00020000 */
#define ETH_MACTSEACR_OSTEAC_18 (0x40000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00040000 */
#define ETH_MACTSEACR_OSTEAC_19 (0x80000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00080000 */
#define ETH_MACTSEACR_OSTEAC_20 (0x100000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00100000 */
#define ETH_MACTSEACR_OSTEAC_21 (0x200000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00200000 */
#define ETH_MACTSEACR_OSTEAC_22 (0x400000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00400000 */
#define ETH_MACTSEACR_OSTEAC_23 (0x800000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x00800000 */
#define ETH_MACTSEACR_OSTEAC_24 (0x1000000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x01000000 */
#define ETH_MACTSEACR_OSTEAC_25 (0x2000000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x02000000 */
#define ETH_MACTSEACR_OSTEAC_26 (0x4000000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x04000000 */
#define ETH_MACTSEACR_OSTEAC_27 (0x8000000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x08000000 */
#define ETH_MACTSEACR_OSTEAC_28 (0x10000000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x10000000 */
#define ETH_MACTSEACR_OSTEAC_29 (0x20000000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x20000000 */
#define ETH_MACTSEACR_OSTEAC_30 (0x40000000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x40000000 */
#define ETH_MACTSEACR_OSTEAC_31 (0x80000000U << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0x80000000 */
/************* Bit definition for ETH_MACTSICNR register *************/
#define ETH_MACTSICNR_TSIC_Pos (0U)
#define ETH_MACTSICNR_TSIC_Msk (0xFFFFFFFFU << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACTSICNR_TSIC ETH_MACTSICNR_TSIC_Msk /*!< Timestamp Ingress Correction */
#define ETH_MACTSICNR_TSIC_0 (0x1U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00000001 */
#define ETH_MACTSICNR_TSIC_1 (0x2U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00000002 */
#define ETH_MACTSICNR_TSIC_2 (0x4U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00000004 */
#define ETH_MACTSICNR_TSIC_3 (0x8U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00000008 */
#define ETH_MACTSICNR_TSIC_4 (0x10U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00000010 */
#define ETH_MACTSICNR_TSIC_5 (0x20U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00000020 */
#define ETH_MACTSICNR_TSIC_6 (0x40U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00000040 */
#define ETH_MACTSICNR_TSIC_7 (0x80U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00000080 */
#define ETH_MACTSICNR_TSIC_8 (0x100U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00000100 */
#define ETH_MACTSICNR_TSIC_9 (0x200U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00000200 */
#define ETH_MACTSICNR_TSIC_10 (0x400U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00000400 */
#define ETH_MACTSICNR_TSIC_11 (0x800U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00000800 */
#define ETH_MACTSICNR_TSIC_12 (0x1000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00001000 */
#define ETH_MACTSICNR_TSIC_13 (0x2000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00002000 */
#define ETH_MACTSICNR_TSIC_14 (0x4000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00004000 */
#define ETH_MACTSICNR_TSIC_15 (0x8000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00008000 */
#define ETH_MACTSICNR_TSIC_16 (0x10000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00010000 */
#define ETH_MACTSICNR_TSIC_17 (0x20000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00020000 */
#define ETH_MACTSICNR_TSIC_18 (0x40000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00040000 */
#define ETH_MACTSICNR_TSIC_19 (0x80000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00080000 */
#define ETH_MACTSICNR_TSIC_20 (0x100000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00100000 */
#define ETH_MACTSICNR_TSIC_21 (0x200000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00200000 */
#define ETH_MACTSICNR_TSIC_22 (0x400000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00400000 */
#define ETH_MACTSICNR_TSIC_23 (0x800000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x00800000 */
#define ETH_MACTSICNR_TSIC_24 (0x1000000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x01000000 */
#define ETH_MACTSICNR_TSIC_25 (0x2000000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x02000000 */
#define ETH_MACTSICNR_TSIC_26 (0x4000000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x04000000 */
#define ETH_MACTSICNR_TSIC_27 (0x8000000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x08000000 */
#define ETH_MACTSICNR_TSIC_28 (0x10000000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x10000000 */
#define ETH_MACTSICNR_TSIC_29 (0x20000000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x20000000 */
#define ETH_MACTSICNR_TSIC_30 (0x40000000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x40000000 */
#define ETH_MACTSICNR_TSIC_31 (0x80000000U << ETH_MACTSICNR_TSIC_Pos) /*!< 0x80000000 */
/************* Bit definition for ETH_MACTSECNR register *************/
#define ETH_MACTSECNR_TSEC_Pos (0U)
#define ETH_MACTSECNR_TSEC_Msk (0xFFFFFFFFU << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACTSECNR_TSEC ETH_MACTSECNR_TSEC_Msk /*!< Timestamp Egress Correction */
#define ETH_MACTSECNR_TSEC_0 (0x1U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00000001 */
#define ETH_MACTSECNR_TSEC_1 (0x2U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00000002 */
#define ETH_MACTSECNR_TSEC_2 (0x4U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00000004 */
#define ETH_MACTSECNR_TSEC_3 (0x8U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00000008 */
#define ETH_MACTSECNR_TSEC_4 (0x10U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00000010 */
#define ETH_MACTSECNR_TSEC_5 (0x20U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00000020 */
#define ETH_MACTSECNR_TSEC_6 (0x40U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00000040 */
#define ETH_MACTSECNR_TSEC_7 (0x80U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00000080 */
#define ETH_MACTSECNR_TSEC_8 (0x100U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00000100 */
#define ETH_MACTSECNR_TSEC_9 (0x200U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00000200 */
#define ETH_MACTSECNR_TSEC_10 (0x400U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00000400 */
#define ETH_MACTSECNR_TSEC_11 (0x800U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00000800 */
#define ETH_MACTSECNR_TSEC_12 (0x1000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00001000 */
#define ETH_MACTSECNR_TSEC_13 (0x2000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00002000 */
#define ETH_MACTSECNR_TSEC_14 (0x4000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00004000 */
#define ETH_MACTSECNR_TSEC_15 (0x8000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00008000 */
#define ETH_MACTSECNR_TSEC_16 (0x10000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00010000 */
#define ETH_MACTSECNR_TSEC_17 (0x20000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00020000 */
#define ETH_MACTSECNR_TSEC_18 (0x40000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00040000 */
#define ETH_MACTSECNR_TSEC_19 (0x80000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00080000 */
#define ETH_MACTSECNR_TSEC_20 (0x100000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00100000 */
#define ETH_MACTSECNR_TSEC_21 (0x200000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00200000 */
#define ETH_MACTSECNR_TSEC_22 (0x400000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00400000 */
#define ETH_MACTSECNR_TSEC_23 (0x800000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x00800000 */
#define ETH_MACTSECNR_TSEC_24 (0x1000000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x01000000 */
#define ETH_MACTSECNR_TSEC_25 (0x2000000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x02000000 */
#define ETH_MACTSECNR_TSEC_26 (0x4000000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x04000000 */
#define ETH_MACTSECNR_TSEC_27 (0x8000000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x08000000 */
#define ETH_MACTSECNR_TSEC_28 (0x10000000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x10000000 */
#define ETH_MACTSECNR_TSEC_29 (0x20000000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x20000000 */
#define ETH_MACTSECNR_TSEC_30 (0x40000000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x40000000 */
#define ETH_MACTSECNR_TSEC_31 (0x80000000U << ETH_MACTSECNR_TSEC_Pos) /*!< 0x80000000 */
/************* Bit definition for ETH_MACPPSCR register **************/
#define ETH_MACPPSCR_PPSCTRL_Pos (0U)
#define ETH_MACPPSCR_PPSCTRL_Msk (0xFU << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */
#define ETH_MACPPSCR_PPSCTRL ETH_MACPPSCR_PPSCTRL_Msk /*!< PPS Output Frequency Control */
#define ETH_MACPPSCR_PPSCTRL_0 (0x1U << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x00000001 */
#define ETH_MACPPSCR_PPSCTRL_1 (0x2U << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x00000002 */
#define ETH_MACPPSCR_PPSCTRL_2 (0x4U << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x00000004 */
#define ETH_MACPPSCR_PPSCTRL_3 (0x8U << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x00000008 */
#define ETH_MACPPSCR_PPSEN0_Pos (4U)
#define ETH_MACPPSCR_PPSEN0_Msk (0x1U << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */
#define ETH_MACPPSCR_PPSEN0 ETH_MACPPSCR_PPSEN0_Msk /*!< Flexible PPS Output Mode Enable */
#define ETH_MACPPSCR_TRGTMODSEL0_Pos (5U)
#define ETH_MACPPSCR_TRGTMODSEL0_Msk (0x3U << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */
#define ETH_MACPPSCR_TRGTMODSEL0 ETH_MACPPSCR_TRGTMODSEL0_Msk /*!< Target Time Register Mode for PPS Output */
#define ETH_MACPPSCR_TRGTMODSEL0_0 (0x1U << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000020 */
#define ETH_MACPPSCR_TRGTMODSEL0_1 (0x2U << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000040 */
#define ETH_MACPPSCR_PPSCMD_Pos (0U)
#define ETH_MACPPSCR_PPSCMD_Msk (0xFU << ETH_MACPPSCR_PPSCMD_Pos) /*!< 0x0000000F */
#define ETH_MACPPSCR_PPSCMD ETH_MACPPSCR_PPSCMD_Msk /*!< Flexible PPS Output (ptp_pps_o[0]) Control */
#define ETH_MACPPSCR_PPSCMD_0 (0x1U << ETH_MACPPSCR_PPSCMD_Pos) /*!< 0x00000001 */
#define ETH_MACPPSCR_PPSCMD_1 (0x2U << ETH_MACPPSCR_PPSCMD_Pos) /*!< 0x00000002 */
#define ETH_MACPPSCR_PPSCMD_2 (0x4U << ETH_MACPPSCR_PPSCMD_Pos) /*!< 0x00000004 */
#define ETH_MACPPSCR_PPSCMD_3 (0x8U << ETH_MACPPSCR_PPSCMD_Pos) /*!< 0x00000008 */
#define ETH_MACPPSCR_PPSEN0_Pos (4U)
#define ETH_MACPPSCR_PPSEN0_Msk (0x1U << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */
#define ETH_MACPPSCR_PPSEN0 ETH_MACPPSCR_PPSEN0_Msk /*!< Flexible PPS Output Mode Enable */
#define ETH_MACPPSCR_TRGTMODSEL0_Pos (5U)
#define ETH_MACPPSCR_TRGTMODSEL0_Msk (0x3U << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */
#define ETH_MACPPSCR_TRGTMODSEL0 ETH_MACPPSCR_TRGTMODSEL0_Msk /*!< Target Time Register Mode for PPS Output */
#define ETH_MACPPSCR_TRGTMODSEL0_0 (0x1U << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000020 */
#define ETH_MACPPSCR_TRGTMODSEL0_1 (0x2U << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000040 */
/************ Bit definition for ETH_MACPPSTTSR register *************/
#define ETH_MACPPSTTSR_TSTRH0_Pos (0U)
#define ETH_MACPPSTTSR_TSTRH0_Msk (0xFFFFFFFFU << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACPPSTTSR_TSTRH0 ETH_MACPPSTTSR_TSTRH0_Msk /*!< PPS Target Time Seconds Register */
#define ETH_MACPPSTTSR_TSTRH0_0 (0x1U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00000001 */
#define ETH_MACPPSTTSR_TSTRH0_1 (0x2U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00000002 */
#define ETH_MACPPSTTSR_TSTRH0_2 (0x4U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00000004 */
#define ETH_MACPPSTTSR_TSTRH0_3 (0x8U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00000008 */
#define ETH_MACPPSTTSR_TSTRH0_4 (0x10U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00000010 */
#define ETH_MACPPSTTSR_TSTRH0_5 (0x20U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00000020 */
#define ETH_MACPPSTTSR_TSTRH0_6 (0x40U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00000040 */
#define ETH_MACPPSTTSR_TSTRH0_7 (0x80U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00000080 */
#define ETH_MACPPSTTSR_TSTRH0_8 (0x100U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00000100 */
#define ETH_MACPPSTTSR_TSTRH0_9 (0x200U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00000200 */
#define ETH_MACPPSTTSR_TSTRH0_10 (0x400U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00000400 */
#define ETH_MACPPSTTSR_TSTRH0_11 (0x800U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00000800 */
#define ETH_MACPPSTTSR_TSTRH0_12 (0x1000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00001000 */
#define ETH_MACPPSTTSR_TSTRH0_13 (0x2000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00002000 */
#define ETH_MACPPSTTSR_TSTRH0_14 (0x4000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00004000 */
#define ETH_MACPPSTTSR_TSTRH0_15 (0x8000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00008000 */
#define ETH_MACPPSTTSR_TSTRH0_16 (0x10000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00010000 */
#define ETH_MACPPSTTSR_TSTRH0_17 (0x20000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00020000 */
#define ETH_MACPPSTTSR_TSTRH0_18 (0x40000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00040000 */
#define ETH_MACPPSTTSR_TSTRH0_19 (0x80000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00080000 */
#define ETH_MACPPSTTSR_TSTRH0_20 (0x100000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00100000 */
#define ETH_MACPPSTTSR_TSTRH0_21 (0x200000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00200000 */
#define ETH_MACPPSTTSR_TSTRH0_22 (0x400000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00400000 */
#define ETH_MACPPSTTSR_TSTRH0_23 (0x800000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x00800000 */
#define ETH_MACPPSTTSR_TSTRH0_24 (0x1000000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x01000000 */
#define ETH_MACPPSTTSR_TSTRH0_25 (0x2000000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x02000000 */
#define ETH_MACPPSTTSR_TSTRH0_26 (0x4000000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x04000000 */
#define ETH_MACPPSTTSR_TSTRH0_27 (0x8000000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x08000000 */
#define ETH_MACPPSTTSR_TSTRH0_28 (0x10000000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x10000000 */
#define ETH_MACPPSTTSR_TSTRH0_29 (0x20000000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x20000000 */
#define ETH_MACPPSTTSR_TSTRH0_30 (0x40000000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x40000000 */
#define ETH_MACPPSTTSR_TSTRH0_31 (0x80000000U << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0x80000000 */
/************ Bit definition for ETH_MACPPSTTNR register *************/
#define ETH_MACPPSTTNR_TTSL0_Pos (0U)
#define ETH_MACPPSTTNR_TTSL0_Msk (0x7FFFFFFFU << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */
#define ETH_MACPPSTTNR_TTSL0 ETH_MACPPSTTNR_TTSL0_Msk /*!< Target Time Low for PPS Register */
#define ETH_MACPPSTTNR_TTSL0_0 (0x1U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00000001 */
#define ETH_MACPPSTTNR_TTSL0_1 (0x2U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00000002 */
#define ETH_MACPPSTTNR_TTSL0_2 (0x4U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00000004 */
#define ETH_MACPPSTTNR_TTSL0_3 (0x8U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00000008 */
#define ETH_MACPPSTTNR_TTSL0_4 (0x10U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00000010 */
#define ETH_MACPPSTTNR_TTSL0_5 (0x20U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00000020 */
#define ETH_MACPPSTTNR_TTSL0_6 (0x40U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00000040 */
#define ETH_MACPPSTTNR_TTSL0_7 (0x80U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00000080 */
#define ETH_MACPPSTTNR_TTSL0_8 (0x100U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00000100 */
#define ETH_MACPPSTTNR_TTSL0_9 (0x200U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00000200 */
#define ETH_MACPPSTTNR_TTSL0_10 (0x400U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00000400 */
#define ETH_MACPPSTTNR_TTSL0_11 (0x800U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00000800 */
#define ETH_MACPPSTTNR_TTSL0_12 (0x1000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00001000 */
#define ETH_MACPPSTTNR_TTSL0_13 (0x2000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00002000 */
#define ETH_MACPPSTTNR_TTSL0_14 (0x4000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00004000 */
#define ETH_MACPPSTTNR_TTSL0_15 (0x8000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00008000 */
#define ETH_MACPPSTTNR_TTSL0_16 (0x10000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00010000 */
#define ETH_MACPPSTTNR_TTSL0_17 (0x20000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00020000 */
#define ETH_MACPPSTTNR_TTSL0_18 (0x40000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00040000 */
#define ETH_MACPPSTTNR_TTSL0_19 (0x80000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00080000 */
#define ETH_MACPPSTTNR_TTSL0_20 (0x100000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00100000 */
#define ETH_MACPPSTTNR_TTSL0_21 (0x200000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00200000 */
#define ETH_MACPPSTTNR_TTSL0_22 (0x400000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00400000 */
#define ETH_MACPPSTTNR_TTSL0_23 (0x800000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x00800000 */
#define ETH_MACPPSTTNR_TTSL0_24 (0x1000000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x01000000 */
#define ETH_MACPPSTTNR_TTSL0_25 (0x2000000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x02000000 */
#define ETH_MACPPSTTNR_TTSL0_26 (0x4000000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x04000000 */
#define ETH_MACPPSTTNR_TTSL0_27 (0x8000000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x08000000 */
#define ETH_MACPPSTTNR_TTSL0_28 (0x10000000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x10000000 */
#define ETH_MACPPSTTNR_TTSL0_29 (0x20000000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x20000000 */
#define ETH_MACPPSTTNR_TTSL0_30 (0x40000000U << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x40000000 */
#define ETH_MACPPSTTNR_TRGTBUSY0_Pos (31U)
#define ETH_MACPPSTTNR_TRGTBUSY0_Msk (0x1U << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */
#define ETH_MACPPSTTNR_TRGTBUSY0 ETH_MACPPSTTNR_TRGTBUSY0_Msk /*!< PPS Target Time Register Busy */
/************* Bit definition for ETH_MACPPSIR register **************/
#define ETH_MACPPSIR_PPSINT0_Pos (0U)
#define ETH_MACPPSIR_PPSINT0_Msk (0xFFFFFFFFU << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACPPSIR_PPSINT0 ETH_MACPPSIR_PPSINT0_Msk /*!< PPS Output Signal Interval */
#define ETH_MACPPSIR_PPSINT0_0 (0x1U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00000001 */
#define ETH_MACPPSIR_PPSINT0_1 (0x2U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00000002 */
#define ETH_MACPPSIR_PPSINT0_2 (0x4U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00000004 */
#define ETH_MACPPSIR_PPSINT0_3 (0x8U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00000008 */
#define ETH_MACPPSIR_PPSINT0_4 (0x10U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00000010 */
#define ETH_MACPPSIR_PPSINT0_5 (0x20U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00000020 */
#define ETH_MACPPSIR_PPSINT0_6 (0x40U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00000040 */
#define ETH_MACPPSIR_PPSINT0_7 (0x80U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00000080 */
#define ETH_MACPPSIR_PPSINT0_8 (0x100U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00000100 */
#define ETH_MACPPSIR_PPSINT0_9 (0x200U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00000200 */
#define ETH_MACPPSIR_PPSINT0_10 (0x400U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00000400 */
#define ETH_MACPPSIR_PPSINT0_11 (0x800U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00000800 */
#define ETH_MACPPSIR_PPSINT0_12 (0x1000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00001000 */
#define ETH_MACPPSIR_PPSINT0_13 (0x2000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00002000 */
#define ETH_MACPPSIR_PPSINT0_14 (0x4000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00004000 */
#define ETH_MACPPSIR_PPSINT0_15 (0x8000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00008000 */
#define ETH_MACPPSIR_PPSINT0_16 (0x10000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00010000 */
#define ETH_MACPPSIR_PPSINT0_17 (0x20000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00020000 */
#define ETH_MACPPSIR_PPSINT0_18 (0x40000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00040000 */
#define ETH_MACPPSIR_PPSINT0_19 (0x80000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00080000 */
#define ETH_MACPPSIR_PPSINT0_20 (0x100000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00100000 */
#define ETH_MACPPSIR_PPSINT0_21 (0x200000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00200000 */
#define ETH_MACPPSIR_PPSINT0_22 (0x400000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00400000 */
#define ETH_MACPPSIR_PPSINT0_23 (0x800000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x00800000 */
#define ETH_MACPPSIR_PPSINT0_24 (0x1000000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x01000000 */
#define ETH_MACPPSIR_PPSINT0_25 (0x2000000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x02000000 */
#define ETH_MACPPSIR_PPSINT0_26 (0x4000000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x04000000 */
#define ETH_MACPPSIR_PPSINT0_27 (0x8000000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x08000000 */
#define ETH_MACPPSIR_PPSINT0_28 (0x10000000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x10000000 */
#define ETH_MACPPSIR_PPSINT0_29 (0x20000000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x20000000 */
#define ETH_MACPPSIR_PPSINT0_30 (0x40000000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x40000000 */
#define ETH_MACPPSIR_PPSINT0_31 (0x80000000U << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0x80000000 */
/************* Bit definition for ETH_MACPPSWR register **************/
#define ETH_MACPPSWR_PPSWIDTH0_Pos (0U)
#define ETH_MACPPSWR_PPSWIDTH0_Msk (0xFFFFFFFFU << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACPPSWR_PPSWIDTH0 ETH_MACPPSWR_PPSWIDTH0_Msk /*!< PPS Output Signal Width */
#define ETH_MACPPSWR_PPSWIDTH0_0 (0x1U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00000001 */
#define ETH_MACPPSWR_PPSWIDTH0_1 (0x2U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00000002 */
#define ETH_MACPPSWR_PPSWIDTH0_2 (0x4U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00000004 */
#define ETH_MACPPSWR_PPSWIDTH0_3 (0x8U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00000008 */
#define ETH_MACPPSWR_PPSWIDTH0_4 (0x10U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00000010 */
#define ETH_MACPPSWR_PPSWIDTH0_5 (0x20U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00000020 */
#define ETH_MACPPSWR_PPSWIDTH0_6 (0x40U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00000040 */
#define ETH_MACPPSWR_PPSWIDTH0_7 (0x80U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00000080 */
#define ETH_MACPPSWR_PPSWIDTH0_8 (0x100U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00000100 */
#define ETH_MACPPSWR_PPSWIDTH0_9 (0x200U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00000200 */
#define ETH_MACPPSWR_PPSWIDTH0_10 (0x400U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00000400 */
#define ETH_MACPPSWR_PPSWIDTH0_11 (0x800U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00000800 */
#define ETH_MACPPSWR_PPSWIDTH0_12 (0x1000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00001000 */
#define ETH_MACPPSWR_PPSWIDTH0_13 (0x2000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00002000 */
#define ETH_MACPPSWR_PPSWIDTH0_14 (0x4000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00004000 */
#define ETH_MACPPSWR_PPSWIDTH0_15 (0x8000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00008000 */
#define ETH_MACPPSWR_PPSWIDTH0_16 (0x10000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00010000 */
#define ETH_MACPPSWR_PPSWIDTH0_17 (0x20000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00020000 */
#define ETH_MACPPSWR_PPSWIDTH0_18 (0x40000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00040000 */
#define ETH_MACPPSWR_PPSWIDTH0_19 (0x80000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00080000 */
#define ETH_MACPPSWR_PPSWIDTH0_20 (0x100000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00100000 */
#define ETH_MACPPSWR_PPSWIDTH0_21 (0x200000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00200000 */
#define ETH_MACPPSWR_PPSWIDTH0_22 (0x400000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00400000 */
#define ETH_MACPPSWR_PPSWIDTH0_23 (0x800000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x00800000 */
#define ETH_MACPPSWR_PPSWIDTH0_24 (0x1000000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x01000000 */
#define ETH_MACPPSWR_PPSWIDTH0_25 (0x2000000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x02000000 */
#define ETH_MACPPSWR_PPSWIDTH0_26 (0x4000000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x04000000 */
#define ETH_MACPPSWR_PPSWIDTH0_27 (0x8000000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x08000000 */
#define ETH_MACPPSWR_PPSWIDTH0_28 (0x10000000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x10000000 */
#define ETH_MACPPSWR_PPSWIDTH0_29 (0x20000000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x20000000 */
#define ETH_MACPPSWR_PPSWIDTH0_30 (0x40000000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x40000000 */
#define ETH_MACPPSWR_PPSWIDTH0_31 (0x80000000U << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0x80000000 */
/************** Bit definition for ETH_MACPOCR register **************/
#define ETH_MACPOCR_PTOEN_Pos (0U)
#define ETH_MACPOCR_PTOEN_Msk (0x1U << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */
#define ETH_MACPOCR_PTOEN ETH_MACPOCR_PTOEN_Msk /*!< PTP Offload Enable */
#define ETH_MACPOCR_ASYNCEN_Pos (1U)
#define ETH_MACPOCR_ASYNCEN_Msk (0x1U << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */
#define ETH_MACPOCR_ASYNCEN ETH_MACPOCR_ASYNCEN_Msk /*!< Automatic PTP SYNC message Enable */
#define ETH_MACPOCR_APDREQEN_Pos (2U)
#define ETH_MACPOCR_APDREQEN_Msk (0x1U << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */
#define ETH_MACPOCR_APDREQEN ETH_MACPOCR_APDREQEN_Msk /*!< Automatic PTP Pdelay_Req message Enable */
#define ETH_MACPOCR_ASYNCTRIG_Pos (4U)
#define ETH_MACPOCR_ASYNCTRIG_Msk (0x1U << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */
#define ETH_MACPOCR_ASYNCTRIG ETH_MACPOCR_ASYNCTRIG_Msk /*!< Automatic PTP SYNC message Trigger */
#define ETH_MACPOCR_APDREQTRIG_Pos (5U)
#define ETH_MACPOCR_APDREQTRIG_Msk (0x1U << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */
#define ETH_MACPOCR_APDREQTRIG ETH_MACPOCR_APDREQTRIG_Msk /*!< Automatic PTP Pdelay_Req message Trigger */
#define ETH_MACPOCR_DRRDIS_Pos (6U)
#define ETH_MACPOCR_DRRDIS_Msk (0x1U << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */
#define ETH_MACPOCR_DRRDIS ETH_MACPOCR_DRRDIS_Msk /*!< Disable PTO Delay Request/Response response generation */
#define ETH_MACPOCR_DN_Pos (8U)
#define ETH_MACPOCR_DN_Msk (0xFFU << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */
#define ETH_MACPOCR_DN ETH_MACPOCR_DN_Msk /*!< Domain Number */
#define ETH_MACPOCR_DN_0 (0x1U << ETH_MACPOCR_DN_Pos) /*!< 0x00000100 */
#define ETH_MACPOCR_DN_1 (0x2U << ETH_MACPOCR_DN_Pos) /*!< 0x00000200 */
#define ETH_MACPOCR_DN_2 (0x4U << ETH_MACPOCR_DN_Pos) /*!< 0x00000400 */
#define ETH_MACPOCR_DN_3 (0x8U << ETH_MACPOCR_DN_Pos) /*!< 0x00000800 */
#define ETH_MACPOCR_DN_4 (0x10U << ETH_MACPOCR_DN_Pos) /*!< 0x00001000 */
#define ETH_MACPOCR_DN_5 (0x20U << ETH_MACPOCR_DN_Pos) /*!< 0x00002000 */
#define ETH_MACPOCR_DN_6 (0x40U << ETH_MACPOCR_DN_Pos) /*!< 0x00004000 */
#define ETH_MACPOCR_DN_7 (0x80U << ETH_MACPOCR_DN_Pos) /*!< 0x00008000 */
/************* Bit definition for ETH_MACSPI0R register **************/
#define ETH_MACSPI0R_SPI0_Pos (0U)
#define ETH_MACSPI0R_SPI0_Msk (0xFFFFFFFFU << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACSPI0R_SPI0 ETH_MACSPI0R_SPI0_Msk /*!< Source Port Identity 0 */
#define ETH_MACSPI0R_SPI0_0 (0x1U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00000001 */
#define ETH_MACSPI0R_SPI0_1 (0x2U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00000002 */
#define ETH_MACSPI0R_SPI0_2 (0x4U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00000004 */
#define ETH_MACSPI0R_SPI0_3 (0x8U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00000008 */
#define ETH_MACSPI0R_SPI0_4 (0x10U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00000010 */
#define ETH_MACSPI0R_SPI0_5 (0x20U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00000020 */
#define ETH_MACSPI0R_SPI0_6 (0x40U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00000040 */
#define ETH_MACSPI0R_SPI0_7 (0x80U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00000080 */
#define ETH_MACSPI0R_SPI0_8 (0x100U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00000100 */
#define ETH_MACSPI0R_SPI0_9 (0x200U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00000200 */
#define ETH_MACSPI0R_SPI0_10 (0x400U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00000400 */
#define ETH_MACSPI0R_SPI0_11 (0x800U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00000800 */
#define ETH_MACSPI0R_SPI0_12 (0x1000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00001000 */
#define ETH_MACSPI0R_SPI0_13 (0x2000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00002000 */
#define ETH_MACSPI0R_SPI0_14 (0x4000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00004000 */
#define ETH_MACSPI0R_SPI0_15 (0x8000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00008000 */
#define ETH_MACSPI0R_SPI0_16 (0x10000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00010000 */
#define ETH_MACSPI0R_SPI0_17 (0x20000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00020000 */
#define ETH_MACSPI0R_SPI0_18 (0x40000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00040000 */
#define ETH_MACSPI0R_SPI0_19 (0x80000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00080000 */
#define ETH_MACSPI0R_SPI0_20 (0x100000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00100000 */
#define ETH_MACSPI0R_SPI0_21 (0x200000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00200000 */
#define ETH_MACSPI0R_SPI0_22 (0x400000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00400000 */
#define ETH_MACSPI0R_SPI0_23 (0x800000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x00800000 */
#define ETH_MACSPI0R_SPI0_24 (0x1000000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x01000000 */
#define ETH_MACSPI0R_SPI0_25 (0x2000000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x02000000 */
#define ETH_MACSPI0R_SPI0_26 (0x4000000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x04000000 */
#define ETH_MACSPI0R_SPI0_27 (0x8000000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x08000000 */
#define ETH_MACSPI0R_SPI0_28 (0x10000000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x10000000 */
#define ETH_MACSPI0R_SPI0_29 (0x20000000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x20000000 */
#define ETH_MACSPI0R_SPI0_30 (0x40000000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x40000000 */
#define ETH_MACSPI0R_SPI0_31 (0x80000000U << ETH_MACSPI0R_SPI0_Pos) /*!< 0x80000000 */
/************* Bit definition for ETH_MACSPI1R register **************/
#define ETH_MACSPI1R_SPI1_Pos (0U)
#define ETH_MACSPI1R_SPI1_Msk (0xFFFFFFFFU << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACSPI1R_SPI1 ETH_MACSPI1R_SPI1_Msk /*!< Source Port Identity 1 */
#define ETH_MACSPI1R_SPI1_0 (0x1U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00000001 */
#define ETH_MACSPI1R_SPI1_1 (0x2U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00000002 */
#define ETH_MACSPI1R_SPI1_2 (0x4U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00000004 */
#define ETH_MACSPI1R_SPI1_3 (0x8U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00000008 */
#define ETH_MACSPI1R_SPI1_4 (0x10U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00000010 */
#define ETH_MACSPI1R_SPI1_5 (0x20U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00000020 */
#define ETH_MACSPI1R_SPI1_6 (0x40U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00000040 */
#define ETH_MACSPI1R_SPI1_7 (0x80U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00000080 */
#define ETH_MACSPI1R_SPI1_8 (0x100U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00000100 */
#define ETH_MACSPI1R_SPI1_9 (0x200U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00000200 */
#define ETH_MACSPI1R_SPI1_10 (0x400U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00000400 */
#define ETH_MACSPI1R_SPI1_11 (0x800U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00000800 */
#define ETH_MACSPI1R_SPI1_12 (0x1000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00001000 */
#define ETH_MACSPI1R_SPI1_13 (0x2000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00002000 */
#define ETH_MACSPI1R_SPI1_14 (0x4000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00004000 */
#define ETH_MACSPI1R_SPI1_15 (0x8000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00008000 */
#define ETH_MACSPI1R_SPI1_16 (0x10000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00010000 */
#define ETH_MACSPI1R_SPI1_17 (0x20000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00020000 */
#define ETH_MACSPI1R_SPI1_18 (0x40000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00040000 */
#define ETH_MACSPI1R_SPI1_19 (0x80000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00080000 */
#define ETH_MACSPI1R_SPI1_20 (0x100000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00100000 */
#define ETH_MACSPI1R_SPI1_21 (0x200000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00200000 */
#define ETH_MACSPI1R_SPI1_22 (0x400000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00400000 */
#define ETH_MACSPI1R_SPI1_23 (0x800000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x00800000 */
#define ETH_MACSPI1R_SPI1_24 (0x1000000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x01000000 */
#define ETH_MACSPI1R_SPI1_25 (0x2000000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x02000000 */
#define ETH_MACSPI1R_SPI1_26 (0x4000000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x04000000 */
#define ETH_MACSPI1R_SPI1_27 (0x8000000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x08000000 */
#define ETH_MACSPI1R_SPI1_28 (0x10000000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x10000000 */
#define ETH_MACSPI1R_SPI1_29 (0x20000000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x20000000 */
#define ETH_MACSPI1R_SPI1_30 (0x40000000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x40000000 */
#define ETH_MACSPI1R_SPI1_31 (0x80000000U << ETH_MACSPI1R_SPI1_Pos) /*!< 0x80000000 */
/************* Bit definition for ETH_MACSPI2R register **************/
#define ETH_MACSPI2R_SPI2_Pos (0U)
#define ETH_MACSPI2R_SPI2_Msk (0xFFFFU << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */
#define ETH_MACSPI2R_SPI2 ETH_MACSPI2R_SPI2_Msk /*!< Source Port Identity 2 */
#define ETH_MACSPI2R_SPI2_0 (0x1U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00000001 */
#define ETH_MACSPI2R_SPI2_1 (0x2U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00000002 */
#define ETH_MACSPI2R_SPI2_2 (0x4U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00000004 */
#define ETH_MACSPI2R_SPI2_3 (0x8U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00000008 */
#define ETH_MACSPI2R_SPI2_4 (0x10U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00000010 */
#define ETH_MACSPI2R_SPI2_5 (0x20U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00000020 */
#define ETH_MACSPI2R_SPI2_6 (0x40U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00000040 */
#define ETH_MACSPI2R_SPI2_7 (0x80U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00000080 */
#define ETH_MACSPI2R_SPI2_8 (0x100U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00000100 */
#define ETH_MACSPI2R_SPI2_9 (0x200U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00000200 */
#define ETH_MACSPI2R_SPI2_10 (0x400U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00000400 */
#define ETH_MACSPI2R_SPI2_11 (0x800U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00000800 */
#define ETH_MACSPI2R_SPI2_12 (0x1000U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00001000 */
#define ETH_MACSPI2R_SPI2_13 (0x2000U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00002000 */
#define ETH_MACSPI2R_SPI2_14 (0x4000U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00004000 */
#define ETH_MACSPI2R_SPI2_15 (0x8000U << ETH_MACSPI2R_SPI2_Pos) /*!< 0x00008000 */
/************** Bit definition for ETH_MACLMIR register **************/
#define ETH_MACLMIR_LSI_Pos (0U)
#define ETH_MACLMIR_LSI_Msk (0xFFU << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */
#define ETH_MACLMIR_LSI ETH_MACLMIR_LSI_Msk /*!< Log Sync Interval */
#define ETH_MACLMIR_LSI_0 (0x1U << ETH_MACLMIR_LSI_Pos) /*!< 0x00000001 */
#define ETH_MACLMIR_LSI_1 (0x2U << ETH_MACLMIR_LSI_Pos) /*!< 0x00000002 */
#define ETH_MACLMIR_LSI_2 (0x4U << ETH_MACLMIR_LSI_Pos) /*!< 0x00000004 */
#define ETH_MACLMIR_LSI_3 (0x8U << ETH_MACLMIR_LSI_Pos) /*!< 0x00000008 */
#define ETH_MACLMIR_LSI_4 (0x10U << ETH_MACLMIR_LSI_Pos) /*!< 0x00000010 */
#define ETH_MACLMIR_LSI_5 (0x20U << ETH_MACLMIR_LSI_Pos) /*!< 0x00000020 */
#define ETH_MACLMIR_LSI_6 (0x40U << ETH_MACLMIR_LSI_Pos) /*!< 0x00000040 */
#define ETH_MACLMIR_LSI_7 (0x80U << ETH_MACLMIR_LSI_Pos) /*!< 0x00000080 */
#define ETH_MACLMIR_DRSYNCR_Pos (8U)
#define ETH_MACLMIR_DRSYNCR_Msk (0x7U << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */
#define ETH_MACLMIR_DRSYNCR ETH_MACLMIR_DRSYNCR_Msk /*!< Delay_Req to SYNC Ratio */
#define ETH_MACLMIR_DRSYNCR_0 (0x1U << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000100 */
#define ETH_MACLMIR_DRSYNCR_1 (0x2U << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000200 */
#define ETH_MACLMIR_DRSYNCR_2 (0x4U << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000400 */
#define ETH_MACLMIR_LMPDRI_Pos (24U)
#define ETH_MACLMIR_LMPDRI_Msk (0xFFU << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */
#define ETH_MACLMIR_LMPDRI ETH_MACLMIR_LMPDRI_Msk /*!< Log Min Pdelay_Req Interval */
#define ETH_MACLMIR_LMPDRI_0 (0x1U << ETH_MACLMIR_LMPDRI_Pos) /*!< 0x01000000 */
#define ETH_MACLMIR_LMPDRI_1 (0x2U << ETH_MACLMIR_LMPDRI_Pos) /*!< 0x02000000 */
#define ETH_MACLMIR_LMPDRI_2 (0x4U << ETH_MACLMIR_LMPDRI_Pos) /*!< 0x04000000 */
#define ETH_MACLMIR_LMPDRI_3 (0x8U << ETH_MACLMIR_LMPDRI_Pos) /*!< 0x08000000 */
#define ETH_MACLMIR_LMPDRI_4 (0x10U << ETH_MACLMIR_LMPDRI_Pos) /*!< 0x10000000 */
#define ETH_MACLMIR_LMPDRI_5 (0x20U << ETH_MACLMIR_LMPDRI_Pos) /*!< 0x20000000 */
#define ETH_MACLMIR_LMPDRI_6 (0x40U << ETH_MACLMIR_LMPDRI_Pos) /*!< 0x40000000 */
#define ETH_MACLMIR_LMPDRI_7 (0x80U << ETH_MACLMIR_LMPDRI_Pos) /*!< 0x80000000 */
/************** Bit definition for ETH_MTLOMR register ***************/
#define ETH_MTLOMR_DTXSTS_Pos (1U)
#define ETH_MTLOMR_DTXSTS_Msk (0x1U << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */
#define ETH_MTLOMR_DTXSTS ETH_MTLOMR_DTXSTS_Msk /*!< Drop Transmit Status */
#define ETH_MTLOMR_RAA_Pos (2U)
#define ETH_MTLOMR_RAA_Msk (0x1U << ETH_MTLOMR_RAA_Pos) /*!< 0x00000004 */
#define ETH_MTLOMR_RAA ETH_MTLOMR_RAA_Msk /*!< Receive Arbitration Algorithm */
#define ETH_MTLOMR_SCHALG_Pos (5U)
#define ETH_MTLOMR_SCHALG_Msk (0x3U << ETH_MTLOMR_SCHALG_Pos) /*!< 0x00000060 */
#define ETH_MTLOMR_SCHALG ETH_MTLOMR_SCHALG_Msk /*!< Tx Scheduling Algorithm */
#define ETH_MTLOMR_SCHALG_0 (0x1U << ETH_MTLOMR_SCHALG_Pos) /*!< 0x00000020 */
#define ETH_MTLOMR_SCHALG_1 (0x2U << ETH_MTLOMR_SCHALG_Pos) /*!< 0x00000040 */
#define ETH_MTLOMR_CNTPRST_Pos (8U)
#define ETH_MTLOMR_CNTPRST_Msk (0x1U << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */
#define ETH_MTLOMR_CNTPRST ETH_MTLOMR_CNTPRST_Msk /*!< Counters Preset */
#define ETH_MTLOMR_CNTCLR_Pos (9U)
#define ETH_MTLOMR_CNTCLR_Msk (0x1U << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */
#define ETH_MTLOMR_CNTCLR ETH_MTLOMR_CNTCLR_Msk /*!< Counters Reset */
/************** Bit definition for ETH_MTLISR register ***************/
#define ETH_MTLISR_Q0IS_Pos (0U)
#define ETH_MTLISR_Q0IS_Msk (0x1U << ETH_MTLISR_Q0IS_Pos) /*!< 0x00000001 */
#define ETH_MTLISR_Q0IS ETH_MTLISR_Q0IS_Msk /*!< Queue 0 interrupt status */
#define ETH_MTLISR_Q1IS_Pos (1U)
#define ETH_MTLISR_Q1IS_Msk (0x1U << ETH_MTLISR_Q1IS_Pos) /*!< 0x00000002 */
#define ETH_MTLISR_Q1IS ETH_MTLISR_Q1IS_Msk /*!< Queue 1 interrupt status */
/************ Bit definition for ETH_MTLTXQ0OMR register *************/
#define ETH_MTLTXQ0OMR_FTQ_Pos (0U)
#define ETH_MTLTXQ0OMR_FTQ_Msk (0x1U << ETH_MTLTXQ0OMR_FTQ_Pos) /*!< 0x00000001 */
#define ETH_MTLTXQ0OMR_FTQ ETH_MTLTXQ0OMR_FTQ_Msk /*!< Flush Transmit Queue */
#define ETH_MTLTXQ0OMR_TSF_Pos (1U)
#define ETH_MTLTXQ0OMR_TSF_Msk (0x1U << ETH_MTLTXQ0OMR_TSF_Pos) /*!< 0x00000002 */
#define ETH_MTLTXQ0OMR_TSF ETH_MTLTXQ0OMR_TSF_Msk /*!< Transmit Store and Forward */
#define ETH_MTLTXQ0OMR_TXQEN_Pos (2U)
#define ETH_MTLTXQ0OMR_TXQEN_Msk (0x3U << ETH_MTLTXQ0OMR_TXQEN_Pos) /*!< 0x0000000C */
#define ETH_MTLTXQ0OMR_TXQEN ETH_MTLTXQ0OMR_TXQEN_Msk /*!< Transmit Queue Enable */
#define ETH_MTLTXQ0OMR_TXQEN_0 (0x1U << ETH_MTLTXQ0OMR_TXQEN_Pos) /*!< 0x00000004 */
#define ETH_MTLTXQ0OMR_TXQEN_1 (0x2U << ETH_MTLTXQ0OMR_TXQEN_Pos) /*!< 0x00000008 */
#define ETH_MTLTXQ0OMR_TTC_Pos (4U)
#define ETH_MTLTXQ0OMR_TTC_Msk (0x7U << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000070 */
#define ETH_MTLTXQ0OMR_TTC ETH_MTLTXQ0OMR_TTC_Msk /*!< Transmit Threshold Control */
#define ETH_MTLTXQ0OMR_TTC_0 (0x1U << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000010 */
#define ETH_MTLTXQ0OMR_TTC_1 (0x2U << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000020 */
#define ETH_MTLTXQ0OMR_TTC_2 (0x4U << ETH_MTLTXQ0OMR_TTC_Pos) /*!< 0x00000040 */
#define ETH_MTLTXQ0OMR_TQS_Pos (16U)
#define ETH_MTLTXQ0OMR_TQS_Msk (0x1FFU << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01FF0000 */
#define ETH_MTLTXQ0OMR_TQS ETH_MTLTXQ0OMR_TQS_Msk /*!< Transmit Queue Size */
#define ETH_MTLTXQ0OMR_TQS_0 (0x1U << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x00010000 */
#define ETH_MTLTXQ0OMR_TQS_1 (0x2U << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x00020000 */
#define ETH_MTLTXQ0OMR_TQS_2 (0x4U << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x00040000 */
#define ETH_MTLTXQ0OMR_TQS_3 (0x8U << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x00080000 */
#define ETH_MTLTXQ0OMR_TQS_4 (0x10U << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x00100000 */
#define ETH_MTLTXQ0OMR_TQS_5 (0x20U << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x00200000 */
#define ETH_MTLTXQ0OMR_TQS_6 (0x40U << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x00400000 */
#define ETH_MTLTXQ0OMR_TQS_7 (0x80U << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x00800000 */
#define ETH_MTLTXQ0OMR_TQS_8 (0x100U << ETH_MTLTXQ0OMR_TQS_Pos) /*!< 0x01000000 */
/************* Bit definition for ETH_MTLTXQ0UR register *************/
#define ETH_MTLTXQ0UR_UFFRMCNT_Pos (0U)
#define ETH_MTLTXQ0UR_UFFRMCNT_Msk (0x7FFU << ETH_MTLTXQ0UR_UFFRMCNT_Pos) /*!< 0x000007FF */
#define ETH_MTLTXQ0UR_UFFRMCNT ETH_MTLTXQ0UR_UFFRMCNT_Msk /*!< Underflow Packet Counter */
#define ETH_MTLTXQ0UR_UFFRMCNT_0 (0x1U << ETH_MTLTXQ0UR_UFFRMCNT_Pos) /*!< 0x00000001 */
#define ETH_MTLTXQ0UR_UFFRMCNT_1 (0x2U << ETH_MTLTXQ0UR_UFFRMCNT_Pos) /*!< 0x00000002 */
#define ETH_MTLTXQ0UR_UFFRMCNT_2 (0x4U << ETH_MTLTXQ0UR_UFFRMCNT_Pos) /*!< 0x00000004 */
#define ETH_MTLTXQ0UR_UFFRMCNT_3 (0x8U << ETH_MTLTXQ0UR_UFFRMCNT_Pos) /*!< 0x00000008 */
#define ETH_MTLTXQ0UR_UFFRMCNT_4 (0x10U << ETH_MTLTXQ0UR_UFFRMCNT_Pos) /*!< 0x00000010 */
#define ETH_MTLTXQ0UR_UFFRMCNT_5 (0x20U << ETH_MTLTXQ0UR_UFFRMCNT_Pos) /*!< 0x00000020 */
#define ETH_MTLTXQ0UR_UFFRMCNT_6 (0x40U << ETH_MTLTXQ0UR_UFFRMCNT_Pos) /*!< 0x00000040 */
#define ETH_MTLTXQ0UR_UFFRMCNT_7 (0x80U << ETH_MTLTXQ0UR_UFFRMCNT_Pos) /*!< 0x00000080 */
#define ETH_MTLTXQ0UR_UFFRMCNT_8 (0x100U << ETH_MTLTXQ0UR_UFFRMCNT_Pos) /*!< 0x00000100 */
#define ETH_MTLTXQ0UR_UFFRMCNT_9 (0x200U << ETH_MTLTXQ0UR_UFFRMCNT_Pos) /*!< 0x00000200 */
#define ETH_MTLTXQ0UR_UFFRMCNT_10 (0x400U << ETH_MTLTXQ0UR_UFFRMCNT_Pos) /*!< 0x00000400 */
#define ETH_MTLTXQ0UR_UFCNTOVF_Pos (11U)
#define ETH_MTLTXQ0UR_UFCNTOVF_Msk (0x1U << ETH_MTLTXQ0UR_UFCNTOVF_Pos) /*!< 0x00000800 */
#define ETH_MTLTXQ0UR_UFCNTOVF ETH_MTLTXQ0UR_UFCNTOVF_Msk /*!< Overflow Bit for Underflow Packet Counter */
/************* Bit definition for ETH_MTLTXQ0DR register *************/
#define ETH_MTLTXQ0DR_TXQPAUSED_Pos (0U)
#define ETH_MTLTXQ0DR_TXQPAUSED_Msk (0x1U << ETH_MTLTXQ0DR_TXQPAUSED_Pos) /*!< 0x00000001 */
#define ETH_MTLTXQ0DR_TXQPAUSED ETH_MTLTXQ0DR_TXQPAUSED_Msk /*!< Transmit Queue in Pause */
#define ETH_MTLTXQ0DR_TRCSTS_Pos (1U)
#define ETH_MTLTXQ0DR_TRCSTS_Msk (0x3U << ETH_MTLTXQ0DR_TRCSTS_Pos) /*!< 0x00000006 */
#define ETH_MTLTXQ0DR_TRCSTS ETH_MTLTXQ0DR_TRCSTS_Msk /*!< MTL Tx Queue Read Controller Status */
#define ETH_MTLTXQ0DR_TRCSTS_0 (0x1U << ETH_MTLTXQ0DR_TRCSTS_Pos) /*!< 0x00000002 */
#define ETH_MTLTXQ0DR_TRCSTS_1 (0x2U << ETH_MTLTXQ0DR_TRCSTS_Pos) /*!< 0x00000004 */
#define ETH_MTLTXQ0DR_TWCSTS_Pos (3U)
#define ETH_MTLTXQ0DR_TWCSTS_Msk (0x1U << ETH_MTLTXQ0DR_TWCSTS_Pos) /*!< 0x00000008 */
#define ETH_MTLTXQ0DR_TWCSTS ETH_MTLTXQ0DR_TWCSTS_Msk /*!< MTL Tx Queue Write Controller Status */
#define ETH_MTLTXQ0DR_TXQSTS_Pos (4U)
#define ETH_MTLTXQ0DR_TXQSTS_Msk (0x1U << ETH_MTLTXQ0DR_TXQSTS_Pos) /*!< 0x00000010 */
#define ETH_MTLTXQ0DR_TXQSTS ETH_MTLTXQ0DR_TXQSTS_Msk /*!< MTL Tx Queue Not Empty Status */
#define ETH_MTLTXQ0DR_TXSTSFSTS_Pos (5U)
#define ETH_MTLTXQ0DR_TXSTSFSTS_Msk (0x1U << ETH_MTLTXQ0DR_TXSTSFSTS_Pos) /*!< 0x00000020 */
#define ETH_MTLTXQ0DR_TXSTSFSTS ETH_MTLTXQ0DR_TXSTSFSTS_Msk /*!< MTL Tx Status FIFO Full Status */
#define ETH_MTLTXQ0DR_PTXQ_Pos (16U)
#define ETH_MTLTXQ0DR_PTXQ_Msk (0x7U << ETH_MTLTXQ0DR_PTXQ_Pos) /*!< 0x00070000 */
#define ETH_MTLTXQ0DR_PTXQ ETH_MTLTXQ0DR_PTXQ_Msk /*!< Number of Packets in the Transmit Queue */
#define ETH_MTLTXQ0DR_PTXQ_0 (0x1U << ETH_MTLTXQ0DR_PTXQ_Pos) /*!< 0x00010000 */
#define ETH_MTLTXQ0DR_PTXQ_1 (0x2U << ETH_MTLTXQ0DR_PTXQ_Pos) /*!< 0x00020000 */
#define ETH_MTLTXQ0DR_PTXQ_2 (0x4U << ETH_MTLTXQ0DR_PTXQ_Pos) /*!< 0x00040000 */
#define ETH_MTLTXQ0DR_STXSTSF_Pos (20U)
#define ETH_MTLTXQ0DR_STXSTSF_Msk (0x7U << ETH_MTLTXQ0DR_STXSTSF_Pos) /*!< 0x00700000 */
#define ETH_MTLTXQ0DR_STXSTSF ETH_MTLTXQ0DR_STXSTSF_Msk /*!< Number of Status Words in Tx Status FIFO of Queue */
#define ETH_MTLTXQ0DR_STXSTSF_0 (0x1U << ETH_MTLTXQ0DR_STXSTSF_Pos) /*!< 0x00100000 */
#define ETH_MTLTXQ0DR_STXSTSF_1 (0x2U << ETH_MTLTXQ0DR_STXSTSF_Pos) /*!< 0x00200000 */
#define ETH_MTLTXQ0DR_STXSTSF_2 (0x4U << ETH_MTLTXQ0DR_STXSTSF_Pos) /*!< 0x00400000 */
/************ Bit definition for ETH_MTLTXQ0ESR register *************/
#define ETH_MTLTXQ0ESR_ABS_Pos (0U)
#define ETH_MTLTXQ0ESR_ABS_Msk (0xFFFFFFU << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00FFFFFF */
#define ETH_MTLTXQ0ESR_ABS ETH_MTLTXQ0ESR_ABS_Msk /*!< Average Bits per Slot */
#define ETH_MTLTXQ0ESR_ABS_0 (0x1U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00000001 */
#define ETH_MTLTXQ0ESR_ABS_1 (0x2U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00000002 */
#define ETH_MTLTXQ0ESR_ABS_2 (0x4U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00000004 */
#define ETH_MTLTXQ0ESR_ABS_3 (0x8U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00000008 */
#define ETH_MTLTXQ0ESR_ABS_4 (0x10U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00000010 */
#define ETH_MTLTXQ0ESR_ABS_5 (0x20U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00000020 */
#define ETH_MTLTXQ0ESR_ABS_6 (0x40U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00000040 */
#define ETH_MTLTXQ0ESR_ABS_7 (0x80U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00000080 */
#define ETH_MTLTXQ0ESR_ABS_8 (0x100U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00000100 */
#define ETH_MTLTXQ0ESR_ABS_9 (0x200U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00000200 */
#define ETH_MTLTXQ0ESR_ABS_10 (0x400U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00000400 */
#define ETH_MTLTXQ0ESR_ABS_11 (0x800U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00000800 */
#define ETH_MTLTXQ0ESR_ABS_12 (0x1000U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00001000 */
#define ETH_MTLTXQ0ESR_ABS_13 (0x2000U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00002000 */
#define ETH_MTLTXQ0ESR_ABS_14 (0x4000U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00004000 */
#define ETH_MTLTXQ0ESR_ABS_15 (0x8000U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00008000 */
#define ETH_MTLTXQ0ESR_ABS_16 (0x10000U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00010000 */
#define ETH_MTLTXQ0ESR_ABS_17 (0x20000U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00020000 */
#define ETH_MTLTXQ0ESR_ABS_18 (0x40000U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00040000 */
#define ETH_MTLTXQ0ESR_ABS_19 (0x80000U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00080000 */
#define ETH_MTLTXQ0ESR_ABS_20 (0x100000U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00100000 */
#define ETH_MTLTXQ0ESR_ABS_21 (0x200000U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00200000 */
#define ETH_MTLTXQ0ESR_ABS_22 (0x400000U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00400000 */
#define ETH_MTLTXQ0ESR_ABS_23 (0x800000U << ETH_MTLTXQ0ESR_ABS_Pos) /*!< 0x00800000 */
/************* Bit definition for ETH_MTLQ0ICSR register *************/
#define ETH_MTLQ0ICSR_TXUNFIS_Pos (0U)
#define ETH_MTLQ0ICSR_TXUNFIS_Msk (0x1U << ETH_MTLQ0ICSR_TXUNFIS_Pos) /*!< 0x00000001 */
#define ETH_MTLQ0ICSR_TXUNFIS ETH_MTLQ0ICSR_TXUNFIS_Msk /*!< Transmit Queue Underflow Interrupt Status */
#define ETH_MTLQ0ICSR_ABPSIS_Pos (1U)
#define ETH_MTLQ0ICSR_ABPSIS_Msk (0x1U << ETH_MTLQ0ICSR_ABPSIS_Pos) /*!< 0x00000002 */
#define ETH_MTLQ0ICSR_ABPSIS ETH_MTLQ0ICSR_ABPSIS_Msk /*!< Average Bits Per Slot Interrupt Status */
#define ETH_MTLQ0ICSR_TXUIE_Pos (8U)
#define ETH_MTLQ0ICSR_TXUIE_Msk (0x1U << ETH_MTLQ0ICSR_TXUIE_Pos) /*!< 0x00000100 */
#define ETH_MTLQ0ICSR_TXUIE ETH_MTLQ0ICSR_TXUIE_Msk /*!< Transmit Queue Underflow Interrupt Enable */
#define ETH_MTLQ0ICSR_ABPSIE_Pos (9U)
#define ETH_MTLQ0ICSR_ABPSIE_Msk (0x1U << ETH_MTLQ0ICSR_ABPSIE_Pos) /*!< 0x00000200 */
#define ETH_MTLQ0ICSR_ABPSIE ETH_MTLQ0ICSR_ABPSIE_Msk /*!< Average Bits Per Slot Interrupt Enable */
#define ETH_MTLQ0ICSR_RXOVFIS_Pos (16U)
#define ETH_MTLQ0ICSR_RXOVFIS_Msk (0x1U << ETH_MTLQ0ICSR_RXOVFIS_Pos) /*!< 0x00010000 */
#define ETH_MTLQ0ICSR_RXOVFIS ETH_MTLQ0ICSR_RXOVFIS_Msk /*!< Receive Queue Overflow Interrupt Status */
#define ETH_MTLQ0ICSR_RXOIE_Pos (24U)
#define ETH_MTLQ0ICSR_RXOIE_Msk (0x1U << ETH_MTLQ0ICSR_RXOIE_Pos) /*!< 0x01000000 */
#define ETH_MTLQ0ICSR_RXOIE ETH_MTLQ0ICSR_RXOIE_Msk /*!< Receive Queue Overflow Interrupt Enable */
/************ Bit definition for ETH_MTLRXQ0OMR register *************/
#define ETH_MTLRXQ0OMR_RTC_Pos (0U)
#define ETH_MTLRXQ0OMR_RTC_Msk (0x3U << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000003 */
#define ETH_MTLRXQ0OMR_RTC ETH_MTLRXQ0OMR_RTC_Msk /*!< Receive Queue Threshold Control */
#define ETH_MTLRXQ0OMR_RTC_0 (0x1U << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000001 */
#define ETH_MTLRXQ0OMR_RTC_1 (0x2U << ETH_MTLRXQ0OMR_RTC_Pos) /*!< 0x00000002 */
#define ETH_MTLRXQ0OMR_FUP_Pos (3U)
#define ETH_MTLRXQ0OMR_FUP_Msk (0x1U << ETH_MTLRXQ0OMR_FUP_Pos) /*!< 0x00000008 */
#define ETH_MTLRXQ0OMR_FUP ETH_MTLRXQ0OMR_FUP_Msk /*!< Forward Undersized Good Packets */
#define ETH_MTLRXQ0OMR_FEP_Pos (4U)
#define ETH_MTLRXQ0OMR_FEP_Msk (0x1U << ETH_MTLRXQ0OMR_FEP_Pos) /*!< 0x00000010 */
#define ETH_MTLRXQ0OMR_FEP ETH_MTLRXQ0OMR_FEP_Msk /*!< Forward Error Packets */
#define ETH_MTLRXQ0OMR_RSF_Pos (5U)
#define ETH_MTLRXQ0OMR_RSF_Msk (0x1U << ETH_MTLRXQ0OMR_RSF_Pos) /*!< 0x00000020 */
#define ETH_MTLRXQ0OMR_RSF ETH_MTLRXQ0OMR_RSF_Msk /*!< Receive Queue Store and Forward */
#define ETH_MTLRXQ0OMR_DIS_TCP_EF_Pos (6U)
#define ETH_MTLRXQ0OMR_DIS_TCP_EF_Msk (0x1U << ETH_MTLRXQ0OMR_DIS_TCP_EF_Pos) /*!< 0x00000040 */
#define ETH_MTLRXQ0OMR_DIS_TCP_EF ETH_MTLRXQ0OMR_DIS_TCP_EF_Msk /*!< Disable Dropping of TCP/IP Checksum Error Packets */
#define ETH_MTLRXQ0OMR_EHFC_Pos (7U)
#define ETH_MTLRXQ0OMR_EHFC_Msk (0x1U << ETH_MTLRXQ0OMR_EHFC_Pos) /*!< 0x00000080 */
#define ETH_MTLRXQ0OMR_EHFC ETH_MTLRXQ0OMR_EHFC_Msk /*!< Enable Hardware Flow Control */
#define ETH_MTLRXQ0OMR_RFA_Pos (8U)
#define ETH_MTLRXQ0OMR_RFA_Msk (0x7U << ETH_MTLRXQ0OMR_RFA_Pos) /*!< 0x00000700 */
#define ETH_MTLRXQ0OMR_RFA ETH_MTLRXQ0OMR_RFA_Msk /*!< Threshold for Activating Flow Control (in half-duplex and full-duplex */
#define ETH_MTLRXQ0OMR_RFA_0 (0x1U << ETH_MTLRXQ0OMR_RFA_Pos) /*!< 0x00000100 */
#define ETH_MTLRXQ0OMR_RFA_1 (0x2U << ETH_MTLRXQ0OMR_RFA_Pos) /*!< 0x00000200 */
#define ETH_MTLRXQ0OMR_RFA_2 (0x4U << ETH_MTLRXQ0OMR_RFA_Pos) /*!< 0x00000400 */
#define ETH_MTLRXQ0OMR_RFD_Pos (14U)
#define ETH_MTLRXQ0OMR_RFD_Msk (0x7U << ETH_MTLRXQ0OMR_RFD_Pos) /*!< 0x0001C000 */
#define ETH_MTLRXQ0OMR_RFD ETH_MTLRXQ0OMR_RFD_Msk /*!< Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
#define ETH_MTLRXQ0OMR_RFD_0 (0x1U << ETH_MTLRXQ0OMR_RFD_Pos) /*!< 0x00004000 */
#define ETH_MTLRXQ0OMR_RFD_1 (0x2U << ETH_MTLRXQ0OMR_RFD_Pos) /*!< 0x00008000 */
#define ETH_MTLRXQ0OMR_RFD_2 (0x4U << ETH_MTLRXQ0OMR_RFD_Pos) /*!< 0x00010000 */
#define ETH_MTLRXQ0OMR_RQS_Pos (20U)
#define ETH_MTLRXQ0OMR_RQS_Msk (0xFU << ETH_MTLRXQ0OMR_RQS_Pos) /*!< 0x00F00000 */
#define ETH_MTLRXQ0OMR_RQS ETH_MTLRXQ0OMR_RQS_Msk /*!< Receive Queue Size */
#define ETH_MTLRXQ0OMR_RQS_0 (0x1U << ETH_MTLRXQ0OMR_RQS_Pos) /*!< 0x00100000 */
#define ETH_MTLRXQ0OMR_RQS_1 (0x2U << ETH_MTLRXQ0OMR_RQS_Pos) /*!< 0x00200000 */
#define ETH_MTLRXQ0OMR_RQS_2 (0x4U << ETH_MTLRXQ0OMR_RQS_Pos) /*!< 0x00400000 */
#define ETH_MTLRXQ0OMR_RQS_3 (0x8U << ETH_MTLRXQ0OMR_RQS_Pos) /*!< 0x00800000 */
/*********** Bit definition for ETH_MTLRXQ0MPOCR register ************/
#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos (0U)
#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_Msk (0x7FFU << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */
#define ETH_MTLRXQ0MPOCR_OVFPKTCNT ETH_MTLRXQ0MPOCR_OVFPKTCNT_Msk /*!< Overflow Packet Counter */
#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_0 (0x1U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos) /*!< 0x00000001 */
#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_1 (0x2U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos) /*!< 0x00000002 */
#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_2 (0x4U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos) /*!< 0x00000004 */
#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_3 (0x8U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos) /*!< 0x00000008 */
#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_4 (0x10U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos) /*!< 0x00000010 */
#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_5 (0x20U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos) /*!< 0x00000020 */
#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_6 (0x40U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos) /*!< 0x00000040 */
#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_7 (0x80U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos) /*!< 0x00000080 */
#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_8 (0x100U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos) /*!< 0x00000100 */
#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_9 (0x200U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos) /*!< 0x00000200 */
#define ETH_MTLRXQ0MPOCR_OVFPKTCNT_10 (0x400U << ETH_MTLRXQ0MPOCR_OVFPKTCNT_Pos) /*!< 0x00000400 */
#define ETH_MTLRXQ0MPOCR_OVFCNTOVF_Pos (11U)
#define ETH_MTLRXQ0MPOCR_OVFCNTOVF_Msk (0x1U << ETH_MTLRXQ0MPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */
#define ETH_MTLRXQ0MPOCR_OVFCNTOVF ETH_MTLRXQ0MPOCR_OVFCNTOVF_Msk /*!< Overflow Counter Overflow Bit */
#define ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos (16U)
#define ETH_MTLRXQ0MPOCR_MISPKTCNT_Msk (0x7FFU << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */
#define ETH_MTLRXQ0MPOCR_MISPKTCNT ETH_MTLRXQ0MPOCR_MISPKTCNT_Msk /*!< Missed Packet Counter */
#define ETH_MTLRXQ0MPOCR_MISPKTCNT_0 (0x1U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos) /*!< 0x00010000 */
#define ETH_MTLRXQ0MPOCR_MISPKTCNT_1 (0x2U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos) /*!< 0x00020000 */
#define ETH_MTLRXQ0MPOCR_MISPKTCNT_2 (0x4U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos) /*!< 0x00040000 */
#define ETH_MTLRXQ0MPOCR_MISPKTCNT_3 (0x8U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos) /*!< 0x00080000 */
#define ETH_MTLRXQ0MPOCR_MISPKTCNT_4 (0x10U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos) /*!< 0x00100000 */
#define ETH_MTLRXQ0MPOCR_MISPKTCNT_5 (0x20U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos) /*!< 0x00200000 */
#define ETH_MTLRXQ0MPOCR_MISPKTCNT_6 (0x40U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos) /*!< 0x00400000 */
#define ETH_MTLRXQ0MPOCR_MISPKTCNT_7 (0x80U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos) /*!< 0x00800000 */
#define ETH_MTLRXQ0MPOCR_MISPKTCNT_8 (0x100U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos) /*!< 0x01000000 */
#define ETH_MTLRXQ0MPOCR_MISPKTCNT_9 (0x200U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos) /*!< 0x02000000 */
#define ETH_MTLRXQ0MPOCR_MISPKTCNT_10 (0x400U << ETH_MTLRXQ0MPOCR_MISPKTCNT_Pos) /*!< 0x04000000 */
#define ETH_MTLRXQ0MPOCR_MISCNTOVF_Pos (27U)
#define ETH_MTLRXQ0MPOCR_MISCNTOVF_Msk (0x1U << ETH_MTLRXQ0MPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */
#define ETH_MTLRXQ0MPOCR_MISCNTOVF ETH_MTLRXQ0MPOCR_MISCNTOVF_Msk /*!< Missed Packet Counter Overflow Bit */
/************* Bit definition for ETH_MTLRXQ0DR register *************/
#define ETH_MTLRXQ0DR_RWCSTS_Pos (0U)
#define ETH_MTLRXQ0DR_RWCSTS_Msk (0x1U << ETH_MTLRXQ0DR_RWCSTS_Pos) /*!< 0x00000001 */
#define ETH_MTLRXQ0DR_RWCSTS ETH_MTLRXQ0DR_RWCSTS_Msk /*!< MTL Rx Queue Write Controller Active Status */
#define ETH_MTLRXQ0DR_RRCSTS_Pos (1U)
#define ETH_MTLRXQ0DR_RRCSTS_Msk (0x3U << ETH_MTLRXQ0DR_RRCSTS_Pos) /*!< 0x00000006 */
#define ETH_MTLRXQ0DR_RRCSTS ETH_MTLRXQ0DR_RRCSTS_Msk /*!< MTL Rx Queue Read Controller State */
#define ETH_MTLRXQ0DR_RRCSTS_0 (0x1U << ETH_MTLRXQ0DR_RRCSTS_Pos) /*!< 0x00000002 */
#define ETH_MTLRXQ0DR_RRCSTS_1 (0x2U << ETH_MTLRXQ0DR_RRCSTS_Pos) /*!< 0x00000004 */
#define ETH_MTLRXQ0DR_RXQSTS_Pos (4U)
#define ETH_MTLRXQ0DR_RXQSTS_Msk (0x3U << ETH_MTLRXQ0DR_RXQSTS_Pos) /*!< 0x00000030 */
#define ETH_MTLRXQ0DR_RXQSTS ETH_MTLRXQ0DR_RXQSTS_Msk /*!< MTL Rx Queue Fill-Level Status */
#define ETH_MTLRXQ0DR_RXQSTS_0 (0x1U << ETH_MTLRXQ0DR_RXQSTS_Pos) /*!< 0x00000010 */
#define ETH_MTLRXQ0DR_RXQSTS_1 (0x2U << ETH_MTLRXQ0DR_RXQSTS_Pos) /*!< 0x00000020 */
#define ETH_MTLRXQ0DR_PRXQ_Pos (16U)
#define ETH_MTLRXQ0DR_PRXQ_Msk (0x3FFFU << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x3FFF0000 */
#define ETH_MTLRXQ0DR_PRXQ ETH_MTLRXQ0DR_PRXQ_Msk /*!< Number of Packets in Receive Queue */
#define ETH_MTLRXQ0DR_PRXQ_0 (0x1U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x00010000 */
#define ETH_MTLRXQ0DR_PRXQ_1 (0x2U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x00020000 */
#define ETH_MTLRXQ0DR_PRXQ_2 (0x4U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x00040000 */
#define ETH_MTLRXQ0DR_PRXQ_3 (0x8U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x00080000 */
#define ETH_MTLRXQ0DR_PRXQ_4 (0x10U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x00100000 */
#define ETH_MTLRXQ0DR_PRXQ_5 (0x20U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x00200000 */
#define ETH_MTLRXQ0DR_PRXQ_6 (0x40U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x00400000 */
#define ETH_MTLRXQ0DR_PRXQ_7 (0x80U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x00800000 */
#define ETH_MTLRXQ0DR_PRXQ_8 (0x100U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x01000000 */
#define ETH_MTLRXQ0DR_PRXQ_9 (0x200U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x02000000 */
#define ETH_MTLRXQ0DR_PRXQ_10 (0x400U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x04000000 */
#define ETH_MTLRXQ0DR_PRXQ_11 (0x800U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x08000000 */
#define ETH_MTLRXQ0DR_PRXQ_12 (0x1000U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x10000000 */
#define ETH_MTLRXQ0DR_PRXQ_13 (0x2000U << ETH_MTLRXQ0DR_PRXQ_Pos) /*!< 0x20000000 */
/************* Bit definition for ETH_MTLRXQ0CR register *************/
#define ETH_MTLRXQ0CR_RXQ_WEGT_Pos (0U)
#define ETH_MTLRXQ0CR_RXQ_WEGT_Msk (0x7U << ETH_MTLRXQ0CR_RXQ_WEGT_Pos) /*!< 0x00000007 */
#define ETH_MTLRXQ0CR_RXQ_WEGT ETH_MTLRXQ0CR_RXQ_WEGT_Msk /*!< Receive Queue Weight */
#define ETH_MTLRXQ0CR_RXQ_WEGT_0 (0x1U << ETH_MTLRXQ0CR_RXQ_WEGT_Pos) /*!< 0x00000001 */
#define ETH_MTLRXQ0CR_RXQ_WEGT_1 (0x2U << ETH_MTLRXQ0CR_RXQ_WEGT_Pos) /*!< 0x00000002 */
#define ETH_MTLRXQ0CR_RXQ_WEGT_2 (0x4U << ETH_MTLRXQ0CR_RXQ_WEGT_Pos) /*!< 0x00000004 */
#define ETH_MTLRXQ0CR_RXQ_FRM_ARBIT_Pos (3U)
#define ETH_MTLRXQ0CR_RXQ_FRM_ARBIT_Msk (0x1U << ETH_MTLRXQ0CR_RXQ_FRM_ARBIT_Pos) /*!< 0x00000008 */
#define ETH_MTLRXQ0CR_RXQ_FRM_ARBIT ETH_MTLRXQ0CR_RXQ_FRM_ARBIT_Msk /*!< Receive Queue Packet Arbitration */
/************ Bit definition for ETH_MTLTXQ1OMR register *************/
#define ETH_MTLTXQ1OMR_FTQ_Pos (0U)
#define ETH_MTLTXQ1OMR_FTQ_Msk (0x1U << ETH_MTLTXQ1OMR_FTQ_Pos) /*!< 0x00000001 */
#define ETH_MTLTXQ1OMR_FTQ ETH_MTLTXQ1OMR_FTQ_Msk /*!< Flush Transmit Queue */
#define ETH_MTLTXQ1OMR_TSF_Pos (1U)
#define ETH_MTLTXQ1OMR_TSF_Msk (0x1U << ETH_MTLTXQ1OMR_TSF_Pos) /*!< 0x00000002 */
#define ETH_MTLTXQ1OMR_TSF ETH_MTLTXQ1OMR_TSF_Msk /*!< Transmit Store and Forward */
#define ETH_MTLTXQ1OMR_TXQEN_Pos (2U)
#define ETH_MTLTXQ1OMR_TXQEN_Msk (0x3U << ETH_MTLTXQ1OMR_TXQEN_Pos) /*!< 0x0000000C */
#define ETH_MTLTXQ1OMR_TXQEN ETH_MTLTXQ1OMR_TXQEN_Msk /*!< Transmit Queue Enable */
#define ETH_MTLTXQ1OMR_TXQEN_0 (0x1U << ETH_MTLTXQ1OMR_TXQEN_Pos) /*!< 0x00000004 */
#define ETH_MTLTXQ1OMR_TXQEN_1 (0x2U << ETH_MTLTXQ1OMR_TXQEN_Pos) /*!< 0x00000008 */
#define ETH_MTLTXQ1OMR_TTC_Pos (4U)
#define ETH_MTLTXQ1OMR_TTC_Msk (0x7U << ETH_MTLTXQ1OMR_TTC_Pos) /*!< 0x00000070 */
#define ETH_MTLTXQ1OMR_TTC ETH_MTLTXQ1OMR_TTC_Msk /*!< Transmit Threshold Control */
#define ETH_MTLTXQ1OMR_TTC_0 (0x1U << ETH_MTLTXQ1OMR_TTC_Pos) /*!< 0x00000010 */
#define ETH_MTLTXQ1OMR_TTC_1 (0x2U << ETH_MTLTXQ1OMR_TTC_Pos) /*!< 0x00000020 */
#define ETH_MTLTXQ1OMR_TTC_2 (0x4U << ETH_MTLTXQ1OMR_TTC_Pos) /*!< 0x00000040 */
#define ETH_MTLTXQ1OMR_TQS_Pos (16U)
#define ETH_MTLTXQ1OMR_TQS_Msk (0x1FFU << ETH_MTLTXQ1OMR_TQS_Pos) /*!< 0x01FF0000 */
#define ETH_MTLTXQ1OMR_TQS ETH_MTLTXQ1OMR_TQS_Msk /*!< Transmit Queue Size */
#define ETH_MTLTXQ1OMR_TQS_0 (0x1U << ETH_MTLTXQ1OMR_TQS_Pos) /*!< 0x00010000 */
#define ETH_MTLTXQ1OMR_TQS_1 (0x2U << ETH_MTLTXQ1OMR_TQS_Pos) /*!< 0x00020000 */
#define ETH_MTLTXQ1OMR_TQS_2 (0x4U << ETH_MTLTXQ1OMR_TQS_Pos) /*!< 0x00040000 */
#define ETH_MTLTXQ1OMR_TQS_3 (0x8U << ETH_MTLTXQ1OMR_TQS_Pos) /*!< 0x00080000 */
#define ETH_MTLTXQ1OMR_TQS_4 (0x10U << ETH_MTLTXQ1OMR_TQS_Pos) /*!< 0x00100000 */
#define ETH_MTLTXQ1OMR_TQS_5 (0x20U << ETH_MTLTXQ1OMR_TQS_Pos) /*!< 0x00200000 */
#define ETH_MTLTXQ1OMR_TQS_6 (0x40U << ETH_MTLTXQ1OMR_TQS_Pos) /*!< 0x00400000 */
#define ETH_MTLTXQ1OMR_TQS_7 (0x80U << ETH_MTLTXQ1OMR_TQS_Pos) /*!< 0x00800000 */
#define ETH_MTLTXQ1OMR_TQS_8 (0x100U << ETH_MTLTXQ1OMR_TQS_Pos) /*!< 0x01000000 */
/************* Bit definition for ETH_MTLTXQ1UR register *************/
#define ETH_MTLTXQ1UR_UFFRMCNT_Pos (0U)
#define ETH_MTLTXQ1UR_UFFRMCNT_Msk (0x7FFU << ETH_MTLTXQ1UR_UFFRMCNT_Pos) /*!< 0x000007FF */
#define ETH_MTLTXQ1UR_UFFRMCNT ETH_MTLTXQ1UR_UFFRMCNT_Msk /*!< Underflow Packet Counter */
#define ETH_MTLTXQ1UR_UFFRMCNT_0 (0x1U << ETH_MTLTXQ1UR_UFFRMCNT_Pos) /*!< 0x00000001 */
#define ETH_MTLTXQ1UR_UFFRMCNT_1 (0x2U << ETH_MTLTXQ1UR_UFFRMCNT_Pos) /*!< 0x00000002 */
#define ETH_MTLTXQ1UR_UFFRMCNT_2 (0x4U << ETH_MTLTXQ1UR_UFFRMCNT_Pos) /*!< 0x00000004 */
#define ETH_MTLTXQ1UR_UFFRMCNT_3 (0x8U << ETH_MTLTXQ1UR_UFFRMCNT_Pos) /*!< 0x00000008 */
#define ETH_MTLTXQ1UR_UFFRMCNT_4 (0x10U << ETH_MTLTXQ1UR_UFFRMCNT_Pos) /*!< 0x00000010 */
#define ETH_MTLTXQ1UR_UFFRMCNT_5 (0x20U << ETH_MTLTXQ1UR_UFFRMCNT_Pos) /*!< 0x00000020 */
#define ETH_MTLTXQ1UR_UFFRMCNT_6 (0x40U << ETH_MTLTXQ1UR_UFFRMCNT_Pos) /*!< 0x00000040 */
#define ETH_MTLTXQ1UR_UFFRMCNT_7 (0x80U << ETH_MTLTXQ1UR_UFFRMCNT_Pos) /*!< 0x00000080 */
#define ETH_MTLTXQ1UR_UFFRMCNT_8 (0x100U << ETH_MTLTXQ1UR_UFFRMCNT_Pos) /*!< 0x00000100 */
#define ETH_MTLTXQ1UR_UFFRMCNT_9 (0x200U << ETH_MTLTXQ1UR_UFFRMCNT_Pos) /*!< 0x00000200 */
#define ETH_MTLTXQ1UR_UFFRMCNT_10 (0x400U << ETH_MTLTXQ1UR_UFFRMCNT_Pos) /*!< 0x00000400 */
#define ETH_MTLTXQ1UR_UFCNTOVF_Pos (11U)
#define ETH_MTLTXQ1UR_UFCNTOVF_Msk (0x1U << ETH_MTLTXQ1UR_UFCNTOVF_Pos) /*!< 0x00000800 */
#define ETH_MTLTXQ1UR_UFCNTOVF ETH_MTLTXQ1UR_UFCNTOVF_Msk /*!< Overflow Bit for Underflow Packet Counter */
/************* Bit definition for ETH_MTLTXQ1DR register *************/
#define ETH_MTLTXQ1DR_TXQPAUSED_Pos (0U)
#define ETH_MTLTXQ1DR_TXQPAUSED_Msk (0x1U << ETH_MTLTXQ1DR_TXQPAUSED_Pos) /*!< 0x00000001 */
#define ETH_MTLTXQ1DR_TXQPAUSED ETH_MTLTXQ1DR_TXQPAUSED_Msk /*!< Transmit Queue in Pause */
#define ETH_MTLTXQ1DR_TRCSTS_Pos (1U)
#define ETH_MTLTXQ1DR_TRCSTS_Msk (0x3U << ETH_MTLTXQ1DR_TRCSTS_Pos) /*!< 0x00000006 */
#define ETH_MTLTXQ1DR_TRCSTS ETH_MTLTXQ1DR_TRCSTS_Msk /*!< MTL Tx Queue Read Controller Status */
#define ETH_MTLTXQ1DR_TRCSTS_0 (0x1U << ETH_MTLTXQ1DR_TRCSTS_Pos) /*!< 0x00000002 */
#define ETH_MTLTXQ1DR_TRCSTS_1 (0x2U << ETH_MTLTXQ1DR_TRCSTS_Pos) /*!< 0x00000004 */
#define ETH_MTLTXQ1DR_TWCSTS_Pos (3U)
#define ETH_MTLTXQ1DR_TWCSTS_Msk (0x1U << ETH_MTLTXQ1DR_TWCSTS_Pos) /*!< 0x00000008 */
#define ETH_MTLTXQ1DR_TWCSTS ETH_MTLTXQ1DR_TWCSTS_Msk /*!< MTL Tx Queue Write Controller Status */
#define ETH_MTLTXQ1DR_TXQSTS_Pos (4U)
#define ETH_MTLTXQ1DR_TXQSTS_Msk (0x1U << ETH_MTLTXQ1DR_TXQSTS_Pos) /*!< 0x00000010 */
#define ETH_MTLTXQ1DR_TXQSTS ETH_MTLTXQ1DR_TXQSTS_Msk /*!< MTL Tx Queue Not Empty Status */
#define ETH_MTLTXQ1DR_TXSTSFSTS_Pos (5U)
#define ETH_MTLTXQ1DR_TXSTSFSTS_Msk (0x1U << ETH_MTLTXQ1DR_TXSTSFSTS_Pos) /*!< 0x00000020 */
#define ETH_MTLTXQ1DR_TXSTSFSTS ETH_MTLTXQ1DR_TXSTSFSTS_Msk /*!< MTL Tx Status FIFO Full Status */
#define ETH_MTLTXQ1DR_PTXQ_Pos (16U)
#define ETH_MTLTXQ1DR_PTXQ_Msk (0x7U << ETH_MTLTXQ1DR_PTXQ_Pos) /*!< 0x00070000 */
#define ETH_MTLTXQ1DR_PTXQ ETH_MTLTXQ1DR_PTXQ_Msk /*!< Number of Packets in the Transmit Queue */
#define ETH_MTLTXQ1DR_PTXQ_0 (0x1U << ETH_MTLTXQ1DR_PTXQ_Pos) /*!< 0x00010000 */
#define ETH_MTLTXQ1DR_PTXQ_1 (0x2U << ETH_MTLTXQ1DR_PTXQ_Pos) /*!< 0x00020000 */
#define ETH_MTLTXQ1DR_PTXQ_2 (0x4U << ETH_MTLTXQ1DR_PTXQ_Pos) /*!< 0x00040000 */
#define ETH_MTLTXQ1DR_STXSTSF_Pos (20U)
#define ETH_MTLTXQ1DR_STXSTSF_Msk (0x7U << ETH_MTLTXQ1DR_STXSTSF_Pos) /*!< 0x00700000 */
#define ETH_MTLTXQ1DR_STXSTSF ETH_MTLTXQ1DR_STXSTSF_Msk /*!< Number of Status Words in Tx Status FIFO of Queue */
#define ETH_MTLTXQ1DR_STXSTSF_0 (0x1U << ETH_MTLTXQ1DR_STXSTSF_Pos) /*!< 0x00100000 */
#define ETH_MTLTXQ1DR_STXSTSF_1 (0x2U << ETH_MTLTXQ1DR_STXSTSF_Pos) /*!< 0x00200000 */
#define ETH_MTLTXQ1DR_STXSTSF_2 (0x4U << ETH_MTLTXQ1DR_STXSTSF_Pos) /*!< 0x00400000 */
/************ Bit definition for ETH_MTLTXQ1ECR register *************/
#define ETH_MTLTXQ1ECR_AVALG_Pos (2U)
#define ETH_MTLTXQ1ECR_AVALG_Msk (0x1U << ETH_MTLTXQ1ECR_AVALG_Pos) /*!< 0x00000004 */
#define ETH_MTLTXQ1ECR_AVALG ETH_MTLTXQ1ECR_AVALG_Msk /*!< AV Algorithm */
#define ETH_MTLTXQ1ECR_CC_Pos (3U)
#define ETH_MTLTXQ1ECR_CC_Msk (0x1U << ETH_MTLTXQ1ECR_CC_Pos) /*!< 0x00000008 */
#define ETH_MTLTXQ1ECR_CC ETH_MTLTXQ1ECR_CC_Msk /*!< Credit Control */
#define ETH_MTLTXQ1ECR_SLC_Pos (4U)
#define ETH_MTLTXQ1ECR_SLC_Msk (0x7U << ETH_MTLTXQ1ECR_SLC_Pos) /*!< 0x00000070 */
#define ETH_MTLTXQ1ECR_SLC ETH_MTLTXQ1ECR_SLC_Msk /*!< Slot Count */
#define ETH_MTLTXQ1ECR_SLC_0 (0x1U << ETH_MTLTXQ1ECR_SLC_Pos) /*!< 0x00000010 */
#define ETH_MTLTXQ1ECR_SLC_1 (0x2U << ETH_MTLTXQ1ECR_SLC_Pos) /*!< 0x00000020 */
#define ETH_MTLTXQ1ECR_SLC_2 (0x4U << ETH_MTLTXQ1ECR_SLC_Pos) /*!< 0x00000040 */
/************ Bit definition for ETH_MTLTXQ1ESR register *************/
#define ETH_MTLTXQ1ESR_ABS_Pos (0U)
#define ETH_MTLTXQ1ESR_ABS_Msk (0xFFFFFFU << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00FFFFFF */
#define ETH_MTLTXQ1ESR_ABS ETH_MTLTXQ1ESR_ABS_Msk /*!< Average Bits per Slot */
#define ETH_MTLTXQ1ESR_ABS_0 (0x1U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00000001 */
#define ETH_MTLTXQ1ESR_ABS_1 (0x2U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00000002 */
#define ETH_MTLTXQ1ESR_ABS_2 (0x4U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00000004 */
#define ETH_MTLTXQ1ESR_ABS_3 (0x8U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00000008 */
#define ETH_MTLTXQ1ESR_ABS_4 (0x10U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00000010 */
#define ETH_MTLTXQ1ESR_ABS_5 (0x20U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00000020 */
#define ETH_MTLTXQ1ESR_ABS_6 (0x40U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00000040 */
#define ETH_MTLTXQ1ESR_ABS_7 (0x80U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00000080 */
#define ETH_MTLTXQ1ESR_ABS_8 (0x100U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00000100 */
#define ETH_MTLTXQ1ESR_ABS_9 (0x200U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00000200 */
#define ETH_MTLTXQ1ESR_ABS_10 (0x400U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00000400 */
#define ETH_MTLTXQ1ESR_ABS_11 (0x800U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00000800 */
#define ETH_MTLTXQ1ESR_ABS_12 (0x1000U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00001000 */
#define ETH_MTLTXQ1ESR_ABS_13 (0x2000U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00002000 */
#define ETH_MTLTXQ1ESR_ABS_14 (0x4000U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00004000 */
#define ETH_MTLTXQ1ESR_ABS_15 (0x8000U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00008000 */
#define ETH_MTLTXQ1ESR_ABS_16 (0x10000U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00010000 */
#define ETH_MTLTXQ1ESR_ABS_17 (0x20000U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00020000 */
#define ETH_MTLTXQ1ESR_ABS_18 (0x40000U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00040000 */
#define ETH_MTLTXQ1ESR_ABS_19 (0x80000U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00080000 */
#define ETH_MTLTXQ1ESR_ABS_20 (0x100000U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00100000 */
#define ETH_MTLTXQ1ESR_ABS_21 (0x200000U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00200000 */
#define ETH_MTLTXQ1ESR_ABS_22 (0x400000U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00400000 */
#define ETH_MTLTXQ1ESR_ABS_23 (0x800000U << ETH_MTLTXQ1ESR_ABS_Pos) /*!< 0x00800000 */
/************ Bit definition for ETH_MTLTXQ1QWR register *************/
#define ETH_MTLTXQ1QWR_ISCQW_Pos (0U)
#define ETH_MTLTXQ1QWR_ISCQW_Msk (0x1FFFFFU << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x001FFFFF */
#define ETH_MTLTXQ1QWR_ISCQW ETH_MTLTXQ1QWR_ISCQW_Msk /*!< idleSlopeCredit value for queue 1 */
#define ETH_MTLTXQ1QWR_ISCQW_0 (0x1U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00000001 */
#define ETH_MTLTXQ1QWR_ISCQW_1 (0x2U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00000002 */
#define ETH_MTLTXQ1QWR_ISCQW_2 (0x4U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00000004 */
#define ETH_MTLTXQ1QWR_ISCQW_3 (0x8U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00000008 */
#define ETH_MTLTXQ1QWR_ISCQW_4 (0x10U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00000010 */
#define ETH_MTLTXQ1QWR_ISCQW_5 (0x20U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00000020 */
#define ETH_MTLTXQ1QWR_ISCQW_6 (0x40U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00000040 */
#define ETH_MTLTXQ1QWR_ISCQW_7 (0x80U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00000080 */
#define ETH_MTLTXQ1QWR_ISCQW_8 (0x100U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00000100 */
#define ETH_MTLTXQ1QWR_ISCQW_9 (0x200U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00000200 */
#define ETH_MTLTXQ1QWR_ISCQW_10 (0x400U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00000400 */
#define ETH_MTLTXQ1QWR_ISCQW_11 (0x800U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00000800 */
#define ETH_MTLTXQ1QWR_ISCQW_12 (0x1000U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00001000 */
#define ETH_MTLTXQ1QWR_ISCQW_13 (0x2000U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00002000 */
#define ETH_MTLTXQ1QWR_ISCQW_14 (0x4000U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00004000 */
#define ETH_MTLTXQ1QWR_ISCQW_15 (0x8000U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00008000 */
#define ETH_MTLTXQ1QWR_ISCQW_16 (0x10000U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00010000 */
#define ETH_MTLTXQ1QWR_ISCQW_17 (0x20000U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00020000 */
#define ETH_MTLTXQ1QWR_ISCQW_18 (0x40000U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00040000 */
#define ETH_MTLTXQ1QWR_ISCQW_19 (0x80000U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00080000 */
#define ETH_MTLTXQ1QWR_ISCQW_20 (0x100000U << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00100000 */
/************ Bit definition for ETH_MTLTXQ1SSCR register ************/
#define ETH_MTLTXQ1SSCR_SSC_Pos (0U)
#define ETH_MTLTXQ1SSCR_SSC_Msk (0x3FFFU << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00003FFF */
#define ETH_MTLTXQ1SSCR_SSC ETH_MTLTXQ1SSCR_SSC_Msk /*!< sendSlopeCredit Value */
#define ETH_MTLTXQ1SSCR_SSC_0 (0x1U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00000001 */
#define ETH_MTLTXQ1SSCR_SSC_1 (0x2U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00000002 */
#define ETH_MTLTXQ1SSCR_SSC_2 (0x4U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00000004 */
#define ETH_MTLTXQ1SSCR_SSC_3 (0x8U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00000008 */
#define ETH_MTLTXQ1SSCR_SSC_4 (0x10U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00000010 */
#define ETH_MTLTXQ1SSCR_SSC_5 (0x20U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00000020 */
#define ETH_MTLTXQ1SSCR_SSC_6 (0x40U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00000040 */
#define ETH_MTLTXQ1SSCR_SSC_7 (0x80U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00000080 */
#define ETH_MTLTXQ1SSCR_SSC_8 (0x100U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00000100 */
#define ETH_MTLTXQ1SSCR_SSC_9 (0x200U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00000200 */
#define ETH_MTLTXQ1SSCR_SSC_10 (0x400U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00000400 */
#define ETH_MTLTXQ1SSCR_SSC_11 (0x800U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00000800 */
#define ETH_MTLTXQ1SSCR_SSC_12 (0x1000U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00001000 */
#define ETH_MTLTXQ1SSCR_SSC_13 (0x2000U << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00002000 */
/************ Bit definition for ETH_MTLTXQ1HCR register *************/
#define ETH_MTLTXQ1HCR_HC_Pos (0U)
#define ETH_MTLTXQ1HCR_HC_Msk (0x1FFFFFFFU << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x1FFFFFFF */
#define ETH_MTLTXQ1HCR_HC ETH_MTLTXQ1HCR_HC_Msk /*!< hiCredit Value */
#define ETH_MTLTXQ1HCR_HC_0 (0x1U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00000001 */
#define ETH_MTLTXQ1HCR_HC_1 (0x2U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00000002 */
#define ETH_MTLTXQ1HCR_HC_2 (0x4U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00000004 */
#define ETH_MTLTXQ1HCR_HC_3 (0x8U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00000008 */
#define ETH_MTLTXQ1HCR_HC_4 (0x10U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00000010 */
#define ETH_MTLTXQ1HCR_HC_5 (0x20U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00000020 */
#define ETH_MTLTXQ1HCR_HC_6 (0x40U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00000040 */
#define ETH_MTLTXQ1HCR_HC_7 (0x80U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00000080 */
#define ETH_MTLTXQ1HCR_HC_8 (0x100U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00000100 */
#define ETH_MTLTXQ1HCR_HC_9 (0x200U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00000200 */
#define ETH_MTLTXQ1HCR_HC_10 (0x400U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00000400 */
#define ETH_MTLTXQ1HCR_HC_11 (0x800U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00000800 */
#define ETH_MTLTXQ1HCR_HC_12 (0x1000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00001000 */
#define ETH_MTLTXQ1HCR_HC_13 (0x2000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00002000 */
#define ETH_MTLTXQ1HCR_HC_14 (0x4000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00004000 */
#define ETH_MTLTXQ1HCR_HC_15 (0x8000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00008000 */
#define ETH_MTLTXQ1HCR_HC_16 (0x10000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00010000 */
#define ETH_MTLTXQ1HCR_HC_17 (0x20000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00020000 */
#define ETH_MTLTXQ1HCR_HC_18 (0x40000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00040000 */
#define ETH_MTLTXQ1HCR_HC_19 (0x80000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00080000 */
#define ETH_MTLTXQ1HCR_HC_20 (0x100000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00100000 */
#define ETH_MTLTXQ1HCR_HC_21 (0x200000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00200000 */
#define ETH_MTLTXQ1HCR_HC_22 (0x400000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00400000 */
#define ETH_MTLTXQ1HCR_HC_23 (0x800000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x00800000 */
#define ETH_MTLTXQ1HCR_HC_24 (0x1000000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x01000000 */
#define ETH_MTLTXQ1HCR_HC_25 (0x2000000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x02000000 */
#define ETH_MTLTXQ1HCR_HC_26 (0x4000000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x04000000 */
#define ETH_MTLTXQ1HCR_HC_27 (0x8000000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x08000000 */
#define ETH_MTLTXQ1HCR_HC_28 (0x10000000U << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x10000000 */
/************ Bit definition for ETH_MTLTXQ1LCR register *************/
#define ETH_MTLTXQ1LCR_LC_Pos (0U)
#define ETH_MTLTXQ1LCR_LC_Msk (0x1FFFFFFFU << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x1FFFFFFF */
#define ETH_MTLTXQ1LCR_LC ETH_MTLTXQ1LCR_LC_Msk /*!< loCredit Value */
#define ETH_MTLTXQ1LCR_LC_0 (0x1U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00000001 */
#define ETH_MTLTXQ1LCR_LC_1 (0x2U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00000002 */
#define ETH_MTLTXQ1LCR_LC_2 (0x4U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00000004 */
#define ETH_MTLTXQ1LCR_LC_3 (0x8U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00000008 */
#define ETH_MTLTXQ1LCR_LC_4 (0x10U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00000010 */
#define ETH_MTLTXQ1LCR_LC_5 (0x20U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00000020 */
#define ETH_MTLTXQ1LCR_LC_6 (0x40U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00000040 */
#define ETH_MTLTXQ1LCR_LC_7 (0x80U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00000080 */
#define ETH_MTLTXQ1LCR_LC_8 (0x100U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00000100 */
#define ETH_MTLTXQ1LCR_LC_9 (0x200U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00000200 */
#define ETH_MTLTXQ1LCR_LC_10 (0x400U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00000400 */
#define ETH_MTLTXQ1LCR_LC_11 (0x800U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00000800 */
#define ETH_MTLTXQ1LCR_LC_12 (0x1000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00001000 */
#define ETH_MTLTXQ1LCR_LC_13 (0x2000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00002000 */
#define ETH_MTLTXQ1LCR_LC_14 (0x4000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00004000 */
#define ETH_MTLTXQ1LCR_LC_15 (0x8000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00008000 */
#define ETH_MTLTXQ1LCR_LC_16 (0x10000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00010000 */
#define ETH_MTLTXQ1LCR_LC_17 (0x20000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00020000 */
#define ETH_MTLTXQ1LCR_LC_18 (0x40000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00040000 */
#define ETH_MTLTXQ1LCR_LC_19 (0x80000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00080000 */
#define ETH_MTLTXQ1LCR_LC_20 (0x100000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00100000 */
#define ETH_MTLTXQ1LCR_LC_21 (0x200000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00200000 */
#define ETH_MTLTXQ1LCR_LC_22 (0x400000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00400000 */
#define ETH_MTLTXQ1LCR_LC_23 (0x800000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x00800000 */
#define ETH_MTLTXQ1LCR_LC_24 (0x1000000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x01000000 */
#define ETH_MTLTXQ1LCR_LC_25 (0x2000000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x02000000 */
#define ETH_MTLTXQ1LCR_LC_26 (0x4000000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x04000000 */
#define ETH_MTLTXQ1LCR_LC_27 (0x8000000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x08000000 */
#define ETH_MTLTXQ1LCR_LC_28 (0x10000000U << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x10000000 */
/************* Bit definition for ETH_MTLQ1ICSR register *************/
#define ETH_MTLQ1ICSR_TXUNFIS_Pos (0U)
#define ETH_MTLQ1ICSR_TXUNFIS_Msk (0x1U << ETH_MTLQ1ICSR_TXUNFIS_Pos) /*!< 0x00000001 */
#define ETH_MTLQ1ICSR_TXUNFIS ETH_MTLQ1ICSR_TXUNFIS_Msk /*!< Transmit Queue Underflow Interrupt Status */
#define ETH_MTLQ1ICSR_ABPSIS_Pos (1U)
#define ETH_MTLQ1ICSR_ABPSIS_Msk (0x1U << ETH_MTLQ1ICSR_ABPSIS_Pos) /*!< 0x00000002 */
#define ETH_MTLQ1ICSR_ABPSIS ETH_MTLQ1ICSR_ABPSIS_Msk /*!< Average Bits Per Slot Interrupt Status */
#define ETH_MTLQ1ICSR_TXUIE_Pos (8U)
#define ETH_MTLQ1ICSR_TXUIE_Msk (0x1U << ETH_MTLQ1ICSR_TXUIE_Pos) /*!< 0x00000100 */
#define ETH_MTLQ1ICSR_TXUIE ETH_MTLQ1ICSR_TXUIE_Msk /*!< Transmit Queue Underflow Interrupt Enable */
#define ETH_MTLQ1ICSR_ABPSIE_Pos (9U)
#define ETH_MTLQ1ICSR_ABPSIE_Msk (0x1U << ETH_MTLQ1ICSR_ABPSIE_Pos) /*!< 0x00000200 */
#define ETH_MTLQ1ICSR_ABPSIE ETH_MTLQ1ICSR_ABPSIE_Msk /*!< Average Bits Per Slot Interrupt Enable */
#define ETH_MTLQ1ICSR_RXOVFIS_Pos (16U)
#define ETH_MTLQ1ICSR_RXOVFIS_Msk (0x1U << ETH_MTLQ1ICSR_RXOVFIS_Pos) /*!< 0x00010000 */
#define ETH_MTLQ1ICSR_RXOVFIS ETH_MTLQ1ICSR_RXOVFIS_Msk /*!< Receive Queue Overflow Interrupt Status */
#define ETH_MTLQ1ICSR_RXOIE_Pos (24U)
#define ETH_MTLQ1ICSR_RXOIE_Msk (0x1U << ETH_MTLQ1ICSR_RXOIE_Pos) /*!< 0x01000000 */
#define ETH_MTLQ1ICSR_RXOIE ETH_MTLQ1ICSR_RXOIE_Msk /*!< Receive Queue Overflow Interrupt Enable */
/************ Bit definition for ETH_MTLRXQ1OMR register *************/
#define ETH_MTLRXQ1OMR_RTC_Pos (0U)
#define ETH_MTLRXQ1OMR_RTC_Msk (0x3U << ETH_MTLRXQ1OMR_RTC_Pos) /*!< 0x00000003 */
#define ETH_MTLRXQ1OMR_RTC ETH_MTLRXQ1OMR_RTC_Msk /*!< Receive Queue Threshold Control */
#define ETH_MTLRXQ1OMR_RTC_0 (0x1U << ETH_MTLRXQ1OMR_RTC_Pos) /*!< 0x00000001 */
#define ETH_MTLRXQ1OMR_RTC_1 (0x2U << ETH_MTLRXQ1OMR_RTC_Pos) /*!< 0x00000002 */
#define ETH_MTLRXQ1OMR_FUP_Pos (3U)
#define ETH_MTLRXQ1OMR_FUP_Msk (0x1U << ETH_MTLRXQ1OMR_FUP_Pos) /*!< 0x00000008 */
#define ETH_MTLRXQ1OMR_FUP ETH_MTLRXQ1OMR_FUP_Msk /*!< Forward Undersized Good Packets */
#define ETH_MTLRXQ1OMR_FEP_Pos (4U)
#define ETH_MTLRXQ1OMR_FEP_Msk (0x1U << ETH_MTLRXQ1OMR_FEP_Pos) /*!< 0x00000010 */
#define ETH_MTLRXQ1OMR_FEP ETH_MTLRXQ1OMR_FEP_Msk /*!< Forward Error Packets */
#define ETH_MTLRXQ1OMR_RSF_Pos (5U)
#define ETH_MTLRXQ1OMR_RSF_Msk (0x1U << ETH_MTLRXQ1OMR_RSF_Pos) /*!< 0x00000020 */
#define ETH_MTLRXQ1OMR_RSF ETH_MTLRXQ1OMR_RSF_Msk /*!< Receive Queue Store and Forward */
#define ETH_MTLRXQ1OMR_DIS_TCP_EF_Pos (6U)
#define ETH_MTLRXQ1OMR_DIS_TCP_EF_Msk (0x1U << ETH_MTLRXQ1OMR_DIS_TCP_EF_Pos) /*!< 0x00000040 */
#define ETH_MTLRXQ1OMR_DIS_TCP_EF ETH_MTLRXQ1OMR_DIS_TCP_EF_Msk /*!< Disable Dropping of TCP/IP Checksum Error Packets */
#define ETH_MTLRXQ1OMR_EHFC_Pos (7U)
#define ETH_MTLRXQ1OMR_EHFC_Msk (0x1U << ETH_MTLRXQ1OMR_EHFC_Pos) /*!< 0x00000080 */
#define ETH_MTLRXQ1OMR_EHFC ETH_MTLRXQ1OMR_EHFC_Msk /*!< Enable Hardware Flow Control */
#define ETH_MTLRXQ1OMR_RFA_Pos (8U)
#define ETH_MTLRXQ1OMR_RFA_Msk (0x7U << ETH_MTLRXQ1OMR_RFA_Pos) /*!< 0x00000700 */
#define ETH_MTLRXQ1OMR_RFA ETH_MTLRXQ1OMR_RFA_Msk /*!< Threshold for Activating Flow Control (in half-duplex and full-duplex */
#define ETH_MTLRXQ1OMR_RFA_0 (0x1U << ETH_MTLRXQ1OMR_RFA_Pos) /*!< 0x00000100 */
#define ETH_MTLRXQ1OMR_RFA_1 (0x2U << ETH_MTLRXQ1OMR_RFA_Pos) /*!< 0x00000200 */
#define ETH_MTLRXQ1OMR_RFA_2 (0x4U << ETH_MTLRXQ1OMR_RFA_Pos) /*!< 0x00000400 */
#define ETH_MTLRXQ1OMR_RFD_Pos (14U)
#define ETH_MTLRXQ1OMR_RFD_Msk (0x7U << ETH_MTLRXQ1OMR_RFD_Pos) /*!< 0x0001C000 */
#define ETH_MTLRXQ1OMR_RFD ETH_MTLRXQ1OMR_RFD_Msk /*!< Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
#define ETH_MTLRXQ1OMR_RFD_0 (0x1U << ETH_MTLRXQ1OMR_RFD_Pos) /*!< 0x00004000 */
#define ETH_MTLRXQ1OMR_RFD_1 (0x2U << ETH_MTLRXQ1OMR_RFD_Pos) /*!< 0x00008000 */
#define ETH_MTLRXQ1OMR_RFD_2 (0x4U << ETH_MTLRXQ1OMR_RFD_Pos) /*!< 0x00010000 */
#define ETH_MTLRXQ1OMR_RQS_Pos (20U)
#define ETH_MTLRXQ1OMR_RQS_Msk (0xFU << ETH_MTLRXQ1OMR_RQS_Pos) /*!< 0x00F00000 */
#define ETH_MTLRXQ1OMR_RQS ETH_MTLRXQ1OMR_RQS_Msk /*!< Receive Queue Size */
#define ETH_MTLRXQ1OMR_RQS_0 (0x1U << ETH_MTLRXQ1OMR_RQS_Pos) /*!< 0x00100000 */
#define ETH_MTLRXQ1OMR_RQS_1 (0x2U << ETH_MTLRXQ1OMR_RQS_Pos) /*!< 0x00200000 */
#define ETH_MTLRXQ1OMR_RQS_2 (0x4U << ETH_MTLRXQ1OMR_RQS_Pos) /*!< 0x00400000 */
#define ETH_MTLRXQ1OMR_RQS_3 (0x8U << ETH_MTLRXQ1OMR_RQS_Pos) /*!< 0x00800000 */
/*********** Bit definition for ETH_MTLRXQ1MPOCR register ************/
#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos (0U)
#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_Msk (0x7FFU << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */
#define ETH_MTLRXQ1MPOCR_OVFPKTCNT ETH_MTLRXQ1MPOCR_OVFPKTCNT_Msk /*!< Overflow Packet Counter */
#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_0 (0x1U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos) /*!< 0x00000001 */
#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_1 (0x2U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos) /*!< 0x00000002 */
#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_2 (0x4U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos) /*!< 0x00000004 */
#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_3 (0x8U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos) /*!< 0x00000008 */
#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_4 (0x10U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos) /*!< 0x00000010 */
#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_5 (0x20U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos) /*!< 0x00000020 */
#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_6 (0x40U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos) /*!< 0x00000040 */
#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_7 (0x80U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos) /*!< 0x00000080 */
#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_8 (0x100U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos) /*!< 0x00000100 */
#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_9 (0x200U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos) /*!< 0x00000200 */
#define ETH_MTLRXQ1MPOCR_OVFPKTCNT_10 (0x400U << ETH_MTLRXQ1MPOCR_OVFPKTCNT_Pos) /*!< 0x00000400 */
#define ETH_MTLRXQ1MPOCR_OVFCNTOVF_Pos (11U)
#define ETH_MTLRXQ1MPOCR_OVFCNTOVF_Msk (0x1U << ETH_MTLRXQ1MPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */
#define ETH_MTLRXQ1MPOCR_OVFCNTOVF ETH_MTLRXQ1MPOCR_OVFCNTOVF_Msk /*!< Overflow Counter Overflow Bit */
#define ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos (16U)
#define ETH_MTLRXQ1MPOCR_MISPKTCNT_Msk (0x7FFU << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */
#define ETH_MTLRXQ1MPOCR_MISPKTCNT ETH_MTLRXQ1MPOCR_MISPKTCNT_Msk /*!< Missed Packet Counter */
#define ETH_MTLRXQ1MPOCR_MISPKTCNT_0 (0x1U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos) /*!< 0x00010000 */
#define ETH_MTLRXQ1MPOCR_MISPKTCNT_1 (0x2U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos) /*!< 0x00020000 */
#define ETH_MTLRXQ1MPOCR_MISPKTCNT_2 (0x4U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos) /*!< 0x00040000 */
#define ETH_MTLRXQ1MPOCR_MISPKTCNT_3 (0x8U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos) /*!< 0x00080000 */
#define ETH_MTLRXQ1MPOCR_MISPKTCNT_4 (0x10U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos) /*!< 0x00100000 */
#define ETH_MTLRXQ1MPOCR_MISPKTCNT_5 (0x20U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos) /*!< 0x00200000 */
#define ETH_MTLRXQ1MPOCR_MISPKTCNT_6 (0x40U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos) /*!< 0x00400000 */
#define ETH_MTLRXQ1MPOCR_MISPKTCNT_7 (0x80U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos) /*!< 0x00800000 */
#define ETH_MTLRXQ1MPOCR_MISPKTCNT_8 (0x100U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos) /*!< 0x01000000 */
#define ETH_MTLRXQ1MPOCR_MISPKTCNT_9 (0x200U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos) /*!< 0x02000000 */
#define ETH_MTLRXQ1MPOCR_MISPKTCNT_10 (0x400U << ETH_MTLRXQ1MPOCR_MISPKTCNT_Pos) /*!< 0x04000000 */
#define ETH_MTLRXQ1MPOCR_MISCNTOVF_Pos (27U)
#define ETH_MTLRXQ1MPOCR_MISCNTOVF_Msk (0x1U << ETH_MTLRXQ1MPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */
#define ETH_MTLRXQ1MPOCR_MISCNTOVF ETH_MTLRXQ1MPOCR_MISCNTOVF_Msk /*!< Missed Packet Counter Overflow Bit */
/************* Bit definition for ETH_MTLRXQ1DR register *************/
#define ETH_MTLRXQ1DR_RWCSTS_Pos (0U)
#define ETH_MTLRXQ1DR_RWCSTS_Msk (0x1U << ETH_MTLRXQ1DR_RWCSTS_Pos) /*!< 0x00000001 */
#define ETH_MTLRXQ1DR_RWCSTS ETH_MTLRXQ1DR_RWCSTS_Msk /*!< MTL Rx Queue Write Controller Active Status */
#define ETH_MTLRXQ1DR_RRCSTS_Pos (1U)
#define ETH_MTLRXQ1DR_RRCSTS_Msk (0x3U << ETH_MTLRXQ1DR_RRCSTS_Pos) /*!< 0x00000006 */
#define ETH_MTLRXQ1DR_RRCSTS ETH_MTLRXQ1DR_RRCSTS_Msk /*!< MTL Rx Queue Read Controller State */
#define ETH_MTLRXQ1DR_RRCSTS_0 (0x1U << ETH_MTLRXQ1DR_RRCSTS_Pos) /*!< 0x00000002 */
#define ETH_MTLRXQ1DR_RRCSTS_1 (0x2U << ETH_MTLRXQ1DR_RRCSTS_Pos) /*!< 0x00000004 */
#define ETH_MTLRXQ1DR_RXQSTS_Pos (4U)
#define ETH_MTLRXQ1DR_RXQSTS_Msk (0x3U << ETH_MTLRXQ1DR_RXQSTS_Pos) /*!< 0x00000030 */
#define ETH_MTLRXQ1DR_RXQSTS ETH_MTLRXQ1DR_RXQSTS_Msk /*!< MTL Rx Queue Fill-Level Status */
#define ETH_MTLRXQ1DR_RXQSTS_0 (0x1U << ETH_MTLRXQ1DR_RXQSTS_Pos) /*!< 0x00000010 */
#define ETH_MTLRXQ1DR_RXQSTS_1 (0x2U << ETH_MTLRXQ1DR_RXQSTS_Pos) /*!< 0x00000020 */
#define ETH_MTLRXQ1DR_PRXQ_Pos (16U)
#define ETH_MTLRXQ1DR_PRXQ_Msk (0x3FFFU << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x3FFF0000 */
#define ETH_MTLRXQ1DR_PRXQ ETH_MTLRXQ1DR_PRXQ_Msk /*!< Number of Packets in Receive Queue */
#define ETH_MTLRXQ1DR_PRXQ_0 (0x1U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x00010000 */
#define ETH_MTLRXQ1DR_PRXQ_1 (0x2U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x00020000 */
#define ETH_MTLRXQ1DR_PRXQ_2 (0x4U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x00040000 */
#define ETH_MTLRXQ1DR_PRXQ_3 (0x8U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x00080000 */
#define ETH_MTLRXQ1DR_PRXQ_4 (0x10U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x00100000 */
#define ETH_MTLRXQ1DR_PRXQ_5 (0x20U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x00200000 */
#define ETH_MTLRXQ1DR_PRXQ_6 (0x40U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x00400000 */
#define ETH_MTLRXQ1DR_PRXQ_7 (0x80U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x00800000 */
#define ETH_MTLRXQ1DR_PRXQ_8 (0x100U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x01000000 */
#define ETH_MTLRXQ1DR_PRXQ_9 (0x200U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x02000000 */
#define ETH_MTLRXQ1DR_PRXQ_10 (0x400U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x04000000 */
#define ETH_MTLRXQ1DR_PRXQ_11 (0x800U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x08000000 */
#define ETH_MTLRXQ1DR_PRXQ_12 (0x1000U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x10000000 */
#define ETH_MTLRXQ1DR_PRXQ_13 (0x2000U << ETH_MTLRXQ1DR_PRXQ_Pos) /*!< 0x20000000 */
/************* Bit definition for ETH_MTLRXQ1CR register *************/
#define ETH_MTLRXQ1CR_RXQ_WEGT_Pos (0U)
#define ETH_MTLRXQ1CR_RXQ_WEGT_Msk (0x7U << ETH_MTLRXQ1CR_RXQ_WEGT_Pos) /*!< 0x00000007 */
#define ETH_MTLRXQ1CR_RXQ_WEGT ETH_MTLRXQ1CR_RXQ_WEGT_Msk /*!< Receive Queue Weight */
#define ETH_MTLRXQ1CR_RXQ_WEGT_0 (0x1U << ETH_MTLRXQ1CR_RXQ_WEGT_Pos) /*!< 0x00000001 */
#define ETH_MTLRXQ1CR_RXQ_WEGT_1 (0x2U << ETH_MTLRXQ1CR_RXQ_WEGT_Pos) /*!< 0x00000002 */
#define ETH_MTLRXQ1CR_RXQ_WEGT_2 (0x4U << ETH_MTLRXQ1CR_RXQ_WEGT_Pos) /*!< 0x00000004 */
#define ETH_MTLRXQ1CR_RXQ_FRM_ARBIT_Pos (3U)
#define ETH_MTLRXQ1CR_RXQ_FRM_ARBIT_Msk (0x1U << ETH_MTLRXQ1CR_RXQ_FRM_ARBIT_Pos) /*!< 0x00000008 */
#define ETH_MTLRXQ1CR_RXQ_FRM_ARBIT ETH_MTLRXQ1CR_RXQ_FRM_ARBIT_Msk /*!< Receive Queue Packet Arbitration */
/*************** Bit definition for ETH_DMAMR register ***************/
#define ETH_DMAMR_SWR_Pos (0U)
#define ETH_DMAMR_SWR_Msk (0x1U << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */
#define ETH_DMAMR_SWR ETH_DMAMR_SWR_Msk /*!< Software Reset */
#define ETH_DMAMR_TAA_Pos (2U)
#define ETH_DMAMR_TAA_Msk (0x7U << ETH_DMAMR_TAA_Pos) /*!< 0x0000001C */
#define ETH_DMAMR_TAA ETH_DMAMR_TAA_Msk /*!< Transmit Arbitration Algorithm */
#define ETH_DMAMR_TAA_0 (0x1U << ETH_DMAMR_TAA_Pos) /*!< 0x00000004 */
#define ETH_DMAMR_TAA_1 (0x2U << ETH_DMAMR_TAA_Pos) /*!< 0x00000008 */
#define ETH_DMAMR_TAA_2 (0x4U << ETH_DMAMR_TAA_Pos) /*!< 0x00000010 */
#define ETH_DMAMR_TXPR_Pos (11U)
#define ETH_DMAMR_TXPR_Msk (0x1U << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /*!< Transmit priority */
#define ETH_DMAMR_PR_Pos (12U)
#define ETH_DMAMR_PR_Msk (0x7U << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /*!< Priority ratio */
#define ETH_DMAMR_PR_0 (0x1U << ETH_DMAMR_PR_Pos) /*!< 0x00001000 */
#define ETH_DMAMR_PR_1 (0x2U << ETH_DMAMR_PR_Pos) /*!< 0x00002000 */
#define ETH_DMAMR_PR_2 (0x4U << ETH_DMAMR_PR_Pos) /*!< 0x00004000 */
#define ETH_DMAMR_INTM_Pos (16U)
#define ETH_DMAMR_INTM_Msk (0x3U << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */
#define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /*!< Interrupt Mode */
#define ETH_DMAMR_INTM_0 (0x1U << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */
#define ETH_DMAMR_INTM_1 (0x2U << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */
/************** Bit definition for ETH_DMASBMR register **************/
#define ETH_DMASBMR_FB_Pos (0U)
#define ETH_DMASBMR_FB_Msk (0x1U << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */
#define ETH_DMASBMR_FB ETH_DMASBMR_FB_Msk /*!< Fixed Burst Length */
#define ETH_DMASBMR_BLEN4_Pos (1U)
#define ETH_DMASBMR_BLEN4_Msk (0x1U << ETH_DMASBMR_BLEN4_Pos) /*!< 0x00000002 */
#define ETH_DMASBMR_BLEN4 ETH_DMASBMR_BLEN4_Msk /*!< AXI Burst Length 4 */
#define ETH_DMASBMR_BLEN8_Pos (2U)
#define ETH_DMASBMR_BLEN8_Msk (0x1U << ETH_DMASBMR_BLEN8_Pos) /*!< 0x00000004 */
#define ETH_DMASBMR_BLEN8 ETH_DMASBMR_BLEN8_Msk /*!< AXI Burst Length 8 */
#define ETH_DMASBMR_BLEN16_Pos (3U)
#define ETH_DMASBMR_BLEN16_Msk (0x1U << ETH_DMASBMR_BLEN16_Pos) /*!< 0x00000008 */
#define ETH_DMASBMR_BLEN16 ETH_DMASBMR_BLEN16_Msk /*!< AXI Burst Length 16 */
#define ETH_DMASBMR_BLEN32_Pos (4U)
#define ETH_DMASBMR_BLEN32_Msk (0x1U << ETH_DMASBMR_BLEN32_Pos) /*!< 0x00000010 */
#define ETH_DMASBMR_BLEN32 ETH_DMASBMR_BLEN32_Msk /*!< AXI Burst Length 32 */
#define ETH_DMASBMR_BLEN64_Pos (5U)
#define ETH_DMASBMR_BLEN64_Msk (0x1U << ETH_DMASBMR_BLEN64_Pos) /*!< 0x00000020 */
#define ETH_DMASBMR_BLEN64 ETH_DMASBMR_BLEN64_Msk /*!< AXI Burst Length 64 */
#define ETH_DMASBMR_BLEN128_Pos (6U)
#define ETH_DMASBMR_BLEN128_Msk (0x1U << ETH_DMASBMR_BLEN128_Pos) /*!< 0x00000040 */
#define ETH_DMASBMR_BLEN128 ETH_DMASBMR_BLEN128_Msk /*!< AXI Burst Length 128 */
#define ETH_DMASBMR_BLEN256_Pos (7U)
#define ETH_DMASBMR_BLEN256_Msk (0x1U << ETH_DMASBMR_BLEN256_Pos) /*!< 0x00000080 */
#define ETH_DMASBMR_BLEN256 ETH_DMASBMR_BLEN256_Msk /*!< AXI Burst Length 256 */
#define ETH_DMASBMR_AAL_Pos (12U)
#define ETH_DMASBMR_AAL_Msk (0x1U << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */
#define ETH_DMASBMR_AAL ETH_DMASBMR_AAL_Msk /*!< Address-Aligned Beats */
#define ETH_DMASBMR_ONEKBBE_Pos (13U)
#define ETH_DMASBMR_ONEKBBE_Msk (0x1U << ETH_DMASBMR_ONEKBBE_Pos) /*!< 0x00002000 */
#define ETH_DMASBMR_ONEKBBE ETH_DMASBMR_ONEKBBE_Msk /*!< 1 Kbyte Boundary Crossing Enable for the AXI Master */
#define ETH_DMASBMR_RD_OSR_LMT_Pos (16U)
#define ETH_DMASBMR_RD_OSR_LMT_Msk (0x3U << ETH_DMASBMR_RD_OSR_LMT_Pos) /*!< 0x00030000 */
#define ETH_DMASBMR_RD_OSR_LMT ETH_DMASBMR_RD_OSR_LMT_Msk /*!< AXI Maximum Read Outstanding Request Limit */
#define ETH_DMASBMR_RD_OSR_LMT_0 (0x1U << ETH_DMASBMR_RD_OSR_LMT_Pos) /*!< 0x00010000 */
#define ETH_DMASBMR_RD_OSR_LMT_1 (0x2U << ETH_DMASBMR_RD_OSR_LMT_Pos) /*!< 0x00020000 */
#define ETH_DMASBMR_WR_OSR_LMT_Pos (24U)
#define ETH_DMASBMR_WR_OSR_LMT_Msk (0x3U << ETH_DMASBMR_WR_OSR_LMT_Pos) /*!< 0x03000000 */
#define ETH_DMASBMR_WR_OSR_LMT ETH_DMASBMR_WR_OSR_LMT_Msk /*!< AXI Maximum Write Outstanding Request Limit */
#define ETH_DMASBMR_WR_OSR_LMT_0 (0x1U << ETH_DMASBMR_WR_OSR_LMT_Pos) /*!< 0x01000000 */
#define ETH_DMASBMR_WR_OSR_LMT_1 (0x2U << ETH_DMASBMR_WR_OSR_LMT_Pos) /*!< 0x02000000 */
#define ETH_DMASBMR_LPI_XIT_PKT_Pos (30U)
#define ETH_DMASBMR_LPI_XIT_PKT_Msk (0x1U << ETH_DMASBMR_LPI_XIT_PKT_Pos) /*!< 0x40000000 */
#define ETH_DMASBMR_LPI_XIT_PKT ETH_DMASBMR_LPI_XIT_PKT_Msk /*!< Unlock on Magic Packet or Remote wakeup Packet */
#define ETH_DMASBMR_EN_LPI_Pos (31U)
#define ETH_DMASBMR_EN_LPI_Msk (0x1U << ETH_DMASBMR_EN_LPI_Pos) /*!< 0x80000000 */
#define ETH_DMASBMR_EN_LPI ETH_DMASBMR_EN_LPI_Msk /*!< Enable Low Power Interface (LPI) */
/************** Bit definition for ETH_DMAISR register ***************/
#define ETH_DMAISR_DC0IS_Pos (0U)
#define ETH_DMAISR_DC0IS_Msk (0x1U << ETH_DMAISR_DC0IS_Pos) /*!< 0x00000001 */
#define ETH_DMAISR_DC0IS ETH_DMAISR_DC0IS_Msk /*!< DMA Channel 0 Interrupt Status */
#define ETH_DMAISR_DC1IS_Pos (1U)
#define ETH_DMAISR_DC1IS_Msk (0x1U << ETH_DMAISR_DC1IS_Pos) /*!< 0x00000002 */
#define ETH_DMAISR_DC1IS ETH_DMAISR_DC1IS_Msk /*!< DMA Channel 1 Interrupt Status */
#define ETH_DMAISR_MTLIS_Pos (16U)
#define ETH_DMAISR_MTLIS_Msk (0x1U << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */
#define ETH_DMAISR_MTLIS ETH_DMAISR_MTLIS_Msk /*!< MTL Interrupt Status */
#define ETH_DMAISR_MACIS_Pos (17U)
#define ETH_DMAISR_MACIS_Msk (0x1U << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */
#define ETH_DMAISR_MACIS ETH_DMAISR_MACIS_Msk /*!< MAC Interrupt Status */
/************** Bit definition for ETH_DMADSR register ***************/
#define ETH_DMADSR_AXWHSTS_Pos (0U)
#define ETH_DMADSR_AXWHSTS_Msk (0x1U << ETH_DMADSR_AXWHSTS_Pos) /*!< 0x00000001 */
#define ETH_DMADSR_AXWHSTS ETH_DMADSR_AXWHSTS_Msk /*!< AXI Master Write Channel */
#define ETH_DMADSR_AXRHSTS_Pos (1U)
#define ETH_DMADSR_AXRHSTS_Msk (0x1U << ETH_DMADSR_AXRHSTS_Pos) /*!< 0x00000002 */
#define ETH_DMADSR_AXRHSTS ETH_DMADSR_AXRHSTS_Msk /*!< AXI Master Read Channel Status */
#define ETH_DMADSR_RPS0_Pos (8U)
#define ETH_DMADSR_RPS0_Msk (0xFU << ETH_DMADSR_RPS0_Pos) /*!< 0x00000F00 */
#define ETH_DMADSR_RPS0 ETH_DMADSR_RPS0_Msk /*!< DMA Channel 0 Receive Process State */
#define ETH_DMADSR_RPS0_0 (0x1U << ETH_DMADSR_RPS0_Pos) /*!< 0x00000100 */
#define ETH_DMADSR_RPS0_1 (0x2U << ETH_DMADSR_RPS0_Pos) /*!< 0x00000200 */
#define ETH_DMADSR_RPS0_2 (0x4U << ETH_DMADSR_RPS0_Pos) /*!< 0x00000400 */
#define ETH_DMADSR_RPS0_3 (0x8U << ETH_DMADSR_RPS0_Pos) /*!< 0x00000800 */
#define ETH_DMADSR_TPS0_Pos (12U)
#define ETH_DMADSR_TPS0_Msk (0xFU << ETH_DMADSR_TPS0_Pos) /*!< 0x0000F000 */
#define ETH_DMADSR_TPS0 ETH_DMADSR_TPS0_Msk /*!< DMA Channel 0 Transmit Process State */
#define ETH_DMADSR_TPS0_0 (0x1U << ETH_DMADSR_TPS0_Pos) /*!< 0x00001000 */
#define ETH_DMADSR_TPS0_1 (0x2U << ETH_DMADSR_TPS0_Pos) /*!< 0x00002000 */
#define ETH_DMADSR_TPS0_2 (0x4U << ETH_DMADSR_TPS0_Pos) /*!< 0x00004000 */
#define ETH_DMADSR_TPS0_3 (0x8U << ETH_DMADSR_TPS0_Pos) /*!< 0x00008000 */
#define ETH_DMADSR_RPS1_Pos (16U)
#define ETH_DMADSR_RPS1_Msk (0xFU << ETH_DMADSR_RPS1_Pos) /*!< 0x000F0000 */
#define ETH_DMADSR_RPS1 ETH_DMADSR_RPS1_Msk /*!< DMA Channel 1 Receive Process State */
#define ETH_DMADSR_RPS1_0 (0x1U << ETH_DMADSR_RPS1_Pos) /*!< 0x00010000 */
#define ETH_DMADSR_RPS1_1 (0x2U << ETH_DMADSR_RPS1_Pos) /*!< 0x00020000 */
#define ETH_DMADSR_RPS1_2 (0x4U << ETH_DMADSR_RPS1_Pos) /*!< 0x00040000 */
#define ETH_DMADSR_RPS1_3 (0x8U << ETH_DMADSR_RPS1_Pos) /*!< 0x00080000 */
#define ETH_DMADSR_TPS1_Pos (20U)
#define ETH_DMADSR_TPS1_Msk (0xFU << ETH_DMADSR_TPS1_Pos) /*!< 0x00F00000 */
#define ETH_DMADSR_TPS1 ETH_DMADSR_TPS1_Msk /*!< DMA Channel 1 Transmit Process State */
#define ETH_DMADSR_TPS1_0 (0x1U << ETH_DMADSR_TPS1_Pos) /*!< 0x00100000 */
#define ETH_DMADSR_TPS1_1 (0x2U << ETH_DMADSR_TPS1_Pos) /*!< 0x00200000 */
#define ETH_DMADSR_TPS1_2 (0x4U << ETH_DMADSR_TPS1_Pos) /*!< 0x00400000 */
#define ETH_DMADSR_TPS1_3 (0x8U << ETH_DMADSR_TPS1_Pos) /*!< 0x00800000 */
/************ Bit definition for ETH_DMAA4TXACR register *************/
#define ETH_DMAA4TXACR_TDRC_Pos (0U)
#define ETH_DMAA4TXACR_TDRC_Msk (0xFU << ETH_DMAA4TXACR_TDRC_Pos) /*!< 0x0000000F */
#define ETH_DMAA4TXACR_TDRC ETH_DMAA4TXACR_TDRC_Msk /*!< Transmit DMA Read Descriptor Cache Control */
#define ETH_DMAA4TXACR_TDRC_0 (0x1U << ETH_DMAA4TXACR_TDRC_Pos) /*!< 0x00000001 */
#define ETH_DMAA4TXACR_TDRC_1 (0x2U << ETH_DMAA4TXACR_TDRC_Pos) /*!< 0x00000002 */
#define ETH_DMAA4TXACR_TDRC_2 (0x4U << ETH_DMAA4TXACR_TDRC_Pos) /*!< 0x00000004 */
#define ETH_DMAA4TXACR_TDRC_3 (0x8U << ETH_DMAA4TXACR_TDRC_Pos) /*!< 0x00000008 */
#define ETH_DMAA4TXACR_TEC_Pos (8U)
#define ETH_DMAA4TXACR_TEC_Msk (0xFU << ETH_DMAA4TXACR_TEC_Pos) /*!< 0x00000F00 */
#define ETH_DMAA4TXACR_TEC ETH_DMAA4TXACR_TEC_Msk /*!< Transmit DMA Extended Packet Buffer or TSO Payload Cache Control */
#define ETH_DMAA4TXACR_TEC_0 (0x1U << ETH_DMAA4TXACR_TEC_Pos) /*!< 0x00000100 */
#define ETH_DMAA4TXACR_TEC_1 (0x2U << ETH_DMAA4TXACR_TEC_Pos) /*!< 0x00000200 */
#define ETH_DMAA4TXACR_TEC_2 (0x4U << ETH_DMAA4TXACR_TEC_Pos) /*!< 0x00000400 */
#define ETH_DMAA4TXACR_TEC_3 (0x8U << ETH_DMAA4TXACR_TEC_Pos) /*!< 0x00000800 */
#define ETH_DMAA4TXACR_THC_Pos (16U)
#define ETH_DMAA4TXACR_THC_Msk (0xFU << ETH_DMAA4TXACR_THC_Pos) /*!< 0x000F0000 */
#define ETH_DMAA4TXACR_THC ETH_DMAA4TXACR_THC_Msk /*!< Transmit DMA First Packet Buffer or TSO Header Cache Control */
#define ETH_DMAA4TXACR_THC_0 (0x1U << ETH_DMAA4TXACR_THC_Pos) /*!< 0x00010000 */
#define ETH_DMAA4TXACR_THC_1 (0x2U << ETH_DMAA4TXACR_THC_Pos) /*!< 0x00020000 */
#define ETH_DMAA4TXACR_THC_2 (0x4U << ETH_DMAA4TXACR_THC_Pos) /*!< 0x00040000 */
#define ETH_DMAA4TXACR_THC_3 (0x8U << ETH_DMAA4TXACR_THC_Pos) /*!< 0x00080000 */
/************ Bit definition for ETH_DMAA4RXACR register *************/
#define ETH_DMAA4RXACR_RDWC_Pos (0U)
#define ETH_DMAA4RXACR_RDWC_Msk (0xFU << ETH_DMAA4RXACR_RDWC_Pos) /*!< 0x0000000F */
#define ETH_DMAA4RXACR_RDWC ETH_DMAA4RXACR_RDWC_Msk /*!< Receive DMA Write Descriptor Cache Control */
#define ETH_DMAA4RXACR_RDWC_0 (0x1U << ETH_DMAA4RXACR_RDWC_Pos) /*!< 0x00000001 */
#define ETH_DMAA4RXACR_RDWC_1 (0x2U << ETH_DMAA4RXACR_RDWC_Pos) /*!< 0x00000002 */
#define ETH_DMAA4RXACR_RDWC_2 (0x4U << ETH_DMAA4RXACR_RDWC_Pos) /*!< 0x00000004 */
#define ETH_DMAA4RXACR_RDWC_3 (0x8U << ETH_DMAA4RXACR_RDWC_Pos) /*!< 0x00000008 */
#define ETH_DMAA4RXACR_RPC_Pos (8U)
#define ETH_DMAA4RXACR_RPC_Msk (0xFU << ETH_DMAA4RXACR_RPC_Pos) /*!< 0x00000F00 */
#define ETH_DMAA4RXACR_RPC ETH_DMAA4RXACR_RPC_Msk /*!< Receive DMA Payload Cache Control */
#define ETH_DMAA4RXACR_RPC_0 (0x1U << ETH_DMAA4RXACR_RPC_Pos) /*!< 0x00000100 */
#define ETH_DMAA4RXACR_RPC_1 (0x2U << ETH_DMAA4RXACR_RPC_Pos) /*!< 0x00000200 */
#define ETH_DMAA4RXACR_RPC_2 (0x4U << ETH_DMAA4RXACR_RPC_Pos) /*!< 0x00000400 */
#define ETH_DMAA4RXACR_RPC_3 (0x8U << ETH_DMAA4RXACR_RPC_Pos) /*!< 0x00000800 */
#define ETH_DMAA4RXACR_RHC_Pos (16U)
#define ETH_DMAA4RXACR_RHC_Msk (0xFU << ETH_DMAA4RXACR_RHC_Pos) /*!< 0x000F0000 */
#define ETH_DMAA4RXACR_RHC ETH_DMAA4RXACR_RHC_Msk /*!< Receive DMA Header Cache Control */
#define ETH_DMAA4RXACR_RHC_0 (0x1U << ETH_DMAA4RXACR_RHC_Pos) /*!< 0x00010000 */
#define ETH_DMAA4RXACR_RHC_1 (0x2U << ETH_DMAA4RXACR_RHC_Pos) /*!< 0x00020000 */
#define ETH_DMAA4RXACR_RHC_2 (0x4U << ETH_DMAA4RXACR_RHC_Pos) /*!< 0x00040000 */
#define ETH_DMAA4RXACR_RHC_3 (0x8U << ETH_DMAA4RXACR_RHC_Pos) /*!< 0x00080000 */
#define ETH_DMAA4RXACR_RDC_Pos (24U)
#define ETH_DMAA4RXACR_RDC_Msk (0xFU << ETH_DMAA4RXACR_RDC_Pos) /*!< 0x0F000000 */
#define ETH_DMAA4RXACR_RDC ETH_DMAA4RXACR_RDC_Msk /*!< Receive DMA Buffer Cache Control */
#define ETH_DMAA4RXACR_RDC_0 (0x1U << ETH_DMAA4RXACR_RDC_Pos) /*!< 0x01000000 */
#define ETH_DMAA4RXACR_RDC_1 (0x2U << ETH_DMAA4RXACR_RDC_Pos) /*!< 0x02000000 */
#define ETH_DMAA4RXACR_RDC_2 (0x4U << ETH_DMAA4RXACR_RDC_Pos) /*!< 0x04000000 */
#define ETH_DMAA4RXACR_RDC_3 (0x8U << ETH_DMAA4RXACR_RDC_Pos) /*!< 0x08000000 */
/************* Bit definition for ETH_DMAA4DACR register *************/
#define ETH_DMAA4DACR_TDWC_Pos (0U)
#define ETH_DMAA4DACR_TDWC_Msk (0xFU << ETH_DMAA4DACR_TDWC_Pos) /*!< 0x0000000F */
#define ETH_DMAA4DACR_TDWC ETH_DMAA4DACR_TDWC_Msk /*!< Transmit DMA Write Descriptor Cache control */
#define ETH_DMAA4DACR_TDWC_0 (0x1U << ETH_DMAA4DACR_TDWC_Pos) /*!< 0x00000001 */
#define ETH_DMAA4DACR_TDWC_1 (0x2U << ETH_DMAA4DACR_TDWC_Pos) /*!< 0x00000002 */
#define ETH_DMAA4DACR_TDWC_2 (0x4U << ETH_DMAA4DACR_TDWC_Pos) /*!< 0x00000004 */
#define ETH_DMAA4DACR_TDWC_3 (0x8U << ETH_DMAA4DACR_TDWC_Pos) /*!< 0x00000008 */
#define ETH_DMAA4DACR_TDWD_Pos (4U)
#define ETH_DMAA4DACR_TDWD_Msk (0x3U << ETH_DMAA4DACR_TDWD_Pos) /*!< 0x00000030 */
#define ETH_DMAA4DACR_TDWD ETH_DMAA4DACR_TDWD_Msk /*!< Transmit DMA Write Descriptor Domain control */
#define ETH_DMAA4DACR_TDWD_0 (0x1U << ETH_DMAA4DACR_TDWD_Pos) /*!< 0x00000010 */
#define ETH_DMAA4DACR_TDWD_1 (0x2U << ETH_DMAA4DACR_TDWD_Pos) /*!< 0x00000020 */
#define ETH_DMAA4DACR_RDRC_Pos (8U)
#define ETH_DMAA4DACR_RDRC_Msk (0xFU << ETH_DMAA4DACR_RDRC_Pos) /*!< 0x00000F00 */
#define ETH_DMAA4DACR_RDRC ETH_DMAA4DACR_RDRC_Msk /*!< Receive DMA Read Descriptor Cache control */
#define ETH_DMAA4DACR_RDRC_0 (0x1U << ETH_DMAA4DACR_RDRC_Pos) /*!< 0x00000100 */
#define ETH_DMAA4DACR_RDRC_1 (0x2U << ETH_DMAA4DACR_RDRC_Pos) /*!< 0x00000200 */
#define ETH_DMAA4DACR_RDRC_2 (0x4U << ETH_DMAA4DACR_RDRC_Pos) /*!< 0x00000400 */
#define ETH_DMAA4DACR_RDRC_3 (0x8U << ETH_DMAA4DACR_RDRC_Pos) /*!< 0x00000800 */
/************** Bit definition for ETH_DMAC0CR register **************/
#define ETH_DMAC0CR_MSS_Pos (0U)
#define ETH_DMAC0CR_MSS_Msk (0x3FFFU << ETH_DMAC0CR_MSS_Pos) /*!< 0x00003FFF */
#define ETH_DMAC0CR_MSS ETH_DMAC0CR_MSS_Msk /*!< Maximum Segment Size */
#define ETH_DMAC0CR_MSS_0 (0x1U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00000001 */
#define ETH_DMAC0CR_MSS_1 (0x2U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00000002 */
#define ETH_DMAC0CR_MSS_2 (0x4U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00000004 */
#define ETH_DMAC0CR_MSS_3 (0x8U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00000008 */
#define ETH_DMAC0CR_MSS_4 (0x10U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00000010 */
#define ETH_DMAC0CR_MSS_5 (0x20U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00000020 */
#define ETH_DMAC0CR_MSS_6 (0x40U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00000040 */
#define ETH_DMAC0CR_MSS_7 (0x80U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00000080 */
#define ETH_DMAC0CR_MSS_8 (0x100U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00000100 */
#define ETH_DMAC0CR_MSS_9 (0x200U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00000200 */
#define ETH_DMAC0CR_MSS_10 (0x400U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00000400 */
#define ETH_DMAC0CR_MSS_11 (0x800U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00000800 */
#define ETH_DMAC0CR_MSS_12 (0x1000U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00001000 */
#define ETH_DMAC0CR_MSS_13 (0x2000U << ETH_DMAC0CR_MSS_Pos) /*!< 0x00002000 */
#define ETH_DMAC0CR_PBLX8_Pos (16U)
#define ETH_DMAC0CR_PBLX8_Msk (0x1U << ETH_DMAC0CR_PBLX8_Pos) /*!< 0x00010000 */
#define ETH_DMAC0CR_PBLX8 ETH_DMAC0CR_PBLX8_Msk /*!< 8xPBL mode */
#define ETH_DMAC0CR_DSL_Pos (18U)
#define ETH_DMAC0CR_DSL_Msk (0x7U << ETH_DMAC0CR_DSL_Pos) /*!< 0x001C0000 */
#define ETH_DMAC0CR_DSL ETH_DMAC0CR_DSL_Msk /*!< Descriptor Skip Length */
#define ETH_DMAC0CR_DSL_0 (0x1U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00040000 */
#define ETH_DMAC0CR_DSL_1 (0x2U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00080000 */
#define ETH_DMAC0CR_DSL_2 (0x4U << ETH_DMAC0CR_DSL_Pos) /*!< 0x00100000 */
/************* Bit definition for ETH_DMAC0TXCR register *************/
#define ETH_DMAC0TXCR_ST_Pos (0U)
#define ETH_DMAC0TXCR_ST_Msk (0x1U << ETH_DMAC0TXCR_ST_Pos) /*!< 0x00000001 */
#define ETH_DMAC0TXCR_ST ETH_DMAC0TXCR_ST_Msk /*!< Start or Stop Transmission Command */
#define ETH_DMAC0TXCR_TCW_Pos (1U)
#define ETH_DMAC0TXCR_TCW_Msk (0x7U << ETH_DMAC0TXCR_TCW_Pos) /*!< 0x0000000E */
#define ETH_DMAC0TXCR_TCW ETH_DMAC0TXCR_TCW_Msk /*!< Transmit Channel Weight */
#define ETH_DMAC0TXCR_TCW_0 (0x1U << ETH_DMAC0TXCR_TCW_Pos) /*!< 0x00000002 */
#define ETH_DMAC0TXCR_TCW_1 (0x2U << ETH_DMAC0TXCR_TCW_Pos) /*!< 0x00000004 */
#define ETH_DMAC0TXCR_TCW_2 (0x4U << ETH_DMAC0TXCR_TCW_Pos) /*!< 0x00000008 */
#define ETH_DMAC0TXCR_OSF_Pos (4U)
#define ETH_DMAC0TXCR_OSF_Msk (0x1U << ETH_DMAC0TXCR_OSF_Pos) /*!< 0x00000010 */
#define ETH_DMAC0TXCR_OSF ETH_DMAC0TXCR_OSF_Msk /*!< Operate on Second Packet */
#define ETH_DMAC0TXCR_TSE_Pos (12U)
#define ETH_DMAC0TXCR_TSE_Msk (0x1U << ETH_DMAC0TXCR_TSE_Pos) /*!< 0x00001000 */
#define ETH_DMAC0TXCR_TSE ETH_DMAC0TXCR_TSE_Msk /*!< TCP Segmentation Enabled */
#define ETH_DMAC0TXCR_TXPBL_Pos (16U)
#define ETH_DMAC0TXCR_TXPBL_Msk (0x3FU << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x003F0000 */
#define ETH_DMAC0TXCR_TXPBL ETH_DMAC0TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */
#define ETH_DMAC0TXCR_TXPBL_0 (0x1U << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00010000 */
#define ETH_DMAC0TXCR_TXPBL_1 (0x2U << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00020000 */
#define ETH_DMAC0TXCR_TXPBL_2 (0x4U << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00040000 */
#define ETH_DMAC0TXCR_TXPBL_3 (0x8U << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00080000 */
#define ETH_DMAC0TXCR_TXPBL_4 (0x10U << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00100000 */
#define ETH_DMAC0TXCR_TXPBL_5 (0x20U << ETH_DMAC0TXCR_TXPBL_Pos) /*!< 0x00200000 */
#define ETH_DMAC0TXCR_TQOS_Pos (24U)
#define ETH_DMAC0TXCR_TQOS_Msk (0xFU << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x0F000000 */
#define ETH_DMAC0TXCR_TQOS ETH_DMAC0TXCR_TQOS_Msk /*!< Transmit QOS. */
#define ETH_DMAC0TXCR_TQOS_0 (0x1U << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x01000000 */
#define ETH_DMAC0TXCR_TQOS_1 (0x2U << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x02000000 */
#define ETH_DMAC0TXCR_TQOS_2 (0x4U << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x04000000 */
#define ETH_DMAC0TXCR_TQOS_3 (0x8U << ETH_DMAC0TXCR_TQOS_Pos) /*!< 0x08000000 */
/************* Bit definition for ETH_DMAC0RXCR register *************/
#define ETH_DMAC0RXCR_SR_Pos (0U)
#define ETH_DMAC0RXCR_SR_Msk (0x1U << ETH_DMAC0RXCR_SR_Pos) /*!< 0x00000001 */
#define ETH_DMAC0RXCR_SR ETH_DMAC0RXCR_SR_Msk /*!< Start or Stop Receive */
#define ETH_DMAC0RXCR_RBSZ_Pos (1U)
#define ETH_DMAC0RXCR_RBSZ_Msk (0x3FFFU << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00007FFE */
#define ETH_DMAC0RXCR_RBSZ ETH_DMAC0RXCR_RBSZ_Msk /*!< Receive Buffer size */
#define ETH_DMAC0RXCR_RBSZ_0 (0x1U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00000002 */
#define ETH_DMAC0RXCR_RBSZ_1 (0x2U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00000004 */
#define ETH_DMAC0RXCR_RBSZ_2 (0x4U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00000008 */
#define ETH_DMAC0RXCR_RBSZ_3 (0x8U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00000010 */
#define ETH_DMAC0RXCR_RBSZ_4 (0x10U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00000020 */
#define ETH_DMAC0RXCR_RBSZ_5 (0x20U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00000040 */
#define ETH_DMAC0RXCR_RBSZ_6 (0x40U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00000080 */
#define ETH_DMAC0RXCR_RBSZ_7 (0x80U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00000100 */
#define ETH_DMAC0RXCR_RBSZ_8 (0x100U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00000200 */
#define ETH_DMAC0RXCR_RBSZ_9 (0x200U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00000400 */
#define ETH_DMAC0RXCR_RBSZ_10 (0x400U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00000800 */
#define ETH_DMAC0RXCR_RBSZ_11 (0x800U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00001000 */
#define ETH_DMAC0RXCR_RBSZ_12 (0x1000U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00002000 */
#define ETH_DMAC0RXCR_RBSZ_13 (0x2000U << ETH_DMAC0RXCR_RBSZ_Pos) /*!< 0x00004000 */
#define ETH_DMAC0RXCR_RXPBL_Pos (16U)
#define ETH_DMAC0RXCR_RXPBL_Msk (0x3FU << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x003F0000 */
#define ETH_DMAC0RXCR_RXPBL ETH_DMAC0RXCR_RXPBL_Msk /*!< Receive Programmable Burst Length */
#define ETH_DMAC0RXCR_RXPBL_0 (0x1U << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00010000 */
#define ETH_DMAC0RXCR_RXPBL_1 (0x2U << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00020000 */
#define ETH_DMAC0RXCR_RXPBL_2 (0x4U << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00040000 */
#define ETH_DMAC0RXCR_RXPBL_3 (0x8U << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00080000 */
#define ETH_DMAC0RXCR_RXPBL_4 (0x10U << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00100000 */
#define ETH_DMAC0RXCR_RXPBL_5 (0x20U << ETH_DMAC0RXCR_RXPBL_Pos) /*!< 0x00200000 */
#define ETH_DMAC0RXCR_RQOS_Pos (24U)
#define ETH_DMAC0RXCR_RQOS_Msk (0xFU << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x0F000000 */
#define ETH_DMAC0RXCR_RQOS ETH_DMAC0RXCR_RQOS_Msk /*!< Rx AXI4 QOS. */
#define ETH_DMAC0RXCR_RQOS_0 (0x1U << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x01000000 */
#define ETH_DMAC0RXCR_RQOS_1 (0x2U << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x02000000 */
#define ETH_DMAC0RXCR_RQOS_2 (0x4U << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x04000000 */
#define ETH_DMAC0RXCR_RQOS_3 (0x8U << ETH_DMAC0RXCR_RQOS_Pos) /*!< 0x08000000 */
#define ETH_DMAC0RXCR_RPF_Pos (31U)
#define ETH_DMAC0RXCR_RPF_Msk (0x1U << ETH_DMAC0RXCR_RPF_Pos) /*!< 0x80000000 */
#define ETH_DMAC0RXCR_RPF ETH_DMAC0RXCR_RPF_Msk /*!< DMA Rx Channel0 Packet Flush */
/************ Bit definition for ETH_DMAC0TXDLAR register ************/
#define ETH_DMAC0TXDLAR_TDESLA_Pos (3U)
#define ETH_DMAC0TXDLAR_TDESLA_Msk (0x1FFFFFFFU << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0xFFFFFFF8 */
#define ETH_DMAC0TXDLAR_TDESLA ETH_DMAC0TXDLAR_TDESLA_Msk /*!< Start of Transmit List */
#define ETH_DMAC0TXDLAR_TDESLA_0 (0x1U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00000008 */
#define ETH_DMAC0TXDLAR_TDESLA_1 (0x2U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00000010 */
#define ETH_DMAC0TXDLAR_TDESLA_2 (0x4U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00000020 */
#define ETH_DMAC0TXDLAR_TDESLA_3 (0x8U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00000040 */
#define ETH_DMAC0TXDLAR_TDESLA_4 (0x10U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00000080 */
#define ETH_DMAC0TXDLAR_TDESLA_5 (0x20U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00000100 */
#define ETH_DMAC0TXDLAR_TDESLA_6 (0x40U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00000200 */
#define ETH_DMAC0TXDLAR_TDESLA_7 (0x80U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00000400 */
#define ETH_DMAC0TXDLAR_TDESLA_8 (0x100U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00000800 */
#define ETH_DMAC0TXDLAR_TDESLA_9 (0x200U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00001000 */
#define ETH_DMAC0TXDLAR_TDESLA_10 (0x400U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00002000 */
#define ETH_DMAC0TXDLAR_TDESLA_11 (0x800U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00004000 */
#define ETH_DMAC0TXDLAR_TDESLA_12 (0x1000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00008000 */
#define ETH_DMAC0TXDLAR_TDESLA_13 (0x2000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00010000 */
#define ETH_DMAC0TXDLAR_TDESLA_14 (0x4000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00020000 */
#define ETH_DMAC0TXDLAR_TDESLA_15 (0x8000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00040000 */
#define ETH_DMAC0TXDLAR_TDESLA_16 (0x10000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00080000 */
#define ETH_DMAC0TXDLAR_TDESLA_17 (0x20000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00100000 */
#define ETH_DMAC0TXDLAR_TDESLA_18 (0x40000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00200000 */
#define ETH_DMAC0TXDLAR_TDESLA_19 (0x80000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00400000 */
#define ETH_DMAC0TXDLAR_TDESLA_20 (0x100000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x00800000 */
#define ETH_DMAC0TXDLAR_TDESLA_21 (0x200000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x01000000 */
#define ETH_DMAC0TXDLAR_TDESLA_22 (0x400000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x02000000 */
#define ETH_DMAC0TXDLAR_TDESLA_23 (0x800000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x04000000 */
#define ETH_DMAC0TXDLAR_TDESLA_24 (0x1000000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x08000000 */
#define ETH_DMAC0TXDLAR_TDESLA_25 (0x2000000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x10000000 */
#define ETH_DMAC0TXDLAR_TDESLA_26 (0x4000000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x20000000 */
#define ETH_DMAC0TXDLAR_TDESLA_27 (0x8000000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x40000000 */
#define ETH_DMAC0TXDLAR_TDESLA_28 (0x10000000U << ETH_DMAC0TXDLAR_TDESLA_Pos) /*!< 0x80000000 */
/************ Bit definition for ETH_DMAC0RXDLAR register ************/
#define ETH_DMAC0RXDLAR_RDESLA_Pos (3U)
#define ETH_DMAC0RXDLAR_RDESLA_Msk (0x1FFFFFFFU << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0xFFFFFFF8 */
#define ETH_DMAC0RXDLAR_RDESLA ETH_DMAC0RXDLAR_RDESLA_Msk /*!< Start of Receive List */
#define ETH_DMAC0RXDLAR_RDESLA_0 (0x1U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00000008 */
#define ETH_DMAC0RXDLAR_RDESLA_1 (0x2U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00000010 */
#define ETH_DMAC0RXDLAR_RDESLA_2 (0x4U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00000020 */
#define ETH_DMAC0RXDLAR_RDESLA_3 (0x8U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00000040 */
#define ETH_DMAC0RXDLAR_RDESLA_4 (0x10U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00000080 */
#define ETH_DMAC0RXDLAR_RDESLA_5 (0x20U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00000100 */
#define ETH_DMAC0RXDLAR_RDESLA_6 (0x40U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00000200 */
#define ETH_DMAC0RXDLAR_RDESLA_7 (0x80U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00000400 */
#define ETH_DMAC0RXDLAR_RDESLA_8 (0x100U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00000800 */
#define ETH_DMAC0RXDLAR_RDESLA_9 (0x200U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00001000 */
#define ETH_DMAC0RXDLAR_RDESLA_10 (0x400U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00002000 */
#define ETH_DMAC0RXDLAR_RDESLA_11 (0x800U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00004000 */
#define ETH_DMAC0RXDLAR_RDESLA_12 (0x1000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00008000 */
#define ETH_DMAC0RXDLAR_RDESLA_13 (0x2000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00010000 */
#define ETH_DMAC0RXDLAR_RDESLA_14 (0x4000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00020000 */
#define ETH_DMAC0RXDLAR_RDESLA_15 (0x8000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00040000 */
#define ETH_DMAC0RXDLAR_RDESLA_16 (0x10000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00080000 */
#define ETH_DMAC0RXDLAR_RDESLA_17 (0x20000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00100000 */
#define ETH_DMAC0RXDLAR_RDESLA_18 (0x40000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00200000 */
#define ETH_DMAC0RXDLAR_RDESLA_19 (0x80000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00400000 */
#define ETH_DMAC0RXDLAR_RDESLA_20 (0x100000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x00800000 */
#define ETH_DMAC0RXDLAR_RDESLA_21 (0x200000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x01000000 */
#define ETH_DMAC0RXDLAR_RDESLA_22 (0x400000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x02000000 */
#define ETH_DMAC0RXDLAR_RDESLA_23 (0x800000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x04000000 */
#define ETH_DMAC0RXDLAR_RDESLA_24 (0x1000000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x08000000 */
#define ETH_DMAC0RXDLAR_RDESLA_25 (0x2000000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x10000000 */
#define ETH_DMAC0RXDLAR_RDESLA_26 (0x4000000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x20000000 */
#define ETH_DMAC0RXDLAR_RDESLA_27 (0x8000000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x40000000 */
#define ETH_DMAC0RXDLAR_RDESLA_28 (0x10000000U << ETH_DMAC0RXDLAR_RDESLA_Pos) /*!< 0x80000000 */
/************ Bit definition for ETH_DMAC0TXDTPR register ************/
#define ETH_DMAC0TXDTPR_TDT_Pos (3U)
#define ETH_DMAC0TXDTPR_TDT_Msk (0x1FFFFFFFU << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0xFFFFFFF8 */
#define ETH_DMAC0TXDTPR_TDT ETH_DMAC0TXDTPR_TDT_Msk /*!< Transmit Descriptor Tail Pointer */
#define ETH_DMAC0TXDTPR_TDT_0 (0x1U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00000008 */
#define ETH_DMAC0TXDTPR_TDT_1 (0x2U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00000010 */
#define ETH_DMAC0TXDTPR_TDT_2 (0x4U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00000020 */
#define ETH_DMAC0TXDTPR_TDT_3 (0x8U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00000040 */
#define ETH_DMAC0TXDTPR_TDT_4 (0x10U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00000080 */
#define ETH_DMAC0TXDTPR_TDT_5 (0x20U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00000100 */
#define ETH_DMAC0TXDTPR_TDT_6 (0x40U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00000200 */
#define ETH_DMAC0TXDTPR_TDT_7 (0x80U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00000400 */
#define ETH_DMAC0TXDTPR_TDT_8 (0x100U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00000800 */
#define ETH_DMAC0TXDTPR_TDT_9 (0x200U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00001000 */
#define ETH_DMAC0TXDTPR_TDT_10 (0x400U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00002000 */
#define ETH_DMAC0TXDTPR_TDT_11 (0x800U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00004000 */
#define ETH_DMAC0TXDTPR_TDT_12 (0x1000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00008000 */
#define ETH_DMAC0TXDTPR_TDT_13 (0x2000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00010000 */
#define ETH_DMAC0TXDTPR_TDT_14 (0x4000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00020000 */
#define ETH_DMAC0TXDTPR_TDT_15 (0x8000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00040000 */
#define ETH_DMAC0TXDTPR_TDT_16 (0x10000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00080000 */
#define ETH_DMAC0TXDTPR_TDT_17 (0x20000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00100000 */
#define ETH_DMAC0TXDTPR_TDT_18 (0x40000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00200000 */
#define ETH_DMAC0TXDTPR_TDT_19 (0x80000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00400000 */
#define ETH_DMAC0TXDTPR_TDT_20 (0x100000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x00800000 */
#define ETH_DMAC0TXDTPR_TDT_21 (0x200000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x01000000 */
#define ETH_DMAC0TXDTPR_TDT_22 (0x400000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x02000000 */
#define ETH_DMAC0TXDTPR_TDT_23 (0x800000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x04000000 */
#define ETH_DMAC0TXDTPR_TDT_24 (0x1000000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x08000000 */
#define ETH_DMAC0TXDTPR_TDT_25 (0x2000000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x10000000 */
#define ETH_DMAC0TXDTPR_TDT_26 (0x4000000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x20000000 */
#define ETH_DMAC0TXDTPR_TDT_27 (0x8000000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x40000000 */
#define ETH_DMAC0TXDTPR_TDT_28 (0x10000000U << ETH_DMAC0TXDTPR_TDT_Pos) /*!< 0x80000000 */
/************ Bit definition for ETH_DMAC0RXDTPR register ************/
#define ETH_DMAC0RXDTPR_RDT_Pos (3U)
#define ETH_DMAC0RXDTPR_RDT_Msk (0x1FFFFFFFU << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0xFFFFFFF8 */
#define ETH_DMAC0RXDTPR_RDT ETH_DMAC0RXDTPR_RDT_Msk /*!< Receive Descriptor Tail Pointer */
#define ETH_DMAC0RXDTPR_RDT_0 (0x1U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00000008 */
#define ETH_DMAC0RXDTPR_RDT_1 (0x2U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00000010 */
#define ETH_DMAC0RXDTPR_RDT_2 (0x4U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00000020 */
#define ETH_DMAC0RXDTPR_RDT_3 (0x8U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00000040 */
#define ETH_DMAC0RXDTPR_RDT_4 (0x10U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00000080 */
#define ETH_DMAC0RXDTPR_RDT_5 (0x20U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00000100 */
#define ETH_DMAC0RXDTPR_RDT_6 (0x40U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00000200 */
#define ETH_DMAC0RXDTPR_RDT_7 (0x80U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00000400 */
#define ETH_DMAC0RXDTPR_RDT_8 (0x100U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00000800 */
#define ETH_DMAC0RXDTPR_RDT_9 (0x200U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00001000 */
#define ETH_DMAC0RXDTPR_RDT_10 (0x400U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00002000 */
#define ETH_DMAC0RXDTPR_RDT_11 (0x800U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00004000 */
#define ETH_DMAC0RXDTPR_RDT_12 (0x1000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00008000 */
#define ETH_DMAC0RXDTPR_RDT_13 (0x2000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00010000 */
#define ETH_DMAC0RXDTPR_RDT_14 (0x4000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00020000 */
#define ETH_DMAC0RXDTPR_RDT_15 (0x8000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00040000 */
#define ETH_DMAC0RXDTPR_RDT_16 (0x10000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00080000 */
#define ETH_DMAC0RXDTPR_RDT_17 (0x20000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00100000 */
#define ETH_DMAC0RXDTPR_RDT_18 (0x40000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00200000 */
#define ETH_DMAC0RXDTPR_RDT_19 (0x80000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00400000 */
#define ETH_DMAC0RXDTPR_RDT_20 (0x100000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x00800000 */
#define ETH_DMAC0RXDTPR_RDT_21 (0x200000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x01000000 */
#define ETH_DMAC0RXDTPR_RDT_22 (0x400000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x02000000 */
#define ETH_DMAC0RXDTPR_RDT_23 (0x800000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x04000000 */
#define ETH_DMAC0RXDTPR_RDT_24 (0x1000000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x08000000 */
#define ETH_DMAC0RXDTPR_RDT_25 (0x2000000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x10000000 */
#define ETH_DMAC0RXDTPR_RDT_26 (0x4000000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x20000000 */
#define ETH_DMAC0RXDTPR_RDT_27 (0x8000000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x40000000 */
#define ETH_DMAC0RXDTPR_RDT_28 (0x10000000U << ETH_DMAC0RXDTPR_RDT_Pos) /*!< 0x80000000 */
/************ Bit definition for ETH_DMAC0TXRLR register *************/
#define ETH_DMAC0TXRLR_TDRL_Pos (0U)
#define ETH_DMAC0TXRLR_TDRL_Msk (0x3FFU << ETH_DMAC0TXRLR_TDRL_Pos) /*!< 0x000003FF */
#define ETH_DMAC0TXRLR_TDRL ETH_DMAC0TXRLR_TDRL_Msk /*!< Transmit Descriptor Ring Length */
#define ETH_DMAC0TXRLR_TDRL_0 (0x1U << ETH_DMAC0TXRLR_TDRL_Pos) /*!< 0x00000001 */
#define ETH_DMAC0TXRLR_TDRL_1 (0x2U << ETH_DMAC0TXRLR_TDRL_Pos) /*!< 0x00000002 */
#define ETH_DMAC0TXRLR_TDRL_2 (0x4U << ETH_DMAC0TXRLR_TDRL_Pos) /*!< 0x00000004 */
#define ETH_DMAC0TXRLR_TDRL_3 (0x8U << ETH_DMAC0TXRLR_TDRL_Pos) /*!< 0x00000008 */
#define ETH_DMAC0TXRLR_TDRL_4 (0x10U << ETH_DMAC0TXRLR_TDRL_Pos) /*!< 0x00000010 */
#define ETH_DMAC0TXRLR_TDRL_5 (0x20U << ETH_DMAC0TXRLR_TDRL_Pos) /*!< 0x00000020 */
#define ETH_DMAC0TXRLR_TDRL_6 (0x40U << ETH_DMAC0TXRLR_TDRL_Pos) /*!< 0x00000040 */
#define ETH_DMAC0TXRLR_TDRL_7 (0x80U << ETH_DMAC0TXRLR_TDRL_Pos) /*!< 0x00000080 */
#define ETH_DMAC0TXRLR_TDRL_8 (0x100U << ETH_DMAC0TXRLR_TDRL_Pos) /*!< 0x00000100 */
#define ETH_DMAC0TXRLR_TDRL_9 (0x200U << ETH_DMAC0TXRLR_TDRL_Pos) /*!< 0x00000200 */
/************ Bit definition for ETH_DMAC0RXRLR register *************/
#define ETH_DMAC0RXRLR_RDRL_Pos (0U)
#define ETH_DMAC0RXRLR_RDRL_Msk (0x3FFU << ETH_DMAC0RXRLR_RDRL_Pos) /*!< 0x000003FF */
#define ETH_DMAC0RXRLR_RDRL ETH_DMAC0RXRLR_RDRL_Msk /*!< Receive Descriptor Ring Length */
#define ETH_DMAC0RXRLR_RDRL_0 (0x1U << ETH_DMAC0RXRLR_RDRL_Pos) /*!< 0x00000001 */
#define ETH_DMAC0RXRLR_RDRL_1 (0x2U << ETH_DMAC0RXRLR_RDRL_Pos) /*!< 0x00000002 */
#define ETH_DMAC0RXRLR_RDRL_2 (0x4U << ETH_DMAC0RXRLR_RDRL_Pos) /*!< 0x00000004 */
#define ETH_DMAC0RXRLR_RDRL_3 (0x8U << ETH_DMAC0RXRLR_RDRL_Pos) /*!< 0x00000008 */
#define ETH_DMAC0RXRLR_RDRL_4 (0x10U << ETH_DMAC0RXRLR_RDRL_Pos) /*!< 0x00000010 */
#define ETH_DMAC0RXRLR_RDRL_5 (0x20U << ETH_DMAC0RXRLR_RDRL_Pos) /*!< 0x00000020 */
#define ETH_DMAC0RXRLR_RDRL_6 (0x40U << ETH_DMAC0RXRLR_RDRL_Pos) /*!< 0x00000040 */
#define ETH_DMAC0RXRLR_RDRL_7 (0x80U << ETH_DMAC0RXRLR_RDRL_Pos) /*!< 0x00000080 */
#define ETH_DMAC0RXRLR_RDRL_8 (0x100U << ETH_DMAC0RXRLR_RDRL_Pos) /*!< 0x00000100 */
#define ETH_DMAC0RXRLR_RDRL_9 (0x200U << ETH_DMAC0RXRLR_RDRL_Pos) /*!< 0x00000200 */
/************* Bit definition for ETH_DMAC0IER register **************/
#define ETH_DMAC0IER_TIE_Pos (0U)
#define ETH_DMAC0IER_TIE_Msk (0x1U << ETH_DMAC0IER_TIE_Pos) /*!< 0x00000001 */
#define ETH_DMAC0IER_TIE ETH_DMAC0IER_TIE_Msk /*!< Transmit Interrupt Enable */
#define ETH_DMAC0IER_TXSE_Pos (1U)
#define ETH_DMAC0IER_TXSE_Msk (0x1U << ETH_DMAC0IER_TXSE_Pos) /*!< 0x00000002 */
#define ETH_DMAC0IER_TXSE ETH_DMAC0IER_TXSE_Msk /*!< Transmit Stopped Enable */
#define ETH_DMAC0IER_TBUE_Pos (2U)
#define ETH_DMAC0IER_TBUE_Msk (0x1U << ETH_DMAC0IER_TBUE_Pos) /*!< 0x00000004 */
#define ETH_DMAC0IER_TBUE ETH_DMAC0IER_TBUE_Msk /*!< Transmit Buffer Unavailable Enable */
#define ETH_DMAC0IER_RIE_Pos (6U)
#define ETH_DMAC0IER_RIE_Msk (0x1U << ETH_DMAC0IER_RIE_Pos) /*!< 0x00000040 */
#define ETH_DMAC0IER_RIE ETH_DMAC0IER_RIE_Msk /*!< Receive Interrupt Enable */
#define ETH_DMAC0IER_RBUE_Pos (7U)
#define ETH_DMAC0IER_RBUE_Msk (0x1U << ETH_DMAC0IER_RBUE_Pos) /*!< 0x00000080 */
#define ETH_DMAC0IER_RBUE ETH_DMAC0IER_RBUE_Msk /*!< Receive Buffer Unavailable Enable */
#define ETH_DMAC0IER_RSE_Pos (8U)
#define ETH_DMAC0IER_RSE_Msk (0x1U << ETH_DMAC0IER_RSE_Pos) /*!< 0x00000100 */
#define ETH_DMAC0IER_RSE ETH_DMAC0IER_RSE_Msk /*!< Receive Stopped Enable */
#define ETH_DMAC0IER_RWTE_Pos (9U)
#define ETH_DMAC0IER_RWTE_Msk (0x1U << ETH_DMAC0IER_RWTE_Pos) /*!< 0x00000200 */
#define ETH_DMAC0IER_RWTE ETH_DMAC0IER_RWTE_Msk /*!< Receive Watchdog Timeout Enable */
#define ETH_DMAC0IER_ETIE_Pos (10U)
#define ETH_DMAC0IER_ETIE_Msk (0x1U << ETH_DMAC0IER_ETIE_Pos) /*!< 0x00000400 */
#define ETH_DMAC0IER_ETIE ETH_DMAC0IER_ETIE_Msk /*!< Early Transmit Interrupt Enable */
#define ETH_DMAC0IER_ERIE_Pos (11U)
#define ETH_DMAC0IER_ERIE_Msk (0x1U << ETH_DMAC0IER_ERIE_Pos) /*!< 0x00000800 */
#define ETH_DMAC0IER_ERIE ETH_DMAC0IER_ERIE_Msk /*!< Early Receive Interrupt Enable */
#define ETH_DMAC0IER_FBEE_Pos (12U)
#define ETH_DMAC0IER_FBEE_Msk (0x1U << ETH_DMAC0IER_FBEE_Pos) /*!< 0x00001000 */
#define ETH_DMAC0IER_FBEE ETH_DMAC0IER_FBEE_Msk /*!< Fatal Bus Error Enable */
#define ETH_DMAC0IER_CDEE_Pos (13U)
#define ETH_DMAC0IER_CDEE_Msk (0x1U << ETH_DMAC0IER_CDEE_Pos) /*!< 0x00002000 */
#define ETH_DMAC0IER_CDEE ETH_DMAC0IER_CDEE_Msk /*!< Context Descriptor Error Enable */
#define ETH_DMAC0IER_AIE_Pos (14U)
#define ETH_DMAC0IER_AIE_Msk (0x1U << ETH_DMAC0IER_AIE_Pos) /*!< 0x00004000 */
#define ETH_DMAC0IER_AIE ETH_DMAC0IER_AIE_Msk /*!< Abnormal Interrupt Summary Enable */
#define ETH_DMAC0IER_NIE_Pos (15U)
#define ETH_DMAC0IER_NIE_Msk (0x1U << ETH_DMAC0IER_NIE_Pos) /*!< 0x00008000 */
#define ETH_DMAC0IER_NIE ETH_DMAC0IER_NIE_Msk /*!< Normal Interrupt Summary Enable */
/************ Bit definition for ETH_DMAC0RXIWTR register ************/
#define ETH_DMAC0RXIWTR_RWT_Pos (0U)
#define ETH_DMAC0RXIWTR_RWT_Msk (0xFFU << ETH_DMAC0RXIWTR_RWT_Pos) /*!< 0x000000FF */
#define ETH_DMAC0RXIWTR_RWT ETH_DMAC0RXIWTR_RWT_Msk /*!< Receive Interrupt Watchdog Timer Count */
#define ETH_DMAC0RXIWTR_RWT_0 (0x1U << ETH_DMAC0RXIWTR_RWT_Pos) /*!< 0x00000001 */
#define ETH_DMAC0RXIWTR_RWT_1 (0x2U << ETH_DMAC0RXIWTR_RWT_Pos) /*!< 0x00000002 */
#define ETH_DMAC0RXIWTR_RWT_2 (0x4U << ETH_DMAC0RXIWTR_RWT_Pos) /*!< 0x00000004 */
#define ETH_DMAC0RXIWTR_RWT_3 (0x8U << ETH_DMAC0RXIWTR_RWT_Pos) /*!< 0x00000008 */
#define ETH_DMAC0RXIWTR_RWT_4 (0x10U << ETH_DMAC0RXIWTR_RWT_Pos) /*!< 0x00000010 */
#define ETH_DMAC0RXIWTR_RWT_5 (0x20U << ETH_DMAC0RXIWTR_RWT_Pos) /*!< 0x00000020 */
#define ETH_DMAC0RXIWTR_RWT_6 (0x40U << ETH_DMAC0RXIWTR_RWT_Pos) /*!< 0x00000040 */
#define ETH_DMAC0RXIWTR_RWT_7 (0x80U << ETH_DMAC0RXIWTR_RWT_Pos) /*!< 0x00000080 */
/************ Bit definition for ETH_DMAC0SFCSR register *************/
#define ETH_DMAC0SFCSR_ESC_Pos (0U)
#define ETH_DMAC0SFCSR_ESC_Msk (0x1U << ETH_DMAC0SFCSR_ESC_Pos) /*!< 0x00000001 */
#define ETH_DMAC0SFCSR_ESC ETH_DMAC0SFCSR_ESC_Msk /*!< Enable Slot Comparison */
#define ETH_DMAC0SFCSR_ASC_Pos (1U)
#define ETH_DMAC0SFCSR_ASC_Msk (0x1U << ETH_DMAC0SFCSR_ASC_Pos) /*!< 0x00000002 */
#define ETH_DMAC0SFCSR_ASC ETH_DMAC0SFCSR_ASC_Msk /*!< Advance Slot Check */
#define ETH_DMAC0SFCSR_RSN_Pos (16U)
#define ETH_DMAC0SFCSR_RSN_Msk (0xFU << ETH_DMAC0SFCSR_RSN_Pos) /*!< 0x000F0000 */
#define ETH_DMAC0SFCSR_RSN ETH_DMAC0SFCSR_RSN_Msk /*!< Reference Slot Number */
#define ETH_DMAC0SFCSR_RSN_0 (0x1U << ETH_DMAC0SFCSR_RSN_Pos) /*!< 0x00010000 */
#define ETH_DMAC0SFCSR_RSN_1 (0x2U << ETH_DMAC0SFCSR_RSN_Pos) /*!< 0x00020000 */
#define ETH_DMAC0SFCSR_RSN_2 (0x4U << ETH_DMAC0SFCSR_RSN_Pos) /*!< 0x00040000 */
#define ETH_DMAC0SFCSR_RSN_3 (0x8U << ETH_DMAC0SFCSR_RSN_Pos) /*!< 0x00080000 */
/************ Bit definition for ETH_DMAC0CATXDR register ************/
#define ETH_DMAC0CATXDR_CURTDESAPTR_Pos (0U)
#define ETH_DMAC0CATXDR_CURTDESAPTR_Msk (0xFFFFFFFFU << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */
#define ETH_DMAC0CATXDR_CURTDESAPTR ETH_DMAC0CATXDR_CURTDESAPTR_Msk /*!< Application Transmit Descriptor Address Pointer */
#define ETH_DMAC0CATXDR_CURTDESAPTR_0 (0x1U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00000001 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_1 (0x2U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00000002 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_2 (0x4U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00000004 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_3 (0x8U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00000008 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_4 (0x10U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00000010 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_5 (0x20U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00000020 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_6 (0x40U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00000040 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_7 (0x80U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00000080 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_8 (0x100U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00000100 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_9 (0x200U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00000200 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_10 (0x400U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00000400 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_11 (0x800U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00000800 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_12 (0x1000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00001000 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_13 (0x2000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00002000 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_14 (0x4000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00004000 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_15 (0x8000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00008000 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_16 (0x10000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00010000 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_17 (0x20000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00020000 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_18 (0x40000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00040000 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_19 (0x80000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00080000 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_20 (0x100000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00100000 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_21 (0x200000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00200000 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_22 (0x400000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00400000 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_23 (0x800000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x00800000 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_24 (0x1000000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x01000000 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_25 (0x2000000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x02000000 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_26 (0x4000000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x04000000 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_27 (0x8000000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x08000000 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_28 (0x10000000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x10000000 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_29 (0x20000000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x20000000 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_30 (0x40000000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x40000000 */
#define ETH_DMAC0CATXDR_CURTDESAPTR_31 (0x80000000U << ETH_DMAC0CATXDR_CURTDESAPTR_Pos) /*!< 0x80000000 */
/************ Bit definition for ETH_DMAC0CARXDR register ************/
#define ETH_DMAC0CARXDR_CURRDESAPTR_Pos (0U)
#define ETH_DMAC0CARXDR_CURRDESAPTR_Msk (0xFFFFFFFFU << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */
#define ETH_DMAC0CARXDR_CURRDESAPTR ETH_DMAC0CARXDR_CURRDESAPTR_Msk /*!< Application Receive Descriptor Address Pointer */
#define ETH_DMAC0CARXDR_CURRDESAPTR_0 (0x1U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00000001 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_1 (0x2U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00000002 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_2 (0x4U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00000004 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_3 (0x8U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00000008 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_4 (0x10U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00000010 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_5 (0x20U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00000020 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_6 (0x40U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00000040 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_7 (0x80U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00000080 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_8 (0x100U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00000100 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_9 (0x200U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00000200 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_10 (0x400U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00000400 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_11 (0x800U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00000800 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_12 (0x1000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00001000 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_13 (0x2000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00002000 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_14 (0x4000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00004000 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_15 (0x8000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00008000 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_16 (0x10000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00010000 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_17 (0x20000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00020000 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_18 (0x40000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00040000 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_19 (0x80000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00080000 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_20 (0x100000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00100000 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_21 (0x200000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00200000 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_22 (0x400000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00400000 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_23 (0x800000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x00800000 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_24 (0x1000000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x01000000 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_25 (0x2000000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x02000000 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_26 (0x4000000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x04000000 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_27 (0x8000000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x08000000 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_28 (0x10000000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x10000000 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_29 (0x20000000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x20000000 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_30 (0x40000000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x40000000 */
#define ETH_DMAC0CARXDR_CURRDESAPTR_31 (0x80000000U << ETH_DMAC0CARXDR_CURRDESAPTR_Pos) /*!< 0x80000000 */
/************ Bit definition for ETH_DMAC0CATXBR register ************/
#define ETH_DMAC0CATXBR_CURTBUFAPTR_Pos (0U)
#define ETH_DMAC0CATXBR_CURTBUFAPTR_Msk (0xFFFFFFFFU << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */
#define ETH_DMAC0CATXBR_CURTBUFAPTR ETH_DMAC0CATXBR_CURTBUFAPTR_Msk /*!< Application Transmit Buffer Address Pointer */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_0 (0x1U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000001 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_1 (0x2U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000002 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_2 (0x4U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000004 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_3 (0x8U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000008 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_4 (0x10U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000010 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_5 (0x20U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000020 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_6 (0x40U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000040 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_7 (0x80U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000080 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_8 (0x100U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000100 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_9 (0x200U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000200 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_10 (0x400U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000400 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_11 (0x800U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000800 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_12 (0x1000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00001000 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_13 (0x2000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00002000 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_14 (0x4000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00004000 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_15 (0x8000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00008000 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_16 (0x10000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00010000 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_17 (0x20000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00020000 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_18 (0x40000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00040000 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_19 (0x80000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00080000 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_20 (0x100000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00100000 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_21 (0x200000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00200000 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_22 (0x400000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00400000 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_23 (0x800000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x00800000 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_24 (0x1000000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x01000000 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_25 (0x2000000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x02000000 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_26 (0x4000000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x04000000 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_27 (0x8000000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x08000000 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_28 (0x10000000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x10000000 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_29 (0x20000000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x20000000 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_30 (0x40000000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x40000000 */
#define ETH_DMAC0CATXBR_CURTBUFAPTR_31 (0x80000000U << ETH_DMAC0CATXBR_CURTBUFAPTR_Pos) /*!< 0x80000000 */
/************ Bit definition for ETH_DMAC0CARXBR register ************/
#define ETH_DMAC0CARXBR_CURRBUFAPTR_Pos (0U)
#define ETH_DMAC0CARXBR_CURRBUFAPTR_Msk (0xFFFFFFFFU << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */
#define ETH_DMAC0CARXBR_CURRBUFAPTR ETH_DMAC0CARXBR_CURRBUFAPTR_Msk /*!< Application Receive Buffer Address Pointer */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_0 (0x1U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00000001 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_1 (0x2U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00000002 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_2 (0x4U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00000004 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_3 (0x8U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00000008 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_4 (0x10U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00000010 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_5 (0x20U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00000020 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_6 (0x40U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00000040 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_7 (0x80U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00000080 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_8 (0x100U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00000100 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_9 (0x200U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00000200 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_10 (0x400U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00000400 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_11 (0x800U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00000800 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_12 (0x1000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00001000 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_13 (0x2000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00002000 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_14 (0x4000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00004000 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_15 (0x8000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00008000 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_16 (0x10000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00010000 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_17 (0x20000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00020000 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_18 (0x40000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00040000 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_19 (0x80000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00080000 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_20 (0x100000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00100000 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_21 (0x200000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00200000 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_22 (0x400000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00400000 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_23 (0x800000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x00800000 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_24 (0x1000000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x01000000 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_25 (0x2000000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x02000000 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_26 (0x4000000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x04000000 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_27 (0x8000000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x08000000 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_28 (0x10000000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x10000000 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_29 (0x20000000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x20000000 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_30 (0x40000000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x40000000 */
#define ETH_DMAC0CARXBR_CURRBUFAPTR_31 (0x80000000U << ETH_DMAC0CARXBR_CURRBUFAPTR_Pos) /*!< 0x80000000 */
/************** Bit definition for ETH_DMAC0SR register **************/
#define ETH_DMAC0SR_TI_Pos (0U)
#define ETH_DMAC0SR_TI_Msk (0x1U << ETH_DMAC0SR_TI_Pos) /*!< 0x00000001 */
#define ETH_DMAC0SR_TI ETH_DMAC0SR_TI_Msk /*!< Transmit Interrupt */
#define ETH_DMAC0SR_TPS_Pos (1U)
#define ETH_DMAC0SR_TPS_Msk (0x1U << ETH_DMAC0SR_TPS_Pos) /*!< 0x00000002 */
#define ETH_DMAC0SR_TPS ETH_DMAC0SR_TPS_Msk /*!< Transmit Process Stopped */
#define ETH_DMAC0SR_TBU_Pos (2U)
#define ETH_DMAC0SR_TBU_Msk (0x1U << ETH_DMAC0SR_TBU_Pos) /*!< 0x00000004 */
#define ETH_DMAC0SR_TBU ETH_DMAC0SR_TBU_Msk /*!< Transmit Buffer Unavailable */
#define ETH_DMAC0SR_RI_Pos (6U)
#define ETH_DMAC0SR_RI_Msk (0x1U << ETH_DMAC0SR_RI_Pos) /*!< 0x00000040 */
#define ETH_DMAC0SR_RI ETH_DMAC0SR_RI_Msk /*!< Receive Interrupt */
#define ETH_DMAC0SR_RBU_Pos (7U)
#define ETH_DMAC0SR_RBU_Msk (0x1U << ETH_DMAC0SR_RBU_Pos) /*!< 0x00000080 */
#define ETH_DMAC0SR_RBU ETH_DMAC0SR_RBU_Msk /*!< Receive Buffer Unavailable */
#define ETH_DMAC0SR_RPS_Pos (8U)
#define ETH_DMAC0SR_RPS_Msk (0x1U << ETH_DMAC0SR_RPS_Pos) /*!< 0x00000100 */
#define ETH_DMAC0SR_RPS ETH_DMAC0SR_RPS_Msk /*!< Receive Process Stopped */
#define ETH_DMAC0SR_RWT_Pos (9U)
#define ETH_DMAC0SR_RWT_Msk (0x1U << ETH_DMAC0SR_RWT_Pos) /*!< 0x00000200 */
#define ETH_DMAC0SR_RWT ETH_DMAC0SR_RWT_Msk /*!< Receive Watchdog Timeout */
#define ETH_DMAC0SR_ETI_Pos (10U)
#define ETH_DMAC0SR_ETI_Msk (0x1U << ETH_DMAC0SR_ETI_Pos) /*!< 0x00000400 */
#define ETH_DMAC0SR_ETI ETH_DMAC0SR_ETI_Msk /*!< Early Transmit Interrupt */
#define ETH_DMAC0SR_ERI_Pos (11U)
#define ETH_DMAC0SR_ERI_Msk (0x1U << ETH_DMAC0SR_ERI_Pos) /*!< 0x00000800 */
#define ETH_DMAC0SR_ERI ETH_DMAC0SR_ERI_Msk /*!< Early Receive Interrupt */
#define ETH_DMAC0SR_FBE_Pos (12U)
#define ETH_DMAC0SR_FBE_Msk (0x1U << ETH_DMAC0SR_FBE_Pos) /*!< 0x00001000 */
#define ETH_DMAC0SR_FBE ETH_DMAC0SR_FBE_Msk /*!< Fatal Bus Error */
#define ETH_DMAC0SR_CDE_Pos (13U)
#define ETH_DMAC0SR_CDE_Msk (0x1U << ETH_DMAC0SR_CDE_Pos) /*!< 0x00002000 */
#define ETH_DMAC0SR_CDE ETH_DMAC0SR_CDE_Msk /*!< Context Descriptor Error */
#define ETH_DMAC0SR_AIS_Pos (14U)
#define ETH_DMAC0SR_AIS_Msk (0x1U << ETH_DMAC0SR_AIS_Pos) /*!< 0x00004000 */
#define ETH_DMAC0SR_AIS ETH_DMAC0SR_AIS_Msk /*!< Abnormal Interrupt Summary */
#define ETH_DMAC0SR_NIS_Pos (15U)
#define ETH_DMAC0SR_NIS_Msk (0x1U << ETH_DMAC0SR_NIS_Pos) /*!< 0x00008000 */
#define ETH_DMAC0SR_NIS ETH_DMAC0SR_NIS_Msk /*!< Normal Interrupt Summary */
#define ETH_DMAC0SR_TEB_Pos (16U)
#define ETH_DMAC0SR_TEB_Msk (0x7U << ETH_DMAC0SR_TEB_Pos) /*!< 0x00070000 */
#define ETH_DMAC0SR_TEB ETH_DMAC0SR_TEB_Msk /*!< Tx DMA Error Bits */
#define ETH_DMAC0SR_TEB_0 (0x1U << ETH_DMAC0SR_TEB_Pos) /*!< 0x00010000 */
#define ETH_DMAC0SR_TEB_1 (0x2U << ETH_DMAC0SR_TEB_Pos) /*!< 0x00020000 */
#define ETH_DMAC0SR_TEB_2 (0x4U << ETH_DMAC0SR_TEB_Pos) /*!< 0x00040000 */
#define ETH_DMAC0SR_REB_Pos (19U)
#define ETH_DMAC0SR_REB_Msk (0x7U << ETH_DMAC0SR_REB_Pos) /*!< 0x00380000 */
#define ETH_DMAC0SR_REB ETH_DMAC0SR_REB_Msk /*!< Rx DMA Error Bits */
#define ETH_DMAC0SR_REB_0 (0x1U << ETH_DMAC0SR_REB_Pos) /*!< 0x00080000 */
#define ETH_DMAC0SR_REB_1 (0x2U << ETH_DMAC0SR_REB_Pos) /*!< 0x00100000 */
#define ETH_DMAC0SR_REB_2 (0x4U << ETH_DMAC0SR_REB_Pos) /*!< 0x00200000 */
/************* Bit definition for ETH_DMAC0MFCR register *************/
#define ETH_DMAC0MFCR_MFC_Pos (0U)
#define ETH_DMAC0MFCR_MFC_Msk (0x7FFU << ETH_DMAC0MFCR_MFC_Pos) /*!< 0x000007FF */
#define ETH_DMAC0MFCR_MFC ETH_DMAC0MFCR_MFC_Msk /*!< Dropped Packet Counters */
#define ETH_DMAC0MFCR_MFC_0 (0x1U << ETH_DMAC0MFCR_MFC_Pos) /*!< 0x00000001 */
#define ETH_DMAC0MFCR_MFC_1 (0x2U << ETH_DMAC0MFCR_MFC_Pos) /*!< 0x00000002 */
#define ETH_DMAC0MFCR_MFC_2 (0x4U << ETH_DMAC0MFCR_MFC_Pos) /*!< 0x00000004 */
#define ETH_DMAC0MFCR_MFC_3 (0x8U << ETH_DMAC0MFCR_MFC_Pos) /*!< 0x00000008 */
#define ETH_DMAC0MFCR_MFC_4 (0x10U << ETH_DMAC0MFCR_MFC_Pos) /*!< 0x00000010 */
#define ETH_DMAC0MFCR_MFC_5 (0x20U << ETH_DMAC0MFCR_MFC_Pos) /*!< 0x00000020 */
#define ETH_DMAC0MFCR_MFC_6 (0x40U << ETH_DMAC0MFCR_MFC_Pos) /*!< 0x00000040 */
#define ETH_DMAC0MFCR_MFC_7 (0x80U << ETH_DMAC0MFCR_MFC_Pos) /*!< 0x00000080 */
#define ETH_DMAC0MFCR_MFC_8 (0x100U << ETH_DMAC0MFCR_MFC_Pos) /*!< 0x00000100 */
#define ETH_DMAC0MFCR_MFC_9 (0x200U << ETH_DMAC0MFCR_MFC_Pos) /*!< 0x00000200 */
#define ETH_DMAC0MFCR_MFC_10 (0x400U << ETH_DMAC0MFCR_MFC_Pos) /*!< 0x00000400 */
#define ETH_DMAC0MFCR_MFCO_Pos (15U)
#define ETH_DMAC0MFCR_MFCO_Msk (0x1U << ETH_DMAC0MFCR_MFCO_Pos) /*!< 0x00008000 */
#define ETH_DMAC0MFCR_MFCO ETH_DMAC0MFCR_MFCO_Msk /*!< Overflow status of the MFC Counter */
/************** Bit definition for ETH_DMAC1CR register **************/
#define ETH_DMAC1CR_MSS_Pos (0U)
#define ETH_DMAC1CR_MSS_Msk (0x3FFFU << ETH_DMAC1CR_MSS_Pos) /*!< 0x00003FFF */
#define ETH_DMAC1CR_MSS ETH_DMAC1CR_MSS_Msk /*!< Maximum Segment Size */
#define ETH_DMAC1CR_MSS_0 (0x1U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00000001 */
#define ETH_DMAC1CR_MSS_1 (0x2U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00000002 */
#define ETH_DMAC1CR_MSS_2 (0x4U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00000004 */
#define ETH_DMAC1CR_MSS_3 (0x8U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00000008 */
#define ETH_DMAC1CR_MSS_4 (0x10U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00000010 */
#define ETH_DMAC1CR_MSS_5 (0x20U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00000020 */
#define ETH_DMAC1CR_MSS_6 (0x40U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00000040 */
#define ETH_DMAC1CR_MSS_7 (0x80U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00000080 */
#define ETH_DMAC1CR_MSS_8 (0x100U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00000100 */
#define ETH_DMAC1CR_MSS_9 (0x200U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00000200 */
#define ETH_DMAC1CR_MSS_10 (0x400U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00000400 */
#define ETH_DMAC1CR_MSS_11 (0x800U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00000800 */
#define ETH_DMAC1CR_MSS_12 (0x1000U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00001000 */
#define ETH_DMAC1CR_MSS_13 (0x2000U << ETH_DMAC1CR_MSS_Pos) /*!< 0x00002000 */
#define ETH_DMAC1CR_PBLX8_Pos (16U)
#define ETH_DMAC1CR_PBLX8_Msk (0x1U << ETH_DMAC1CR_PBLX8_Pos) /*!< 0x00010000 */
#define ETH_DMAC1CR_PBLX8 ETH_DMAC1CR_PBLX8_Msk /*!< 8xPBL mode */
#define ETH_DMAC1CR_DSL_Pos (18U)
#define ETH_DMAC1CR_DSL_Msk (0x7U << ETH_DMAC1CR_DSL_Pos) /*!< 0x001C0000 */
#define ETH_DMAC1CR_DSL ETH_DMAC1CR_DSL_Msk /*!< Descriptor Skip Length */
#define ETH_DMAC1CR_DSL_0 (0x1U << ETH_DMAC1CR_DSL_Pos) /*!< 0x00040000 */
#define ETH_DMAC1CR_DSL_1 (0x2U << ETH_DMAC1CR_DSL_Pos) /*!< 0x00080000 */
#define ETH_DMAC1CR_DSL_2 (0x4U << ETH_DMAC1CR_DSL_Pos) /*!< 0x00100000 */
/************* Bit definition for ETH_DMAC1TXCR register *************/
#define ETH_DMAC1TXCR_ST_Pos (0U)
#define ETH_DMAC1TXCR_ST_Msk (0x1U << ETH_DMAC1TXCR_ST_Pos) /*!< 0x00000001 */
#define ETH_DMAC1TXCR_ST ETH_DMAC1TXCR_ST_Msk /*!< Start or Stop Transmission Command */
#define ETH_DMAC1TXCR_TCW_Pos (1U)
#define ETH_DMAC1TXCR_TCW_Msk (0x7U << ETH_DMAC1TXCR_TCW_Pos) /*!< 0x0000000E */
#define ETH_DMAC1TXCR_TCW ETH_DMAC1TXCR_TCW_Msk /*!< Transmit Channel Weight */
#define ETH_DMAC1TXCR_TCW_0 (0x1U << ETH_DMAC1TXCR_TCW_Pos) /*!< 0x00000002 */
#define ETH_DMAC1TXCR_TCW_1 (0x2U << ETH_DMAC1TXCR_TCW_Pos) /*!< 0x00000004 */
#define ETH_DMAC1TXCR_TCW_2 (0x4U << ETH_DMAC1TXCR_TCW_Pos) /*!< 0x00000008 */
#define ETH_DMAC1TXCR_OSF_Pos (4U)
#define ETH_DMAC1TXCR_OSF_Msk (0x1U << ETH_DMAC1TXCR_OSF_Pos) /*!< 0x00000010 */
#define ETH_DMAC1TXCR_OSF ETH_DMAC1TXCR_OSF_Msk /*!< Operate on Second Packet */
#define ETH_DMAC1TXCR_TSE_Pos (12U)
#define ETH_DMAC1TXCR_TSE_Msk (0x1U << ETH_DMAC1TXCR_TSE_Pos) /*!< 0x00001000 */
#define ETH_DMAC1TXCR_TSE ETH_DMAC1TXCR_TSE_Msk /*!< TCP Segmentation Enabled */
#define ETH_DMAC1TXCR_TXPBL_Pos (16U)
#define ETH_DMAC1TXCR_TXPBL_Msk (0x3FU << ETH_DMAC1TXCR_TXPBL_Pos) /*!< 0x003F0000 */
#define ETH_DMAC1TXCR_TXPBL ETH_DMAC1TXCR_TXPBL_Msk /*!< Transmit Programmable Burst Length */
#define ETH_DMAC1TXCR_TXPBL_0 (0x1U << ETH_DMAC1TXCR_TXPBL_Pos) /*!< 0x00010000 */
#define ETH_DMAC1TXCR_TXPBL_1 (0x2U << ETH_DMAC1TXCR_TXPBL_Pos) /*!< 0x00020000 */
#define ETH_DMAC1TXCR_TXPBL_2 (0x4U << ETH_DMAC1TXCR_TXPBL_Pos) /*!< 0x00040000 */
#define ETH_DMAC1TXCR_TXPBL_3 (0x8U << ETH_DMAC1TXCR_TXPBL_Pos) /*!< 0x00080000 */
#define ETH_DMAC1TXCR_TXPBL_4 (0x10U << ETH_DMAC1TXCR_TXPBL_Pos) /*!< 0x00100000 */
#define ETH_DMAC1TXCR_TXPBL_5 (0x20U << ETH_DMAC1TXCR_TXPBL_Pos) /*!< 0x00200000 */
#define ETH_DMAC1TXCR_TQOS_Pos (24U)
#define ETH_DMAC1TXCR_TQOS_Msk (0xFU << ETH_DMAC1TXCR_TQOS_Pos) /*!< 0x0F000000 */
#define ETH_DMAC1TXCR_TQOS ETH_DMAC1TXCR_TQOS_Msk /*!< Transmit QOS. */
#define ETH_DMAC1TXCR_TQOS_0 (0x1U << ETH_DMAC1TXCR_TQOS_Pos) /*!< 0x01000000 */
#define ETH_DMAC1TXCR_TQOS_1 (0x2U << ETH_DMAC1TXCR_TQOS_Pos) /*!< 0x02000000 */
#define ETH_DMAC1TXCR_TQOS_2 (0x4U << ETH_DMAC1TXCR_TQOS_Pos) /*!< 0x04000000 */
#define ETH_DMAC1TXCR_TQOS_3 (0x8U << ETH_DMAC1TXCR_TQOS_Pos) /*!< 0x08000000 */
/************ Bit definition for ETH_DMAC1TXDLAR register ************/
#define ETH_DMAC1TXDLAR_TDESLA_Pos (3U)
#define ETH_DMAC1TXDLAR_TDESLA_Msk (0x1FFFFFFFU << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0xFFFFFFF8 */
#define ETH_DMAC1TXDLAR_TDESLA ETH_DMAC1TXDLAR_TDESLA_Msk /*!< Start of Transmit List */
#define ETH_DMAC1TXDLAR_TDESLA_0 (0x1U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00000008 */
#define ETH_DMAC1TXDLAR_TDESLA_1 (0x2U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00000010 */
#define ETH_DMAC1TXDLAR_TDESLA_2 (0x4U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00000020 */
#define ETH_DMAC1TXDLAR_TDESLA_3 (0x8U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00000040 */
#define ETH_DMAC1TXDLAR_TDESLA_4 (0x10U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00000080 */
#define ETH_DMAC1TXDLAR_TDESLA_5 (0x20U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00000100 */
#define ETH_DMAC1TXDLAR_TDESLA_6 (0x40U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00000200 */
#define ETH_DMAC1TXDLAR_TDESLA_7 (0x80U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00000400 */
#define ETH_DMAC1TXDLAR_TDESLA_8 (0x100U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00000800 */
#define ETH_DMAC1TXDLAR_TDESLA_9 (0x200U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00001000 */
#define ETH_DMAC1TXDLAR_TDESLA_10 (0x400U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00002000 */
#define ETH_DMAC1TXDLAR_TDESLA_11 (0x800U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00004000 */
#define ETH_DMAC1TXDLAR_TDESLA_12 (0x1000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00008000 */
#define ETH_DMAC1TXDLAR_TDESLA_13 (0x2000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00010000 */
#define ETH_DMAC1TXDLAR_TDESLA_14 (0x4000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00020000 */
#define ETH_DMAC1TXDLAR_TDESLA_15 (0x8000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00040000 */
#define ETH_DMAC1TXDLAR_TDESLA_16 (0x10000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00080000 */
#define ETH_DMAC1TXDLAR_TDESLA_17 (0x20000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00100000 */
#define ETH_DMAC1TXDLAR_TDESLA_18 (0x40000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00200000 */
#define ETH_DMAC1TXDLAR_TDESLA_19 (0x80000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00400000 */
#define ETH_DMAC1TXDLAR_TDESLA_20 (0x100000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x00800000 */
#define ETH_DMAC1TXDLAR_TDESLA_21 (0x200000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x01000000 */
#define ETH_DMAC1TXDLAR_TDESLA_22 (0x400000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x02000000 */
#define ETH_DMAC1TXDLAR_TDESLA_23 (0x800000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x04000000 */
#define ETH_DMAC1TXDLAR_TDESLA_24 (0x1000000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x08000000 */
#define ETH_DMAC1TXDLAR_TDESLA_25 (0x2000000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x10000000 */
#define ETH_DMAC1TXDLAR_TDESLA_26 (0x4000000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x20000000 */
#define ETH_DMAC1TXDLAR_TDESLA_27 (0x8000000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x40000000 */
#define ETH_DMAC1TXDLAR_TDESLA_28 (0x10000000U << ETH_DMAC1TXDLAR_TDESLA_Pos) /*!< 0x80000000 */
/************ Bit definition for ETH_DMAC1TXDTPR register ************/
#define ETH_DMAC1TXDTPR_TDT_Pos (3U)
#define ETH_DMAC1TXDTPR_TDT_Msk (0x1FFFFFFFU << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0xFFFFFFF8 */
#define ETH_DMAC1TXDTPR_TDT ETH_DMAC1TXDTPR_TDT_Msk /*!< Transmit Descriptor Tail Pointer */
#define ETH_DMAC1TXDTPR_TDT_0 (0x1U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00000008 */
#define ETH_DMAC1TXDTPR_TDT_1 (0x2U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00000010 */
#define ETH_DMAC1TXDTPR_TDT_2 (0x4U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00000020 */
#define ETH_DMAC1TXDTPR_TDT_3 (0x8U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00000040 */
#define ETH_DMAC1TXDTPR_TDT_4 (0x10U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00000080 */
#define ETH_DMAC1TXDTPR_TDT_5 (0x20U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00000100 */
#define ETH_DMAC1TXDTPR_TDT_6 (0x40U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00000200 */
#define ETH_DMAC1TXDTPR_TDT_7 (0x80U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00000400 */
#define ETH_DMAC1TXDTPR_TDT_8 (0x100U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00000800 */
#define ETH_DMAC1TXDTPR_TDT_9 (0x200U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00001000 */
#define ETH_DMAC1TXDTPR_TDT_10 (0x400U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00002000 */
#define ETH_DMAC1TXDTPR_TDT_11 (0x800U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00004000 */
#define ETH_DMAC1TXDTPR_TDT_12 (0x1000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00008000 */
#define ETH_DMAC1TXDTPR_TDT_13 (0x2000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00010000 */
#define ETH_DMAC1TXDTPR_TDT_14 (0x4000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00020000 */
#define ETH_DMAC1TXDTPR_TDT_15 (0x8000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00040000 */
#define ETH_DMAC1TXDTPR_TDT_16 (0x10000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00080000 */
#define ETH_DMAC1TXDTPR_TDT_17 (0x20000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00100000 */
#define ETH_DMAC1TXDTPR_TDT_18 (0x40000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00200000 */
#define ETH_DMAC1TXDTPR_TDT_19 (0x80000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00400000 */
#define ETH_DMAC1TXDTPR_TDT_20 (0x100000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x00800000 */
#define ETH_DMAC1TXDTPR_TDT_21 (0x200000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x01000000 */
#define ETH_DMAC1TXDTPR_TDT_22 (0x400000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x02000000 */
#define ETH_DMAC1TXDTPR_TDT_23 (0x800000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x04000000 */
#define ETH_DMAC1TXDTPR_TDT_24 (0x1000000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x08000000 */
#define ETH_DMAC1TXDTPR_TDT_25 (0x2000000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x10000000 */
#define ETH_DMAC1TXDTPR_TDT_26 (0x4000000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x20000000 */
#define ETH_DMAC1TXDTPR_TDT_27 (0x8000000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x40000000 */
#define ETH_DMAC1TXDTPR_TDT_28 (0x10000000U << ETH_DMAC1TXDTPR_TDT_Pos) /*!< 0x80000000 */
/************ Bit definition for ETH_DMAC1TXRLR register *************/
#define ETH_DMAC1TXRLR_TDRL_Pos (0U)
#define ETH_DMAC1TXRLR_TDRL_Msk (0x3FFU << ETH_DMAC1TXRLR_TDRL_Pos) /*!< 0x000003FF */
#define ETH_DMAC1TXRLR_TDRL ETH_DMAC1TXRLR_TDRL_Msk /*!< Transmit Descriptor Ring Length */
#define ETH_DMAC1TXRLR_TDRL_0 (0x1U << ETH_DMAC1TXRLR_TDRL_Pos) /*!< 0x00000001 */
#define ETH_DMAC1TXRLR_TDRL_1 (0x2U << ETH_DMAC1TXRLR_TDRL_Pos) /*!< 0x00000002 */
#define ETH_DMAC1TXRLR_TDRL_2 (0x4U << ETH_DMAC1TXRLR_TDRL_Pos) /*!< 0x00000004 */
#define ETH_DMAC1TXRLR_TDRL_3 (0x8U << ETH_DMAC1TXRLR_TDRL_Pos) /*!< 0x00000008 */
#define ETH_DMAC1TXRLR_TDRL_4 (0x10U << ETH_DMAC1TXRLR_TDRL_Pos) /*!< 0x00000010 */
#define ETH_DMAC1TXRLR_TDRL_5 (0x20U << ETH_DMAC1TXRLR_TDRL_Pos) /*!< 0x00000020 */
#define ETH_DMAC1TXRLR_TDRL_6 (0x40U << ETH_DMAC1TXRLR_TDRL_Pos) /*!< 0x00000040 */
#define ETH_DMAC1TXRLR_TDRL_7 (0x80U << ETH_DMAC1TXRLR_TDRL_Pos) /*!< 0x00000080 */
#define ETH_DMAC1TXRLR_TDRL_8 (0x100U << ETH_DMAC1TXRLR_TDRL_Pos) /*!< 0x00000100 */
#define ETH_DMAC1TXRLR_TDRL_9 (0x200U << ETH_DMAC1TXRLR_TDRL_Pos) /*!< 0x00000200 */
/************* Bit definition for ETH_DMAC1IER register **************/
#define ETH_DMAC1IER_TIE_Pos (0U)
#define ETH_DMAC1IER_TIE_Msk (0x1U << ETH_DMAC1IER_TIE_Pos) /*!< 0x00000001 */
#define ETH_DMAC1IER_TIE ETH_DMAC1IER_TIE_Msk /*!< Transmit Interrupt Enable */
#define ETH_DMAC1IER_TXSE_Pos (1U)
#define ETH_DMAC1IER_TXSE_Msk (0x1U << ETH_DMAC1IER_TXSE_Pos) /*!< 0x00000002 */
#define ETH_DMAC1IER_TXSE ETH_DMAC1IER_TXSE_Msk /*!< Transmit Stopped Enable */
#define ETH_DMAC1IER_TBUE_Pos (2U)
#define ETH_DMAC1IER_TBUE_Msk (0x1U << ETH_DMAC1IER_TBUE_Pos) /*!< 0x00000004 */
#define ETH_DMAC1IER_TBUE ETH_DMAC1IER_TBUE_Msk /*!< Transmit Buffer Unavailable Enable */
#define ETH_DMAC1IER_RIE_Pos (6U)
#define ETH_DMAC1IER_RIE_Msk (0x1U << ETH_DMAC1IER_RIE_Pos) /*!< 0x00000040 */
#define ETH_DMAC1IER_RIE ETH_DMAC1IER_RIE_Msk /*!< Receive Interrupt Enable */
#define ETH_DMAC1IER_RBUE_Pos (7U)
#define ETH_DMAC1IER_RBUE_Msk (0x1U << ETH_DMAC1IER_RBUE_Pos) /*!< 0x00000080 */
#define ETH_DMAC1IER_RBUE ETH_DMAC1IER_RBUE_Msk /*!< Receive Buffer Unavailable Enable */
#define ETH_DMAC1IER_RSE_Pos (8U)
#define ETH_DMAC1IER_RSE_Msk (0x1U << ETH_DMAC1IER_RSE_Pos) /*!< 0x00000100 */
#define ETH_DMAC1IER_RSE ETH_DMAC1IER_RSE_Msk /*!< Receive Stopped Enable */
#define ETH_DMAC1IER_RWTE_Pos (9U)
#define ETH_DMAC1IER_RWTE_Msk (0x1U << ETH_DMAC1IER_RWTE_Pos) /*!< 0x00000200 */
#define ETH_DMAC1IER_RWTE ETH_DMAC1IER_RWTE_Msk /*!< Receive Watchdog Timeout Enable */
#define ETH_DMAC1IER_ETIE_Pos (10U)
#define ETH_DMAC1IER_ETIE_Msk (0x1U << ETH_DMAC1IER_ETIE_Pos) /*!< 0x00000400 */
#define ETH_DMAC1IER_ETIE ETH_DMAC1IER_ETIE_Msk /*!< Early Transmit Interrupt Enable */
#define ETH_DMAC1IER_ERIE_Pos (11U)
#define ETH_DMAC1IER_ERIE_Msk (0x1U << ETH_DMAC1IER_ERIE_Pos) /*!< 0x00000800 */
#define ETH_DMAC1IER_ERIE ETH_DMAC1IER_ERIE_Msk /*!< Early Receive Interrupt Enable */
#define ETH_DMAC1IER_FBEE_Pos (12U)
#define ETH_DMAC1IER_FBEE_Msk (0x1U << ETH_DMAC1IER_FBEE_Pos) /*!< 0x00001000 */
#define ETH_DMAC1IER_FBEE ETH_DMAC1IER_FBEE_Msk /*!< Fatal Bus Error Enable */
#define ETH_DMAC1IER_CDEE_Pos (13U)
#define ETH_DMAC1IER_CDEE_Msk (0x1U << ETH_DMAC1IER_CDEE_Pos) /*!< 0x00002000 */
#define ETH_DMAC1IER_CDEE ETH_DMAC1IER_CDEE_Msk /*!< Context Descriptor Error Enable */
#define ETH_DMAC1IER_AIE_Pos (14U)
#define ETH_DMAC1IER_AIE_Msk (0x1U << ETH_DMAC1IER_AIE_Pos) /*!< 0x00004000 */
#define ETH_DMAC1IER_AIE ETH_DMAC1IER_AIE_Msk /*!< Abnormal Interrupt Summary Enable */
#define ETH_DMAC1IER_NIE_Pos (15U)
#define ETH_DMAC1IER_NIE_Msk (0x1U << ETH_DMAC1IER_NIE_Pos) /*!< 0x00008000 */
#define ETH_DMAC1IER_NIE ETH_DMAC1IER_NIE_Msk /*!< Normal Interrupt Summary Enable */
/************ Bit definition for ETH_DMAC1SFCSR register *************/
#define ETH_DMAC1SFCSR_ESC_Pos (0U)
#define ETH_DMAC1SFCSR_ESC_Msk (0x1U << ETH_DMAC1SFCSR_ESC_Pos) /*!< 0x00000001 */
#define ETH_DMAC1SFCSR_ESC ETH_DMAC1SFCSR_ESC_Msk /*!< Enable Slot Comparison */
#define ETH_DMAC1SFCSR_ASC_Pos (1U)
#define ETH_DMAC1SFCSR_ASC_Msk (0x1U << ETH_DMAC1SFCSR_ASC_Pos) /*!< 0x00000002 */
#define ETH_DMAC1SFCSR_ASC ETH_DMAC1SFCSR_ASC_Msk /*!< Advance Slot Check */
#define ETH_DMAC1SFCSR_RSN_Pos (16U)
#define ETH_DMAC1SFCSR_RSN_Msk (0xFU << ETH_DMAC1SFCSR_RSN_Pos) /*!< 0x000F0000 */
#define ETH_DMAC1SFCSR_RSN ETH_DMAC1SFCSR_RSN_Msk /*!< Reference Slot Number */
#define ETH_DMAC1SFCSR_RSN_0 (0x1U << ETH_DMAC1SFCSR_RSN_Pos) /*!< 0x00010000 */
#define ETH_DMAC1SFCSR_RSN_1 (0x2U << ETH_DMAC1SFCSR_RSN_Pos) /*!< 0x00020000 */
#define ETH_DMAC1SFCSR_RSN_2 (0x4U << ETH_DMAC1SFCSR_RSN_Pos) /*!< 0x00040000 */
#define ETH_DMAC1SFCSR_RSN_3 (0x8U << ETH_DMAC1SFCSR_RSN_Pos) /*!< 0x00080000 */
/************ Bit definition for ETH_DMAC1CATXDR register ************/
#define ETH_DMAC1CATXDR_CURTDESAPTR_Pos (0U)
#define ETH_DMAC1CATXDR_CURTDESAPTR_Msk (0xFFFFFFFFU << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */
#define ETH_DMAC1CATXDR_CURTDESAPTR ETH_DMAC1CATXDR_CURTDESAPTR_Msk /*!< Application Transmit Descriptor Address Pointer */
#define ETH_DMAC1CATXDR_CURTDESAPTR_0 (0x1U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00000001 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_1 (0x2U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00000002 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_2 (0x4U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00000004 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_3 (0x8U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00000008 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_4 (0x10U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00000010 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_5 (0x20U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00000020 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_6 (0x40U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00000040 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_7 (0x80U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00000080 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_8 (0x100U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00000100 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_9 (0x200U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00000200 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_10 (0x400U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00000400 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_11 (0x800U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00000800 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_12 (0x1000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00001000 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_13 (0x2000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00002000 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_14 (0x4000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00004000 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_15 (0x8000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00008000 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_16 (0x10000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00010000 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_17 (0x20000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00020000 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_18 (0x40000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00040000 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_19 (0x80000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00080000 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_20 (0x100000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00100000 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_21 (0x200000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00200000 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_22 (0x400000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00400000 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_23 (0x800000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x00800000 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_24 (0x1000000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x01000000 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_25 (0x2000000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x02000000 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_26 (0x4000000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x04000000 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_27 (0x8000000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x08000000 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_28 (0x10000000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x10000000 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_29 (0x20000000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x20000000 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_30 (0x40000000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x40000000 */
#define ETH_DMAC1CATXDR_CURTDESAPTR_31 (0x80000000U << ETH_DMAC1CATXDR_CURTDESAPTR_Pos) /*!< 0x80000000 */
/************ Bit definition for ETH_DMAC1CATXBR register ************/
#define ETH_DMAC1CATXBR_CURTBUFAPTR_Pos (0U)
#define ETH_DMAC1CATXBR_CURTBUFAPTR_Msk (0xFFFFFFFFU << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */
#define ETH_DMAC1CATXBR_CURTBUFAPTR ETH_DMAC1CATXBR_CURTBUFAPTR_Msk /*!< Application Transmit Buffer Address Pointer */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_0 (0x1U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000001 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_1 (0x2U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000002 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_2 (0x4U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000004 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_3 (0x8U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000008 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_4 (0x10U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000010 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_5 (0x20U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000020 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_6 (0x40U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000040 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_7 (0x80U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000080 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_8 (0x100U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000100 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_9 (0x200U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000200 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_10 (0x400U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000400 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_11 (0x800U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00000800 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_12 (0x1000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00001000 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_13 (0x2000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00002000 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_14 (0x4000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00004000 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_15 (0x8000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00008000 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_16 (0x10000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00010000 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_17 (0x20000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00020000 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_18 (0x40000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00040000 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_19 (0x80000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00080000 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_20 (0x100000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00100000 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_21 (0x200000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00200000 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_22 (0x400000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00400000 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_23 (0x800000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x00800000 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_24 (0x1000000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x01000000 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_25 (0x2000000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x02000000 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_26 (0x4000000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x04000000 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_27 (0x8000000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x08000000 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_28 (0x10000000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x10000000 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_29 (0x20000000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x20000000 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_30 (0x40000000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x40000000 */
#define ETH_DMAC1CATXBR_CURTBUFAPTR_31 (0x80000000U << ETH_DMAC1CATXBR_CURTBUFAPTR_Pos) /*!< 0x80000000 */
/************** Bit definition for ETH_DMAC1SR register **************/
#define ETH_DMAC1SR_TI_Pos (0U)
#define ETH_DMAC1SR_TI_Msk (0x1U << ETH_DMAC1SR_TI_Pos) /*!< 0x00000001 */
#define ETH_DMAC1SR_TI ETH_DMAC1SR_TI_Msk /*!< Transmit Interrupt */
#define ETH_DMAC1SR_TPS_Pos (1U)
#define ETH_DMAC1SR_TPS_Msk (0x1U << ETH_DMAC1SR_TPS_Pos) /*!< 0x00000002 */
#define ETH_DMAC1SR_TPS ETH_DMAC1SR_TPS_Msk /*!< Transmit Process Stopped */
#define ETH_DMAC1SR_TBU_Pos (2U)
#define ETH_DMAC1SR_TBU_Msk (0x1U << ETH_DMAC1SR_TBU_Pos) /*!< 0x00000004 */
#define ETH_DMAC1SR_TBU ETH_DMAC1SR_TBU_Msk /*!< Transmit Buffer Unavailable */
#define ETH_DMAC1SR_RI_Pos (6U)
#define ETH_DMAC1SR_RI_Msk (0x1U << ETH_DMAC1SR_RI_Pos) /*!< 0x00000040 */
#define ETH_DMAC1SR_RI ETH_DMAC1SR_RI_Msk /*!< Receive Interrupt */
#define ETH_DMAC1SR_RBU_Pos (7U)
#define ETH_DMAC1SR_RBU_Msk (0x1U << ETH_DMAC1SR_RBU_Pos) /*!< 0x00000080 */
#define ETH_DMAC1SR_RBU ETH_DMAC1SR_RBU_Msk /*!< Receive Buffer Unavailable */
#define ETH_DMAC1SR_RPS_Pos (8U)
#define ETH_DMAC1SR_RPS_Msk (0x1U << ETH_DMAC1SR_RPS_Pos) /*!< 0x00000100 */
#define ETH_DMAC1SR_RPS ETH_DMAC1SR_RPS_Msk /*!< Receive Process Stopped */
#define ETH_DMAC1SR_RWT_Pos (9U)
#define ETH_DMAC1SR_RWT_Msk (0x1U << ETH_DMAC1SR_RWT_Pos) /*!< 0x00000200 */
#define ETH_DMAC1SR_RWT ETH_DMAC1SR_RWT_Msk /*!< Receive Watchdog Timeout */
#define ETH_DMAC1SR_ETI_Pos (10U)
#define ETH_DMAC1SR_ETI_Msk (0x1U << ETH_DMAC1SR_ETI_Pos) /*!< 0x00000400 */
#define ETH_DMAC1SR_ETI ETH_DMAC1SR_ETI_Msk /*!< Early Transmit Interrupt */
#define ETH_DMAC1SR_ERI_Pos (11U)
#define ETH_DMAC1SR_ERI_Msk (0x1U << ETH_DMAC1SR_ERI_Pos) /*!< 0x00000800 */
#define ETH_DMAC1SR_ERI ETH_DMAC1SR_ERI_Msk /*!< Early Receive Interrupt */
#define ETH_DMAC1SR_FBE_Pos (12U)
#define ETH_DMAC1SR_FBE_Msk (0x1U << ETH_DMAC1SR_FBE_Pos) /*!< 0x00001000 */
#define ETH_DMAC1SR_FBE ETH_DMAC1SR_FBE_Msk /*!< Fatal Bus Error */
#define ETH_DMAC1SR_CDE_Pos (13U)
#define ETH_DMAC1SR_CDE_Msk (0x1U << ETH_DMAC1SR_CDE_Pos) /*!< 0x00002000 */
#define ETH_DMAC1SR_CDE ETH_DMAC1SR_CDE_Msk /*!< Context Descriptor Error */
#define ETH_DMAC1SR_AIS_Pos (14U)
#define ETH_DMAC1SR_AIS_Msk (0x1U << ETH_DMAC1SR_AIS_Pos) /*!< 0x00004000 */
#define ETH_DMAC1SR_AIS ETH_DMAC1SR_AIS_Msk /*!< Abnormal Interrupt Summary */
#define ETH_DMAC1SR_NIS_Pos (15U)
#define ETH_DMAC1SR_NIS_Msk (0x1U << ETH_DMAC1SR_NIS_Pos) /*!< 0x00008000 */
#define ETH_DMAC1SR_NIS ETH_DMAC1SR_NIS_Msk /*!< Normal Interrupt Summary */
#define ETH_DMAC1SR_TEB_Pos (16U)
#define ETH_DMAC1SR_TEB_Msk (0x7U << ETH_DMAC1SR_TEB_Pos) /*!< 0x00070000 */
#define ETH_DMAC1SR_TEB ETH_DMAC1SR_TEB_Msk /*!< Tx DMA Error Bits */
#define ETH_DMAC1SR_TEB_0 (0x1U << ETH_DMAC1SR_TEB_Pos) /*!< 0x00010000 */
#define ETH_DMAC1SR_TEB_1 (0x2U << ETH_DMAC1SR_TEB_Pos) /*!< 0x00020000 */
#define ETH_DMAC1SR_TEB_2 (0x4U << ETH_DMAC1SR_TEB_Pos) /*!< 0x00040000 */
#define ETH_DMAC1SR_REB_Pos (19U)
#define ETH_DMAC1SR_REB_Msk (0x7U << ETH_DMAC1SR_REB_Pos) /*!< 0x00380000 */
#define ETH_DMAC1SR_REB ETH_DMAC1SR_REB_Msk /*!< Rx DMA Error Bits */
#define ETH_DMAC1SR_REB_0 (0x1U << ETH_DMAC1SR_REB_Pos) /*!< 0x00080000 */
#define ETH_DMAC1SR_REB_1 (0x2U << ETH_DMAC1SR_REB_Pos) /*!< 0x00100000 */
#define ETH_DMAC1SR_REB_2 (0x4U << ETH_DMAC1SR_REB_Pos) /*!< 0x00200000 */
/************* Bit definition for ETH_DMAC1MFCR register *************/
#define ETH_DMAC1MFCR_MFC_Pos (0U)
#define ETH_DMAC1MFCR_MFC_Msk (0x7FFU << ETH_DMAC1MFCR_MFC_Pos) /*!< 0x000007FF */
#define ETH_DMAC1MFCR_MFC ETH_DMAC1MFCR_MFC_Msk /*!< Dropped Packet Counters */
#define ETH_DMAC1MFCR_MFC_0 (0x1U << ETH_DMAC1MFCR_MFC_Pos) /*!< 0x00000001 */
#define ETH_DMAC1MFCR_MFC_1 (0x2U << ETH_DMAC1MFCR_MFC_Pos) /*!< 0x00000002 */
#define ETH_DMAC1MFCR_MFC_2 (0x4U << ETH_DMAC1MFCR_MFC_Pos) /*!< 0x00000004 */
#define ETH_DMAC1MFCR_MFC_3 (0x8U << ETH_DMAC1MFCR_MFC_Pos) /*!< 0x00000008 */
#define ETH_DMAC1MFCR_MFC_4 (0x10U << ETH_DMAC1MFCR_MFC_Pos) /*!< 0x00000010 */
#define ETH_DMAC1MFCR_MFC_5 (0x20U << ETH_DMAC1MFCR_MFC_Pos) /*!< 0x00000020 */
#define ETH_DMAC1MFCR_MFC_6 (0x40U << ETH_DMAC1MFCR_MFC_Pos) /*!< 0x00000040 */
#define ETH_DMAC1MFCR_MFC_7 (0x80U << ETH_DMAC1MFCR_MFC_Pos) /*!< 0x00000080 */
#define ETH_DMAC1MFCR_MFC_8 (0x100U << ETH_DMAC1MFCR_MFC_Pos) /*!< 0x00000100 */
#define ETH_DMAC1MFCR_MFC_9 (0x200U << ETH_DMAC1MFCR_MFC_Pos) /*!< 0x00000200 */
#define ETH_DMAC1MFCR_MFC_10 (0x400U << ETH_DMAC1MFCR_MFC_Pos) /*!< 0x00000400 */
#define ETH_DMAC1MFCR_MFCO_Pos (15U)
#define ETH_DMAC1MFCR_MFCO_Msk (0x1U << ETH_DMAC1MFCR_MFCO_Pos) /*!< 0x00008000 */
#define ETH_DMAC1MFCR_MFCO ETH_DMAC1MFCR_MFCO_Msk /*!< Overflow status of the MFC Counter */
/******************************************************************************/
/* */
/* DMA Controller */
/* */
/******************************************************************************/
/******************** Bits definition for DMA_SxCR register *****************/
#define DMA_SxCR_MBURST_Pos (23U)
#define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
#define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
#define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
#define DMA_SxCR_PBURST_Pos (21U)
#define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
#define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
#define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
#define DMA_SxCR_ACK_Pos (20U)
#define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
#define DMA_SxCR_CT_Pos (19U)
#define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
#define DMA_SxCR_CT DMA_SxCR_CT_Msk
#define DMA_SxCR_DBM_Pos (18U)
#define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
#define DMA_SxCR_PL_Pos (16U)
#define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
#define DMA_SxCR_PL DMA_SxCR_PL_Msk
#define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
#define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
#define DMA_SxCR_PINCOS_Pos (15U)
#define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
#define DMA_SxCR_MSIZE_Pos (13U)
#define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
#define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
#define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
#define DMA_SxCR_PSIZE_Pos (11U)
#define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
#define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
#define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
#define DMA_SxCR_MINC_Pos (10U)
#define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
#define DMA_SxCR_PINC_Pos (9U)
#define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
#define DMA_SxCR_CIRC_Pos (8U)
#define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
#define DMA_SxCR_DIR_Pos (6U)
#define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
#define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
#define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
#define DMA_SxCR_PFCTRL_Pos (5U)
#define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
#define DMA_SxCR_TCIE_Pos (4U)
#define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
#define DMA_SxCR_HTIE_Pos (3U)
#define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
#define DMA_SxCR_TEIE_Pos (2U)
#define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
#define DMA_SxCR_DMEIE_Pos (1U)
#define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
#define DMA_SxCR_EN_Pos (0U)
#define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
#define DMA_SxCR_EN DMA_SxCR_EN_Msk
/******************** Bits definition for DMA_SxCNDTR register **************/
#define DMA_SxNDT_Pos (0U)
#define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
#define DMA_SxNDT DMA_SxNDT_Msk
#define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
#define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
#define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
#define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
#define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
#define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
#define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
#define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
#define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
#define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
#define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
#define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
#define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
#define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
#define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
#define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
/******************** Bits definition for DMA_SxFCR register ****************/
#define DMA_SxFCR_FEIE_Pos (7U)
#define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
#define DMA_SxFCR_FS_Pos (3U)
#define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
#define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
#define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
#define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
#define DMA_SxFCR_DMDIS_Pos (2U)
#define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
#define DMA_SxFCR_FTH_Pos (0U)
#define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
#define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
#define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
/****************** Bit definition for DMA_CPAR register ********************/
#define DMA_SxPAR_PA_Pos (0U)
#define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
/****************** Bit definition for DMA_CMAR register ********************/
#define DMA_SxM0AR_M0A_Pos (0U)
#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
#define DMA_SxM1AR_M1A_Pos (0U)
#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
/******************** Bits definition for DMA_LISR register *****************/
#define DMA_LISR_TCIF3_Pos (27U)
#define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
#define DMA_LISR_HTIF3_Pos (26U)
#define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
#define DMA_LISR_TEIF3_Pos (25U)
#define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
#define DMA_LISR_DMEIF3_Pos (24U)
#define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
#define DMA_LISR_FEIF3_Pos (22U)
#define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
#define DMA_LISR_TCIF2_Pos (21U)
#define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
#define DMA_LISR_HTIF2_Pos (20U)
#define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
#define DMA_LISR_TEIF2_Pos (19U)
#define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
#define DMA_LISR_DMEIF2_Pos (18U)
#define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
#define DMA_LISR_FEIF2_Pos (16U)
#define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
#define DMA_LISR_TCIF1_Pos (11U)
#define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
#define DMA_LISR_HTIF1_Pos (10U)
#define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
#define DMA_LISR_TEIF1_Pos (9U)
#define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
#define DMA_LISR_DMEIF1_Pos (8U)
#define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
#define DMA_LISR_FEIF1_Pos (6U)
#define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
#define DMA_LISR_TCIF0_Pos (5U)
#define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
#define DMA_LISR_HTIF0_Pos (4U)
#define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
#define DMA_LISR_TEIF0_Pos (3U)
#define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
#define DMA_LISR_DMEIF0_Pos (2U)
#define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
#define DMA_LISR_FEIF0_Pos (0U)
#define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
/******************** Bits definition for DMA_HISR register *****************/
#define DMA_HISR_TCIF7_Pos (27U)
#define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
#define DMA_HISR_HTIF7_Pos (26U)
#define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
#define DMA_HISR_TEIF7_Pos (25U)
#define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
#define DMA_HISR_DMEIF7_Pos (24U)
#define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
#define DMA_HISR_FEIF7_Pos (22U)
#define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
#define DMA_HISR_TCIF6_Pos (21U)
#define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
#define DMA_HISR_HTIF6_Pos (20U)
#define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
#define DMA_HISR_TEIF6_Pos (19U)
#define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
#define DMA_HISR_DMEIF6_Pos (18U)
#define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
#define DMA_HISR_FEIF6_Pos (16U)
#define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
#define DMA_HISR_TCIF5_Pos (11U)
#define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
#define DMA_HISR_HTIF5_Pos (10U)
#define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
#define DMA_HISR_TEIF5_Pos (9U)
#define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
#define DMA_HISR_DMEIF5_Pos (8U)
#define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
#define DMA_HISR_FEIF5_Pos (6U)
#define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
#define DMA_HISR_TCIF4_Pos (5U)
#define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
#define DMA_HISR_HTIF4_Pos (4U)
#define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
#define DMA_HISR_TEIF4_Pos (3U)
#define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
#define DMA_HISR_DMEIF4_Pos (2U)
#define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
#define DMA_HISR_FEIF4_Pos (0U)
#define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
/******************** Bits definition for DMA_LIFCR register ****************/
#define DMA_LIFCR_CTCIF3_Pos (27U)
#define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
#define DMA_LIFCR_CHTIF3_Pos (26U)
#define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
#define DMA_LIFCR_CTEIF3_Pos (25U)
#define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
#define DMA_LIFCR_CDMEIF3_Pos (24U)
#define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
#define DMA_LIFCR_CFEIF3_Pos (22U)
#define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
#define DMA_LIFCR_CTCIF2_Pos (21U)
#define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
#define DMA_LIFCR_CHTIF2_Pos (20U)
#define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
#define DMA_LIFCR_CTEIF2_Pos (19U)
#define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
#define DMA_LIFCR_CDMEIF2_Pos (18U)
#define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
#define DMA_LIFCR_CFEIF2_Pos (16U)
#define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
#define DMA_LIFCR_CTCIF1_Pos (11U)
#define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
#define DMA_LIFCR_CHTIF1_Pos (10U)
#define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
#define DMA_LIFCR_CTEIF1_Pos (9U)
#define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
#define DMA_LIFCR_CDMEIF1_Pos (8U)
#define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
#define DMA_LIFCR_CFEIF1_Pos (6U)
#define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
#define DMA_LIFCR_CTCIF0_Pos (5U)
#define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
#define DMA_LIFCR_CHTIF0_Pos (4U)
#define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
#define DMA_LIFCR_CTEIF0_Pos (3U)
#define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
#define DMA_LIFCR_CDMEIF0_Pos (2U)
#define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
#define DMA_LIFCR_CFEIF0_Pos (0U)
#define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
/******************** Bits definition for DMA_HIFCR register ****************/
#define DMA_HIFCR_CTCIF7_Pos (27U)
#define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
#define DMA_HIFCR_CHTIF7_Pos (26U)
#define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
#define DMA_HIFCR_CTEIF7_Pos (25U)
#define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
#define DMA_HIFCR_CDMEIF7_Pos (24U)
#define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
#define DMA_HIFCR_CFEIF7_Pos (22U)
#define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
#define DMA_HIFCR_CTCIF6_Pos (21U)
#define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
#define DMA_HIFCR_CHTIF6_Pos (20U)
#define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
#define DMA_HIFCR_CTEIF6_Pos (19U)
#define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
#define DMA_HIFCR_CDMEIF6_Pos (18U)
#define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
#define DMA_HIFCR_CFEIF6_Pos (16U)
#define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
#define DMA_HIFCR_CTCIF5_Pos (11U)
#define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
#define DMA_HIFCR_CHTIF5_Pos (10U)
#define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
#define DMA_HIFCR_CTEIF5_Pos (9U)
#define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
#define DMA_HIFCR_CDMEIF5_Pos (8U)
#define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
#define DMA_HIFCR_CFEIF5_Pos (6U)
#define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
#define DMA_HIFCR_CTCIF4_Pos (5U)
#define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
#define DMA_HIFCR_CHTIF4_Pos (4U)
#define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
#define DMA_HIFCR_CTEIF4_Pos (3U)
#define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
#define DMA_HIFCR_CDMEIF4_Pos (2U)
#define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
#define DMA_HIFCR_CFEIF4_Pos (0U)
#define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
/********************** Bit definition for DMA_HWCFGR2 register ***************/
#define DMA_HWCFGR2_FIFO_SIZE_Pos (0U)
#define DMA_HWCFGR2_FIFO_SIZE_Msk (0x3U << DMA_HWCFGR2_FIFO_SIZE_Pos) /*!< 0x00000003 */
#define DMA_HWCFGR2_FIFO_SIZE DMA_HWCFGR2_FIFO_SIZE_Msk /*!< FIFO size, common to all streams*/
#define DMA_HWCFGR2_WRITE_BUFFERABLE_Pos (4U)
#define DMA_HWCFGR2_WRITE_BUFFERABLE_Msk (0x1U << DMA_HWCFGR2_WRITE_BUFFERABLE_Pos) /*!< 0x00000010 */
#define DMA_HWCFGR2_WRITE_BUFFERABLE DMA_HWCFGR2_WRITE_BUFFERABLE_Msk /*!< Write bufferable*/
#define DMA_HWCFGR2_CHSEL_WIDTH_Pos (8U)
#define DMA_HWCFGR2_CHSEL_WIDTH_Msk (0x7U << DMA_HWCFGR2_CHSEL_WIDTH_Pos) /*!< 0x00000700 */
#define DMA_HWCFGR2_CHSEL_WIDTH DMA_HWCFGR2_CHSEL_WIDTH_Msk /*!< width of the CHSEL field */
/********************** Bit definition for DMA_HWCFGR1 register ***************/
#define DMA_HWCFGR1_DMA_DEF0_Pos (0U)
#define DMA_HWCFGR1_DMA_DEF0_Msk (0x3U << DMA_HWCFGR1_DMA_DEF0_Pos) /*!< 0x00000003 */
#define DMA_HWCFGR1_DMA_DEF0 DMA_HWCFGR1_DMA_DEF0_Msk /*!< Type of the stream 0 */
#define DMA_HWCFGR1_DMA_DEF1_Pos (4U)
#define DMA_HWCFGR1_DMA_DEF1_Msk (0x3U << DMA_HWCFGR1_DMA_DEF1_Pos) /*!< 0x00000030 */
#define DMA_HWCFGR1_DMA_DEF1 DMA_HWCFGR1_DMA_DEF1_Msk /*!< Type of the stream 1 */
#define DMA_HWCFGR1_DMA_DEF2_Pos (8U)
#define DMA_HWCFGR1_DMA_DEF2_Msk (0x3U << DMA_HWCFGR1_DMA_DEF2_Pos) /*!< 0x00000300 */
#define DMA_HWCFGR1_DMA_DEF2 DMA_HWCFGR1_DMA_DEF2_Msk /*!< Type of the stream 2 */
#define DMA_HWCFGR1_DMA_DEF3_Pos (12U)
#define DMA_HWCFGR1_DMA_DEF3_Msk (0x3U << DMA_HWCFGR1_DMA_DEF3_Pos) /*!< 0x00003000 */
#define DMA_HWCFGR1_DMA_DEF3 DMA_HWCFGR1_DMA_DEF3_Msk /*!< Type of the stream 3 */
#define DMA_HWCFGR1_DMA_DEF4_Pos (16U)
#define DMA_HWCFGR1_DMA_DEF4_Msk (0x3U << DMA_HWCFGR1_DMA_DEF4_Pos) /*!< 0x00030000 */
#define DMA_HWCFGR1_DMA_DEF4 DMA_HWCFGR1_DMA_DEF4_Msk /*!< Type of the stream 4 */
#define DMA_HWCFGR1_DMA_DEF5_Pos (20U)
#define DMA_HWCFGR1_DMA_DEF5_Msk (0x3U << DMA_HWCFGR1_DMA_DEF5_Pos) /*!< 0x00300000 */
#define DMA_HWCFGR1_DMA_DEF5 DMA_HWCFGR1_DMA_DEF5_Msk /*!< Type of the stream 5 */
#define DMA_HWCFGR1_DMA_DEF6_Pos (24U)
#define DMA_HWCFGR1_DMA_DEF6_Msk (0x3U << DMA_HWCFGR1_DMA_DEF6_Pos) /*!< 0x03000000 */
#define DMA_HWCFGR1_DMA_DEF6 DMA_HWCFGR1_DMA_DEF6_Msk /*!< Type of the stream 6 */
#define DMA_HWCFGR1_DMA_DEF7_Pos (28U)
#define DMA_HWCFGR1_DMA_DEF7_Msk (0x3U << DMA_HWCFGR1_DMA_DEF7_Pos) /*!< 0x30000000 */
#define DMA_HWCFGR1_DMA_DEF7 DMA_HWCFGR1_DMA_DEF7_Msk /*!< Type of the stream 7 */
/********************** Bit definition for DMA_VERR register *****************/
#define DMA_VERR_MINREV_Pos (0U)
#define DMA_VERR_MINREV_Msk (0xFU << DMA_VERR_MINREV_Pos) /*!< 0x0000000F */
#define DMA_VERR_MINREV DMA_VERR_MINREV_Msk /*!< Minor Revision number */
#define DMA_VERR_MAJREV_Pos (4U)
#define DMA_VERR_MAJREV_Msk (0xFU << DMA_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define DMA_VERR_MAJREV DMA_VERR_MAJREV_Msk /*!< Major Revision number */
/********************** Bit definition for DMA_IPIDR register ****************/
#define DMA_IPIDR_ID_Pos (0U)
#define DMA_IPIDR_ID_Msk (0xFFFFFFFFU << DMA_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
#define DMA_IPIDR_ID DMA_IPIDR_ID_Msk /*!< IP Identification */
/********************** Bit definition for DMA_SIDR register *****************/
#define DMA_SIDR_SID_Pos (0U)
#define DMA_SIDR_SID_Msk (0xFFFFFFFFU << DMA_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define DMA_SIDR_SID DMA_SIDR_SID_Msk /*!< IP size identification */
/******************************************************************************/
/* */
/* DMAMUX Controller */
/* */
/******************************************************************************/
/******************** Bits definition for DMAMUX_CxCR register **************/
#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFU << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */
#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
#define DMAMUX_CxCR_SOIE_Pos (8U)
#define DMAMUX_CxCR_SOIE_Msk (0x1U << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk
#define DMAMUX_CxCR_EGE_Pos (9U)
#define DMAMUX_CxCR_EGE_Msk (0x1U << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */
#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk
#define DMAMUX_CxCR_SE_Pos (16U)
#define DMAMUX_CxCR_SE_Msk (0x1U << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */
#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk
#define DMAMUX_CxCR_SPOL_Pos (17U)
#define DMAMUX_CxCR_SPOL_Msk (0x3U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk
#define DMAMUX_CxCR_SPOL_0 (0x1U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */
#define DMAMUX_CxCR_SPOL_1 (0x2U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */
#define DMAMUX_CxCR_NBREQ_Pos (19U)
#define DMAMUX_CxCR_NBREQ_Msk (0x1FU << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk
#define DMAMUX_CxCR_NBREQ_0 (0x01U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
#define DMAMUX_CxCR_NBREQ_1 (0x02U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
#define DMAMUX_CxCR_NBREQ_2 (0x04U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
#define DMAMUX_CxCR_NBREQ_3 (0x08U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
#define DMAMUX_CxCR_NBREQ_4 (0x10U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FU << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk
#define DMAMUX_CxCR_SYNC_ID_0 (0x01U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
#define DMAMUX_CxCR_SYNC_ID_1 (0x02U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
#define DMAMUX_CxCR_SYNC_ID_2 (0x04U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
#define DMAMUX_CxCR_SYNC_ID_3 (0x08U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
#define DMAMUX_CxCR_SYNC_ID_4 (0x10U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
/******************** Bits definition for DMAMUX_CSR register **************/
#define DMAMUX_CSR_SOF0_Pos (0U)
#define DMAMUX_CSR_SOF0_Msk (0x1U << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */
#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk
#define DMAMUX_CSR_SOF1_Pos (1U)
#define DMAMUX_CSR_SOF1_Msk (0x1U << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */
#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk
#define DMAMUX_CSR_SOF2_Pos (2U)
#define DMAMUX_CSR_SOF2_Msk (0x1U << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */
#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk
#define DMAMUX_CSR_SOF3_Pos (3U)
#define DMAMUX_CSR_SOF3_Msk (0x1U << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */
#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk
#define DMAMUX_CSR_SOF4_Pos (4U)
#define DMAMUX_CSR_SOF4_Msk (0x1U << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */
#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk
#define DMAMUX_CSR_SOF5_Pos (5U)
#define DMAMUX_CSR_SOF5_Msk (0x1U << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */
#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk
#define DMAMUX_CSR_SOF6_Pos (6U)
#define DMAMUX_CSR_SOF6_Msk (0x1U << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */
#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk
#define DMAMUX_CSR_SOF7_Pos (7U)
#define DMAMUX_CSR_SOF7_Msk (0x1U << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */
#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk
#define DMAMUX_CSR_SOF8_Pos (8U)
#define DMAMUX_CSR_SOF8_Msk (0x1U << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */
#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk
#define DMAMUX_CSR_SOF9_Pos (9U)
#define DMAMUX_CSR_SOF9_Msk (0x1U << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */
#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk
#define DMAMUX_CSR_SOF10_Pos (10U)
#define DMAMUX_CSR_SOF10_Msk (0x1U << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */
#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk
#define DMAMUX_CSR_SOF11_Pos (11U)
#define DMAMUX_CSR_SOF11_Msk (0x1U << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */
#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk
#define DMAMUX_CSR_SOF12_Pos (12U)
#define DMAMUX_CSR_SOF12_Msk (0x1U << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */
#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk
#define DMAMUX_CSR_SOF13_Pos (13U)
#define DMAMUX_CSR_SOF13_Msk (0x1U << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */
#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk
#define DMAMUX_CSR_SOF14_Pos (14U)
#define DMAMUX_CSR_SOF14_Msk (0x1U << DMAMUX_CSR_SOF14_Pos) /*!< 0x00004000 */
#define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk
#define DMAMUX_CSR_SOF15_Pos (15U)
#define DMAMUX_CSR_SOF15_Msk (0x1U << DMAMUX_CSR_SOF15_Pos) /*!< 0x00008000 */
#define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk
/******************** Bits definition for DMAMUX_CFR register **************/
#define DMAMUX_CFR_CSOF0_Pos (0U)
#define DMAMUX_CFR_CSOF0_Msk (0x1U << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk
#define DMAMUX_CFR_CSOF1_Pos (1U)
#define DMAMUX_CFR_CSOF1_Msk (0x1U << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk
#define DMAMUX_CFR_CSOF2_Pos (2U)
#define DMAMUX_CFR_CSOF2_Msk (0x1U << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk
#define DMAMUX_CFR_CSOF3_Pos (3U)
#define DMAMUX_CFR_CSOF3_Msk (0x1U << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk
#define DMAMUX_CFR_CSOF4_Pos (4U)
#define DMAMUX_CFR_CSOF4_Msk (0x1U << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk
#define DMAMUX_CFR_CSOF5_Pos (5U)
#define DMAMUX_CFR_CSOF5_Msk (0x1U << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk
#define DMAMUX_CFR_CSOF6_Pos (6U)
#define DMAMUX_CFR_CSOF6_Msk (0x1U << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk
#define DMAMUX_CFR_CSOF7_Pos (7U)
#define DMAMUX_CFR_CSOF7_Msk (0x1U << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */
#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk
#define DMAMUX_CFR_CSOF8_Pos (8U)
#define DMAMUX_CFR_CSOF8_Msk (0x1U << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */
#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk
#define DMAMUX_CFR_CSOF9_Pos (9U)
#define DMAMUX_CFR_CSOF9_Msk (0x1U << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */
#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk
#define DMAMUX_CFR_CSOF10_Pos (10U)
#define DMAMUX_CFR_CSOF10_Msk (0x1U << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */
#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk
#define DMAMUX_CFR_CSOF11_Pos (11U)
#define DMAMUX_CFR_CSOF11_Msk (0x1U << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */
#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk
#define DMAMUX_CFR_CSOF12_Pos (12U)
#define DMAMUX_CFR_CSOF12_Msk (0x1U << DMAMUX_CFR_CSOF12_Pos) /*!< 0x00001000 */
#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk
#define DMAMUX_CFR_CSOF13_Pos (13U)
#define DMAMUX_CFR_CSOF13_Msk (0x1U << DMAMUX_CFR_CSOF13_Pos) /*!< 0x00002000 */
#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk
#define DMAMUX_CFR_CSOF14_Pos (14U)
#define DMAMUX_CFR_CSOF14_Msk (0x1U << DMAMUX_CFR_CSOF14_Pos) /*!< 0x00004000 */
#define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk
#define DMAMUX_CFR_CSOF15_Pos (15U)
#define DMAMUX_CFR_CSOF15_Msk (0x1U << DMAMUX_CFR_CSOF15_Pos) /*!< 0x00008000 */
#define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk
/******************** Bits definition for DMAMUX_RGxCR register ************/
#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FU << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk
#define DMAMUX_RGxCR_SIG_ID_0 (0x01U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
#define DMAMUX_RGxCR_SIG_ID_1 (0x02U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
#define DMAMUX_RGxCR_SIG_ID_2 (0x04U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
#define DMAMUX_RGxCR_SIG_ID_3 (0x08U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
#define DMAMUX_RGxCR_SIG_ID_4 (0x10U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
#define DMAMUX_RGxCR_OIE_Pos (8U)
#define DMAMUX_RGxCR_OIE_Msk (0x1U << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk
#define DMAMUX_RGxCR_GE_Pos (16U)
#define DMAMUX_RGxCR_GE_Msk (0x1U << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */
#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk
#define DMAMUX_RGxCR_GPOL_Pos (17U)
#define DMAMUX_RGxCR_GPOL_Msk (0x3U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk
#define DMAMUX_RGxCR_GPOL_0 (0x1U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
#define DMAMUX_RGxCR_GPOL_1 (0x2U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FU << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of DMA requests to be generated */
#define DMAMUX_RGxCR_GNBREQ_0 (0x01U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
#define DMAMUX_RGxCR_GNBREQ_1 (0x02U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */
#define DMAMUX_RGxCR_GNBREQ_2 (0x04U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */
#define DMAMUX_RGxCR_GNBREQ_3 (0x08U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */
#define DMAMUX_RGxCR_GNBREQ_4 (0x10U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */
/******************** Bits definition for DMAMUX_RGSR register **************/
#define DMAMUX_RGSR_OF0_Pos (0U)
#define DMAMUX_RGSR_OF0_Msk (0x1U << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */
#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk
#define DMAMUX_RGSR_OF1_Pos (1U)
#define DMAMUX_RGSR_OF1_Msk (0x1U << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */
#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk
#define DMAMUX_RGSR_OF2_Pos (2U)
#define DMAMUX_RGSR_OF2_Msk (0x1U << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */
#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk
#define DMAMUX_RGSR_OF3_Pos (3U)
#define DMAMUX_RGSR_OF3_Msk (0x1U << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */
#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk
#define DMAMUX_RGSR_OF4_Pos (4U)
#define DMAMUX_RGSR_OF4_Msk (0x1U << DMAMUX_RGSR_OF4_Pos) /*!< 0x00000010 */
#define DMAMUX_RGSR_OF4 DMAMUX_RGSR_OF4_Msk
#define DMAMUX_RGSR_OF5_Pos (5U)
#define DMAMUX_RGSR_OF5_Msk (0x1U << DMAMUX_RGSR_OF5_Pos) /*!< 0x00000020 */
#define DMAMUX_RGSR_OF5 DMAMUX_RGSR_OF5_Msk
#define DMAMUX_RGSR_OF6_Pos (6U)
#define DMAMUX_RGSR_OF6_Msk (0x1U << DMAMUX_RGSR_OF6_Pos) /*!< 0x00000040 */
#define DMAMUX_RGSR_OF6 DMAMUX_RGSR_OF6_Msk
#define DMAMUX_RGSR_OF7_Pos (7U)
#define DMAMUX_RGSR_OF7_Msk (0x1U << DMAMUX_RGSR_OF7_Pos) /*!< 0x00000080 */
#define DMAMUX_RGSR_OF7 DMAMUX_RGSR_OF7_Msk
/******************** Bits definition for DMAMUX_RGCFR register **************/
#define DMAMUX_RGCFR_COF0_Pos (0U)
#define DMAMUX_RGCFR_COF0_Msk (0x1U << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk
#define DMAMUX_RGCFR_COF1_Pos (1U)
#define DMAMUX_RGCFR_COF1_Msk (0x1U << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk
#define DMAMUX_RGCFR_COF2_Pos (2U)
#define DMAMUX_RGCFR_COF2_Msk (0x1U << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk
#define DMAMUX_RGCFR_COF3_Pos (3U)
#define DMAMUX_RGCFR_COF3_Msk (0x1U << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk
#define DMAMUX_RGCFR_COF4_Pos (4U)
#define DMAMUX_RGCFR_COF4_Msk (0x1U << DMAMUX_RGCFR_COF4_Pos) /*!< 0x00000010 */
#define DMAMUX_RGCFR_COF4 DMAMUX_RGCFR_COF4_Msk
#define DMAMUX_RGCFR_COF5_Pos (5U)
#define DMAMUX_RGCFR_COF5_Msk (0x1U << DMAMUX_RGCFR_COF5_Pos) /*!< 0x00000020 */
#define DMAMUX_RGCFR_COF5 DMAMUX_RGCFR_COF5_Msk
#define DMAMUX_RGCFR_COF6_Pos (6U)
#define DMAMUX_RGCFR_COF6_Msk (0x1U << DMAMUX_RGCFR_COF6_Pos) /*!< 0x00000040 */
#define DMAMUX_RGCFR_COF6 DMAMUX_RGCFR_COF6_Msk
#define DMAMUX_RGCFR_COF7_Pos (7U)
#define DMAMUX_RGCFR_COF7_Msk (0x1U << DMAMUX_RGCFR_COF7_Pos) /*!< 0x00000080 */
#define DMAMUX_RGCFR_COF7 DMAMUX_RGCFR_COF7_Msk
/********************** Bit definition for DMAMUX_VERR register *****************/
#define DMAMUX_VERR_MINREV_Pos (0U)
#define DMAMUX_VERR_MINREV_Msk (0xFU << DMAMUX_VERR_MINREV_Pos) /*!< 0x0000000F */
#define DMAMUX_VERR_MINREV DMAMUX_VERR_MINREV_Msk /*!< Minor Revision number */
#define DMAMUX_VERR_MAJREV_Pos (4U)
#define DMAMUX_VERR_MAJREV_Msk (0xFU << DMAMUX_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define DMAMUX_VERR_MAJREV DMAMUX_VERR_MAJREV_Msk /*!< Major Revision number */
/********************** Bit definition for DMAMUX_IPIDR register ****************/
#define DMAMUX_IPIDR_IPID_Pos (0U)
#define DMAMUX_IPIDR_IPID_Msk (0xFFFFFFFFU << DMAMUX_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
#define DMAMUX_IPIDR_IPID DMAMUX_IPIDR_IPID_Msk /*!< IP Identification */
/********************** Bit definition for DMAMUX_SIDR register *****************/
#define DMAMUX_SIDR_SID_Pos (0U)
#define DMAMUX_SIDR_SID_Msk (0xFFFFFFFFU << DMAMUX_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define DMAMUX_SIDR_SID DMAMUX_SIDR_SID_Msk /*!< IP size identification */
/******************************************************************************/
/* */
/* Display Serial Interface (DSI) */
/* */
/******************************************************************************/
/******************* Bit definition for DSI_VR register *****************/
#define DSI_VR ((uint32_t)0x3133312AU) /*!< DSI Host Version */
/******************* Bit definition for DSI_CR register *****************/
#define DSI_CR_EN ((uint32_t)0x00000001U) /*!< DSI Host power up and reset */
/******************* Bit definition for DSI_CCR register ****************/
#define DSI_CCR_TXECKDIV ((uint32_t)0x000000FFU) /*!< TX Escape Clock Division */
#define DSI_CCR_TXECKDIV0 ((uint32_t)0x00000001U)
#define DSI_CCR_TXECKDIV1 ((uint32_t)0x00000002U)
#define DSI_CCR_TXECKDIV2 ((uint32_t)0x00000004U)
#define DSI_CCR_TXECKDIV3 ((uint32_t)0x00000008U)
#define DSI_CCR_TXECKDIV4 ((uint32_t)0x00000010U)
#define DSI_CCR_TXECKDIV5 ((uint32_t)0x00000020U)
#define DSI_CCR_TXECKDIV6 ((uint32_t)0x00000040U)
#define DSI_CCR_TXECKDIV7 ((uint32_t)0x00000080U)
#define DSI_CCR_TOCKDIV ((uint32_t)0x0000FF00U) /*!< Timeout Clock Division */
#define DSI_CCR_TOCKDIV0 ((uint32_t)0x00000100U)
#define DSI_CCR_TOCKDIV1 ((uint32_t)0x00000200U)
#define DSI_CCR_TOCKDIV2 ((uint32_t)0x00000400U)
#define DSI_CCR_TOCKDIV3 ((uint32_t)0x00000800U)
#define DSI_CCR_TOCKDIV4 ((uint32_t)0x00001000U)
#define DSI_CCR_TOCKDIV5 ((uint32_t)0x00002000U)
#define DSI_CCR_TOCKDIV6 ((uint32_t)0x00004000U)
#define DSI_CCR_TOCKDIV7 ((uint32_t)0x00008000U)
/******************* Bit definition for DSI_LVCIDR register *************/
#define DSI_LVCIDR_VCID ((uint32_t)0x00000003U) /*!< Virtual Channel ID */
#define DSI_LVCIDR_VCID0 ((uint32_t)0x00000001U)
#define DSI_LVCIDR_VCID1 ((uint32_t)0x00000002U)
/******************* Bit definition for DSI_LCOLCR register *************/
#define DSI_LCOLCR_COLC ((uint32_t)0x0000000FU) /*!< Color Coding */
#define DSI_LCOLCR_COLC0 ((uint32_t)0x00000001U)
#define DSI_LCOLCR_COLC1 ((uint32_t)0x00000002U)
#define DSI_LCOLCR_COLC2 ((uint32_t)0x00000004U)
#define DSI_LCOLCR_COLC3 ((uint32_t)0x00000008U)
#define DSI_LCOLCR_LPE ((uint32_t)0x00000100U) /*!< Loosly Packet Enable */
/******************* Bit definition for DSI_LPCR register ***************/
#define DSI_LPCR_DEP ((uint32_t)0x00000001U) /*!< Data Enable Polarity */
#define DSI_LPCR_VSP ((uint32_t)0x00000002U) /*!< VSYNC Polarity */
#define DSI_LPCR_HSP ((uint32_t)0x00000004U) /*!< HSYNC Polarity */
/******************* Bit definition for DSI_LPMCR register **************/
#define DSI_LPMCR_VLPSIZE ((uint32_t)0x000000FFU) /*!< VACT Largest Packet Size */
#define DSI_LPMCR_VLPSIZE0 ((uint32_t)0x00000001U)
#define DSI_LPMCR_VLPSIZE1 ((uint32_t)0x00000002U)
#define DSI_LPMCR_VLPSIZE2 ((uint32_t)0x00000004U)
#define DSI_LPMCR_VLPSIZE3 ((uint32_t)0x00000008U)
#define DSI_LPMCR_VLPSIZE4 ((uint32_t)0x00000010U)
#define DSI_LPMCR_VLPSIZE5 ((uint32_t)0x00000020U)
#define DSI_LPMCR_VLPSIZE6 ((uint32_t)0x00000040U)
#define DSI_LPMCR_VLPSIZE7 ((uint32_t)0x00000080U)
#define DSI_LPMCR_LPSIZE ((uint32_t)0x00FF0000U) /*!< Largest Packet Size */
#define DSI_LPMCR_LPSIZE0 ((uint32_t)0x00010000U)
#define DSI_LPMCR_LPSIZE1 ((uint32_t)0x00020000U)
#define DSI_LPMCR_LPSIZE2 ((uint32_t)0x00040000U)
#define DSI_LPMCR_LPSIZE3 ((uint32_t)0x00080000U)
#define DSI_LPMCR_LPSIZE4 ((uint32_t)0x00100000U)
#define DSI_LPMCR_LPSIZE5 ((uint32_t)0x00200000U)
#define DSI_LPMCR_LPSIZE6 ((uint32_t)0x00400000U)
#define DSI_LPMCR_LPSIZE7 ((uint32_t)0x00800000U)
/******************* Bit definition for DSI_PCR register ****************/
#define DSI_PCR_ETTXE ((uint32_t)0x00000001U) /*!< EoTp Transmission Enable */
#define DSI_PCR_ETRXE ((uint32_t)0x00000002U) /*!< EoTp Reception Enable */
#define DSI_PCR_BTAE ((uint32_t)0x00000004U) /*!< Bus Turn Around Enable */
#define DSI_PCR_ECCRXE ((uint32_t)0x00000008U) /*!< ECC Reception Enable */
#define DSI_PCR_CRCRXE ((uint32_t)0x00000010U) /*!< CRC Reception Enable */
/******************* Bit definition for DSI_GVCIDR register *************/
#define DSI_GVCIDR_VCID ((uint32_t)0x00000003U) /*!< Virtual Channel ID */
#define DSI_GVCIDR_VCID0 ((uint32_t)0x00000001U)
#define DSI_GVCIDR_VCID1 ((uint32_t)0x00000002U)
/******************* Bit definition for DSI_MCR register ****************/
#define DSI_MCR_CMDM ((uint32_t)0x00000001U) /*!< Command Mode */
/******************* Bit definition for DSI_VMCR register ***************/
#define DSI_VMCR_VMT ((uint32_t)0x00000003U) /*!< Video Mode Type */
#define DSI_VMCR_VMT0 ((uint32_t)0x00000001U)
#define DSI_VMCR_VMT1 ((uint32_t)0x00000002U)
#define DSI_VMCR_LPVSAE ((uint32_t)0x00000100U) /*!< Low-Power Vertical Sync Active Enable */
#define DSI_VMCR_LPVBPE ((uint32_t)0x00000200U) /*!< Low-power Vertical Back-Porch Enable */
#define DSI_VMCR_LPVFPE ((uint32_t)0x00000400U) /*!< Low-power Vertical Front-porch Enable */
#define DSI_VMCR_LPVAE ((uint32_t)0x00000800U) /*!< Low-Power Vertical Active Enable */
#define DSI_VMCR_LPHBPE ((uint32_t)0x00001000U) /*!< Low-Power Horizontal Back-Porch Enable */
#define DSI_VMCR_LPHFPE ((uint32_t)0x00002000U) /*!< Low-Power Horizontal Front-Porch Enable */
#define DSI_VMCR_FBTAAE ((uint32_t)0x00004000U) /*!< Frame Bus-Turn-Around Acknowledge Enable */
#define DSI_VMCR_LPCE ((uint32_t)0x00008000U) /*!< Low-Power Command Enable */
#define DSI_VMCR_PGE ((uint32_t)0x00010000U) /*!< Pattern Generator Enable */
#define DSI_VMCR_PGM ((uint32_t)0x00100000U) /*!< Pattern Generator Mode */
#define DSI_VMCR_PGO ((uint32_t)0x01000000U) /*!< Pattern Generator Orientation */
/******************* Bit definition for DSI_VPCR register ***************/
#define DSI_VPCR_VPSIZE ((uint32_t)0x00003FFFU) /*!< Video Packet Size */
#define DSI_VPCR_VPSIZE0 ((uint32_t)0x00000001U)
#define DSI_VPCR_VPSIZE1 ((uint32_t)0x00000002U)
#define DSI_VPCR_VPSIZE2 ((uint32_t)0x00000004U)
#define DSI_VPCR_VPSIZE3 ((uint32_t)0x00000008U)
#define DSI_VPCR_VPSIZE4 ((uint32_t)0x00000010U)
#define DSI_VPCR_VPSIZE5 ((uint32_t)0x00000020U)
#define DSI_VPCR_VPSIZE6 ((uint32_t)0x00000040U)
#define DSI_VPCR_VPSIZE7 ((uint32_t)0x00000080U)
#define DSI_VPCR_VPSIZE8 ((uint32_t)0x00000100U)
#define DSI_VPCR_VPSIZE9 ((uint32_t)0x00000200U)
#define DSI_VPCR_VPSIZE10 ((uint32_t)0x00000400U)
#define DSI_VPCR_VPSIZE11 ((uint32_t)0x00000800U)
#define DSI_VPCR_VPSIZE12 ((uint32_t)0x00001000U)
#define DSI_VPCR_VPSIZE13 ((uint32_t)0x00002000U)
/******************* Bit definition for DSI_VCCR register ***************/
#define DSI_VCCR_NUMC ((uint32_t)0x00001FFFU) /*!< Number of Chunks */
#define DSI_VCCR_NUMC0 ((uint32_t)0x00000001U)
#define DSI_VCCR_NUMC1 ((uint32_t)0x00000002U)
#define DSI_VCCR_NUMC2 ((uint32_t)0x00000004U)
#define DSI_VCCR_NUMC3 ((uint32_t)0x00000008U)
#define DSI_VCCR_NUMC4 ((uint32_t)0x00000010U)
#define DSI_VCCR_NUMC5 ((uint32_t)0x00000020U)
#define DSI_VCCR_NUMC6 ((uint32_t)0x00000040U)
#define DSI_VCCR_NUMC7 ((uint32_t)0x00000080U)
#define DSI_VCCR_NUMC8 ((uint32_t)0x00000100U)
#define DSI_VCCR_NUMC9 ((uint32_t)0x00000200U)
#define DSI_VCCR_NUMC10 ((uint32_t)0x00000400U)
#define DSI_VCCR_NUMC11 ((uint32_t)0x00000800U)
#define DSI_VCCR_NUMC12 ((uint32_t)0x00001000U)
/******************* Bit definition for DSI_VNPCR register **************/
#define DSI_VNPCR_NPSIZE ((uint32_t)0x00001FFFU) /*!< Null Packet Size */
#define DSI_VNPCR_NPSIZE0 ((uint32_t)0x00000001U)
#define DSI_VNPCR_NPSIZE1 ((uint32_t)0x00000002U)
#define DSI_VNPCR_NPSIZE2 ((uint32_t)0x00000004U)
#define DSI_VNPCR_NPSIZE3 ((uint32_t)0x00000008U)
#define DSI_VNPCR_NPSIZE4 ((uint32_t)0x00000010U)
#define DSI_VNPCR_NPSIZE5 ((uint32_t)0x00000020U)
#define DSI_VNPCR_NPSIZE6 ((uint32_t)0x00000040U)
#define DSI_VNPCR_NPSIZE7 ((uint32_t)0x00000080U)
#define DSI_VNPCR_NPSIZE8 ((uint32_t)0x00000100U)
#define DSI_VNPCR_NPSIZE9 ((uint32_t)0x00000200U)
#define DSI_VNPCR_NPSIZE10 ((uint32_t)0x00000400U)
#define DSI_VNPCR_NPSIZE11 ((uint32_t)0x00000800U)
#define DSI_VNPCR_NPSIZE12 ((uint32_t)0x00001000U)
/******************* Bit definition for DSI_VHSACR register *************/
#define DSI_VHSACR_HSA ((uint32_t)0x00000FFFU) /*!< Horizontal Synchronism Active duration */
#define DSI_VHSACR_HSA0 ((uint32_t)0x00000001U)
#define DSI_VHSACR_HSA1 ((uint32_t)0x00000002U)
#define DSI_VHSACR_HSA2 ((uint32_t)0x00000004U)
#define DSI_VHSACR_HSA3 ((uint32_t)0x00000008U)
#define DSI_VHSACR_HSA4 ((uint32_t)0x00000010U)
#define DSI_VHSACR_HSA5 ((uint32_t)0x00000020U)
#define DSI_VHSACR_HSA6 ((uint32_t)0x00000040U)
#define DSI_VHSACR_HSA7 ((uint32_t)0x00000080U)
#define DSI_VHSACR_HSA8 ((uint32_t)0x00000100U)
#define DSI_VHSACR_HSA9 ((uint32_t)0x00000200U)
#define DSI_VHSACR_HSA10 ((uint32_t)0x00000400U)
#define DSI_VHSACR_HSA11 ((uint32_t)0x00000800U)
/******************* Bit definition for DSI_VHBPCR register *************/
#define DSI_VHBPCR_HBP ((uint32_t)0x00000FFFU) /*!< Horizontal Back-Porch duration */
#define DSI_VHBPCR_HBP0 ((uint32_t)0x00000001U)
#define DSI_VHBPCR_HBP1 ((uint32_t)0x00000002U)
#define DSI_VHBPCR_HBP2 ((uint32_t)0x00000004U)
#define DSI_VHBPCR_HBP3 ((uint32_t)0x00000008U)
#define DSI_VHBPCR_HBP4 ((uint32_t)0x00000010U)
#define DSI_VHBPCR_HBP5 ((uint32_t)0x00000020U)
#define DSI_VHBPCR_HBP6 ((uint32_t)0x00000040U)
#define DSI_VHBPCR_HBP7 ((uint32_t)0x00000080U)
#define DSI_VHBPCR_HBP8 ((uint32_t)0x00000100U)
#define DSI_VHBPCR_HBP9 ((uint32_t)0x00000200U)
#define DSI_VHBPCR_HBP10 ((uint32_t)0x00000400U)
#define DSI_VHBPCR_HBP11 ((uint32_t)0x00000800U)
/******************* Bit definition for DSI_VLCR register ***************/
#define DSI_VLCR_HLINE ((uint32_t)0x00007FFFU) /*!< Horizontal Line duration */
#define DSI_VLCR_HLINE0 ((uint32_t)0x00000001U)
#define DSI_VLCR_HLINE1 ((uint32_t)0x00000002U)
#define DSI_VLCR_HLINE2 ((uint32_t)0x00000004U)
#define DSI_VLCR_HLINE3 ((uint32_t)0x00000008U)
#define DSI_VLCR_HLINE4 ((uint32_t)0x00000010U)
#define DSI_VLCR_HLINE5 ((uint32_t)0x00000020U)
#define DSI_VLCR_HLINE6 ((uint32_t)0x00000040U)
#define DSI_VLCR_HLINE7 ((uint32_t)0x00000080U)
#define DSI_VLCR_HLINE8 ((uint32_t)0x00000100U)
#define DSI_VLCR_HLINE9 ((uint32_t)0x00000200U)
#define DSI_VLCR_HLINE10 ((uint32_t)0x00000400U)
#define DSI_VLCR_HLINE11 ((uint32_t)0x00000800U)
#define DSI_VLCR_HLINE12 ((uint32_t)0x00001000U)
#define DSI_VLCR_HLINE13 ((uint32_t)0x00002000U)
#define DSI_VLCR_HLINE14 ((uint32_t)0x00004000U)
/******************* Bit definition for DSI_VVSACR register *************/
#define DSI_VVSACR_VSA ((uint32_t)0x000003FFU) /*!< Vertical Synchronism Active duration */
#define DSI_VVSACR_VSA0 ((uint32_t)0x00000001U)
#define DSI_VVSACR_VSA1 ((uint32_t)0x00000002U)
#define DSI_VVSACR_VSA2 ((uint32_t)0x00000004U)
#define DSI_VVSACR_VSA3 ((uint32_t)0x00000008U)
#define DSI_VVSACR_VSA4 ((uint32_t)0x00000010U)
#define DSI_VVSACR_VSA5 ((uint32_t)0x00000020U)
#define DSI_VVSACR_VSA6 ((uint32_t)0x00000040U)
#define DSI_VVSACR_VSA7 ((uint32_t)0x00000080U)
#define DSI_VVSACR_VSA8 ((uint32_t)0x00000100U)
#define DSI_VVSACR_VSA9 ((uint32_t)0x00000200U)
/******************* Bit definition for DSI_VVBPCR register *************/
#define DSI_VVBPCR_VBP ((uint32_t)0x000003FFU) /*!< Vertical Back-Porch duration */
#define DSI_VVBPCR_VBP0 ((uint32_t)0x00000001U)
#define DSI_VVBPCR_VBP1 ((uint32_t)0x00000002U)
#define DSI_VVBPCR_VBP2 ((uint32_t)0x00000004U)
#define DSI_VVBPCR_VBP3 ((uint32_t)0x00000008U)
#define DSI_VVBPCR_VBP4 ((uint32_t)0x00000010U)
#define DSI_VVBPCR_VBP5 ((uint32_t)0x00000020U)
#define DSI_VVBPCR_VBP6 ((uint32_t)0x00000040U)
#define DSI_VVBPCR_VBP7 ((uint32_t)0x00000080U)
#define DSI_VVBPCR_VBP8 ((uint32_t)0x00000100U)
#define DSI_VVBPCR_VBP9 ((uint32_t)0x00000200U)
/******************* Bit definition for DSI_VVFPCR register *************/
#define DSI_VVFPCR_VFP ((uint32_t)0x000003FFU) /*!< Vertical Front-Porch duration */
#define DSI_VVFPCR_VFP0 ((uint32_t)0x00000001U)
#define DSI_VVFPCR_VFP1 ((uint32_t)0x00000002U)
#define DSI_VVFPCR_VFP2 ((uint32_t)0x00000004U)
#define DSI_VVFPCR_VFP3 ((uint32_t)0x00000008U)
#define DSI_VVFPCR_VFP4 ((uint32_t)0x00000010U)
#define DSI_VVFPCR_VFP5 ((uint32_t)0x00000020U)
#define DSI_VVFPCR_VFP6 ((uint32_t)0x00000040U)
#define DSI_VVFPCR_VFP7 ((uint32_t)0x00000080U)
#define DSI_VVFPCR_VFP8 ((uint32_t)0x00000100U)
#define DSI_VVFPCR_VFP9 ((uint32_t)0x00000200U)
/******************* Bit definition for DSI_VVACR register **************/
#define DSI_VVACR_VA ((uint32_t)0x00003FFFU) /*!< Vertical Active duration */
#define DSI_VVACR_VA0 ((uint32_t)0x00000001U)
#define DSI_VVACR_VA1 ((uint32_t)0x00000002U)
#define DSI_VVACR_VA2 ((uint32_t)0x00000004U)
#define DSI_VVACR_VA3 ((uint32_t)0x00000008U)
#define DSI_VVACR_VA4 ((uint32_t)0x00000010U)
#define DSI_VVACR_VA5 ((uint32_t)0x00000020U)
#define DSI_VVACR_VA6 ((uint32_t)0x00000040U)
#define DSI_VVACR_VA7 ((uint32_t)0x00000080U)
#define DSI_VVACR_VA8 ((uint32_t)0x00000100U)
#define DSI_VVACR_VA9 ((uint32_t)0x00000200U)
#define DSI_VVACR_VA10 ((uint32_t)0x00000400U)
#define DSI_VVACR_VA11 ((uint32_t)0x00000800U)
#define DSI_VVACR_VA12 ((uint32_t)0x00001000U)
#define DSI_VVACR_VA13 ((uint32_t)0x00002000U)
/******************* Bit definition for DSI_LCCR register ***************/
#define DSI_LCCR_CMDSIZE ((uint32_t)0x0000FFFFU) /*!< Command Size */
#define DSI_LCCR_CMDSIZE0 ((uint32_t)0x00000001U)
#define DSI_LCCR_CMDSIZE1 ((uint32_t)0x00000002U)
#define DSI_LCCR_CMDSIZE2 ((uint32_t)0x00000004U)
#define DSI_LCCR_CMDSIZE3 ((uint32_t)0x00000008U)
#define DSI_LCCR_CMDSIZE4 ((uint32_t)0x00000010U)
#define DSI_LCCR_CMDSIZE5 ((uint32_t)0x00000020U)
#define DSI_LCCR_CMDSIZE6 ((uint32_t)0x00000040U)
#define DSI_LCCR_CMDSIZE7 ((uint32_t)0x00000080U)
#define DSI_LCCR_CMDSIZE8 ((uint32_t)0x00000100U)
#define DSI_LCCR_CMDSIZE9 ((uint32_t)0x00000200U)
#define DSI_LCCR_CMDSIZE10 ((uint32_t)0x00000400U)
#define DSI_LCCR_CMDSIZE11 ((uint32_t)0x00000800U)
#define DSI_LCCR_CMDSIZE12 ((uint32_t)0x00001000U)
#define DSI_LCCR_CMDSIZE13 ((uint32_t)0x00002000U)
#define DSI_LCCR_CMDSIZE14 ((uint32_t)0x00004000U)
#define DSI_LCCR_CMDSIZE15 ((uint32_t)0x00008000U)
/******************* Bit definition for DSI_CMCR register ***************/
#define DSI_CMCR_TEARE ((uint32_t)0x00000001U) /*!< Tearing Effect Acknowledge Request Enable */
#define DSI_CMCR_ARE ((uint32_t)0x00000002U) /*!< Acknowledge Request Enable */
#define DSI_CMCR_GSW0TX ((uint32_t)0x00000100U) /*!< Generic Short Write Zero parameters Transmission */
#define DSI_CMCR_GSW1TX ((uint32_t)0x00000200U) /*!< Generic Short Write One parameters Transmission */
#define DSI_CMCR_GSW2TX ((uint32_t)0x00000400U) /*!< Generic Short Write Two parameters Transmission */
#define DSI_CMCR_GSR0TX ((uint32_t)0x00000800U) /*!< Generic Short Read Zero parameters Transmission */
#define DSI_CMCR_GSR1TX ((uint32_t)0x00001000U) /*!< Generic Short Read One parameters Transmission */
#define DSI_CMCR_GSR2TX ((uint32_t)0x00002000U) /*!< Generic Short Read Two parameters Transmission */
#define DSI_CMCR_GLWTX ((uint32_t)0x00004000U) /*!< Generic Long Write Transmission */
#define DSI_CMCR_DSW0TX ((uint32_t)0x00010000U) /*!< DCS Short Write Zero parameter Transmission */
#define DSI_CMCR_DSW1TX ((uint32_t)0x00020000U) /*!< DCS Short Read One parameter Transmission */
#define DSI_CMCR_DSR0TX ((uint32_t)0x00040000U) /*!< DCS Short Read Zero parameter Transmission */
#define DSI_CMCR_DLWTX ((uint32_t)0x00080000U) /*!< DCS Long Write Transmission */
#define DSI_CMCR_MRDPS ((uint32_t)0x01000000U) /*!< Maximum Read Packet Size */
/******************* Bit definition for DSI_GHCR register ***************/
#define DSI_GHCR_DT ((uint32_t)0x0000003FU) /*!< Type */
#define DSI_GHCR_DT0 ((uint32_t)0x00000001U)
#define DSI_GHCR_DT1 ((uint32_t)0x00000002U)
#define DSI_GHCR_DT2 ((uint32_t)0x00000004U)
#define DSI_GHCR_DT3 ((uint32_t)0x00000008U)
#define DSI_GHCR_DT4 ((uint32_t)0x00000010U)
#define DSI_GHCR_DT5 ((uint32_t)0x00000020U)
#define DSI_GHCR_VCID ((uint32_t)0x000000C0U) /*!< Channel */
#define DSI_GHCR_VCID0 ((uint32_t)0x00000040U)
#define DSI_GHCR_VCID1 ((uint32_t)0x00000080U)
#define DSI_GHCR_WCLSB ((uint32_t)0x0000FF00U) /*!< WordCount LSB */
#define DSI_GHCR_WCLSB0 ((uint32_t)0x00000100U)
#define DSI_GHCR_WCLSB1 ((uint32_t)0x00000200U)
#define DSI_GHCR_WCLSB2 ((uint32_t)0x00000400U)
#define DSI_GHCR_WCLSB3 ((uint32_t)0x00000800U)
#define DSI_GHCR_WCLSB4 ((uint32_t)0x00001000U)
#define DSI_GHCR_WCLSB5 ((uint32_t)0x00002000U)
#define DSI_GHCR_WCLSB6 ((uint32_t)0x00004000U)
#define DSI_GHCR_WCLSB7 ((uint32_t)0x00008000U)
#define DSI_GHCR_WCMSB ((uint32_t)0x00FF0000U) /*!< WordCount MSB */
#define DSI_GHCR_WCMSB0 ((uint32_t)0x00010000U)
#define DSI_GHCR_WCMSB1 ((uint32_t)0x00020000U)
#define DSI_GHCR_WCMSB2 ((uint32_t)0x00040000U)
#define DSI_GHCR_WCMSB3 ((uint32_t)0x00080000U)
#define DSI_GHCR_WCMSB4 ((uint32_t)0x00100000U)
#define DSI_GHCR_WCMSB5 ((uint32_t)0x00200000U)
#define DSI_GHCR_WCMSB6 ((uint32_t)0x00400000U)
#define DSI_GHCR_WCMSB7 ((uint32_t)0x00800000U)
/******************* Bit definition for DSI_GPDR register ***************/
#define DSI_GPDR_DATA1 ((uint32_t)0x000000FFU) /*!< Payload Byte 1 */
#define DSI_GPDR_DATA1_0 ((uint32_t)0x00000001U)
#define DSI_GPDR_DATA1_1 ((uint32_t)0x00000002U)
#define DSI_GPDR_DATA1_2 ((uint32_t)0x00000004U)
#define DSI_GPDR_DATA1_3 ((uint32_t)0x00000008U)
#define DSI_GPDR_DATA1_4 ((uint32_t)0x00000010U)
#define DSI_GPDR_DATA1_5 ((uint32_t)0x00000020U)
#define DSI_GPDR_DATA1_6 ((uint32_t)0x00000040U)
#define DSI_GPDR_DATA1_7 ((uint32_t)0x00000080U)
#define DSI_GPDR_DATA2 ((uint32_t)0x0000FF00U) /*!< Payload Byte 2 */
#define DSI_GPDR_DATA2_0 ((uint32_t)0x00000100U)
#define DSI_GPDR_DATA2_1 ((uint32_t)0x00000200U)
#define DSI_GPDR_DATA2_2 ((uint32_t)0x00000400U)
#define DSI_GPDR_DATA2_3 ((uint32_t)0x00000800U)
#define DSI_GPDR_DATA2_4 ((uint32_t)0x00001000U)
#define DSI_GPDR_DATA2_5 ((uint32_t)0x00002000U)
#define DSI_GPDR_DATA2_6 ((uint32_t)0x00004000U)
#define DSI_GPDR_DATA2_7 ((uint32_t)0x00008000U)
#define DSI_GPDR_DATA3 ((uint32_t)0x00FF0000U) /*!< Payload Byte 3 */
#define DSI_GPDR_DATA3_0 ((uint32_t)0x00010000U)
#define DSI_GPDR_DATA3_1 ((uint32_t)0x00020000U)
#define DSI_GPDR_DATA3_2 ((uint32_t)0x00040000U)
#define DSI_GPDR_DATA3_3 ((uint32_t)0x00080000U)
#define DSI_GPDR_DATA3_4 ((uint32_t)0x00100000U)
#define DSI_GPDR_DATA3_5 ((uint32_t)0x00200000U)
#define DSI_GPDR_DATA3_6 ((uint32_t)0x00400000U)
#define DSI_GPDR_DATA3_7 ((uint32_t)0x00800000U)
#define DSI_GPDR_DATA4 ((uint32_t)0xFF000000U) /*!< Payload Byte 4 */
#define DSI_GPDR_DATA4_0 ((uint32_t)0x01000000U)
#define DSI_GPDR_DATA4_1 ((uint32_t)0x02000000U)
#define DSI_GPDR_DATA4_2 ((uint32_t)0x04000000U)
#define DSI_GPDR_DATA4_3 ((uint32_t)0x08000000U)
#define DSI_GPDR_DATA4_4 ((uint32_t)0x10000000U)
#define DSI_GPDR_DATA4_5 ((uint32_t)0x20000000U)
#define DSI_GPDR_DATA4_6 ((uint32_t)0x40000000U)
#define DSI_GPDR_DATA4_7 ((uint32_t)0x80000000U)
/******************* Bit definition for DSI_GPSR register ***************/
#define DSI_GPSR_CMDFE ((uint32_t)0x00000001U) /*!< Command FIFO Empty */
#define DSI_GPSR_CMDFF ((uint32_t)0x00000002U) /*!< Command FIFO Full */
#define DSI_GPSR_PWRFE ((uint32_t)0x00000004U) /*!< Payload Write FIFO Empty */
#define DSI_GPSR_PWRFF ((uint32_t)0x00000008U) /*!< Payload Write FIFO Full */
#define DSI_GPSR_PRDFE ((uint32_t)0x00000010U) /*!< Payload Read FIFO Empty */
#define DSI_GPSR_PRDFF ((uint32_t)0x00000020U) /*!< Payload Read FIFO Full */
#define DSI_GPSR_RCB ((uint32_t)0x00000040U) /*!< Read Command Busy */
/******************* Bit definition for DSI_TCCR0 register **************/
#define DSI_TCCR0_LPRX_TOCNT ((uint32_t)0x0000FFFFU) /*!< Low-power Reception Timeout Counter */
#define DSI_TCCR0_LPRX_TOCNT0 ((uint32_t)0x00000001U)
#define DSI_TCCR0_LPRX_TOCNT1 ((uint32_t)0x00000002U)
#define DSI_TCCR0_LPRX_TOCNT2 ((uint32_t)0x00000004U)
#define DSI_TCCR0_LPRX_TOCNT3 ((uint32_t)0x00000008U)
#define DSI_TCCR0_LPRX_TOCNT4 ((uint32_t)0x00000010U)
#define DSI_TCCR0_LPRX_TOCNT5 ((uint32_t)0x00000020U)
#define DSI_TCCR0_LPRX_TOCNT6 ((uint32_t)0x00000040U)
#define DSI_TCCR0_LPRX_TOCNT7 ((uint32_t)0x00000080U)
#define DSI_TCCR0_LPRX_TOCNT8 ((uint32_t)0x00000100U)
#define DSI_TCCR0_LPRX_TOCNT9 ((uint32_t)0x00000200U)
#define DSI_TCCR0_LPRX_TOCNT10 ((uint32_t)0x00000400U)
#define DSI_TCCR0_LPRX_TOCNT11 ((uint32_t)0x00000800U)
#define DSI_TCCR0_LPRX_TOCNT12 ((uint32_t)0x00001000U)
#define DSI_TCCR0_LPRX_TOCNT13 ((uint32_t)0x00002000U)
#define DSI_TCCR0_LPRX_TOCNT14 ((uint32_t)0x00004000U)
#define DSI_TCCR0_LPRX_TOCNT15 ((uint32_t)0x00008000U)
#define DSI_TCCR0_HSTX_TOCNT ((uint32_t)0xFFFF0000U) /*!< High-Speed Transmission Timeout Counter */
#define DSI_TCCR0_HSTX_TOCNT0 ((uint32_t)0x00010000U)
#define DSI_TCCR0_HSTX_TOCNT1 ((uint32_t)0x00020000U)
#define DSI_TCCR0_HSTX_TOCNT2 ((uint32_t)0x00040000U)
#define DSI_TCCR0_HSTX_TOCNT3 ((uint32_t)0x00080000U)
#define DSI_TCCR0_HSTX_TOCNT4 ((uint32_t)0x00100000U)
#define DSI_TCCR0_HSTX_TOCNT5 ((uint32_t)0x00200000U)
#define DSI_TCCR0_HSTX_TOCNT6 ((uint32_t)0x00400000U)
#define DSI_TCCR0_HSTX_TOCNT7 ((uint32_t)0x00800000U)
#define DSI_TCCR0_HSTX_TOCNT8 ((uint32_t)0x01000000U)
#define DSI_TCCR0_HSTX_TOCNT9 ((uint32_t)0x02000000U)
#define DSI_TCCR0_HSTX_TOCNT10 ((uint32_t)0x04000000U)
#define DSI_TCCR0_HSTX_TOCNT11 ((uint32_t)0x08000000U)
#define DSI_TCCR0_HSTX_TOCNT12 ((uint32_t)0x10000000U)
#define DSI_TCCR0_HSTX_TOCNT13 ((uint32_t)0x20000000U)
#define DSI_TCCR0_HSTX_TOCNT14 ((uint32_t)0x40000000U)
#define DSI_TCCR0_HSTX_TOCNT15 ((uint32_t)0x80000000U)
/******************* Bit definition for DSI_TCCR1 register **************/
#define DSI_TCCR1_HSRD_TOCNT ((uint32_t)0x0000FFFFU) /*!< High-Speed Read Timeout Counter */
#define DSI_TCCR1_HSRD_TOCNT0 ((uint32_t)0x00000001U)
#define DSI_TCCR1_HSRD_TOCNT1 ((uint32_t)0x00000002U)
#define DSI_TCCR1_HSRD_TOCNT2 ((uint32_t)0x00000004U)
#define DSI_TCCR1_HSRD_TOCNT3 ((uint32_t)0x00000008U)
#define DSI_TCCR1_HSRD_TOCNT4 ((uint32_t)0x00000010U)
#define DSI_TCCR1_HSRD_TOCNT5 ((uint32_t)0x00000020U)
#define DSI_TCCR1_HSRD_TOCNT6 ((uint32_t)0x00000040U)
#define DSI_TCCR1_HSRD_TOCNT7 ((uint32_t)0x00000080U)
#define DSI_TCCR1_HSRD_TOCNT8 ((uint32_t)0x00000100U)
#define DSI_TCCR1_HSRD_TOCNT9 ((uint32_t)0x00000200U)
#define DSI_TCCR1_HSRD_TOCNT10 ((uint32_t)0x00000400U)
#define DSI_TCCR1_HSRD_TOCNT11 ((uint32_t)0x00000800U)
#define DSI_TCCR1_HSRD_TOCNT12 ((uint32_t)0x00001000U)
#define DSI_TCCR1_HSRD_TOCNT13 ((uint32_t)0x00002000U)
#define DSI_TCCR1_HSRD_TOCNT14 ((uint32_t)0x00004000U)
#define DSI_TCCR1_HSRD_TOCNT15 ((uint32_t)0x00008000U)
/******************* Bit definition for DSI_TCCR2 register **************/
#define DSI_TCCR2_LPRD_TOCNT ((uint32_t)0x0000FFFFU) /*!< Low-Power Read Timeout Counter */
#define DSI_TCCR2_LPRD_TOCNT0 ((uint32_t)0x00000001U)
#define DSI_TCCR2_LPRD_TOCNT1 ((uint32_t)0x00000002U)
#define DSI_TCCR2_LPRD_TOCNT2 ((uint32_t)0x00000004U)
#define DSI_TCCR2_LPRD_TOCNT3 ((uint32_t)0x00000008U)
#define DSI_TCCR2_LPRD_TOCNT4 ((uint32_t)0x00000010U)
#define DSI_TCCR2_LPRD_TOCNT5 ((uint32_t)0x00000020U)
#define DSI_TCCR2_LPRD_TOCNT6 ((uint32_t)0x00000040U)
#define DSI_TCCR2_LPRD_TOCNT7 ((uint32_t)0x00000080U)
#define DSI_TCCR2_LPRD_TOCNT8 ((uint32_t)0x00000100U)
#define DSI_TCCR2_LPRD_TOCNT9 ((uint32_t)0x00000200U)
#define DSI_TCCR2_LPRD_TOCNT10 ((uint32_t)0x00000400U)
#define DSI_TCCR2_LPRD_TOCNT11 ((uint32_t)0x00000800U)
#define DSI_TCCR2_LPRD_TOCNT12 ((uint32_t)0x00001000U)
#define DSI_TCCR2_LPRD_TOCNT13 ((uint32_t)0x00002000U)
#define DSI_TCCR2_LPRD_TOCNT14 ((uint32_t)0x00004000U)
#define DSI_TCCR2_LPRD_TOCNT15 ((uint32_t)0x00008000U)
/******************* Bit definition for DSI_TCCR3 register **************/
#define DSI_TCCR3_HSWR_TOCNT ((uint32_t)0x0000FFFFU) /*!< High-Speed Write Timeout Counter */
#define DSI_TCCR3_HSWR_TOCNT0 ((uint32_t)0x00000001U)
#define DSI_TCCR3_HSWR_TOCNT1 ((uint32_t)0x00000002U)
#define DSI_TCCR3_HSWR_TOCNT2 ((uint32_t)0x00000004U)
#define DSI_TCCR3_HSWR_TOCNT3 ((uint32_t)0x00000008U)
#define DSI_TCCR3_HSWR_TOCNT4 ((uint32_t)0x00000010U)
#define DSI_TCCR3_HSWR_TOCNT5 ((uint32_t)0x00000020U)
#define DSI_TCCR3_HSWR_TOCNT6 ((uint32_t)0x00000040U)
#define DSI_TCCR3_HSWR_TOCNT7 ((uint32_t)0x00000080U)
#define DSI_TCCR3_HSWR_TOCNT8 ((uint32_t)0x00000100U)
#define DSI_TCCR3_HSWR_TOCNT9 ((uint32_t)0x00000200U)
#define DSI_TCCR3_HSWR_TOCNT10 ((uint32_t)0x00000400U)
#define DSI_TCCR3_HSWR_TOCNT11 ((uint32_t)0x00000800U)
#define DSI_TCCR3_HSWR_TOCNT12 ((uint32_t)0x00001000U)
#define DSI_TCCR3_HSWR_TOCNT13 ((uint32_t)0x00002000U)
#define DSI_TCCR3_HSWR_TOCNT14 ((uint32_t)0x00004000U)
#define DSI_TCCR3_HSWR_TOCNT15 ((uint32_t)0x00008000U)
#define DSI_TCCR3_PM ((uint32_t)0x01000000U) /*!< Presp Mode */
/******************* Bit definition for DSI_TCCR4 register **************/
#define DSI_TCCR4_LPWR_TOCNT ((uint32_t)0x0000FFFFU) /*!< Low-Power Write Timeout Counter */
#define DSI_TCCR4_LPWR_TOCNT0 ((uint32_t)0x00000001U)
#define DSI_TCCR4_LPWR_TOCNT1 ((uint32_t)0x00000002U)
#define DSI_TCCR4_LPWR_TOCNT2 ((uint32_t)0x00000004U)
#define DSI_TCCR4_LPWR_TOCNT3 ((uint32_t)0x00000008U)
#define DSI_TCCR4_LPWR_TOCNT4 ((uint32_t)0x00000010U)
#define DSI_TCCR4_LPWR_TOCNT5 ((uint32_t)0x00000020U)
#define DSI_TCCR4_LPWR_TOCNT6 ((uint32_t)0x00000040U)
#define DSI_TCCR4_LPWR_TOCNT7 ((uint32_t)0x00000080U)
#define DSI_TCCR4_LPWR_TOCNT8 ((uint32_t)0x00000100U)
#define DSI_TCCR4_LPWR_TOCNT9 ((uint32_t)0x00000200U)
#define DSI_TCCR4_LPWR_TOCNT10 ((uint32_t)0x00000400U)
#define DSI_TCCR4_LPWR_TOCNT11 ((uint32_t)0x00000800U)
#define DSI_TCCR4_LPWR_TOCNT12 ((uint32_t)0x00001000U)
#define DSI_TCCR4_LPWR_TOCNT13 ((uint32_t)0x00002000U)
#define DSI_TCCR4_LPWR_TOCNT14 ((uint32_t)0x00004000U)
#define DSI_TCCR4_LPWR_TOCNT15 ((uint32_t)0x00008000U)
/******************* Bit definition for DSI_TCCR5 register **************/
#define DSI_TCCR5_BTA_TOCNT ((uint32_t)0x0000FFFFU) /*!< Bus-Turn-Around Timeout Counter */
#define DSI_TCCR5_BTA_TOCNT0 ((uint32_t)0x00000001U)
#define DSI_TCCR5_BTA_TOCNT1 ((uint32_t)0x00000002U)
#define DSI_TCCR5_BTA_TOCNT2 ((uint32_t)0x00000004U)
#define DSI_TCCR5_BTA_TOCNT3 ((uint32_t)0x00000008U)
#define DSI_TCCR5_BTA_TOCNT4 ((uint32_t)0x00000010U)
#define DSI_TCCR5_BTA_TOCNT5 ((uint32_t)0x00000020U)
#define DSI_TCCR5_BTA_TOCNT6 ((uint32_t)0x00000040U)
#define DSI_TCCR5_BTA_TOCNT7 ((uint32_t)0x00000080U)
#define DSI_TCCR5_BTA_TOCNT8 ((uint32_t)0x00000100U)
#define DSI_TCCR5_BTA_TOCNT9 ((uint32_t)0x00000200U)
#define DSI_TCCR5_BTA_TOCNT10 ((uint32_t)0x00000400U)
#define DSI_TCCR5_BTA_TOCNT11 ((uint32_t)0x00000800U)
#define DSI_TCCR5_BTA_TOCNT12 ((uint32_t)0x00001000U)
#define DSI_TCCR5_BTA_TOCNT13 ((uint32_t)0x00002000U)
#define DSI_TCCR5_BTA_TOCNT14 ((uint32_t)0x00004000U)
#define DSI_TCCR5_BTA_TOCNT15 ((uint32_t)0x00008000U)
/******************* Bit definition for DSI_TDCR register ***************/
#define DSI_TDCR_3DM ((uint32_t)0x00000003U) /*!< 3D Mode */
#define DSI_TDCR_3DM0 ((uint32_t)0x00000001U)
#define DSI_TDCR_3DM1 ((uint32_t)0x00000002U)
#define DSI_TDCR_3DF ((uint32_t)0x0000000CU) /*!< 3D Format */
#define DSI_TDCR_3DF0 ((uint32_t)0x00000004U)
#define DSI_TDCR_3DF1 ((uint32_t)0x00000008U)
#define DSI_TDCR_SVS ((uint32_t)0x00000010U) /*!< Second VSYNC */
#define DSI_TDCR_RF ((uint32_t)0x00000020U) /*!< Right First */
#define DSI_TDCR_S3DC ((uint32_t)0x00010000U) /*!< Send 3D Control */
/******************* Bit definition for DSI_CLCR register ***************/
#define DSI_CLCR_DPCC ((uint32_t)0x00000001U) /*!< D-PHY Clock Control */
#define DSI_CLCR_ACR ((uint32_t)0x00000002U) /*!< Automatic Clocklane Control */
/******************* Bit definition for DSI_CLTCR register **************/
#define DSI_CLTCR_LP2HS_TIME ((uint32_t)0x000003FFU) /*!< Low-Power to High-Speed Time */
#define DSI_CLTCR_LP2HS_TIME0 ((uint32_t)0x00000001U)
#define DSI_CLTCR_LP2HS_TIME1 ((uint32_t)0x00000002U)
#define DSI_CLTCR_LP2HS_TIME2 ((uint32_t)0x00000004U)
#define DSI_CLTCR_LP2HS_TIME3 ((uint32_t)0x00000008U)
#define DSI_CLTCR_LP2HS_TIME4 ((uint32_t)0x00000010U)
#define DSI_CLTCR_LP2HS_TIME5 ((uint32_t)0x00000020U)
#define DSI_CLTCR_LP2HS_TIME6 ((uint32_t)0x00000040U)
#define DSI_CLTCR_LP2HS_TIME7 ((uint32_t)0x00000080U)
#define DSI_CLTCR_LP2HS_TIME8 ((uint32_t)0x00000100U)
#define DSI_CLTCR_LP2HS_TIME9 ((uint32_t)0x00000200U)
#define DSI_CLTCR_HS2LP_TIME ((uint32_t)0x03FF0000U) /*!< High-Speed to Low-Power Time */
#define DSI_CLTCR_HS2LP_TIME0 ((uint32_t)0x00010000U)
#define DSI_CLTCR_HS2LP_TIME1 ((uint32_t)0x00020000U)
#define DSI_CLTCR_HS2LP_TIME2 ((uint32_t)0x00040000U)
#define DSI_CLTCR_HS2LP_TIME3 ((uint32_t)0x00080000U)
#define DSI_CLTCR_HS2LP_TIME4 ((uint32_t)0x00100000U)
#define DSI_CLTCR_HS2LP_TIME5 ((uint32_t)0x00200000U)
#define DSI_CLTCR_HS2LP_TIME6 ((uint32_t)0x00400000U)
#define DSI_CLTCR_HS2LP_TIME7 ((uint32_t)0x00800000U)
#define DSI_CLTCR_HS2LP_TIME8 ((uint32_t)0x01000000U)
#define DSI_CLTCR_HS2LP_TIME9 ((uint32_t)0x02000000U)
/******************* Bit definition for DSI_DLTCR register **************/
#define DSI_DLTCR_LP2HS_TIME ((uint32_t)0x000003FFU) /*!< Low-Power to High-Speed Time */
#define DSI_DLTCR_LP2HS_TIME0 ((uint32_t)0x00000001U)
#define DSI_DLTCR_LP2HS_TIME1 ((uint32_t)0x00000002U)
#define DSI_DLTCR_LP2HS_TIME2 ((uint32_t)0x00000004U)
#define DSI_DLTCR_LP2HS_TIME3 ((uint32_t)0x00000008U)
#define DSI_DLTCR_LP2HS_TIME4 ((uint32_t)0x00000010U)
#define DSI_DLTCR_LP2HS_TIME5 ((uint32_t)0x00000020U)
#define DSI_DLTCR_LP2HS_TIME6 ((uint32_t)0x00000040U)
#define DSI_DLTCR_LP2HS_TIME7 ((uint32_t)0x00000080U)
#define DSI_DLTCR_LP2HS_TIME8 ((uint32_t)0x00000100U)
#define DSI_DLTCR_LP2HS_TIME9 ((uint32_t)0x00000200U)
#define DSI_DLTCR_HS2LP_TIME ((uint32_t)0x03FF0000U) /*!< High-Speed to Low-Power Time */
#define DSI_DLTCR_HS2LP_TIME0 ((uint32_t)0x00010000U)
#define DSI_DLTCR_HS2LP_TIME1 ((uint32_t)0x00020000U)
#define DSI_DLTCR_HS2LP_TIME2 ((uint32_t)0x00040000U)
#define DSI_DLTCR_HS2LP_TIME3 ((uint32_t)0x00080000U)
#define DSI_DLTCR_HS2LP_TIME4 ((uint32_t)0x00100000U)
#define DSI_DLTCR_HS2LP_TIME5 ((uint32_t)0x00200000U)
#define DSI_DLTCR_HS2LP_TIME6 ((uint32_t)0x00400000U)
#define DSI_DLTCR_HS2LP_TIME7 ((uint32_t)0x00800000U)
#define DSI_DLTCR_HS2LP_TIME8 ((uint32_t)0x01000000U)
#define DSI_DLTCR_HS2LP_TIME9 ((uint32_t)0x02000000U)
/******************* Bit definition for DSI_PCTLR register **************/
#define DSI_PCTLR_DEN ((uint32_t)0x00000002U) /*!< Digital Enable */
#define DSI_PCTLR_CKE ((uint32_t)0x00000004U) /*!< Clock Enable */
/******************* Bit definition for DSI_PCONFR register *************/
#define DSI_PCONFR_NL ((uint32_t)0x00000003U) /*!< Number of Lanes */
#define DSI_PCONFR_NL0 ((uint32_t)0x00000001U)
#define DSI_PCONFR_NL1 ((uint32_t)0x00000002U)
#define DSI_PCONFR_SW_TIME ((uint32_t)0x0000FF00U) /*!< Stop Wait Time */
#define DSI_PCONFR_SW_TIME0 ((uint32_t)0x00000100U)
#define DSI_PCONFR_SW_TIME1 ((uint32_t)0x00000200U)
#define DSI_PCONFR_SW_TIME2 ((uint32_t)0x00000400U)
#define DSI_PCONFR_SW_TIME3 ((uint32_t)0x00000800U)
#define DSI_PCONFR_SW_TIME4 ((uint32_t)0x00001000U)
#define DSI_PCONFR_SW_TIME5 ((uint32_t)0x00002000U)
#define DSI_PCONFR_SW_TIME6 ((uint32_t)0x00004000U)
#define DSI_PCONFR_SW_TIME7 ((uint32_t)0x00008000U)
/******************* Bit definition for DSI_PUCR register ***************/
#define DSI_PUCR_URCL ((uint32_t)0x00000001U) /*!< ULPS Request on Clock Lane */
#define DSI_PUCR_UECL ((uint32_t)0x00000002U) /*!< ULPS Exit on Clock Lane */
#define DSI_PUCR_URDL ((uint32_t)0x00000004U) /*!< ULPS Request on Data Lane */
#define DSI_PUCR_UEDL ((uint32_t)0x00000008U) /*!< ULPS Exit on Data Lane */
/******************* Bit definition for DSI_PTTCR register **************/
#define DSI_PTTCR_TX_TRIG ((uint32_t)0x0000000FU) /*!< Transmission Trigger */
#define DSI_PTTCR_TX_TRIG0 ((uint32_t)0x00000001U)
#define DSI_PTTCR_TX_TRIG1 ((uint32_t)0x00000002U)
#define DSI_PTTCR_TX_TRIG2 ((uint32_t)0x00000004U)
#define DSI_PTTCR_TX_TRIG3 ((uint32_t)0x00000008U)
/******************* Bit definition for DSI_PSR register ****************/
#define DSI_PSR_PD ((uint32_t)0x00000002U) /*!< PHY Direction */
#define DSI_PSR_PSSC ((uint32_t)0x00000004U) /*!< PHY Stop State Clock lane */
#define DSI_PSR_UANC ((uint32_t)0x00000008U) /*!< ULPS Active Not Clock lane */
#define DSI_PSR_PSS0 ((uint32_t)0x00000010U) /*!< PHY Stop State lane 0 */
#define DSI_PSR_UAN0 ((uint32_t)0x00000020U) /*!< ULPS Active Not lane 0 */
#define DSI_PSR_RUE0 ((uint32_t)0x00000040U) /*!< RX ULPS Escape lane 0 */
#define DSI_PSR_PSS1 ((uint32_t)0x00000080U) /*!< PHY Stop State lane 1 */
#define DSI_PSR_UAN1 ((uint32_t)0x00000100U) /*!< ULPS Active Not lane 1 */
/******************* Bit definition for DSI_ISR0 register ***************/
#define DSI_ISR0_AE0 ((uint32_t)0x00000001U) /*!< Acknowledge Error 0 */
#define DSI_ISR0_AE1 ((uint32_t)0x00000002U) /*!< Acknowledge Error 1 */
#define DSI_ISR0_AE2 ((uint32_t)0x00000004U) /*!< Acknowledge Error 2 */
#define DSI_ISR0_AE3 ((uint32_t)0x00000008U) /*!< Acknowledge Error 3 */
#define DSI_ISR0_AE4 ((uint32_t)0x00000010U) /*!< Acknowledge Error 4 */
#define DSI_ISR0_AE5 ((uint32_t)0x00000020U) /*!< Acknowledge Error 5 */
#define DSI_ISR0_AE6 ((uint32_t)0x00000040U) /*!< Acknowledge Error 6 */
#define DSI_ISR0_AE7 ((uint32_t)0x00000080U) /*!< Acknowledge Error 7 */
#define DSI_ISR0_AE8 ((uint32_t)0x00000100U) /*!< Acknowledge Error 8 */
#define DSI_ISR0_AE9 ((uint32_t)0x00000200U) /*!< Acknowledge Error 9 */
#define DSI_ISR0_AE10 ((uint32_t)0x00000400U) /*!< Acknowledge Error 10 */
#define DSI_ISR0_AE11 ((uint32_t)0x00000800U) /*!< Acknowledge Error 11 */
#define DSI_ISR0_AE12 ((uint32_t)0x00001000U) /*!< Acknowledge Error 12 */
#define DSI_ISR0_AE13 ((uint32_t)0x00002000U) /*!< Acknowledge Error 13 */
#define DSI_ISR0_AE14 ((uint32_t)0x00004000U) /*!< Acknowledge Error 14 */
#define DSI_ISR0_AE15 ((uint32_t)0x00008000U) /*!< Acknowledge Error 15 */
#define DSI_ISR0_PE0 ((uint32_t)0x00010000U) /*!< PHY Error 0 */
#define DSI_ISR0_PE1 ((uint32_t)0x00020000U) /*!< PHY Error 1 */
#define DSI_ISR0_PE2 ((uint32_t)0x00040000U) /*!< PHY Error 2 */
#define DSI_ISR0_PE3 ((uint32_t)0x00080000U) /*!< PHY Error 3 */
#define DSI_ISR0_PE4 ((uint32_t)0x00100000U) /*!< PHY Error 4 */
/******************* Bit definition for DSI_ISR1 register ***************/
#define DSI_ISR1_TOHSTX ((uint32_t)0x00000001U) /*!< Timeout High-Speed Transmission */
#define DSI_ISR1_TOLPRX ((uint32_t)0x00000002U) /*!< Timeout Low-Power Reception */
#define DSI_ISR1_ECCSE ((uint32_t)0x00000004U) /*!< ECC Single-bit Error */
#define DSI_ISR1_ECCME ((uint32_t)0x00000008U) /*!< ECC Multi-bit Error */
#define DSI_ISR1_CRCE ((uint32_t)0x00000010U) /*!< CRC Error */
#define DSI_ISR1_PSE ((uint32_t)0x00000020U) /*!< Packet Size Error */
#define DSI_ISR1_EOTPE ((uint32_t)0x00000040U) /*!< EoTp Error */
#define DSI_ISR1_LPWRE ((uint32_t)0x00000080U) /*!< LTDC Payload Write Error */
#define DSI_ISR1_GCWRE ((uint32_t)0x00000100U) /*!< Generic Command Write Error */
#define DSI_ISR1_GPWRE ((uint32_t)0x00000200U) /*!< Generic Payload Write Error */
#define DSI_ISR1_GPTXE ((uint32_t)0x00000400U) /*!< Generic Payload Transmit Error */
#define DSI_ISR1_GPRDE ((uint32_t)0x00000800U) /*!< Generic Payload Read Error */
#define DSI_ISR1_GPRXE ((uint32_t)0x00001000U) /*!< Generic Payload Receive Error */
/******************* Bit definition for DSI_IER0 register ***************/
#define DSI_IER0_AE0IE ((uint32_t)0x00000001U) /*!< Acknowledge Error 0 Interrupt Enable */
#define DSI_IER0_AE1IE ((uint32_t)0x00000002U) /*!< Acknowledge Error 1 Interrupt Enable */
#define DSI_IER0_AE2IE ((uint32_t)0x00000004U) /*!< Acknowledge Error 2 Interrupt Enable */
#define DSI_IER0_AE3IE ((uint32_t)0x00000008U) /*!< Acknowledge Error 3 Interrupt Enable */
#define DSI_IER0_AE4IE ((uint32_t)0x00000010U) /*!< Acknowledge Error 4 Interrupt Enable */
#define DSI_IER0_AE5IE ((uint32_t)0x00000020U) /*!< Acknowledge Error 5 Interrupt Enable */
#define DSI_IER0_AE6IE ((uint32_t)0x00000040U) /*!< Acknowledge Error 6 Interrupt Enable */
#define DSI_IER0_AE7IE ((uint32_t)0x00000080U) /*!< Acknowledge Error 7 Interrupt Enable */
#define DSI_IER0_AE8IE ((uint32_t)0x00000100U) /*!< Acknowledge Error 8 Interrupt Enable */
#define DSI_IER0_AE9IE ((uint32_t)0x00000200U) /*!< Acknowledge Error 9 Interrupt Enable */
#define DSI_IER0_AE10IE ((uint32_t)0x00000400U) /*!< Acknowledge Error 10 Interrupt Enable */
#define DSI_IER0_AE11IE ((uint32_t)0x00000800U) /*!< Acknowledge Error 11 Interrupt Enable */
#define DSI_IER0_AE12IE ((uint32_t)0x00001000U) /*!< Acknowledge Error 12 Interrupt Enable */
#define DSI_IER0_AE13IE ((uint32_t)0x00002000U) /*!< Acknowledge Error 13 Interrupt Enable */
#define DSI_IER0_AE14IE ((uint32_t)0x00004000U) /*!< Acknowledge Error 14 Interrupt Enable */
#define DSI_IER0_AE15IE ((uint32_t)0x00008000U) /*!< Acknowledge Error 15 Interrupt Enable */
#define DSI_IER0_PE0IE ((uint32_t)0x00010000U) /*!< PHY Error 0 Interrupt Enable */
#define DSI_IER0_PE1IE ((uint32_t)0x00020000U) /*!< PHY Error 1 Interrupt Enable */
#define DSI_IER0_PE2IE ((uint32_t)0x00040000U) /*!< PHY Error 2 Interrupt Enable */
#define DSI_IER0_PE3IE ((uint32_t)0x00080000U) /*!< PHY Error 3 Interrupt Enable */
#define DSI_IER0_PE4IE ((uint32_t)0x00100000U) /*!< PHY Error 4 Interrupt Enable */
/******************* Bit definition for DSI_IER1 register ***************/
#define DSI_IER1_TOHSTXIE ((uint32_t)0x00000001U) /*!< Timeout High-Speed Transmission Interrupt Enable */
#define DSI_IER1_TOLPRXIE ((uint32_t)0x00000002U) /*!< Timeout Low-Power Reception Interrupt Enable */
#define DSI_IER1_ECCSEIE ((uint32_t)0x00000004U) /*!< ECC Single-bit Error Interrupt Enable */
#define DSI_IER1_ECCMEIE ((uint32_t)0x00000008U) /*!< ECC Multi-bit Error Interrupt Enable */
#define DSI_IER1_CRCEIE ((uint32_t)0x00000010U) /*!< CRC Error Interrupt Enable */
#define DSI_IER1_PSEIE ((uint32_t)0x00000020U) /*!< Packet Size Error Interrupt Enable */
#define DSI_IER1_EOTPEIE ((uint32_t)0x00000040U) /*!< EoTp Error Interrupt Enable */
#define DSI_IER1_LPWREIE ((uint32_t)0x00000080U) /*!< LTDC Payload Write Error Interrupt Enable */
#define DSI_IER1_GCWREIE ((uint32_t)0x00000100U) /*!< Generic Command Write Error Interrupt Enable */
#define DSI_IER1_GPWREIE ((uint32_t)0x00000200U) /*!< Generic Payload Write Error Interrupt Enable */
#define DSI_IER1_GPTXEIE ((uint32_t)0x00000400U) /*!< Generic Payload Transmit Error Interrupt Enable */
#define DSI_IER1_GPRDEIE ((uint32_t)0x00000800U) /*!< Generic Payload Read Error Interrupt Enable */
#define DSI_IER1_GPRXEIE ((uint32_t)0x00001000U) /*!< Generic Payload Receive Error Interrupt Enable */
/******************* Bit definition for DSI_FIR0 register ***************/
#define DSI_FIR0_FAE0 ((uint32_t)0x00000001U) /*!< Force Acknowledge Error 0 */
#define DSI_FIR0_FAE1 ((uint32_t)0x00000002U) /*!< Force Acknowledge Error 1 */
#define DSI_FIR0_FAE2 ((uint32_t)0x00000004U) /*!< Force Acknowledge Error 2 */
#define DSI_FIR0_FAE3 ((uint32_t)0x00000008U) /*!< Force Acknowledge Error 3 */
#define DSI_FIR0_FAE4 ((uint32_t)0x00000010U) /*!< Force Acknowledge Error 4 */
#define DSI_FIR0_FAE5 ((uint32_t)0x00000020U) /*!< Force Acknowledge Error 5 */
#define DSI_FIR0_FAE6 ((uint32_t)0x00000040U) /*!< Force Acknowledge Error 6 */
#define DSI_FIR0_FAE7 ((uint32_t)0x00000080U) /*!< Force Acknowledge Error 7 */
#define DSI_FIR0_FAE8 ((uint32_t)0x00000100U) /*!< Force Acknowledge Error 8 */
#define DSI_FIR0_FAE9 ((uint32_t)0x00000200U) /*!< Force Acknowledge Error 9 */
#define DSI_FIR0_FAE10 ((uint32_t)0x00000400U) /*!< Force Acknowledge Error 10 */
#define DSI_FIR0_FAE11 ((uint32_t)0x00000800U) /*!< Force Acknowledge Error 11 */
#define DSI_FIR0_FAE12 ((uint32_t)0x00001000U) /*!< Force Acknowledge Error 12 */
#define DSI_FIR0_FAE13 ((uint32_t)0x00002000U) /*!< Force Acknowledge Error 13 */
#define DSI_FIR0_FAE14 ((uint32_t)0x00004000U) /*!< Force Acknowledge Error 14 */
#define DSI_FIR0_FAE15 ((uint32_t)0x00008000U) /*!< Force Acknowledge Error 15 */
#define DSI_FIR0_FPE0 ((uint32_t)0x00010000U) /*!< Force PHY Error 0 */
#define DSI_FIR0_FPE1 ((uint32_t)0x00020000U) /*!< Force PHY Error 1 */
#define DSI_FIR0_FPE2 ((uint32_t)0x00040000U) /*!< Force PHY Error 2 */
#define DSI_FIR0_FPE3 ((uint32_t)0x00080000U) /*!< Force PHY Error 3 */
#define DSI_FIR0_FPE4 ((uint32_t)0x00100000U) /*!< Force PHY Error 4 */
/******************* Bit definition for DSI_FIR1 register ***************/
#define DSI_FIR1_FTOHSTX ((uint32_t)0x00000001U) /*!< Force Timeout High-Speed Transmission */
#define DSI_FIR1_FTOLPRX ((uint32_t)0x00000002U) /*!< Force Timeout Low-Power Reception */
#define DSI_FIR1_FECCSE ((uint32_t)0x00000004U) /*!< Force ECC Single-bit Error */
#define DSI_FIR1_FECCME ((uint32_t)0x00000008U) /*!< Force ECC Multi-bit Error */
#define DSI_FIR1_FCRCE ((uint32_t)0x00000010U) /*!< Force CRC Error */
#define DSI_FIR1_FPSE ((uint32_t)0x00000020U) /*!< Force Packet Size Error */
#define DSI_FIR1_FEOTPE ((uint32_t)0x00000040U) /*!< Force EoTp Error */
#define DSI_FIR1_FLPWRE ((uint32_t)0x00000080U) /*!< Force LTDC Payload Write Error */
#define DSI_FIR1_FGCWRE ((uint32_t)0x00000100U) /*!< Force Generic Command Write Error */
#define DSI_FIR1_FGPWRE ((uint32_t)0x00000200U) /*!< Force Generic Payload Write Error */
#define DSI_FIR1_FGPTXE ((uint32_t)0x00000400U) /*!< Force Generic Payload Transmit Error */
#define DSI_FIR1_FGPRDE ((uint32_t)0x00000800U) /*!< Force Generic Payload Read Error */
#define DSI_FIR1_FGPRXE ((uint32_t)0x00001000U) /*!< Force Generic Payload Receive Error */
/******************* Bit definition for DSI_DLTRCR register *************/
#define DSI_DLTRCR_MRD_TIME ((uint32_t)0x00007FFFU) /*!< Maximum Read Time */
#define DSI_DLTRCR_MRD_TIME0 ((uint32_t)0x00000001U)
#define DSI_DLTRCR_MRD_TIME1 ((uint32_t)0x00000002U)
#define DSI_DLTRCR_MRD_TIME2 ((uint32_t)0x00000004U)
#define DSI_DLTRCR_MRD_TIME3 ((uint32_t)0x00000008U)
#define DSI_DLTRCR_MRD_TIME4 ((uint32_t)0x00000010U)
#define DSI_DLTRCR_MRD_TIME5 ((uint32_t)0x00000020U)
#define DSI_DLTRCR_MRD_TIME6 ((uint32_t)0x00000040U)
#define DSI_DLTRCR_MRD_TIME7 ((uint32_t)0x00000080U)
#define DSI_DLTRCR_MRD_TIME8 ((uint32_t)0x00000100U)
#define DSI_DLTRCR_MRD_TIME9 ((uint32_t)0x00000200U)
#define DSI_DLTRCR_MRD_TIME10 ((uint32_t)0x00000400U)
#define DSI_DLTRCR_MRD_TIME11 ((uint32_t)0x00000800U)
#define DSI_DLTRCR_MRD_TIME12 ((uint32_t)0x00001000U)
#define DSI_DLTRCR_MRD_TIME13 ((uint32_t)0x00002000U)
#define DSI_DLTRCR_MRD_TIME14 ((uint32_t)0x00004000U)
/******************* Bit definition for DSI_VSCR register ***************/
#define DSI_VSCR_EN ((uint32_t)0x00000001U) /*!< Enable */
#define DSI_VSCR_UR ((uint32_t)0x00000100U) /*!< Update Register */
/******************* Bit definition for DSI_LCVCIDR register ************/
#define DSI_LCVCIDR_VCID ((uint32_t)0x00000003U) /*!< Virtual Channel ID */
#define DSI_LCVCIDR_VCID0 ((uint32_t)0x00000001U)
#define DSI_LCVCIDR_VCID1 ((uint32_t)0x00000002U)
/******************* Bit definition for DSI_LCCCR register **************/
#define DSI_LCCCR_COLC ((uint32_t)0x0000000FU) /*!< Color Coding */
#define DSI_LCCCR_COLC0 ((uint32_t)0x00000001U)
#define DSI_LCCCR_COLC1 ((uint32_t)0x00000002U)
#define DSI_LCCCR_COLC2 ((uint32_t)0x00000004U)
#define DSI_LCCCR_COLC3 ((uint32_t)0x00000008U)
#define DSI_LCCCR_LPE ((uint32_t)0x00000100U) /*!< Loosely Packed Enable */
/******************* Bit definition for DSI_LPMCCR register *************/
#define DSI_LPMCCR_VLPSIZE ((uint32_t)0x000000FFU) /*!< VACT Largest Packet Size */
#define DSI_LPMCCR_VLPSIZE0 ((uint32_t)0x00000001U)
#define DSI_LPMCCR_VLPSIZE1 ((uint32_t)0x00000002U)
#define DSI_LPMCCR_VLPSIZE2 ((uint32_t)0x00000004U)
#define DSI_LPMCCR_VLPSIZE3 ((uint32_t)0x00000008U)
#define DSI_LPMCCR_VLPSIZE4 ((uint32_t)0x00000010U)
#define DSI_LPMCCR_VLPSIZE5 ((uint32_t)0x00000020U)
#define DSI_LPMCCR_VLPSIZE6 ((uint32_t)0x00000040U)
#define DSI_LPMCCR_VLPSIZE7 ((uint32_t)0x00000080U)
#define DSI_LPMCCR_LPSIZE ((uint32_t)0x00FF0000U) /*!< Largest Packet Size */
#define DSI_LPMCCR_LPSIZE0 ((uint32_t)0x00010000U)
#define DSI_LPMCCR_LPSIZE1 ((uint32_t)0x00020000U)
#define DSI_LPMCCR_LPSIZE2 ((uint32_t)0x00040000U)
#define DSI_LPMCCR_LPSIZE3 ((uint32_t)0x00080000U)
#define DSI_LPMCCR_LPSIZE4 ((uint32_t)0x00100000U)
#define DSI_LPMCCR_LPSIZE5 ((uint32_t)0x00200000U)
#define DSI_LPMCCR_LPSIZE6 ((uint32_t)0x00400000U)
#define DSI_LPMCCR_LPSIZE7 ((uint32_t)0x00800000U)
/******************* Bit definition for DSI_VMCCR register **************/
#define DSI_VMCCR_VMT ((uint32_t)0x00000003U) /*!< Video Mode Type */
#define DSI_VMCCR_VMT0 ((uint32_t)0x00000001U)
#define DSI_VMCCR_VMT1 ((uint32_t)0x00000002U)
#define DSI_VMCCR_LPVSAE ((uint32_t)0x00000100U) /*!< Low-power Vertical Sync time Enable */
#define DSI_VMCCR_LPVBPE ((uint32_t)0x00000200U) /*!< Low-power Vertical Back-porch Enable */
#define DSI_VMCCR_LPVFPE ((uint32_t)0x00000400U) /*!< Low-power Vertical Front-porch Enable */
#define DSI_VMCCR_LPVAE ((uint32_t)0x00000800U) /*!< Low-power Vertical Active Enable */
#define DSI_VMCCR_LPHBPE ((uint32_t)0x00001000U) /*!< Low-power Horizontal Back-porch Enable */
#define DSI_VMCCR_LPHFE ((uint32_t)0x00002000U) /*!< Low-power Horizontal Front-porch Enable */
#define DSI_VMCCR_FBTAAE ((uint32_t)0x00004000U) /*!< Frame BTA Acknowledge Enable */
#define DSI_VMCCR_LPCE ((uint32_t)0x00008000U) /*!< Low-power Command Enable */
/******************* Bit definition for DSI_VPCCR register **************/
#define DSI_VPCCR_VPSIZE ((uint32_t)0x00003FFFU) /*!< Video Packet Size */
#define DSI_VPCCR_VPSIZE0 ((uint32_t)0x00000001U)
#define DSI_VPCCR_VPSIZE1 ((uint32_t)0x00000002U)
#define DSI_VPCCR_VPSIZE2 ((uint32_t)0x00000004U)
#define DSI_VPCCR_VPSIZE3 ((uint32_t)0x00000008U)
#define DSI_VPCCR_VPSIZE4 ((uint32_t)0x00000010U)
#define DSI_VPCCR_VPSIZE5 ((uint32_t)0x00000020U)
#define DSI_VPCCR_VPSIZE6 ((uint32_t)0x00000040U)
#define DSI_VPCCR_VPSIZE7 ((uint32_t)0x00000080U)
#define DSI_VPCCR_VPSIZE8 ((uint32_t)0x00000100U)
#define DSI_VPCCR_VPSIZE9 ((uint32_t)0x00000200U)
#define DSI_VPCCR_VPSIZE10 ((uint32_t)0x00000400U)
#define DSI_VPCCR_VPSIZE11 ((uint32_t)0x00000800U)
#define DSI_VPCCR_VPSIZE12 ((uint32_t)0x00001000U)
#define DSI_VPCCR_VPSIZE13 ((uint32_t)0x00002000U)
/******************* Bit definition for DSI_VCCCR register **************/
#define DSI_VCCCR_NUMC ((uint32_t)0x00001FFFU) /*!< Number of Chunks */
#define DSI_VCCCR_NUMC0 ((uint32_t)0x00000001U)
#define DSI_VCCCR_NUMC1 ((uint32_t)0x00000002U)
#define DSI_VCCCR_NUMC2 ((uint32_t)0x00000004U)
#define DSI_VCCCR_NUMC3 ((uint32_t)0x00000008U)
#define DSI_VCCCR_NUMC4 ((uint32_t)0x00000010U)
#define DSI_VCCCR_NUMC5 ((uint32_t)0x00000020U)
#define DSI_VCCCR_NUMC6 ((uint32_t)0x00000040U)
#define DSI_VCCCR_NUMC7 ((uint32_t)0x00000080U)
#define DSI_VCCCR_NUMC8 ((uint32_t)0x00000100U)
#define DSI_VCCCR_NUMC9 ((uint32_t)0x00000200U)
#define DSI_VCCCR_NUMC10 ((uint32_t)0x00000400U)
#define DSI_VCCCR_NUMC11 ((uint32_t)0x00000800U)
#define DSI_VCCCR_NUMC12 ((uint32_t)0x00001000U)
/******************* Bit definition for DSI_VNPCCR register *************/
#define DSI_VNPCCR_NPSIZE ((uint32_t)0x00001FFFU) /*!< Number of Chunks */
#define DSI_VNPCCR_NPSIZE0 ((uint32_t)0x00000001U)
#define DSI_VNPCCR_NPSIZE1 ((uint32_t)0x00000002U)
#define DSI_VNPCCR_NPSIZE2 ((uint32_t)0x00000004U)
#define DSI_VNPCCR_NPSIZE3 ((uint32_t)0x00000008U)
#define DSI_VNPCCR_NPSIZE4 ((uint32_t)0x00000010U)
#define DSI_VNPCCR_NPSIZE5 ((uint32_t)0x00000020U)
#define DSI_VNPCCR_NPSIZE6 ((uint32_t)0x00000040U)
#define DSI_VNPCCR_NPSIZE7 ((uint32_t)0x00000080U)
#define DSI_VNPCCR_NPSIZE8 ((uint32_t)0x00000100U)
#define DSI_VNPCCR_NPSIZE9 ((uint32_t)0x00000200U)
#define DSI_VNPCCR_NPSIZE10 ((uint32_t)0x00000400U)
#define DSI_VNPCCR_NPSIZE11 ((uint32_t)0x00000800U)
#define DSI_VNPCCR_NPSIZE12 ((uint32_t)0x00001000U)
/******************* Bit definition for DSI_VHSACCR register ************/
#define DSI_VHSACCR_HSA ((uint32_t)0x00000FFFU) /*!< Horizontal Synchronism Active duration */
#define DSI_VHSACCR_HSA0 ((uint32_t)0x00000001U)
#define DSI_VHSACCR_HSA1 ((uint32_t)0x00000002U)
#define DSI_VHSACCR_HSA2 ((uint32_t)0x00000004U)
#define DSI_VHSACCR_HSA3 ((uint32_t)0x00000008U)
#define DSI_VHSACCR_HSA4 ((uint32_t)0x00000010U)
#define DSI_VHSACCR_HSA5 ((uint32_t)0x00000020U)
#define DSI_VHSACCR_HSA6 ((uint32_t)0x00000040U)
#define DSI_VHSACCR_HSA7 ((uint32_t)0x00000080U)
#define DSI_VHSACCR_HSA8 ((uint32_t)0x00000100U)
#define DSI_VHSACCR_HSA9 ((uint32_t)0x00000200U)
#define DSI_VHSACCR_HSA10 ((uint32_t)0x00000400U)
#define DSI_VHSACCR_HSA11 ((uint32_t)0x00000800U)
/******************* Bit definition for DSI_VHBPCCR register ************/
#define DSI_VHBPCCR_HBP ((uint32_t)0x00000FFFU) /*!< Horizontal Back-Porch duration */
#define DSI_VHBPCCR_HBP0 ((uint32_t)0x00000001U)
#define DSI_VHBPCCR_HBP1 ((uint32_t)0x00000002U)
#define DSI_VHBPCCR_HBP2 ((uint32_t)0x00000004U)
#define DSI_VHBPCCR_HBP3 ((uint32_t)0x00000008U)
#define DSI_VHBPCCR_HBP4 ((uint32_t)0x00000010U)
#define DSI_VHBPCCR_HBP5 ((uint32_t)0x00000020U)
#define DSI_VHBPCCR_HBP6 ((uint32_t)0x00000040U)
#define DSI_VHBPCCR_HBP7 ((uint32_t)0x00000080U)
#define DSI_VHBPCCR_HBP8 ((uint32_t)0x00000100U)
#define DSI_VHBPCCR_HBP9 ((uint32_t)0x00000200U)
#define DSI_VHBPCCR_HBP10 ((uint32_t)0x00000400U)
#define DSI_VHBPCCR_HBP11 ((uint32_t)0x00000800U)
/******************* Bit definition for DSI_VLCCR register **************/
#define DSI_VLCCR_HLINE ((uint32_t)0x00007FFFU) /*!< Horizontal Line duration */
#define DSI_VLCCR_HLINE0 ((uint32_t)0x00000001U)
#define DSI_VLCCR_HLINE1 ((uint32_t)0x00000002U)
#define DSI_VLCCR_HLINE2 ((uint32_t)0x00000004U)
#define DSI_VLCCR_HLINE3 ((uint32_t)0x00000008U)
#define DSI_VLCCR_HLINE4 ((uint32_t)0x00000010U)
#define DSI_VLCCR_HLINE5 ((uint32_t)0x00000020U)
#define DSI_VLCCR_HLINE6 ((uint32_t)0x00000040U)
#define DSI_VLCCR_HLINE7 ((uint32_t)0x00000080U)
#define DSI_VLCCR_HLINE8 ((uint32_t)0x00000100U)
#define DSI_VLCCR_HLINE9 ((uint32_t)0x00000200U)
#define DSI_VLCCR_HLINE10 ((uint32_t)0x00000400U)
#define DSI_VLCCR_HLINE11 ((uint32_t)0x00000800U)
#define DSI_VLCCR_HLINE12 ((uint32_t)0x00001000U)
#define DSI_VLCCR_HLINE13 ((uint32_t)0x00002000U)
#define DSI_VLCCR_HLINE14 ((uint32_t)0x00004000U)
/******************* Bit definition for DSI_VVSACCR register ***************/
#define DSI_VVSACCR_VSA ((uint32_t)0x000003FFU) /*!< Vertical Synchronism Active duration */
#define DSI_VVSACCR_VSA0 ((uint32_t)0x00000001U)
#define DSI_VVSACCR_VSA1 ((uint32_t)0x00000002U)
#define DSI_VVSACCR_VSA2 ((uint32_t)0x00000004U)
#define DSI_VVSACCR_VSA3 ((uint32_t)0x00000008U)
#define DSI_VVSACCR_VSA4 ((uint32_t)0x00000010U)
#define DSI_VVSACCR_VSA5 ((uint32_t)0x00000020U)
#define DSI_VVSACCR_VSA6 ((uint32_t)0x00000040U)
#define DSI_VVSACCR_VSA7 ((uint32_t)0x00000080U)
#define DSI_VVSACCR_VSA8 ((uint32_t)0x00000100U)
#define DSI_VVSACCR_VSA9 ((uint32_t)0x00000200U)
/******************* Bit definition for DSI_VVBPCCR register ************/
#define DSI_VVBPCCR_VBP ((uint32_t)0x000003FFU) /*!< Vertical Back-Porch duration */
#define DSI_VVBPCCR_VBP0 ((uint32_t)0x00000001U)
#define DSI_VVBPCCR_VBP1 ((uint32_t)0x00000002U)
#define DSI_VVBPCCR_VBP2 ((uint32_t)0x00000004U)
#define DSI_VVBPCCR_VBP3 ((uint32_t)0x00000008U)
#define DSI_VVBPCCR_VBP4 ((uint32_t)0x00000010U)
#define DSI_VVBPCCR_VBP5 ((uint32_t)0x00000020U)
#define DSI_VVBPCCR_VBP6 ((uint32_t)0x00000040U)
#define DSI_VVBPCCR_VBP7 ((uint32_t)0x00000080U)
#define DSI_VVBPCCR_VBP8 ((uint32_t)0x00000100U)
#define DSI_VVBPCCR_VBP9 ((uint32_t)0x00000200U)
/******************* Bit definition for DSI_VVFPCCR register ************/
#define DSI_VVFPCCR_VFP ((uint32_t)0x000003FFU) /*!< Vertical Front-Porch duration */
#define DSI_VVFPCCR_VFP0 ((uint32_t)0x00000001U)
#define DSI_VVFPCCR_VFP1 ((uint32_t)0x00000002U)
#define DSI_VVFPCCR_VFP2 ((uint32_t)0x00000004U)
#define DSI_VVFPCCR_VFP3 ((uint32_t)0x00000008U)
#define DSI_VVFPCCR_VFP4 ((uint32_t)0x00000010U)
#define DSI_VVFPCCR_VFP5 ((uint32_t)0x00000020U)
#define DSI_VVFPCCR_VFP6 ((uint32_t)0x00000040U)
#define DSI_VVFPCCR_VFP7 ((uint32_t)0x00000080U)
#define DSI_VVFPCCR_VFP8 ((uint32_t)0x00000100U)
#define DSI_VVFPCCR_VFP9 ((uint32_t)0x00000200U)
/******************* Bit definition for DSI_VVACCR register *************/
#define DSI_VVACCR_VA ((uint32_t)0x00003FFFU) /*!< Vertical Active duration */
#define DSI_VVACCR_VA0 ((uint32_t)0x00000001U)
#define DSI_VVACCR_VA1 ((uint32_t)0x00000002U)
#define DSI_VVACCR_VA2 ((uint32_t)0x00000004U)
#define DSI_VVACCR_VA3 ((uint32_t)0x00000008U)
#define DSI_VVACCR_VA4 ((uint32_t)0x00000010U)
#define DSI_VVACCR_VA5 ((uint32_t)0x00000020U)
#define DSI_VVACCR_VA6 ((uint32_t)0x00000040U)
#define DSI_VVACCR_VA7 ((uint32_t)0x00000080U)
#define DSI_VVACCR_VA8 ((uint32_t)0x00000100U)
#define DSI_VVACCR_VA9 ((uint32_t)0x00000200U)
#define DSI_VVACCR_VA10 ((uint32_t)0x00000400U)
#define DSI_VVACCR_VA11 ((uint32_t)0x00000800U)
#define DSI_VVACCR_VA12 ((uint32_t)0x00001000U)
#define DSI_VVACCR_VA13 ((uint32_t)0x00002000U)
/******************* Bit definition for DSI_TDCCR register **************/
#define DSI_TDCCR_3DM ((uint32_t)0x00000003U) /*!< 3D Mode */
#define DSI_TDCCR_3DM0 ((uint32_t)0x00000001U)
#define DSI_TDCCR_3DM1 ((uint32_t)0x00000002U)
#define DSI_TDCCR_3DF ((uint32_t)0x0000000CU) /*!< 3D Format */
#define DSI_TDCCR_3DF0 ((uint32_t)0x00000004U)
#define DSI_TDCCR_3DF1 ((uint32_t)0x00000008U)
#define DSI_TDCCR_SVS ((uint32_t)0x00000010U) /*!< Second VSYNC */
#define DSI_TDCCR_RF ((uint32_t)0x00000020U) /*!< Right First */
#define DSI_TDCCR_S3DC ((uint32_t)0x00010000U) /*!< Send 3D Control */
/******************* Bit definition for DSI_WCFGR register ***************/
#define DSI_WCFGR_DSIM ((uint32_t)0x00000001U) /*!< DSI Mode */
#define DSI_WCFGR_COLMUX ((uint32_t)0x0000000EU) /*!< Color Multiplexing */
#define DSI_WCFGR_COLMUX0 ((uint32_t)0x00000002U)
#define DSI_WCFGR_COLMUX1 ((uint32_t)0x00000004U)
#define DSI_WCFGR_COLMUX2 ((uint32_t)0x00000008U)
#define DSI_WCFGR_TESRC ((uint32_t)0x00000010U) /*!< Tearing Effect Source */
#define DSI_WCFGR_TEPOL ((uint32_t)0x00000020U) /*!< Tearing Effect Polarity */
#define DSI_WCFGR_AR ((uint32_t)0x00000040U) /*!< Automatic Refresh */
#define DSI_WCFGR_VSPOL ((uint32_t)0x00000080U) /*!< VSync Polarity */
/******************* Bit definition for DSI_WCR register *****************/
#define DSI_WCR_COLM ((uint32_t)0x00000001U) /*!< Color Mode */
#define DSI_WCR_SHTDN ((uint32_t)0x00000002U) /*!< Shutdown */
#define DSI_WCR_LTDCEN ((uint32_t)0x00000004U) /*!< LTDC Enable */
#define DSI_WCR_DSIEN ((uint32_t)0x00000008U) /*!< DSI Enable */
/******************* Bit definition for DSI_WIER register ****************/
#define DSI_WIER_TEIE ((uint32_t)0x00000001U) /*!< Tearing Effect Interrupt Enable */
#define DSI_WIER_ERIE ((uint32_t)0x00000002U) /*!< End of Refresh Interrupt Enable */
#define DSI_WIER_PLLLIE ((uint32_t)0x00000200U) /*!< PLL Lock Interrupt Enable */
#define DSI_WIER_PLLUIE ((uint32_t)0x00000400U) /*!< PLL Unlock Interrupt Enable */
#define DSI_WIER_RRIE ((uint32_t)0x00002000U) /*!< Regulator Ready Interrupt Enable */
/******************* Bit definition for DSI_WISR register ****************/
#define DSI_WISR_TEIF ((uint32_t)0x00000001U) /*!< Tearing Effect Interrupt Flag */
#define DSI_WISR_ERIF ((uint32_t)0x00000002U) /*!< End of Refresh Interrupt Flag */
#define DSI_WISR_BUSY ((uint32_t)0x00000004U) /*!< Busy Flag */
#define DSI_WISR_PLLLS ((uint32_t)0x00000100U) /*!< PLL Lock Status */
#define DSI_WISR_PLLLIF ((uint32_t)0x00000200U) /*!< PLL Lock Interrupt Flag */
#define DSI_WISR_PLLUIF ((uint32_t)0x00000400U) /*!< PLL Unlock Interrupt Flag */
#define DSI_WISR_RRS ((uint32_t)0x00001000U) /*!< Regulator Ready Flag */
#define DSI_WISR_RRIF ((uint32_t)0x00002000U) /*!< Regulator Ready Interrupt Flag */
/******************* Bit definition for DSI_WIFCR register ***************/
#define DSI_WIFCR_CTEIF ((uint32_t)0x00000001U) /*!< Clear Tearing Effect Interrupt Flag */
#define DSI_WIFCR_CERIF ((uint32_t)0x00000002U) /*!< Clear End of Refresh Interrupt Flag */
#define DSI_WIFCR_CPLLLIF ((uint32_t)0x00000200U) /*!< Clear PLL Lock Interrupt Flag */
#define DSI_WIFCR_CPLLUIF ((uint32_t)0x00000400U) /*!< Clear PLL Unlock Interrupt Flag */
#define DSI_WIFCR_CRRIF ((uint32_t)0x00002000U) /*!< Clear Regulator Ready Interrupt Flag */
/******************* Bit definition for DSI_WPCR0 register ***************/
#define DSI_WPCR0_UIX4 ((uint32_t)0x0000003FU) /*!< Unit Interval multiplied by 4 */
#define DSI_WPCR0_UIX4_0 ((uint32_t)0x00000001U)
#define DSI_WPCR0_UIX4_1 ((uint32_t)0x00000002U)
#define DSI_WPCR0_UIX4_2 ((uint32_t)0x00000004U)
#define DSI_WPCR0_UIX4_3 ((uint32_t)0x00000008U)
#define DSI_WPCR0_UIX4_4 ((uint32_t)0x00000010U)
#define DSI_WPCR0_UIX4_5 ((uint32_t)0x00000020U)
#define DSI_WPCR0_SWCL ((uint32_t)0x00000040U) /*!< Swap pins on clock lane */
#define DSI_WPCR0_SWDL0 ((uint32_t)0x00000080U) /*!< Swap pins on data lane 1 */
#define DSI_WPCR0_SWDL1 ((uint32_t)0x00000100U) /*!< Swap pins on data lane 2 */
#define DSI_WPCR0_HSICL ((uint32_t)0x00000200U) /*!< Invert the high-speed data signal on clock lane */
#define DSI_WPCR0_HSIDL0 ((uint32_t)0x00000400U) /*!< Invert the high-speed data signal on lane 1 */
#define DSI_WPCR0_HSIDL1 ((uint32_t)0x00000800U) /*!< Invert the high-speed data signal on lane 2 */
#define DSI_WPCR0_FTXSMCL ((uint32_t)0x00001000U) /*!< Force clock lane in TX stop mode */
#define DSI_WPCR0_FTXSMDL ((uint32_t)0x00002000U) /*!< Force data lanes in TX stop mode */
#define DSI_WPCR0_CDOFFDL ((uint32_t)0x00004000U) /*!< Contention detection OFF */
#define DSI_WPCR0_TDDL ((uint32_t)0x00010000U) /*!< Turn Disable Data Lanes */
/******************* Bit definition for DSI_WPCR1 register ***************/
#define DSI_WPCR1_SKEWCL ((uint32_t)0x00000003U) /*!< Skew on Clock Lanes */
#define DSI_WPCR1_SKEWCL0 ((uint32_t)0x00000001U)
#define DSI_WPCR1_SKEWCL1 ((uint32_t)0x00000002U)
#define DSI_WPCR1_SKEWDL ((uint32_t)0x0000000CU) /*!< Skew on Data Lanes */
#define DSI_WPCR1_SKEWDL0 ((uint32_t)0x00000004U)
#define DSI_WPCR1_SKEWDL1 ((uint32_t)0x00000008U)
#define DSI_WPCR1_LPTXSRCL ((uint32_t)0x000000C0U) /*!< Low-Power TX Slew Rate on Clock Lanes */
#define DSI_WPCR1_LPTXSRCL0 ((uint32_t)0x00000040U)
#define DSI_WPCR1_LPTXSRCL1 ((uint32_t)0x00000080U)
#define DSI_WPCR1_LPTXSRDL ((uint32_t)0x00000300U) /*!< Low-Power TX Slew Rate on Data Lanes */
#define DSI_WPCR1_LPTXSRDL0 ((uint32_t)0x00000100U)
#define DSI_WPCR1_LPTXSRDL1 ((uint32_t)0x00000200U)
#define DSI_WPCR1_SDDCCL ((uint32_t)0x00001000U) /*!< SDD Control Clock Lane */
#define DSI_WPCR1_SDDCDL ((uint32_t)0x00002000U) /*!< SDD Control Data Lanes */
#define DSI_WPCR1_HSTXSRUCL ((uint32_t)0x00010000U) /*!< High-Speed TX Slew-Rate Up Clock Lane */
#define DSI_WPCR1_HSTXSRDCL ((uint32_t)0x00020000U) /*!< High-Speed TX Slew-Rate Down Clock Lane */
#define DSI_WPCR1_HSTXSRUDL ((uint32_t)0x00040000U) /*!< High-Speed TX Slew-Rate Up Data Lane */
#define DSI_WPCR1_HSTXSRDDL ((uint32_t)0x00080000U) /*!< High-Speed TX Slew-Rate Down Data Lane */
/******************* Bit definition for DSI_WRPCR register ***************/
#define DSI_WRPCR_PLLEN ((uint32_t)0x00000001U) /*!< PLL Enable */
#define DSI_WRPCR_PLL_NDIV ((uint32_t)0x000001FCU) /*!< PLL Loop Division Factor */
#define DSI_WRPCR_PLL_NDIV0 ((uint32_t)0x00000004U)
#define DSI_WRPCR_PLL_NDIV1 ((uint32_t)0x00000008U)
#define DSI_WRPCR_PLL_NDIV2 ((uint32_t)0x00000010U)
#define DSI_WRPCR_PLL_NDIV3 ((uint32_t)0x00000020U)
#define DSI_WRPCR_PLL_NDIV4 ((uint32_t)0x00000040U)
#define DSI_WRPCR_PLL_NDIV5 ((uint32_t)0x00000080U)
#define DSI_WRPCR_PLL_NDIV6 ((uint32_t)0x00000100U)
#define DSI_WRPCR_PLL_IDF ((uint32_t)0x00007800U) /*!< PLL Input Division Factor */
#define DSI_WRPCR_PLL_IDF0 ((uint32_t)0x00000800U)
#define DSI_WRPCR_PLL_IDF1 ((uint32_t)0x00001000U)
#define DSI_WRPCR_PLL_IDF2 ((uint32_t)0x00002000U)
#define DSI_WRPCR_PLL_IDF3 ((uint32_t)0x00004000U)
#define DSI_WRPCR_PLL_ODF ((uint32_t)0x00030000U) /*!< PLL Output Division Factor */
#define DSI_WRPCR_PLL_ODF0 ((uint32_t)0x00010000U)
#define DSI_WRPCR_PLL_ODF1 ((uint32_t)0x00020000U)
#define DSI_WRPCR_REGEN ((uint32_t)0x01000000U) /*!< Regulator Enable */
#define DSI_WRPCR_BGREN ((uint32_t)0x10000000U) /*!< Bandgap Enable */
/********************** Bit definition for DSI_HWCFGR register ***************/
#define DSI_HWCFGR_TECHNO_Pos (0U)
#define DSI_HWCFGR_TECHNO_Msk (0xFU << DSI_HWCFGR_TECHNO_Pos) /*!< 0x0000000F */
#define DSI_HWCFGR_TECHNO DSI_HWCFGR_TECHNO_Msk /*!< Size of the payload FIFO */
#define DSI_HWCFGR_FIFOSIZE_Pos (4U)
#define DSI_HWCFGR_FIFOSIZE_Msk (0xFFFU << DSI_HWCFGR_FIFOSIZE_Pos) /*!< 0x0000FFF0 */
#define DSI_HWCFGR_FIFOSIZE DSI_HWCFGR_FIFOSIZE_Msk /*!< Technology used. */
/********************** Bit definition for DSI_VERR register *****************/
#define DSI_VERR_MINREV_Pos (0U)
#define DSI_VERR_MINREV_Msk (0xFU << DSI_VERR_MINREV_Pos) /*!< 0x0000000F */
#define DSI_VERR_MINREV DSI_VERR_MINREV_Msk /*!< Minor Revision number */
#define DSI_VERR_MAJREV_Pos (4U)
#define DSI_VERR_MAJREV_Msk (0xFU << DSI_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define DSI_VERR_MAJREV DSI_VERR_MAJREV_Msk /*!< Major Revision number */
/********************** Bit definition for DSI_IPIDR register ****************/
#define DSI_IPIDR_IPID_Pos (0U)
#define DSI_IPIDR_IPID_Msk (0xFFFFFFFFU << DSI_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
#define DSI_IPIDR_IPID DSI_IPIDR_IPID_Msk /*!< IP Identification */
/********************** Bit definition for DSI_SIDR register *****************/
#define DSI_SIDR_SID_Pos (0U)
#define DSI_SIDR_SID_Msk (0xFFFFFFFFU << DSI_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define DSI_SIDR_SID DSI_SIDR_SID_Msk /*!< IP size identification */
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
/******************* Bit definition for EXTI_IMR1 register *******************/
#define EXTI_IMR1_IM0_Pos (0U)
#define EXTI_IMR1_IM0_Msk (0x1U << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
#define EXTI_IMR1_IM1_Pos (1U)
#define EXTI_IMR1_IM1_Msk (0x1U << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
#define EXTI_IMR1_IM2_Pos (2U)
#define EXTI_IMR1_IM2_Msk (0x1U << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
#define EXTI_IMR1_IM3_Pos (3U)
#define EXTI_IMR1_IM3_Msk (0x1U << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
#define EXTI_IMR1_IM4_Pos (4U)
#define EXTI_IMR1_IM4_Msk (0x1U << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
#define EXTI_IMR1_IM5_Pos (5U)
#define EXTI_IMR1_IM5_Msk (0x1U << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
#define EXTI_IMR1_IM6_Pos (6U)
#define EXTI_IMR1_IM6_Msk (0x1U << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
#define EXTI_IMR1_IM7_Pos (7U)
#define EXTI_IMR1_IM7_Msk (0x1U << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
#define EXTI_IMR1_IM8_Pos (8U)
#define EXTI_IMR1_IM8_Msk (0x1U << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
#define EXTI_IMR1_IM9_Pos (9U)
#define EXTI_IMR1_IM9_Msk (0x1U << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
#define EXTI_IMR1_IM10_Pos (10U)
#define EXTI_IMR1_IM10_Msk (0x1U << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
#define EXTI_IMR1_IM11_Pos (11U)
#define EXTI_IMR1_IM11_Msk (0x1U << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
#define EXTI_IMR1_IM12_Pos (12U)
#define EXTI_IMR1_IM12_Msk (0x1U << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
#define EXTI_IMR1_IM13_Pos (13U)
#define EXTI_IMR1_IM13_Msk (0x1U << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
#define EXTI_IMR1_IM14_Pos (14U)
#define EXTI_IMR1_IM14_Msk (0x1U << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
#define EXTI_IMR1_IM15_Pos (15U)
#define EXTI_IMR1_IM15_Msk (0x1U << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
#define EXTI_IMR1_IM16_Pos (16U)
#define EXTI_IMR1_IM16_Msk (0x1U << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
#define EXTI_IMR1_IM17_Pos (17U)
#define EXTI_IMR1_IM17_Msk (0x1U << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
#define EXTI_IMR1_IM18_Pos (18U)
#define EXTI_IMR1_IM18_Msk (0x1U << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
#define EXTI_IMR1_IM19_Pos (19U)
#define EXTI_IMR1_IM19_Msk (0x1U << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
#define EXTI_IMR1_IM20_Pos (20U)
#define EXTI_IMR1_IM20_Msk (0x1U << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
#define EXTI_IMR1_IM21_Pos (21U)
#define EXTI_IMR1_IM21_Msk (0x1U << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
#define EXTI_IMR1_IM22_Pos (22U)
#define EXTI_IMR1_IM22_Msk (0x1U << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
#define EXTI_IMR1_IM23_Pos (23U)
#define EXTI_IMR1_IM23_Msk (0x1U << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
#define EXTI_IMR1_IM24_Pos (24U)
#define EXTI_IMR1_IM24_Msk (0x1U << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
#define EXTI_IMR1_IM25_Pos (25U)
#define EXTI_IMR1_IM25_Msk (0x1U << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
#define EXTI_IMR1_IM26_Pos (26U)
#define EXTI_IMR1_IM26_Msk (0x1U << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
#define EXTI_IMR1_IM27_Pos (27U)
#define EXTI_IMR1_IM27_Msk (0x1U << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
#define EXTI_IMR1_IM28_Pos (28U)
#define EXTI_IMR1_IM28_Msk (0x1U << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
#define EXTI_IMR1_IM29_Pos (29U)
#define EXTI_IMR1_IM29_Msk (0x1U << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
#define EXTI_IMR1_IM30_Pos (30U)
#define EXTI_IMR1_IM30_Msk (0x1U << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
#define EXTI_IMR1_IM31_Pos (31U)
#define EXTI_IMR1_IM31_Msk (0x1U << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
/******************* Bit definition for EXTI_IMR2 register *******************/
#define EXTI_IMR2_IM32_Pos (0U)
#define EXTI_IMR2_IM32_Msk (0x1U << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
#define EXTI_IMR2_IM33_Pos (1U)
#define EXTI_IMR2_IM33_Msk (0x1U << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
#define EXTI_IMR2_IM34_Pos (2U)
#define EXTI_IMR2_IM34_Msk (0x1U << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
#define EXTI_IMR2_IM35_Pos (3U)
#define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
#define EXTI_IMR2_IM36_Pos (4U)
#define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
#define EXTI_IMR2_IM37_Pos (5U)
#define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
#define EXTI_IMR2_IM38_Pos (6U)
#define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
#define EXTI_IMR2_IM39_Pos (7U)
#define EXTI_IMR2_IM39_Msk (0x1U << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
#define EXTI_IMR2_IM40_Pos (8U)
#define EXTI_IMR2_IM40_Msk (0x1U << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
#define EXTI_IMR2_IM41_Pos (9U)
#define EXTI_IMR2_IM41_Msk (0x1U << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */
#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< Interrupt Mask on line 41 */
#define EXTI_IMR2_IM42_Pos (10U)
#define EXTI_IMR2_IM42_Msk (0x1U << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */
#define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< Interrupt Mask on line 42 */
#define EXTI_IMR2_IM43_Pos (11U)
#define EXTI_IMR2_IM43_Msk (0x1U << EXTI_IMR2_IM43_Pos) /*!< 0x00000800 */
#define EXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk /*!< Interrupt Mask on line 43 */
#define EXTI_IMR2_IM44_Pos (12U)
#define EXTI_IMR2_IM44_Msk (0x1U << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */
#define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< Interrupt Mask on line 44 */
#define EXTI_IMR2_IM45_Pos (13U)
#define EXTI_IMR2_IM45_Msk (0x1U << EXTI_IMR2_IM45_Pos) /*!< 0x00002000 */
#define EXTI_IMR2_IM45 EXTI_IMR2_IM45_Msk /*!< Interrupt Mask on line 45 */
#define EXTI_IMR2_IM46_Pos (14U)
#define EXTI_IMR2_IM46_Msk (0x1U << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */
#define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< Interrupt Mask on line 46 */
#define EXTI_IMR2_IM47_Pos (15U)
#define EXTI_IMR2_IM47_Msk (0x1U << EXTI_IMR2_IM47_Pos) /*!< 0x00008000 */
#define EXTI_IMR2_IM47 EXTI_IMR2_IM47_Msk /*!< Interrupt Mask on line 47 */
#define EXTI_IMR2_IM48_Pos (16U)
#define EXTI_IMR2_IM48_Msk (0x1U << EXTI_IMR2_IM48_Pos) /*!< 0x00010000 */
#define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk /*!< Interrupt Mask on line 48 */
#define EXTI_IMR2_IM49_Pos (17U)
#define EXTI_IMR2_IM49_Msk (0x1U << EXTI_IMR2_IM49_Pos) /*!< 0x00020000 */
#define EXTI_IMR2_IM49 EXTI_IMR2_IM49_Msk /*!< Interrupt Mask on line 49 */
#define EXTI_IMR2_IM50_Pos (18U)
#define EXTI_IMR2_IM50_Msk (0x1U << EXTI_IMR2_IM50_Pos) /*!< 0x00040000 */
#define EXTI_IMR2_IM50 EXTI_IMR2_IM50_Msk /*!< Interrupt Mask on line 50 */
#define EXTI_IMR2_IM51_Pos (19U)
#define EXTI_IMR2_IM51_Msk (0x1U << EXTI_IMR2_IM51_Pos) /*!< 0x00080000 */
#define EXTI_IMR2_IM51 EXTI_IMR2_IM51_Msk /*!< Interrupt Mask on line 51 */
#define EXTI_IMR2_IM52_Pos (20U)
#define EXTI_IMR2_IM52_Msk (0x1U << EXTI_IMR2_IM52_Pos) /*!< 0x00100000 */
#define EXTI_IMR2_IM52 EXTI_IMR2_IM52_Msk /*!< Interrupt Mask on line 52 */
#define EXTI_IMR2_IM53_Pos (21U)
#define EXTI_IMR2_IM53_Msk (0x1U << EXTI_IMR2_IM53_Pos) /*!< 0x00200000 */
#define EXTI_IMR2_IM53 EXTI_IMR2_IM53_Msk /*!< Interrupt Mask on line 53 */
#define EXTI_IMR2_IM54_Pos (22U)
#define EXTI_IMR2_IM54_Msk (0x1U << EXTI_IMR2_IM54_Pos) /*!< 0x00400000 */
#define EXTI_IMR2_IM54 EXTI_IMR2_IM54_Msk /*!< Interrupt Mask on line 54 */
#define EXTI_IMR2_IM55_Pos (23U)
#define EXTI_IMR2_IM55_Msk (0x1U << EXTI_IMR2_IM55_Pos) /*!< 0x00800000 */
#define EXTI_IMR2_IM55 EXTI_IMR2_IM55_Msk /*!< Interrupt Mask on line 55 */
#define EXTI_IMR2_IM56_Pos (24U)
#define EXTI_IMR2_IM56_Msk (0x1U << EXTI_IMR2_IM56_Pos) /*!< 0x01000000 */
#define EXTI_IMR2_IM56 EXTI_IMR2_IM56_Msk /*!< Interrupt Mask on line 56 */
#define EXTI_IMR2_IM57_Pos (25U)
#define EXTI_IMR2_IM57_Msk (0x1U << EXTI_IMR2_IM57_Pos) /*!< 0x02000000 */
#define EXTI_IMR2_IM57 EXTI_IMR2_IM57_Msk /*!< Interrupt Mask on line 57 */
#define EXTI_IMR2_IM58_Pos (26U)
#define EXTI_IMR2_IM58_Msk (0x1U << EXTI_IMR2_IM58_Pos) /*!< 0x04000000 */
#define EXTI_IMR2_IM58 EXTI_IMR2_IM58_Msk /*!< Interrupt Mask on line 58 */
#define EXTI_IMR2_IM59_Pos (27U)
#define EXTI_IMR2_IM59_Msk (0x1U << EXTI_IMR2_IM59_Pos) /*!< 0x08000000 */
#define EXTI_IMR2_IM59 EXTI_IMR2_IM59_Msk /*!< Interrupt Mask on line 59 */
#define EXTI_IMR2_IM60_Pos (28U)
#define EXTI_IMR2_IM60_Msk (0x1U << EXTI_IMR2_IM60_Pos) /*!< 0x10000000 */
#define EXTI_IMR2_IM60 EXTI_IMR2_IM60_Msk /*!< Interrupt Mask on line 60 */
#define EXTI_IMR2_IM61_Pos (29U)
#define EXTI_IMR2_IM61_Msk (0x1U << EXTI_IMR2_IM61_Pos) /*!< 0x20000000 */
#define EXTI_IMR2_IM61 EXTI_IMR2_IM61_Msk /*!< Interrupt Mask on line 61 */
#define EXTI_IMR2_IM62_Pos (30U)
#define EXTI_IMR2_IM62_Msk (0x1U << EXTI_IMR2_IM62_Pos) /*!< 0x40000000 */
#define EXTI_IMR2_IM62 EXTI_IMR2_IM62_Msk /*!< Interrupt Mask on line 62 */
#define EXTI_IMR2_IM63_Pos (31U)
#define EXTI_IMR2_IM63_Msk (0x1U << EXTI_IMR2_IM63_Pos) /*!< 0x80000000 */
#define EXTI_IMR2_IM63 EXTI_IMR2_IM63_Msk /*!< Interrupt Mask on line 63 */
/******************* Bit definition for EXTI_IMR3 register *******************/
#define EXTI_IMR3_IM64_Pos (0U)
#define EXTI_IMR3_IM64_Msk (0x1U << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */
#define EXTI_IMR3_IM64 EXTI_IMR3_IM64_Msk /*!< Interrupt Mask on line 64 */
#define EXTI_IMR3_IM65_Pos (1U)
#define EXTI_IMR3_IM65_Msk (0x1U << EXTI_IMR3_IM65_Pos) /*!< 0x00000002 */
#define EXTI_IMR3_IM65 EXTI_IMR3_IM65_Msk /*!< Interrupt Mask on line 65 */
#define EXTI_IMR3_IM66_Pos (2U)
#define EXTI_IMR3_IM66_Msk (0x1U << EXTI_IMR3_IM66_Pos) /*!< 0x00000004 */
#define EXTI_IMR3_IM66 EXTI_IMR3_IM66_Msk /*!< Interrupt Mask on line 66 */
#define EXTI_IMR3_IM67_Pos (3U)
#define EXTI_IMR3_IM67_Msk (0x1U << EXTI_IMR3_IM67_Pos) /*!< 0x00000008 */
#define EXTI_IMR3_IM67 EXTI_IMR3_IM67_Msk /*!< Interrupt Mask on line 67 */
#define EXTI_IMR3_IM68_Pos (4U)
#define EXTI_IMR3_IM68_Msk (0x1U << EXTI_IMR3_IM68_Pos) /*!< 0x00000010 */
#define EXTI_IMR3_IM68 EXTI_IMR3_IM68_Msk /*!< Interrupt Mask on line 68 */
#define EXTI_IMR3_IM69_Pos (5U)
#define EXTI_IMR3_IM69_Msk (0x1U << EXTI_IMR3_IM69_Pos) /*!< 0x00000020 */
#define EXTI_IMR3_IM69 EXTI_IMR3_IM69_Msk /*!< Interrupt Mask on line 69 */
#define EXTI_IMR3_IM70_Pos (6U)
#define EXTI_IMR3_IM70_Msk (0x1U << EXTI_IMR3_IM70_Pos) /*!< 0x00000040 */
#define EXTI_IMR3_IM70 EXTI_IMR3_IM70_Msk /*!< Interrupt Mask on line 70 */
#define EXTI_IMR3_IM71_Pos (7U)
#define EXTI_IMR3_IM71_Msk (0x1U << EXTI_IMR3_IM71_Pos) /*!< 0x00000080 */
#define EXTI_IMR3_IM71 EXTI_IMR3_IM71_Msk /*!< Interrupt Mask on line 71 */
#define EXTI_IMR3_IM72_Pos (8U)
#define EXTI_IMR3_IM72_Msk (0x1U << EXTI_IMR3_IM72_Pos) /*!< 0x00000100 */
#define EXTI_IMR3_IM72 EXTI_IMR3_IM72_Msk /*!< Interrupt Mask on line 72 */
#define EXTI_IMR3_IM73_Pos (9U)
#define EXTI_IMR3_IM73_Msk (0x1U << EXTI_IMR3_IM73_Pos) /*!< 0x00000200 */
#define EXTI_IMR3_IM73 EXTI_IMR3_IM73_Msk /*!< Interrupt Mask on line 73 */
#define EXTI_IMR3_IM74_Pos (10U)
#define EXTI_IMR3_IM74_Msk (0x1U << EXTI_IMR3_IM74_Pos) /*!< 0x00000400 */
#define EXTI_IMR3_IM74 EXTI_IMR3_IM74_Msk /*!< Interrupt Mask on line 74 */
#define EXTI_IMR3_IM75_Pos (11U)
#define EXTI_IMR3_IM75_Msk (0x1U << EXTI_IMR3_IM75_Pos) /*!< 0x00000800 */
#define EXTI_IMR3_IM75 EXTI_IMR3_IM75_Msk /*!< Interrupt Mask on line 75 */
#define EXTI_IMR3_IM76_Pos (12U)
#define EXTI_IMR3_IM76_Msk (0x1U << EXTI_IMR3_IM76_Pos) /*!< 0x00001000 */
#define EXTI_IMR3_IM76 EXTI_IMR3_IM76_Msk /*!< Interrupt Mask on line 76 */
#define EXTI_IMR3_IM77_Pos (13U)
#define EXTI_IMR3_IM77_Msk (0x1U << EXTI_IMR3_IM77_Pos) /*!< 0x00002000 */
#define EXTI_IMR3_IM77 EXTI_IMR3_IM77_Msk /*!< Interrupt Mask on line 77 */
#define EXTI_IMR3_IM78_Pos (14U)
#define EXTI_IMR3_IM78_Msk (0x1U << EXTI_IMR3_IM78_Pos) /*!< 0x00004000 */
#define EXTI_IMR3_IM78 EXTI_IMR3_IM78_Msk /*!< Interrupt Mask on line 78 */
#define EXTI_IMR3_IM79_Pos (15U)
#define EXTI_IMR3_IM79_Msk (0x1U << EXTI_IMR3_IM79_Pos) /*!< 0x00008000 */
#define EXTI_IMR3_IM79 EXTI_IMR3_IM79_Msk /*!< Interrupt Mask on line 79 */
#define EXTI_IMR3_IM80_Pos (16U)
#define EXTI_IMR3_IM80_Msk (0x1U << EXTI_IMR3_IM80_Pos) /*!< 0x00010000 */
#define EXTI_IMR3_IM80 EXTI_IMR3_IM80_Msk /*!< Interrupt Mask on line 80 */
#define EXTI_IMR3_IM81_Pos (17U)
#define EXTI_IMR3_IM81_Msk (0x1U << EXTI_IMR3_IM81_Pos) /*!< 0x00020000 */
#define EXTI_IMR3_IM81 EXTI_IMR3_IM81_Msk /*!< Interrupt Mask on line 81 */
#define EXTI_IMR3_IM82_Pos (18U)
#define EXTI_IMR3_IM82_Msk (0x1U << EXTI_IMR3_IM82_Pos) /*!< 0x00040000 */
#define EXTI_IMR3_IM82 EXTI_IMR3_IM82_Msk /*!< Interrupt Mask on line 82 */
#define EXTI_IMR3_IM84_Pos (20U)
#define EXTI_IMR3_IM84_Msk (0x1U << EXTI_IMR3_IM84_Pos) /*!< 0x00100000 */
#define EXTI_IMR3_IM84 EXTI_IMR3_IM84_Msk /*!< Interrupt Mask on line 84 */
#define EXTI_IMR3_IM85_Pos (21U)
#define EXTI_IMR3_IM85_Msk (0x1U << EXTI_IMR3_IM85_Pos) /*!< 0x00200000 */
#define EXTI_IMR3_IM85 EXTI_IMR3_IM85_Msk /*!< Interrupt Mask on line 85 */
#define EXTI_IMR3_IM86_Pos (22U)
#define EXTI_IMR3_IM86_Msk (0x1U << EXTI_IMR3_IM86_Pos) /*!< 0x00400000 */
#define EXTI_IMR3_IM86 EXTI_IMR3_IM86_Msk /*!< Interrupt Mask on line 86 */
#define EXTI_IMR3_IM87_Pos (23U)
#define EXTI_IMR3_IM87_Msk (0x1U << EXTI_IMR3_IM87_Pos) /*!< 0x00800000 */
#define EXTI_IMR3_IM87 EXTI_IMR3_IM87_Msk /*!< Interrupt Mask on line 87 */
#define EXTI_IMR3_IM88_Pos (24U)
#define EXTI_IMR3_IM88_Msk (0x1U << EXTI_IMR3_IM88_Pos) /*!< 0x01000000 */
#define EXTI_IMR3_IM88 EXTI_IMR3_IM88_Msk /*!< Interrupt Mask on line 88 */
/******************* Bit definition for EXTI_EMR1 register *******************/
#define EXTI_EMR1_EM0_Pos (0U)
#define EXTI_EMR1_EM0_Msk (0x1U << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
#define EXTI_EMR1_EM1_Pos (1U)
#define EXTI_EMR1_EM1_Msk (0x1U << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
#define EXTI_EMR1_EM2_Pos (2U)
#define EXTI_EMR1_EM2_Msk (0x1U << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
#define EXTI_EMR1_EM3_Pos (3U)
#define EXTI_EMR1_EM3_Msk (0x1U << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
#define EXTI_EMR1_EM4_Pos (4U)
#define EXTI_EMR1_EM4_Msk (0x1U << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
#define EXTI_EMR1_EM5_Pos (5U)
#define EXTI_EMR1_EM5_Msk (0x1U << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
#define EXTI_EMR1_EM6_Pos (6U)
#define EXTI_EMR1_EM6_Msk (0x1U << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
#define EXTI_EMR1_EM7_Pos (7U)
#define EXTI_EMR1_EM7_Msk (0x1U << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
#define EXTI_EMR1_EM8_Pos (8U)
#define EXTI_EMR1_EM8_Msk (0x1U << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
#define EXTI_EMR1_EM9_Pos (9U)
#define EXTI_EMR1_EM9_Msk (0x1U << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
#define EXTI_EMR1_EM10_Pos (10U)
#define EXTI_EMR1_EM10_Msk (0x1U << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
#define EXTI_EMR1_EM11_Pos (11U)
#define EXTI_EMR1_EM11_Msk (0x1U << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
#define EXTI_EMR1_EM12_Pos (12U)
#define EXTI_EMR1_EM12_Msk (0x1U << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
#define EXTI_EMR1_EM13_Pos (13U)
#define EXTI_EMR1_EM13_Msk (0x1U << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
#define EXTI_EMR1_EM14_Pos (14U)
#define EXTI_EMR1_EM14_Msk (0x1U << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
#define EXTI_EMR1_EM15_Pos (15U)
#define EXTI_EMR1_EM15_Msk (0x1U << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
#define EXTI_EMR1_EM16_Pos (16U)
#define EXTI_EMR1_EM16_Msk (0x1U << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
#define EXTI_EMR1_EM17_Pos (17U)
#define EXTI_EMR1_EM17_Msk (0x1U << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
#define EXTI_EMR1_EM18_Pos (18U)
#define EXTI_EMR1_EM18_Msk (0x1U << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
#define EXTI_EMR1_EM20_Pos (20U)
#define EXTI_EMR1_EM20_Msk (0x1U << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
#define EXTI_EMR1_EM21_Pos (21U)
#define EXTI_EMR1_EM21_Msk (0x1U << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
#define EXTI_EMR1_EM22_Pos (22U)
#define EXTI_EMR1_EM22_Msk (0x1U << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
#define EXTI_EMR1_EM23_Pos (23U)
#define EXTI_EMR1_EM23_Msk (0x1U << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
#define EXTI_EMR1_EM24_Pos (24U)
#define EXTI_EMR1_EM24_Msk (0x1U << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
#define EXTI_EMR1_EM25_Pos (25U)
#define EXTI_EMR1_EM25_Msk (0x1U << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
#define EXTI_EMR1_EM26_Pos (26U)
#define EXTI_EMR1_EM26_Msk (0x1U << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
#define EXTI_EMR1_EM27_Pos (27U)
#define EXTI_EMR1_EM27_Msk (0x1U << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
#define EXTI_EMR1_EM28_Pos (28U)
#define EXTI_EMR1_EM28_Msk (0x1U << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
#define EXTI_EMR1_EM29_Pos (29U)
#define EXTI_EMR1_EM29_Msk (0x1U << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
#define EXTI_EMR1_EM30_Pos (30U)
#define EXTI_EMR1_EM30_Msk (0x1U << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
#define EXTI_EMR1_EM31_Pos (31U)
#define EXTI_EMR1_EM31_Msk (0x1U << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
/******************* Bit definition for EXTI_EMR2 register *******************/
#define EXTI_EMR2_EM32_Pos (0U)
#define EXTI_EMR2_EM32_Msk (0x1U << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32*/
#define EXTI_EMR2_EM33_Pos (1U)
#define EXTI_EMR2_EM33_Msk (0x1U << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33*/
#define EXTI_EMR2_EM34_Pos (2U)
#define EXTI_EMR2_EM34_Msk (0x1U << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34*/
#define EXTI_EMR2_EM35_Pos (3U)
#define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35*/
#define EXTI_EMR2_EM36_Pos (4U)
#define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36*/
#define EXTI_EMR2_EM37_Pos (5U)
#define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37*/
#define EXTI_EMR2_EM38_Pos (6U)
#define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38*/
#define EXTI_EMR2_EM39_Pos (7U)
#define EXTI_EMR2_EM39_Msk (0x1U << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39*/
#define EXTI_EMR2_EM40_Pos (8U)
#define EXTI_EMR2_EM40_Msk (0x1U << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40*/
#define EXTI_EMR2_EM41_Pos (9U)
#define EXTI_EMR2_EM41_Msk (0x1U << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */
#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< Event Mask on line 41*/
#define EXTI_EMR2_EM42_Pos (10U)
#define EXTI_EMR2_EM42_Msk (0x1U << EXTI_EMR2_EM42_Pos) /*!< 0x00000400 */
#define EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk /*!< Event Mask on line 42 */
#define EXTI_EMR2_EM43_Pos (11U)
#define EXTI_EMR2_EM43_Msk (0x1U << EXTI_EMR2_EM43_Pos) /*!< 0x00000800 */
#define EXTI_EMR2_EM43 EXTI_EMR2_EM43_Msk /*!< Event Mask on line 43 */
#define EXTI_EMR2_EM44_Pos (12U)
#define EXTI_EMR2_EM44_Msk (0x1U << EXTI_EMR2_EM44_Pos) /*!< 0x00001000 */
#define EXTI_EMR2_EM44 EXTI_EMR2_EM44_Msk /*!< Event Mask on line 44 */
#define EXTI_EMR2_EM45_Pos (13U)
#define EXTI_EMR2_EM45_Msk (0x1U << EXTI_EMR2_EM45_Pos) /*!< 0x00002000 */
#define EXTI_EMR2_EM45 EXTI_EMR2_EM45_Msk /*!< Event Mask on line 45 */
#define EXTI_EMR2_EM46_Pos (14U)
#define EXTI_EMR2_EM46_Msk (0x1U << EXTI_EMR2_EM46_Pos) /*!< 0x00004000 */
#define EXTI_EMR2_EM46 EXTI_EMR2_EM46_Msk /*!< Event Mask on line 46 */
#define EXTI_EMR2_EM47_Pos (15U)
#define EXTI_EMR2_EM47_Msk (0x1U << EXTI_EMR2_EM47_Pos) /*!< 0x00008000 */
#define EXTI_EMR2_EM47 EXTI_EMR2_EM47_Msk /*!< Event Mask on line 47 */
#define EXTI_EMR2_EM48_Pos (16U)
#define EXTI_EMR2_EM48_Msk (0x1U << EXTI_EMR2_EM48_Pos) /*!< 0x00010000 */
#define EXTI_EMR2_EM48 EXTI_EMR2_EM48_Msk /*!< Event Mask on line 48 */
#define EXTI_EMR2_EM49_Pos (17U)
#define EXTI_EMR2_EM49_Msk (0x1U << EXTI_EMR2_EM49_Pos) /*!< 0x00020000 */
#define EXTI_EMR2_EM49 EXTI_EMR2_EM49_Msk /*!< Event Mask on line 49 */
#define EXTI_EMR2_EM50_Pos (18U)
#define EXTI_EMR2_EM50_Msk (0x1U << EXTI_EMR2_EM50_Pos) /*!< 0x00040000 */
#define EXTI_EMR2_EM50 EXTI_EMR2_EM50_Msk /*!< Event Mask on line 50 */
#define EXTI_EMR2_EM51_Pos (19U)
#define EXTI_EMR2_EM51_Msk (0x1U << EXTI_EMR2_EM51_Pos) /*!< 0x00080000 */
#define EXTI_EMR2_EM51 EXTI_EMR2_EM51_Msk /*!< Event Mask on line 51 */
#define EXTI_EMR2_EM52_Pos (20U)
#define EXTI_EMR2_EM52_Msk (0x1U << EXTI_EMR2_EM52_Pos) /*!< 0x00100000 */
#define EXTI_EMR2_EM52 EXTI_EMR2_EM52_Msk /*!< Event Mask on line 52 */
#define EXTI_EMR2_EM53_Pos (21U)
#define EXTI_EMR2_EM53_Msk (0x1U << EXTI_EMR2_EM53_Pos) /*!< 0x00200000 */
#define EXTI_EMR2_EM53 EXTI_EMR2_EM53_Msk /*!< Event Mask on line 53 */
#define EXTI_EMR2_EM54_Pos (22U)
#define EXTI_EMR2_EM54_Msk (0x1U << EXTI_EMR2_EM54_Pos) /*!< 0x00400000 */
#define EXTI_EMR2_EM54 EXTI_EMR2_EM54_Msk /*!< Event Mask on line 54 */
#define EXTI_EMR2_EM55_Pos (23U)
#define EXTI_EMR2_EM55_Msk (0x1U << EXTI_EMR2_EM55_Pos) /*!< 0x00800000 */
#define EXTI_EMR2_EM55 EXTI_EMR2_EM55_Msk /*!< Event Mask on line 55 */
#define EXTI_EMR2_EM56_Pos (24U)
#define EXTI_EMR2_EM56_Msk (0x1U << EXTI_EMR2_EM56_Pos) /*!< 0x01000000 */
#define EXTI_EMR2_EM56 EXTI_EMR2_EM56_Msk /*!< Event Mask on line 56 */
#define EXTI_EMR2_EM57_Pos (25U)
#define EXTI_EMR2_EM57_Msk (0x1U << EXTI_EMR2_EM57_Pos) /*!< 0x02000000 */
#define EXTI_EMR2_EM57 EXTI_EMR2_EM57_Msk /*!< Event Mask on line 57 */
#define EXTI_EMR2_EM58_Pos (26U)
#define EXTI_EMR2_EM58_Msk (0x1U << EXTI_EMR2_EM58_Pos) /*!< 0x04000000 */
#define EXTI_EMR2_EM58 EXTI_EMR2_EM58_Msk /*!< Event Mask on line 58 */
#define EXTI_EMR2_EM59_Pos (27U)
#define EXTI_EMR2_EM59_Msk (0x1U << EXTI_EMR2_EM59_Pos) /*!< 0x08000000 */
#define EXTI_EMR2_EM59 EXTI_EMR2_EM59_Msk /*!< Event Mask on line 59 */
#define EXTI_EMR2_EM60_Pos (28U)
#define EXTI_EMR2_EM60_Msk (0x1U << EXTI_EMR2_EM60_Pos) /*!< 0x10000000 */
#define EXTI_EMR2_EM60 EXTI_EMR2_EM60_Msk /*!< Event Mask on line 60 */
#define EXTI_EMR2_EM61_Pos (29U)
#define EXTI_EMR2_EM61_Msk (0x1U << EXTI_EMR2_EM61_Pos) /*!< 0x20000000 */
#define EXTI_EMR2_EM61 EXTI_EMR2_EM61_Msk /*!< Event Mask on line 61 */
#define EXTI_EMR2_EM62_Pos (30U)
#define EXTI_EMR2_EM62_Msk (0x1U << EXTI_EMR2_EM62_Pos) /*!< 0x40000000 */
#define EXTI_EMR2_EM62 EXTI_EMR2_EM62_Msk /*!< Event Mask on line 62 */
#define EXTI_EMR2_EM63_Pos (31U)
#define EXTI_EMR2_EM63_Msk (0x1U << EXTI_EMR2_EM63_Pos) /*!< 0x80000000 */
#define EXTI_EMR2_EM63 EXTI_EMR2_EM63_Msk /*!< Event Mask on line 63 */
/******************* Bit definition for EXTI_EMR3 register *******************/
#define EXTI_EMR3_EM64_Pos (0U)
#define EXTI_EMR3_EM64_Msk (0x1U << EXTI_EMR3_EM64_Pos) /*!< 0x00000001 */
#define EXTI_EMR3_EM64 EXTI_EMR3_EM64_Msk /*!< Event Mask on line 64*/
#define EXTI_EMR3_EM65_Pos (1U)
#define EXTI_EMR3_EM65_Msk (0x1U << EXTI_EMR3_EM65_Pos) /*!< 0x00000002 */
#define EXTI_EMR3_EM65 EXTI_EMR3_EM65_Msk /*!< Event Mask on line 65*/
#define EXTI_EMR3_EM66_Pos (2U)
#define EXTI_EMR3_EM66_Msk (0x1U << EXTI_EMR3_EM66_Pos) /*!< 0x00000004 */
#define EXTI_EMR3_EM66 EXTI_EMR3_EM66_Msk /*!< Event Mask on line 66*/
#define EXTI_EMR3_EM67_Pos (3U)
#define EXTI_EMR3_EM67_Msk (0x1U << EXTI_EMR3_EM67_Pos) /*!< 0x00000008 */
#define EXTI_EMR3_EM67 EXTI_EMR3_EM67_Msk /*!< Event Mask on line 67*/
#define EXTI_EMR3_EM68_Pos (4U)
#define EXTI_EMR3_EM68_Msk (0x1U << EXTI_EMR3_EM68_Pos) /*!< 0x00000010 */
#define EXTI_EMR3_EM68 EXTI_EMR3_EM68_Msk /*!< Event Mask on line 68*/
#define EXTI_EMR3_EM69_Pos (5U)
#define EXTI_EMR3_EM69_Msk (0x1U << EXTI_EMR3_EM69_Pos) /*!< 0x00000020 */
#define EXTI_EMR3_EM69 EXTI_EMR3_EM69_Msk /*!< Event Mask on line 69*/
#define EXTI_EMR3_EM70_Pos (6U)
#define EXTI_EMR3_EM70_Msk (0x1U << EXTI_EMR3_EM70_Pos) /*!< 0x00000040 */
#define EXTI_EMR3_EM70 EXTI_EMR3_EM70_Msk /*!< Event Mask on line 70*/
#define EXTI_EMR3_EM71_Pos (7U)
#define EXTI_EMR3_EM71_Msk (0x1U << EXTI_EMR3_EM71_Pos) /*!< 0x00000080 */
#define EXTI_EMR3_EM71 EXTI_EMR3_EM71_Msk /*!< Event Mask on line 71*/
#define EXTI_EMR3_EM72_Pos (8U)
#define EXTI_EMR3_EM72_Msk (0x1U << EXTI_EMR3_EM72_Pos) /*!< 0x00000100 */
#define EXTI_EMR3_EM72 EXTI_EMR3_EM72_Msk /*!< Event Mask on line 72*/
#define EXTI_EMR3_EM73_Pos (9U)
#define EXTI_EMR3_EM73_Msk (0x1U << EXTI_EMR3_EM73_Pos) /*!< 0x00000200 */
#define EXTI_EMR3_EM73 EXTI_EMR3_EM73_Msk /*!< Event Mask on line 73*/
#define EXTI_EMR3_EM74_Pos (10U)
#define EXTI_EMR3_EM74_Msk (0x1U << EXTI_EMR3_EM74_Pos) /*!< 0x00000400 */
#define EXTI_EMR3_EM74 EXTI_EMR3_EM74_Msk /*!< Event Mask on line 74 */
#define EXTI_EMR3_EM75_Pos (11U)
#define EXTI_EMR3_EM75_Msk (0x1U << EXTI_EMR3_EM75_Pos) /*!< 0x00000800 */
#define EXTI_EMR3_EM75 EXTI_EMR3_EM75_Msk /*!< Event Mask on line 75 */
#define EXTI_EMR3_EM76_Pos (12U)
#define EXTI_EMR3_EM76_Msk (0x1U << EXTI_EMR3_EM76_Pos) /*!< 0x00001000 */
#define EXTI_EMR3_EM76 EXTI_EMR3_EM76_Msk /*!< Event Mask on line 76 */
#define EXTI_EMR3_EM77_Pos (13U)
#define EXTI_EMR3_EM77_Msk (0x1U << EXTI_EMR3_EM77_Pos) /*!< 0x00002000 */
#define EXTI_EMR3_EM77 EXTI_EMR3_EM77_Msk /*!< Event Mask on line 77 */
#define EXTI_EMR3_EM78_Pos (14U)
#define EXTI_EMR3_EM78_Msk (0x1U << EXTI_EMR3_EM78_Pos) /*!< 0x00004000 */
#define EXTI_EMR3_EM78 EXTI_EMR3_EM78_Msk /*!< Event Mask on line 78 */
#define EXTI_EMR3_EM79_Pos (15U)
#define EXTI_EMR3_EM79_Msk (0x1U << EXTI_EMR3_EM79_Pos) /*!< 0x00008000 */
#define EXTI_EMR3_EM79 EXTI_EMR3_EM79_Msk /*!< Event Mask on line 79 */
#define EXTI_EMR3_EM80_Pos (16U)
#define EXTI_EMR3_EM80_Msk (0x1U << EXTI_EMR3_EM80_Pos) /*!< 0x00010000 */
#define EXTI_EMR3_EM80 EXTI_EMR3_EM80_Msk /*!< Event Mask on line 80 */
#define EXTI_EMR3_EM81_Pos (17U)
#define EXTI_EMR3_EM81_Msk (0x1U << EXTI_EMR3_EM81_Pos) /*!< 0x00020000 */
#define EXTI_EMR3_EM81 EXTI_EMR3_EM81_Msk /*!< Event Mask on line 81 */
#define EXTI_EMR3_EM82_Pos (18U)
#define EXTI_EMR3_EM82_Msk (0x1U << EXTI_EMR3_EM82_Pos) /*!< 0x00040000 */
#define EXTI_EMR3_EM82 EXTI_EMR3_EM82_Msk /*!< Event Mask on line 82 */
#define EXTI_EMR3_EM84_Pos (20U)
#define EXTI_EMR3_EM84_Msk (0x1U << EXTI_EMR3_EM84_Pos) /*!< 0x00100000 */
#define EXTI_EMR3_EM84 EXTI_EMR3_EM84_Msk /*!< Event Mask on line 84 */
#define EXTI_EMR3_EM85_Pos (21U)
#define EXTI_EMR3_EM85_Msk (0x1U << EXTI_EMR3_EM85_Pos) /*!< 0x00200000 */
#define EXTI_EMR3_EM85 EXTI_EMR3_EM85_Msk /*!< Event Mask on line 85 */
#define EXTI_EMR3_EM86_Pos (22U)
#define EXTI_EMR3_EM86_Msk (0x1U << EXTI_EMR3_EM86_Pos) /*!< 0x00400000 */
#define EXTI_EMR3_EM86 EXTI_EMR3_EM86_Msk /*!< Event Mask on line 86 */
#define EXTI_EMR3_EM87_Pos (23U)
#define EXTI_EMR3_EM87_Msk (0x1U << EXTI_EMR3_EM87_Pos) /*!< 0x00800000 */
#define EXTI_EMR3_EM87 EXTI_EMR3_EM87_Msk /*!< Event Mask on line 87 */
#define EXTI_EMR3_EM88_Pos (24U)
#define EXTI_EMR3_EM88_Msk (0x1U << EXTI_EMR3_EM88_Pos) /*!< 0x01000000 */
#define EXTI_EMR3_EM88 EXTI_EMR3_EM88_Msk /*!< Event Mask on line 88 */
/****************** Bit definition for EXTI_RTSR1 register *******************/
#define EXTI_RTSR1_TR0_Pos (0U)
#define EXTI_RTSR1_TR0_Msk (0x1U << EXTI_RTSR1_TR0_Pos) /*!< 0x00000001 */
#define EXTI_RTSR1_TR0 EXTI_RTSR1_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR1_TR1_Pos (1U)
#define EXTI_RTSR1_TR1_Msk (0x1U << EXTI_RTSR1_TR1_Pos) /*!< 0x00000002 */
#define EXTI_RTSR1_TR1 EXTI_RTSR1_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR1_TR2_Pos (2U)
#define EXTI_RTSR1_TR2_Msk (0x1U << EXTI_RTSR1_TR2_Pos) /*!< 0x00000004 */
#define EXTI_RTSR1_TR2 EXTI_RTSR1_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
#define EXTI_RTSR1_TR3_Pos (3U)
#define EXTI_RTSR1_TR3_Msk (0x1U << EXTI_RTSR1_TR3_Pos) /*!< 0x00000008 */
#define EXTI_RTSR1_TR3 EXTI_RTSR1_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
#define EXTI_RTSR1_TR4_Pos (4U)
#define EXTI_RTSR1_TR4_Msk (0x1U << EXTI_RTSR1_TR4_Pos) /*!< 0x00000010 */
#define EXTI_RTSR1_TR4 EXTI_RTSR1_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
#define EXTI_RTSR1_TR5_Pos (5U)
#define EXTI_RTSR1_TR5_Msk (0x1U << EXTI_RTSR1_TR5_Pos) /*!< 0x00000020 */
#define EXTI_RTSR1_TR5 EXTI_RTSR1_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
#define EXTI_RTSR1_TR6_Pos (6U)
#define EXTI_RTSR1_TR6_Msk (0x1U << EXTI_RTSR1_TR6_Pos) /*!< 0x00000040 */
#define EXTI_RTSR1_TR6 EXTI_RTSR1_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
#define EXTI_RTSR1_TR7_Pos (7U)
#define EXTI_RTSR1_TR7_Msk (0x1U << EXTI_RTSR1_TR7_Pos) /*!< 0x00000080 */
#define EXTI_RTSR1_TR7 EXTI_RTSR1_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
#define EXTI_RTSR1_TR8_Pos (8U)
#define EXTI_RTSR1_TR8_Msk (0x1U << EXTI_RTSR1_TR8_Pos) /*!< 0x00000100 */
#define EXTI_RTSR1_TR8 EXTI_RTSR1_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
#define EXTI_RTSR1_TR9_Pos (9U)
#define EXTI_RTSR1_TR9_Msk (0x1U << EXTI_RTSR1_TR9_Pos) /*!< 0x00000200 */
#define EXTI_RTSR1_TR9 EXTI_RTSR1_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
#define EXTI_RTSR1_TR10_Pos (10U)
#define EXTI_RTSR1_TR10_Msk (0x1U << EXTI_RTSR1_TR10_Pos) /*!< 0x00000400 */
#define EXTI_RTSR1_TR10 EXTI_RTSR1_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
#define EXTI_RTSR1_TR11_Pos (11U)
#define EXTI_RTSR1_TR11_Msk (0x1U << EXTI_RTSR1_TR11_Pos) /*!< 0x00000800 */
#define EXTI_RTSR1_TR11 EXTI_RTSR1_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
#define EXTI_RTSR1_TR12_Pos (12U)
#define EXTI_RTSR1_TR12_Msk (0x1U << EXTI_RTSR1_TR12_Pos) /*!< 0x00001000 */
#define EXTI_RTSR1_TR12 EXTI_RTSR1_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
#define EXTI_RTSR1_TR13_Pos (13U)
#define EXTI_RTSR1_TR13_Msk (0x1U << EXTI_RTSR1_TR13_Pos) /*!< 0x00002000 */
#define EXTI_RTSR1_TR13 EXTI_RTSR1_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
#define EXTI_RTSR1_TR14_Pos (14U)
#define EXTI_RTSR1_TR14_Msk (0x1U << EXTI_RTSR1_TR14_Pos) /*!< 0x00004000 */
#define EXTI_RTSR1_TR14 EXTI_RTSR1_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
#define EXTI_RTSR1_TR15_Pos (15U)
#define EXTI_RTSR1_TR15_Msk (0x1U << EXTI_RTSR1_TR15_Pos) /*!< 0x00008000 */
#define EXTI_RTSR1_TR15 EXTI_RTSR1_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
#define EXTI_RTSR1_TR16_Pos (16U)
#define EXTI_RTSR1_TR16_Msk (0x1U << EXTI_RTSR1_TR16_Pos) /*!< 0x00010000 */
#define EXTI_RTSR1_TR16 EXTI_RTSR1_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
#define EXTI_RTSR1_TR17_Pos (17U)
#define EXTI_RTSR1_TR17_Msk (0x1U << EXTI_RTSR1_TR17_Pos) /*!< 0x00020000 */
#define EXTI_RTSR1_TR17 EXTI_RTSR1_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR1_TR18_Pos (18U)
#define EXTI_RTSR1_TR18_Msk (0x1U << EXTI_RTSR1_TR18_Pos) /*!< 0x00040000 */
#define EXTI_RTSR1_TR18 EXTI_RTSR1_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR1_TR19_Pos (19U)
#define EXTI_RTSR1_TR19_Msk (0x1U << EXTI_RTSR1_TR19_Pos) /*!< 0x00080000 */
#define EXTI_RTSR1_TR19 EXTI_RTSR1_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR1_TR20_Pos (20U)
#define EXTI_RTSR1_TR20_Msk (0x1U << EXTI_RTSR1_TR20_Pos) /*!< 0x00100000 */
#define EXTI_RTSR1_TR20 EXTI_RTSR1_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR1_TR21_Pos (21U)
#define EXTI_RTSR1_TR21_Msk (0x1U << EXTI_RTSR1_TR21_Pos) /*!< 0x00200000 */
#define EXTI_RTSR1_TR21 EXTI_RTSR1_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
/****************** Bit definition for EXTI_RTSR2 register *******************/
#define EXTI_RTSR2_TR49_Pos (17U)
#define EXTI_RTSR2_TR49_Msk (0x1U << EXTI_RTSR2_TR49_Pos) /*!< 0x00020000 */
#define EXTI_RTSR2_TR49 EXTI_RTSR2_TR49_Msk /*!< Rising trigger event configuration bit of line 49 */
#define EXTI_RTSR2_TR51_Pos (19U)
#define EXTI_RTSR2_TR51_Msk (0x1U << EXTI_RTSR2_TR51_Pos) /*!< 0x00080000 */
#define EXTI_RTSR2_TR51 EXTI_RTSR2_TR51_Msk /*!< Rising trigger event configuration bit of line 51 */
/****************** Bit definition for EXTI_RTSR3 register *******************/
#define EXTI_RTSR3_TR85_Pos (21U)
#define EXTI_RTSR3_TR85_Msk (0x1U << EXTI_RTSR3_TR85_Pos) /*!< 0x00200000 */
#define EXTI_RTSR3_TR85 EXTI_RTSR3_TR85_Msk /*!< Rising trigger event configuration bit of line 85 */
#define EXTI_RTSR3_TR86_Pos (22U)
#define EXTI_RTSR3_TR86_Msk (0x1U << EXTI_RTSR3_TR86_Pos) /*!< 0x00400000 */
#define EXTI_RTSR3_TR86 EXTI_RTSR3_TR86_Msk /*!< Rising trigger event configuration bit of line 86 */
/****************** Bit definition for EXTI_FTSR1 register *******************/
#define EXTI_FTSR1_TR0_Pos (0U)
#define EXTI_FTSR1_TR0_Msk (0x1U << EXTI_FTSR1_TR0_Pos) /*!< 0x00000001 */
#define EXTI_FTSR1_TR0 EXTI_FTSR1_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR1_TR1_Pos (1U)
#define EXTI_FTSR1_TR1_Msk (0x1U << EXTI_FTSR1_TR1_Pos) /*!< 0x00000002 */
#define EXTI_FTSR1_TR1 EXTI_FTSR1_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR1_TR2_Pos (2U)
#define EXTI_FTSR1_TR2_Msk (0x1U << EXTI_FTSR1_TR2_Pos) /*!< 0x00000004 */
#define EXTI_FTSR1_TR2 EXTI_FTSR1_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
#define EXTI_FTSR1_TR3_Pos (3U)
#define EXTI_FTSR1_TR3_Msk (0x1U << EXTI_FTSR1_TR3_Pos) /*!< 0x00000008 */
#define EXTI_FTSR1_TR3 EXTI_FTSR1_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
#define EXTI_FTSR1_TR4_Pos (4U)
#define EXTI_FTSR1_TR4_Msk (0x1U << EXTI_FTSR1_TR4_Pos) /*!< 0x00000010 */
#define EXTI_FTSR1_TR4 EXTI_FTSR1_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
#define EXTI_FTSR1_TR5_Pos (5U)
#define EXTI_FTSR1_TR5_Msk (0x1U << EXTI_FTSR1_TR5_Pos) /*!< 0x00000020 */
#define EXTI_FTSR1_TR5 EXTI_FTSR1_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
#define EXTI_FTSR1_TR6_Pos (6U)
#define EXTI_FTSR1_TR6_Msk (0x1U << EXTI_FTSR1_TR6_Pos) /*!< 0x00000040 */
#define EXTI_FTSR1_TR6 EXTI_FTSR1_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
#define EXTI_FTSR1_TR7_Pos (7U)
#define EXTI_FTSR1_TR7_Msk (0x1U << EXTI_FTSR1_TR7_Pos) /*!< 0x00000080 */
#define EXTI_FTSR1_TR7 EXTI_FTSR1_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
#define EXTI_FTSR1_TR8_Pos (8U)
#define EXTI_FTSR1_TR8_Msk (0x1U << EXTI_FTSR1_TR8_Pos) /*!< 0x00000100 */
#define EXTI_FTSR1_TR8 EXTI_FTSR1_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
#define EXTI_FTSR1_TR9_Pos (9U)
#define EXTI_FTSR1_TR9_Msk (0x1U << EXTI_FTSR1_TR9_Pos) /*!< 0x00000200 */
#define EXTI_FTSR1_TR9 EXTI_FTSR1_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
#define EXTI_FTSR1_TR10_Pos (10U)
#define EXTI_FTSR1_TR10_Msk (0x1U << EXTI_FTSR1_TR10_Pos) /*!< 0x00000400 */
#define EXTI_FTSR1_TR10 EXTI_FTSR1_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
#define EXTI_FTSR1_TR11_Pos (11U)
#define EXTI_FTSR1_TR11_Msk (0x1U << EXTI_FTSR1_TR11_Pos) /*!< 0x00000800 */
#define EXTI_FTSR1_TR11 EXTI_FTSR1_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
#define EXTI_FTSR1_TR12_Pos (12U)
#define EXTI_FTSR1_TR12_Msk (0x1U << EXTI_FTSR1_TR12_Pos) /*!< 0x00001000 */
#define EXTI_FTSR1_TR12 EXTI_FTSR1_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
#define EXTI_FTSR1_TR13_Pos (13U)
#define EXTI_FTSR1_TR13_Msk (0x1U << EXTI_FTSR1_TR13_Pos) /*!< 0x00002000 */
#define EXTI_FTSR1_TR13 EXTI_FTSR1_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
#define EXTI_FTSR1_TR14_Pos (14U)
#define EXTI_FTSR1_TR14_Msk (0x1U << EXTI_FTSR1_TR14_Pos) /*!< 0x00004000 */
#define EXTI_FTSR1_TR14 EXTI_FTSR1_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
#define EXTI_FTSR1_TR15_Pos (15U)
#define EXTI_FTSR1_TR15_Msk (0x1U << EXTI_FTSR1_TR15_Pos) /*!< 0x00008000 */
#define EXTI_FTSR1_TR15 EXTI_FTSR1_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
#define EXTI_FTSR1_TR16_Pos (16U)
#define EXTI_FTSR1_TR16_Msk (0x1U << EXTI_FTSR1_TR16_Pos) /*!< 0x00010000 */
#define EXTI_FTSR1_TR16 EXTI_FTSR1_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
#define EXTI_FTSR1_TR17_Pos (17U)
#define EXTI_FTSR1_TR17_Msk (0x1U << EXTI_FTSR1_TR17_Pos) /*!< 0x00020000 */
#define EXTI_FTSR1_TR17 EXTI_FTSR1_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR1_TR18_Pos (18U)
#define EXTI_FTSR1_TR18_Msk (0x1U << EXTI_FTSR1_TR18_Pos) /*!< 0x00040000 */
#define EXTI_FTSR1_TR18 EXTI_FTSR1_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR1_TR19_Pos (19U)
#define EXTI_FTSR1_TR19_Msk (0x1U << EXTI_FTSR1_TR19_Pos) /*!< 0x00080000 */
#define EXTI_FTSR1_TR19 EXTI_FTSR1_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR1_TR20_Pos (20U)
#define EXTI_FTSR1_TR20_Msk (0x1U << EXTI_FTSR1_TR20_Pos) /*!< 0x00100000 */
#define EXTI_FTSR1_TR20 EXTI_FTSR1_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR1_TR21_Pos (21U)
#define EXTI_FTSR1_TR21_Msk (0x1U << EXTI_FTSR1_TR21_Pos) /*!< 0x00200000 */
#define EXTI_FTSR1_TR21 EXTI_FTSR1_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
/****************** Bit definition for EXTI_FTSR2 register *******************/
#define EXTI_FTSR2_TR49_Pos (17U)
#define EXTI_FTSR2_TR49_Msk (0x1U << EXTI_FTSR2_TR49_Pos) /*!< 0x00020000 */
#define EXTI_FTSR2_TR49 EXTI_FTSR2_TR49_Msk /*!< Falling trigger event configuration bit of line 49 */
#define EXTI_FTSR2_TR51_Pos (19U)
#define EXTI_FTSR2_TR51_Msk (0x1U << EXTI_FTSR2_TR51_Pos) /*!< 0x00080000 */
#define EXTI_FTSR2_TR51 EXTI_FTSR2_TR51_Msk /*!< Falling trigger event configuration bit of line 51 */
/****************** Bit definition for EXTI_FTSR3 register *******************/
#define EXTI_FTSR3_TR85_Pos (21U)
#define EXTI_FTSR3_TR85_Msk (0x1U << EXTI_FTSR3_TR85_Pos) /*!< 0x00200000 */
#define EXTI_FTSR3_TR85 EXTI_FTSR3_TR85_Msk /*!< Falling trigger event configuration bit of line 85 */
#define EXTI_FTSR3_TR86_Pos (22U)
#define EXTI_FTSR3_TR86_Msk (0x1U << EXTI_FTSR3_TR86_Pos) /*!< 0x00400000 */
#define EXTI_FTSR3_TR86 EXTI_FTSR3_TR86_Msk /*!< Falling trigger event configuration bit of line 86 */
/****************** Bit definition for EXTI_SWIER1 register ******************/
#define EXTI_SWIER1_SWIER0_Pos (0U)
#define EXTI_SWIER1_SWIER0_Msk (0x1U << EXTI_SWIER1_SWIER0_Pos) /*!< 0x00000001 */
#define EXTI_SWIER1_SWIER0 EXTI_SWIER1_SWIER0_Msk /*!< Software Interrupt on line 0 */
#define EXTI_SWIER1_SWIER1_Pos (1U)
#define EXTI_SWIER1_SWIER1_Msk (0x1U << EXTI_SWIER1_SWIER1_Pos) /*!< 0x00000002 */
#define EXTI_SWIER1_SWIER1 EXTI_SWIER1_SWIER1_Msk /*!< Software Interrupt on line 1 */
#define EXTI_SWIER1_SWIER2_Pos (2U)
#define EXTI_SWIER1_SWIER2_Msk (0x1U << EXTI_SWIER1_SWIER2_Pos) /*!< 0x00000004 */
#define EXTI_SWIER1_SWIER2 EXTI_SWIER1_SWIER2_Msk /*!< Software Interrupt on line 2 */
#define EXTI_SWIER1_SWIER3_Pos (3U)
#define EXTI_SWIER1_SWIER3_Msk (0x1U << EXTI_SWIER1_SWIER3_Pos) /*!< 0x00000008 */
#define EXTI_SWIER1_SWIER3 EXTI_SWIER1_SWIER3_Msk /*!< Software Interrupt on line 3 */
#define EXTI_SWIER1_SWIER4_Pos (4U)
#define EXTI_SWIER1_SWIER4_Msk (0x1U << EXTI_SWIER1_SWIER4_Pos) /*!< 0x00000010 */
#define EXTI_SWIER1_SWIER4 EXTI_SWIER1_SWIER4_Msk /*!< Software Interrupt on line 4 */
#define EXTI_SWIER1_SWIER5_Pos (5U)
#define EXTI_SWIER1_SWIER5_Msk (0x1U << EXTI_SWIER1_SWIER5_Pos) /*!< 0x00000020 */
#define EXTI_SWIER1_SWIER5 EXTI_SWIER1_SWIER5_Msk /*!< Software Interrupt on line 5 */
#define EXTI_SWIER1_SWIER6_Pos (6U)
#define EXTI_SWIER1_SWIER6_Msk (0x1U << EXTI_SWIER1_SWIER6_Pos) /*!< 0x00000040 */
#define EXTI_SWIER1_SWIER6 EXTI_SWIER1_SWIER6_Msk /*!< Software Interrupt on line 6 */
#define EXTI_SWIER1_SWIER7_Pos (7U)
#define EXTI_SWIER1_SWIER7_Msk (0x1U << EXTI_SWIER1_SWIER7_Pos) /*!< 0x00000080 */
#define EXTI_SWIER1_SWIER7 EXTI_SWIER1_SWIER7_Msk /*!< Software Interrupt on line 7 */
#define EXTI_SWIER1_SWIER8_Pos (8U)
#define EXTI_SWIER1_SWIER8_Msk (0x1U << EXTI_SWIER1_SWIER8_Pos) /*!< 0x00000100 */
#define EXTI_SWIER1_SWIER8 EXTI_SWIER1_SWIER8_Msk /*!< Software Interrupt on line 8 */
#define EXTI_SWIER1_SWIER9_Pos (9U)
#define EXTI_SWIER1_SWIER9_Msk (0x1U << EXTI_SWIER1_SWIER9_Pos) /*!< 0x00000200 */
#define EXTI_SWIER1_SWIER9 EXTI_SWIER1_SWIER9_Msk /*!< Software Interrupt on line 9 */
#define EXTI_SWIER1_SWIER10_Pos (10U)
#define EXTI_SWIER1_SWIER10_Msk (0x1U << EXTI_SWIER1_SWIER10_Pos) /*!< 0x00000400 */
#define EXTI_SWIER1_SWIER10 EXTI_SWIER1_SWIER10_Msk /*!< Software Interrupt on line 10 */
#define EXTI_SWIER1_SWIER11_Pos (11U)
#define EXTI_SWIER1_SWIER11_Msk (0x1U << EXTI_SWIER1_SWIER11_Pos) /*!< 0x00000800 */
#define EXTI_SWIER1_SWIER11 EXTI_SWIER1_SWIER11_Msk /*!< Software Interrupt on line 11 */
#define EXTI_SWIER1_SWIER12_Pos (12U)
#define EXTI_SWIER1_SWIER12_Msk (0x1U << EXTI_SWIER1_SWIER12_Pos) /*!< 0x00001000 */
#define EXTI_SWIER1_SWIER12 EXTI_SWIER1_SWIER12_Msk /*!< Software Interrupt on line 12 */
#define EXTI_SWIER1_SWIER13_Pos (13U)
#define EXTI_SWIER1_SWIER13_Msk (0x1U << EXTI_SWIER1_SWIER13_Pos) /*!< 0x00002000 */
#define EXTI_SWIER1_SWIER13 EXTI_SWIER1_SWIER13_Msk /*!< Software Interrupt on line 13 */
#define EXTI_SWIER1_SWIER14_Pos (14U)
#define EXTI_SWIER1_SWIER14_Msk (0x1U << EXTI_SWIER1_SWIER14_Pos) /*!< 0x00004000 */
#define EXTI_SWIER1_SWIER14 EXTI_SWIER1_SWIER14_Msk /*!< Software Interrupt on line 14 */
#define EXTI_SWIER1_SWIER15_Pos (15U)
#define EXTI_SWIER1_SWIER15_Msk (0x1U << EXTI_SWIER1_SWIER15_Pos) /*!< 0x00008000 */
#define EXTI_SWIER1_SWIER15 EXTI_SWIER1_SWIER15_Msk /*!< Software Interrupt on line 15 */
#define EXTI_SWIER1_SWIER16_Pos (16U)
#define EXTI_SWIER1_SWIER16_Msk (0x1U << EXTI_SWIER1_SWIER16_Pos) /*!< 0x00010000 */
#define EXTI_SWIER1_SWIER16 EXTI_SWIER1_SWIER16_Msk /*!< Software Interrupt on line 16 */
#define EXTI_SWIER1_SWIER17_Pos (17U)
#define EXTI_SWIER1_SWIER17_Msk (0x1U << EXTI_SWIER1_SWIER17_Pos) /*!< 0x00020000 */
#define EXTI_SWIER1_SWIER17 EXTI_SWIER1_SWIER17_Msk /*!< Software Interrupt on line 17 */
#define EXTI_SWIER1_SWIER18_Pos (18U)
#define EXTI_SWIER1_SWIER18_Msk (0x1U << EXTI_SWIER1_SWIER18_Pos) /*!< 0x00040000 */
#define EXTI_SWIER1_SWIER18 EXTI_SWIER1_SWIER18_Msk /*!< Software Interrupt on line 18 */
#define EXTI_SWIER1_SWIER19_Pos (19U)
#define EXTI_SWIER1_SWIER19_Msk (0x1U << EXTI_SWIER1_SWIER19_Pos) /*!< 0x00080000 */
#define EXTI_SWIER1_SWIER19 EXTI_SWIER1_SWIER19_Msk /*!< Software Interrupt on line 19 */
#define EXTI_SWIER1_SWIER20_Pos (20U)
#define EXTI_SWIER1_SWIER20_Msk (0x1U << EXTI_SWIER1_SWIER20_Pos) /*!< 0x00100000 */
#define EXTI_SWIER1_SWIER20 EXTI_SWIER1_SWIER20_Msk /*!< Software Interrupt on line 20 */
#define EXTI_SWIER1_SWIER21_Pos (21U)
#define EXTI_SWIER1_SWIER21_Msk (0x1U << EXTI_SWIER1_SWIER21_Pos) /*!< 0x00200000 */
#define EXTI_SWIER1_SWIER21 EXTI_SWIER1_SWIER21_Msk /*!< Software Interrupt on line 21 */
/****************** Bit definition for EXTI_SWIER2 register ******************/
#define EXTI_SWIER2_SWIER49_Pos (17U)
#define EXTI_SWIER2_SWIER49_Msk (0x1U << EXTI_SWIER2_SWIER49_Pos) /*!< 0x00020000 */
#define EXTI_SWIER2_SWIER49 EXTI_SWIER2_SWIER49_Msk /*!< Software Interrupt on line 49 */
#define EXTI_SWIER2_SWIER51_Pos (19U)
#define EXTI_SWIER2_SWIER51_Msk (0x1U << EXTI_SWIER2_SWIER51_Pos) /*!< 0x00080000 */
#define EXTI_SWIER2_SWIER51 EXTI_SWIER2_SWIER51_Msk /*!< Software Interrupt on line 51 */
/****************** Bit definition for EXTI_SWIER3 register ******************/
#define EXTI_SWIER3_SWIER85_Pos (21U)
#define EXTI_SWIER3_SWIER85_Msk (0x1U << EXTI_SWIER3_SWIER85_Pos) /*!< 0x00200000 */
#define EXTI_SWIER3_SWIER85 EXTI_SWIER3_SWIER85_Msk /*!< Software Interrupt on line 85 */
#define EXTI_SWIER3_SWIER86_Pos (22U)
#define EXTI_SWIER3_SWIER86_Msk (0x1U << EXTI_SWIER3_SWIER86_Pos) /*!< 0x00400000 */
#define EXTI_SWIER3_SWIER86 EXTI_SWIER3_SWIER86_Msk /*!< Software Interrupt on line 86 */
/******************* Bit definition for EXTI_PR1 register ********************/
#define EXTI_PR1_PR0_Pos (0U)
#define EXTI_PR1_PR0_Msk (0x1U << EXTI_PR1_PR0_Pos) /*!< 0x00000001 */
#define EXTI_PR1_PR0 EXTI_PR1_PR0_Msk /*!< Pending bit for line 0 */
#define EXTI_PR1_PR1_Pos (1U)
#define EXTI_PR1_PR1_Msk (0x1U << EXTI_PR1_PR1_Pos) /*!< 0x00000002 */
#define EXTI_PR1_PR1 EXTI_PR1_PR1_Msk /*!< Pending bit for line 1 */
#define EXTI_PR1_PR2_Pos (2U)
#define EXTI_PR1_PR2_Msk (0x1U << EXTI_PR1_PR2_Pos) /*!< 0x00000004 */
#define EXTI_PR1_PR2 EXTI_PR1_PR2_Msk /*!< Pending bit for line 2 */
#define EXTI_PR1_PR3_Pos (3U)
#define EXTI_PR1_PR3_Msk (0x1U << EXTI_PR1_PR3_Pos) /*!< 0x00000008 */
#define EXTI_PR1_PR3 EXTI_PR1_PR3_Msk /*!< Pending bit for line 3 */
#define EXTI_PR1_PR4_Pos (4U)
#define EXTI_PR1_PR4_Msk (0x1U << EXTI_PR1_PR4_Pos) /*!< 0x00000010 */
#define EXTI_PR1_PR4 EXTI_PR1_PR4_Msk /*!< Pending bit for line 4 */
#define EXTI_PR1_PR5_Pos (5U)
#define EXTI_PR1_PR5_Msk (0x1U << EXTI_PR1_PR5_Pos) /*!< 0x00000020 */
#define EXTI_PR1_PR5 EXTI_PR1_PR5_Msk /*!< Pending bit for line 5 */
#define EXTI_PR1_PR6_Pos (6U)
#define EXTI_PR1_PR6_Msk (0x1U << EXTI_PR1_PR6_Pos) /*!< 0x00000040 */
#define EXTI_PR1_PR6 EXTI_PR1_PR6_Msk /*!< Pending bit for line 6 */
#define EXTI_PR1_PR7_Pos (7U)
#define EXTI_PR1_PR7_Msk (0x1U << EXTI_PR1_PR7_Pos) /*!< 0x00000080 */
#define EXTI_PR1_PR7 EXTI_PR1_PR7_Msk /*!< Pending bit for line 7 */
#define EXTI_PR1_PR8_Pos (8U)
#define EXTI_PR1_PR8_Msk (0x1U << EXTI_PR1_PR8_Pos) /*!< 0x00000100 */
#define EXTI_PR1_PR8 EXTI_PR1_PR8_Msk /*!< Pending bit for line 8 */
#define EXTI_PR1_PR9_Pos (9U)
#define EXTI_PR1_PR9_Msk (0x1U << EXTI_PR1_PR9_Pos) /*!< 0x00000200 */
#define EXTI_PR1_PR9 EXTI_PR1_PR9_Msk /*!< Pending bit for line 9 */
#define EXTI_PR1_PR10_Pos (10U)
#define EXTI_PR1_PR10_Msk (0x1U << EXTI_PR1_PR10_Pos) /*!< 0x00000400 */
#define EXTI_PR1_PR10 EXTI_PR1_PR10_Msk /*!< Pending bit for line 10 */
#define EXTI_PR1_PR11_Pos (11U)
#define EXTI_PR1_PR11_Msk (0x1U << EXTI_PR1_PR11_Pos) /*!< 0x00000800 */
#define EXTI_PR1_PR11 EXTI_PR1_PR11_Msk /*!< Pending bit for line 11 */
#define EXTI_PR1_PR12_Pos (12U)
#define EXTI_PR1_PR12_Msk (0x1U << EXTI_PR1_PR12_Pos) /*!< 0x00001000 */
#define EXTI_PR1_PR12 EXTI_PR1_PR12_Msk /*!< Pending bit for line 12 */
#define EXTI_PR1_PR13_Pos (13U)
#define EXTI_PR1_PR13_Msk (0x1U << EXTI_PR1_PR13_Pos) /*!< 0x00002000 */
#define EXTI_PR1_PR13 EXTI_PR1_PR13_Msk /*!< Pending bit for line 13 */
#define EXTI_PR1_PR14_Pos (14U)
#define EXTI_PR1_PR14_Msk (0x1U << EXTI_PR1_PR14_Pos) /*!< 0x00004000 */
#define EXTI_PR1_PR14 EXTI_PR1_PR14_Msk /*!< Pending bit for line 14 */
#define EXTI_PR1_PR15_Pos (15U)
#define EXTI_PR1_PR15_Msk (0x1U << EXTI_PR1_PR15_Pos) /*!< 0x00008000 */
#define EXTI_PR1_PR15 EXTI_PR1_PR15_Msk /*!< Pending bit for line 15 */
#define EXTI_PR1_PR16_Pos (16U)
#define EXTI_PR1_PR16_Msk (0x1U << EXTI_PR1_PR16_Pos) /*!< 0x00010000 */
#define EXTI_PR1_PR16 EXTI_PR1_PR16_Msk /*!< Pending bit for line 16 */
/******************* Bit definition for EXTI_PR3 register ********************/
#define EXTI_PR3_PR65_Pos (1U)
#define EXTI_PR3_PR65_Msk (0x1U << EXTI_PR3_PR65_Pos) /*!< 0x00000002 */
#define EXTI_PR3_PR65 EXTI_PR3_PR65_Msk /*!< Pending bit for line 65 */
#define EXTI_PR3_PR66_Pos (2U)
#define EXTI_PR3_PR66_Msk (0x1U << EXTI_PR3_PR66_Pos) /*!< 0x00000004 */
#define EXTI_PR3_PR66 EXTI_PR3_PR66_Msk /*!< Pending bit for line 66 */
#define EXTI_PR3_PR68_Pos (4U)
#define EXTI_PR3_PR68_Msk (0x1U << EXTI_PR3_PR68_Pos) /*!< 0x00000010 */
#define EXTI_PR3_PR68 EXTI_PR3_PR68_Msk /*!< Pending bit for line 68 */
#define EXTI_PR3_PR73_Pos (9U)
#define EXTI_PR3_PR73_Msk (0x1U << EXTI_PR3_PR73_Pos) /*!< 0x00000200 */
#define EXTI_PR3_PR73 EXTI_PR3_PR73_Msk /*!< Pending bit for line 73 */
#define EXTI_PR3_PR74_Pos (10U)
#define EXTI_PR3_PR74_Msk (0x1U << EXTI_PR3_PR74_Pos) /*!< 0x00000400 */
#define EXTI_PR3_PR74 EXTI_PR3_PR74_Msk /*!< Pending bit for line 74 */
/***************** Bit definition for EXTI_EXTICR1 register ***************/
#define EXTI_EXTICR1_EXTI0_Pos (0U)
#define EXTI_EXTICR1_EXTI0_Msk (0x0FU << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
#define EXTI_EXTICR1_EXTI1_Pos (8U)
#define EXTI_EXTICR1_EXTI1_Msk (0x0FU << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000F00 */
#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
#define EXTI_EXTICR1_EXTI2_Pos (16U)
#define EXTI_EXTICR1_EXTI2_Msk (0x0FU << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x000F0000 */
#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
#define EXTI_EXTICR1_EXTI3_Pos (24U)
#define EXTI_EXTICR1_EXTI3_Msk (0x0FU << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x0F000000 */
#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
#define EXTI_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
#define EXTI_EXTICR1_EXTI0_PB_Pos (0U)
#define EXTI_EXTICR1_EXTI0_PB_Msk (0x1U << EXTI_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
#define EXTI_EXTICR1_EXTI0_PB EXTI_EXTICR1_EXTI0_PB_Msk /*!<PB[0] pin */
#define EXTI_EXTICR1_EXTI0_PC_Pos (1U)
#define EXTI_EXTICR1_EXTI0_PC_Msk (0x1U << EXTI_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
#define EXTI_EXTICR1_EXTI0_PC EXTI_EXTICR1_EXTI0_PC_Msk /*!<PC[0] pin */
#define EXTI_EXTICR1_EXTI0_PD_Pos (0U)
#define EXTI_EXTICR1_EXTI0_PD_Msk (0x3U << EXTI_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
#define EXTI_EXTICR1_EXTI0_PD EXTI_EXTICR1_EXTI0_PD_Msk /*!<PD[0] pin */
#define EXTI_EXTICR1_EXTI0_PE_Pos (2U)
#define EXTI_EXTICR1_EXTI0_PE_Msk (0x1U << EXTI_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
#define EXTI_EXTICR1_EXTI0_PE EXTI_EXTICR1_EXTI0_PE_Msk /*!<PE[0] pin */
#define EXTI_EXTICR1_EXTI0_PF_Pos (0U)
#define EXTI_EXTICR1_EXTI0_PF_Msk (0x5U << EXTI_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
#define EXTI_EXTICR1_EXTI0_PF EXTI_EXTICR1_EXTI0_PF_Msk /*!<PF[0] pin */
#define EXTI_EXTICR1_EXTI0_PG_Pos (1U)
#define EXTI_EXTICR1_EXTI0_PG_Msk (0x3U << EXTI_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
#define EXTI_EXTICR1_EXTI0_PG EXTI_EXTICR1_EXTI0_PG_Msk /*!<PG[0] pin */
#define EXTI_EXTICR1_EXTI0_PH_Pos (0U)
#define EXTI_EXTICR1_EXTI0_PH_Msk (0x7U << EXTI_EXTICR1_EXTI0_PH_Pos) /*!< 0x00000007 */
#define EXTI_EXTICR1_EXTI0_PH EXTI_EXTICR1_EXTI0_PH_Msk /*!<PH[0] pin */
#define EXTI_EXTICR1_EXTI0_PI_Pos (3U)
#define EXTI_EXTICR1_EXTI0_PI_Msk (0x1U << EXTI_EXTICR1_EXTI0_PI_Pos) /*!< 0x00000008 */
#define EXTI_EXTICR1_EXTI0_PI EXTI_EXTICR1_EXTI0_PI_Msk /*!<PI[0] pin */
#define EXTI_EXTICR1_EXTI0_PJ_Pos (0U)
#define EXTI_EXTICR1_EXTI0_PJ_Msk (0x9U << EXTI_EXTICR1_EXTI0_PJ_Pos) /*!< 0x00000009 */
#define EXTI_EXTICR1_EXTI0_PJ EXTI_EXTICR1_EXTI0_PJ_Msk /*!<PJ[0] pin */
#define EXTI_EXTICR1_EXTI0_PK_Pos (1U)
#define EXTI_EXTICR1_EXTI0_PK_Msk (0x5U << EXTI_EXTICR1_EXTI0_PK_Pos) /*!< 0x0000000A */
#define EXTI_EXTICR1_EXTI0_PK EXTI_EXTICR1_EXTI0_PK_Msk /*!<PK[0] pin */
#define EXTI_EXTICR1_EXTI0_PZ_Pos (0U)
#define EXTI_EXTICR1_EXTI0_PZ_Msk (0xBU << EXTI_EXTICR1_EXTI0_PZ_Pos) /*!< 0x0000000B */
#define EXTI_EXTICR1_EXTI0_PZ EXTI_EXTICR1_EXTI0_PZ_Msk /*!<PZ[0] pin */
/**
* @brief EXTI1 configuration
*/
#define EXTI_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
#define EXTI_EXTICR1_EXTI1_PB_Pos (8U)
#define EXTI_EXTICR1_EXTI1_PB_Msk (0x1U << EXTI_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000100 */
#define EXTI_EXTICR1_EXTI1_PB EXTI_EXTICR1_EXTI1_PB_Msk /*!<PB[1] pin */
#define EXTI_EXTICR1_EXTI1_PC_Pos (9U)
#define EXTI_EXTICR1_EXTI1_PC_Msk (0x1U << EXTI_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000200 */
#define EXTI_EXTICR1_EXTI1_PC EXTI_EXTICR1_EXTI1_PC_Msk /*!<PC[1] pin */
#define EXTI_EXTICR1_EXTI1_PD_Pos (8U)
#define EXTI_EXTICR1_EXTI1_PD_Msk (0x3U << EXTI_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000300 */
#define EXTI_EXTICR1_EXTI1_PD EXTI_EXTICR1_EXTI1_PD_Msk /*!<PD[1] pin */
#define EXTI_EXTICR1_EXTI1_PE_Pos (10U)
#define EXTI_EXTICR1_EXTI1_PE_Msk (0x1U << EXTI_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000400 */
#define EXTI_EXTICR1_EXTI1_PE EXTI_EXTICR1_EXTI1_PE_Msk /*!<PE[1] pin */
#define EXTI_EXTICR1_EXTI1_PF_Pos (8U)
#define EXTI_EXTICR1_EXTI1_PF_Msk (0x5U << EXTI_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000500 */
#define EXTI_EXTICR1_EXTI1_PF EXTI_EXTICR1_EXTI1_PF_Msk /*!<PF[1] pin */
#define EXTI_EXTICR1_EXTI1_PG_Pos (9U)
#define EXTI_EXTICR1_EXTI1_PG_Msk (0x3U << EXTI_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000600 */
#define EXTI_EXTICR1_EXTI1_PG EXTI_EXTICR1_EXTI1_PG_Msk /*!<PG[1] pin */
#define EXTI_EXTICR1_EXTI1_PH_Pos (8U)
#define EXTI_EXTICR1_EXTI1_PH_Msk (0x7U << EXTI_EXTICR1_EXTI1_PH_Pos) /*!< 0x00000700 */
#define EXTI_EXTICR1_EXTI1_PH EXTI_EXTICR1_EXTI1_PH_Msk /*!<PH[1] pin */
#define EXTI_EXTICR1_EXTI1_PI_Pos (11U)
#define EXTI_EXTICR1_EXTI1_PI_Msk (0x1U << EXTI_EXTICR1_EXTI1_PI_Pos) /*!< 0x00000800 */
#define EXTI_EXTICR1_EXTI1_PI EXTI_EXTICR1_EXTI1_PI_Msk /*!<PI[1] pin */
#define EXTI_EXTICR1_EXTI1_PJ_Pos (8U)
#define EXTI_EXTICR1_EXTI1_PJ_Msk (0x9U << EXTI_EXTICR1_EXTI1_PJ_Pos) /*!< 0x00000900 */
#define EXTI_EXTICR1_EXTI1_PJ EXTI_EXTICR1_EXTI1_PJ_Msk /*!<PJ[1] pin */
#define EXTI_EXTICR1_EXTI1_PK_Pos (9U)
#define EXTI_EXTICR1_EXTI1_PK_Msk (0x5U << EXTI_EXTICR1_EXTI1_PK_Pos) /*!< 0x00000A00 */
#define EXTI_EXTICR1_EXTI1_PK EXTI_EXTICR1_EXTI1_PK_Msk /*!<PK[1] pin */
#define EXTI_EXTICR1_EXTI1_PZ_Pos (8U)
#define EXTI_EXTICR1_EXTI1_PZ_Msk (0xBU << EXTI_EXTICR1_EXTI1_PZ_Pos) /*!< 0x00000B00 */
#define EXTI_EXTICR1_EXTI1_PZ EXTI_EXTICR1_EXTI1_PZ_Msk /*!<PZ[1] pin */
/**
* @brief EXTI2 configuration
*/
#define EXTI_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
#define EXTI_EXTICR1_EXTI2_PB_Pos (16U)
#define EXTI_EXTICR1_EXTI2_PB_Msk (0x1U << EXTI_EXTICR1_EXTI2_PB_Pos) /*!< 0x00010000 */
#define EXTI_EXTICR1_EXTI2_PB EXTI_EXTICR1_EXTI2_PB_Msk /*!<PB[2] pin */
#define EXTI_EXTICR1_EXTI2_PC_Pos (17U)
#define EXTI_EXTICR1_EXTI2_PC_Msk (0x1U << EXTI_EXTICR1_EXTI2_PC_Pos) /*!< 0x00020000 */
#define EXTI_EXTICR1_EXTI2_PC EXTI_EXTICR1_EXTI2_PC_Msk /*!<PC[2] pin */
#define EXTI_EXTICR1_EXTI2_PD_Pos (16U)
#define EXTI_EXTICR1_EXTI2_PD_Msk (0x3U << EXTI_EXTICR1_EXTI2_PD_Pos) /*!< 0x00030000 */
#define EXTI_EXTICR1_EXTI2_PD EXTI_EXTICR1_EXTI2_PD_Msk /*!<PD[2] pin */
#define EXTI_EXTICR1_EXTI2_PE_Pos (18U)
#define EXTI_EXTICR1_EXTI2_PE_Msk (0x1U << EXTI_EXTICR1_EXTI2_PE_Pos) /*!< 0x00040000 */
#define EXTI_EXTICR1_EXTI2_PE EXTI_EXTICR1_EXTI2_PE_Msk /*!<PE[2] pin */
#define EXTI_EXTICR1_EXTI2_PF_Pos (16U)
#define EXTI_EXTICR1_EXTI2_PF_Msk (0x5U << EXTI_EXTICR1_EXTI2_PF_Pos) /*!< 0x00050000 */
#define EXTI_EXTICR1_EXTI2_PF EXTI_EXTICR1_EXTI2_PF_Msk /*!<PF[2] pin */
#define EXTI_EXTICR1_EXTI2_PG_Pos (17U)
#define EXTI_EXTICR1_EXTI2_PG_Msk (0x3U << EXTI_EXTICR1_EXTI2_PG_Pos) /*!< 0x00060000 */
#define EXTI_EXTICR1_EXTI2_PG EXTI_EXTICR1_EXTI2_PG_Msk /*!<PG[2] pin */
#define EXTI_EXTICR1_EXTI2_PH_Pos (16U)
#define EXTI_EXTICR1_EXTI2_PH_Msk (0x7U << EXTI_EXTICR1_EXTI2_PH_Pos) /*!< 0x00070000 */
#define EXTI_EXTICR1_EXTI2_PH EXTI_EXTICR1_EXTI2_PH_Msk /*!<PH[2] pin */
#define EXTI_EXTICR1_EXTI2_PI_Pos (19U)
#define EXTI_EXTICR1_EXTI2_PI_Msk (0x1U << EXTI_EXTICR1_EXTI2_PI_Pos) /*!< 0x00080000 */
#define EXTI_EXTICR1_EXTI2_PI EXTI_EXTICR1_EXTI2_PI_Msk /*!<PI[2] pin */
#define EXTI_EXTICR1_EXTI2_PJ_Pos (16U)
#define EXTI_EXTICR1_EXTI2_PJ_Msk (0x9U << EXTI_EXTICR1_EXTI2_PJ_Pos) /*!< 0x00090000 */
#define EXTI_EXTICR1_EXTI2_PJ EXTI_EXTICR1_EXTI2_PJ_Msk /*!<PJ[2] pin */
#define EXTI_EXTICR1_EXTI2_PK_Pos (17U)
#define EXTI_EXTICR1_EXTI2_PK_Msk (0x5U << EXTI_EXTICR1_EXTI2_PK_Pos) /*!< 0x000A0000 */
#define EXTI_EXTICR1_EXTI2_PK EXTI_EXTICR1_EXTI2_PK_Msk /*!<PK[2] pin */
#define EXTI_EXTICR1_EXTI2_PZ_Pos (16U)
#define EXTI_EXTICR1_EXTI2_PZ_Msk (0xBU << EXTI_EXTICR1_EXTI2_PZ_Pos) /*!< 0x000B0000 */
#define EXTI_EXTICR1_EXTI2_PZ EXTI_EXTICR1_EXTI2_PZ_Msk /*!<PZ[2] pin */
/**
* @brief EXTI3 configuration
*/
#define EXTI_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
#define EXTI_EXTICR1_EXTI3_PB_Pos (24U)
#define EXTI_EXTICR1_EXTI3_PB_Msk (0x1U << EXTI_EXTICR1_EXTI3_PB_Pos) /*!< 0x01000000 */
#define EXTI_EXTICR1_EXTI3_PB EXTI_EXTICR1_EXTI3_PB_Msk /*!<PB[3] pin */
#define EXTI_EXTICR1_EXTI3_PC_Pos (25U)
#define EXTI_EXTICR1_EXTI3_PC_Msk (0x1U << EXTI_EXTICR1_EXTI3_PC_Pos) /*!< 0x02000000 */
#define EXTI_EXTICR1_EXTI3_PC EXTI_EXTICR1_EXTI3_PC_Msk /*!<PC[3] pin */
#define EXTI_EXTICR1_EXTI3_PD_Pos (24U)
#define EXTI_EXTICR1_EXTI3_PD_Msk (0x3U << EXTI_EXTICR1_EXTI3_PD_Pos) /*!< 0x03000000 */
#define EXTI_EXTICR1_EXTI3_PD EXTI_EXTICR1_EXTI3_PD_Msk /*!<PD[3] pin */
#define EXTI_EXTICR1_EXTI3_PE_Pos (26U)
#define EXTI_EXTICR1_EXTI3_PE_Msk (0x1U << EXTI_EXTICR1_EXTI3_PE_Pos) /*!< 0x04000000 */
#define EXTI_EXTICR1_EXTI3_PE EXTI_EXTICR1_EXTI3_PE_Msk /*!<PE[3] pin */
#define EXTI_EXTICR1_EXTI3_PF_Pos (24U)
#define EXTI_EXTICR1_EXTI3_PF_Msk (0x5U << EXTI_EXTICR1_EXTI3_PF_Pos) /*!< 0x05000000 */
#define EXTI_EXTICR1_EXTI3_PF EXTI_EXTICR1_EXTI3_PF_Msk /*!<PF[3] pin */
#define EXTI_EXTICR1_EXTI3_PG_Pos (25U)
#define EXTI_EXTICR1_EXTI3_PG_Msk (0x3U << EXTI_EXTICR1_EXTI3_PG_Pos) /*!< 0x06000000 */
#define EXTI_EXTICR1_EXTI3_PG EXTI_EXTICR1_EXTI3_PG_Msk /*!<PG[3] pin */
#define EXTI_EXTICR1_EXTI3_PH_Pos (24U)
#define EXTI_EXTICR1_EXTI3_PH_Msk (0x7U << EXTI_EXTICR1_EXTI3_PH_Pos) /*!< 0x07000000 */
#define EXTI_EXTICR1_EXTI3_PH EXTI_EXTICR1_EXTI3_PH_Msk /*!<PH[3] pin */
#define EXTI_EXTICR1_EXTI3_PI_Pos (27U)
#define EXTI_EXTICR1_EXTI3_PI_Msk (0x1U << EXTI_EXTICR1_EXTI3_PI_Pos) /*!< 0x08000000 */
#define EXTI_EXTICR1_EXTI3_PI EXTI_EXTICR1_EXTI3_PI_Msk /*!<PI[3] pin */
#define EXTI_EXTICR1_EXTI3_PJ_Pos (24U)
#define EXTI_EXTICR1_EXTI3_PJ_Msk (0x9U << EXTI_EXTICR1_EXTI3_PJ_Pos) /*!< 0x09000000 */
#define EXTI_EXTICR1_EXTI3_PJ EXTI_EXTICR1_EXTI3_PJ_Msk /*!<PJ[3] pin */
#define EXTI_EXTICR1_EXTI3_PK_Pos (25U)
#define EXTI_EXTICR1_EXTI3_PK_Msk (0x5U << EXTI_EXTICR1_EXTI3_PK_Pos) /*!< 0x0A000000 */
#define EXTI_EXTICR1_EXTI3_PK EXTI_EXTICR1_EXTI3_PK_Msk /*!<PK[3] pin */
#define EXTI_EXTICR1_EXTI3_PZ_Pos (24U)
#define EXTI_EXTICR1_EXTI3_PZ_Msk (0xBU << EXTI_EXTICR1_EXTI3_PZ_Pos) /*!< 0x0B000000 */
#define EXTI_EXTICR1_EXTI3_PZ EXTI_EXTICR1_EXTI3_PZ_Msk /*!<PZ[3] pin */
/***************** Bit definition for EXTI_EXTICR2 register ***************/
#define EXTI_EXTICR2_EXTI4_Pos (0U)
#define EXTI_EXTICR2_EXTI4_Msk (0x0FU << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x000000F */
#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
#define EXTI_EXTICR2_EXTI5_Pos (8U)
#define EXTI_EXTICR2_EXTI5_Msk (0x0FU << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000F00 */
#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
#define EXTI_EXTICR2_EXTI6_Pos (16U)
#define EXTI_EXTICR2_EXTI6_Msk (0x0FU << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x000F0000 */
#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
#define EXTI_EXTICR2_EXTI7_Pos (24U)
#define EXTI_EXTICR2_EXTI7_Msk (0x0FU << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x0F000000 */
#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
#define EXTI_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
#define EXTI_EXTICR2_EXTI4_PB_Pos (0U)
#define EXTI_EXTICR2_EXTI4_PB_Msk (0x1U << EXTI_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
#define EXTI_EXTICR2_EXTI4_PB EXTI_EXTICR2_EXTI4_PB_Msk /*!<PB[4] pin */
#define EXTI_EXTICR2_EXTI4_PC_Pos (1U)
#define EXTI_EXTICR2_EXTI4_PC_Msk (0x1U << EXTI_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
#define EXTI_EXTICR2_EXTI4_PC EXTI_EXTICR2_EXTI4_PC_Msk /*!<PC[4] pin */
#define EXTI_EXTICR2_EXTI4_PD_Pos (0U)
#define EXTI_EXTICR2_EXTI4_PD_Msk (0x3U << EXTI_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
#define EXTI_EXTICR2_EXTI4_PD EXTI_EXTICR2_EXTI4_PD_Msk /*!<PD[4] pin */
#define EXTI_EXTICR2_EXTI4_PE_Pos (2U)
#define EXTI_EXTICR2_EXTI4_PE_Msk (0x1U << EXTI_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
#define EXTI_EXTICR2_EXTI4_PE EXTI_EXTICR2_EXTI4_PE_Msk /*!<PE[4] pin */
#define EXTI_EXTICR2_EXTI4_PF_Pos (0U)
#define EXTI_EXTICR2_EXTI4_PF_Msk (0x5U << EXTI_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
#define EXTI_EXTICR2_EXTI4_PF EXTI_EXTICR2_EXTI4_PF_Msk /*!<PF[4] pin */
#define EXTI_EXTICR2_EXTI4_PG_Pos (1U)
#define EXTI_EXTICR2_EXTI4_PG_Msk (0x3U << EXTI_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
#define EXTI_EXTICR2_EXTI4_PG EXTI_EXTICR2_EXTI4_PG_Msk /*!<PG[4] pin */
#define EXTI_EXTICR2_EXTI4_PH_Pos (0U)
#define EXTI_EXTICR2_EXTI4_PH_Msk (0x7U << EXTI_EXTICR2_EXTI4_PH_Pos) /*!< 0x00000007 */
#define EXTI_EXTICR2_EXTI4_PH EXTI_EXTICR2_EXTI4_PH_Msk /*!<PH[4] pin */
#define EXTI_EXTICR2_EXTI4_PI_Pos (3U)
#define EXTI_EXTICR2_EXTI4_PI_Msk (0x1U << EXTI_EXTICR2_EXTI4_PI_Pos) /*!< 0x00000008 */
#define EXTI_EXTICR2_EXTI4_PI EXTI_EXTICR2_EXTI4_PI_Msk /*!<PI[4] pin */
#define EXTI_EXTICR2_EXTI4_PJ_Pos (0U)
#define EXTI_EXTICR2_EXTI4_PJ_Msk (0x9U << EXTI_EXTICR2_EXTI4_PJ_Pos) /*!< 0x00000009 */
#define EXTI_EXTICR2_EXTI4_PJ EXTI_EXTICR2_EXTI4_PJ_Msk /*!<PJ[4] pin */
#define EXTI_EXTICR2_EXTI4_PK_Pos (1U)
#define EXTI_EXTICR2_EXTI4_PK_Msk (0x5U << EXTI_EXTICR2_EXTI4_PK_Pos) /*!< 0x0000000A */
#define EXTI_EXTICR2_EXTI4_PK EXTI_EXTICR2_EXTI4_PK_Msk /*!<PK[4] pin */
#define EXTI_EXTICR2_EXTI4_PZ_Pos (0U)
#define EXTI_EXTICR2_EXTI4_PZ_Msk (0xBU << EXTI_EXTICR2_EXTI4_PZ_Pos) /*!< 0x0000000B */
#define EXTI_EXTICR2_EXTI4_PZ EXTI_EXTICR2_EXTI4_PZ_Msk /*!<PZ[4] pin */
/**
* @brief EXTI5 configuration
*/
#define EXTI_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
#define EXTI_EXTICR2_EXTI5_PB_Pos (8U)
#define EXTI_EXTICR2_EXTI5_PB_Msk (0x1U << EXTI_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000100 */
#define EXTI_EXTICR2_EXTI5_PB EXTI_EXTICR2_EXTI5_PB_Msk /*!<PB[5] pin */
#define EXTI_EXTICR2_EXTI5_PC_Pos (9U)
#define EXTI_EXTICR2_EXTI5_PC_Msk (0x1U << EXTI_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000200 */
#define EXTI_EXTICR2_EXTI5_PC EXTI_EXTICR2_EXTI5_PC_Msk /*!<PC[5] pin */
#define EXTI_EXTICR2_EXTI5_PD_Pos (8U)
#define EXTI_EXTICR2_EXTI5_PD_Msk (0x3U << EXTI_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000300 */
#define EXTI_EXTICR2_EXTI5_PD EXTI_EXTICR2_EXTI5_PD_Msk /*!<PD[5] pin */
#define EXTI_EXTICR2_EXTI5_PE_Pos (10U)
#define EXTI_EXTICR2_EXTI5_PE_Msk (0x1U << EXTI_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000400 */
#define EXTI_EXTICR2_EXTI5_PE EXTI_EXTICR2_EXTI5_PE_Msk /*!<PE[5] pin */
#define EXTI_EXTICR2_EXTI5_PF_Pos (8U)
#define EXTI_EXTICR2_EXTI5_PF_Msk (0x5U << EXTI_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000500 */
#define EXTI_EXTICR2_EXTI5_PF EXTI_EXTICR2_EXTI5_PF_Msk /*!<PF[5] pin */
#define EXTI_EXTICR2_EXTI5_PG_Pos (9U)
#define EXTI_EXTICR2_EXTI5_PG_Msk (0x3U << EXTI_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000600 */
#define EXTI_EXTICR2_EXTI5_PG EXTI_EXTICR2_EXTI5_PG_Msk /*!<PG[5] pin */
#define EXTI_EXTICR2_EXTI5_PH_Pos (8U)
#define EXTI_EXTICR2_EXTI5_PH_Msk (0x7U << EXTI_EXTICR2_EXTI5_PH_Pos) /*!< 0x00000700 */
#define EXTI_EXTICR2_EXTI5_PH EXTI_EXTICR2_EXTI5_PH_Msk /*!<PH[5] pin */
#define EXTI_EXTICR2_EXTI5_PI_Pos (11U)
#define EXTI_EXTICR2_EXTI5_PI_Msk (0x1U << EXTI_EXTICR2_EXTI5_PI_Pos) /*!< 0x00000800 */
#define EXTI_EXTICR2_EXTI5_PI EXTI_EXTICR2_EXTI5_PI_Msk /*!<PI[5] pin */
#define EXTI_EXTICR2_EXTI5_PJ_Pos (8U)
#define EXTI_EXTICR2_EXTI5_PJ_Msk (0x9U << EXTI_EXTICR2_EXTI5_PJ_Pos) /*!< 0x00000900 */
#define EXTI_EXTICR2_EXTI5_PJ EXTI_EXTICR2_EXTI5_PJ_Msk /*!<PJ[5] pin */
#define EXTI_EXTICR2_EXTI5_PK_Pos (9U)
#define EXTI_EXTICR2_EXTI5_PK_Msk (0x5U << EXTI_EXTICR2_EXTI5_PK_Pos) /*!< 0x00000A00 */
#define EXTI_EXTICR2_EXTI5_PK EXTI_EXTICR2_EXTI5_PK_Msk /*!<PK[5] pin */
#define EXTI_EXTICR2_EXTI5_PZ_Pos (8U)
#define EXTI_EXTICR2_EXTI5_PZ_Msk (0xBU << EXTI_EXTICR2_EXTI5_PZ_Pos) /*!< 0x00000B00 */
#define EXTI_EXTICR2_EXTI5_PZ EXTI_EXTICR2_EXTI5_PZ_Msk /*!<PZ[5] pin */
/**
* @brief EXTI6 configuration
*/
#define EXTI_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
#define EXTI_EXTICR2_EXTI6_PB_Pos (16U)
#define EXTI_EXTICR2_EXTI6_PB_Msk (0x1U << EXTI_EXTICR2_EXTI6_PB_Pos) /*!< 0x00010000 */
#define EXTI_EXTICR2_EXTI6_PB EXTI_EXTICR2_EXTI6_PB_Msk /*!<PB[6] pin */
#define EXTI_EXTICR2_EXTI6_PC_Pos (17U)
#define EXTI_EXTICR2_EXTI6_PC_Msk (0x1U << EXTI_EXTICR2_EXTI6_PC_Pos) /*!< 0x00020000 */
#define EXTI_EXTICR2_EXTI6_PC EXTI_EXTICR2_EXTI6_PC_Msk /*!<PC[6] pin */
#define EXTI_EXTICR2_EXTI6_PD_Pos (16U)
#define EXTI_EXTICR2_EXTI6_PD_Msk (0x3U << EXTI_EXTICR2_EXTI6_PD_Pos) /*!< 0x00030000 */
#define EXTI_EXTICR2_EXTI6_PD EXTI_EXTICR2_EXTI6_PD_Msk /*!<PD[6] pin */
#define EXTI_EXTICR2_EXTI6_PE_Pos (18U)
#define EXTI_EXTICR2_EXTI6_PE_Msk (0x1U << EXTI_EXTICR2_EXTI6_PE_Pos) /*!< 0x00040000 */
#define EXTI_EXTICR2_EXTI6_PE EXTI_EXTICR2_EXTI6_PE_Msk /*!<PE[6] pin */
#define EXTI_EXTICR2_EXTI6_PF_Pos (16U)
#define EXTI_EXTICR2_EXTI6_PF_Msk (0x5U << EXTI_EXTICR2_EXTI6_PF_Pos) /*!< 0x00050000 */
#define EXTI_EXTICR2_EXTI6_PF EXTI_EXTICR2_EXTI6_PF_Msk /*!<PF[6] pin */
#define EXTI_EXTICR2_EXTI6_PG_Pos (17U)
#define EXTI_EXTICR2_EXTI6_PG_Msk (0x3U << EXTI_EXTICR2_EXTI6_PG_Pos) /*!< 0x00060000 */
#define EXTI_EXTICR2_EXTI6_PG EXTI_EXTICR2_EXTI6_PG_Msk /*!<PG[6] pin */
#define EXTI_EXTICR2_EXTI6_PH_Pos (16U)
#define EXTI_EXTICR2_EXTI6_PH_Msk (0x7U << EXTI_EXTICR2_EXTI6_PH_Pos) /*!< 0x00070000 */
#define EXTI_EXTICR2_EXTI6_PH EXTI_EXTICR2_EXTI6_PH_Msk /*!<PH[6] pin */
#define EXTI_EXTICR2_EXTI6_PI_Pos (19U)
#define EXTI_EXTICR2_EXTI6_PI_Msk (0x1U << EXTI_EXTICR2_EXTI6_PI_Pos) /*!< 0x00080000 */
#define EXTI_EXTICR2_EXTI6_PI EXTI_EXTICR2_EXTI6_PI_Msk /*!<PI[6] pin */
#define EXTI_EXTICR2_EXTI6_PJ_Pos (16U)
#define EXTI_EXTICR2_EXTI6_PJ_Msk (0x9U << EXTI_EXTICR2_EXTI6_PJ_Pos) /*!< 0x00090000 */
#define EXTI_EXTICR2_EXTI6_PJ EXTI_EXTICR2_EXTI6_PJ_Msk /*!<PJ[6] pin */
#define EXTI_EXTICR2_EXTI6_PK_Pos (17U)
#define EXTI_EXTICR2_EXTI6_PK_Msk (0x5U << EXTI_EXTICR2_EXTI6_PK_Pos) /*!< 0x000A0000 */
#define EXTI_EXTICR2_EXTI6_PK EXTI_EXTICR2_EXTI6_PK_Msk /*!<PK[6] pin */
#define EXTI_EXTICR2_EXTI6_PZ_Pos (16U)
#define EXTI_EXTICR2_EXTI6_PZ_Msk (0xBU << EXTI_EXTICR2_EXTI6_PZ_Pos) /*!< 0x000B0000 */
#define EXTI_EXTICR2_EXTI6_PZ EXTI_EXTICR2_EXTI6_PZ_Msk /*!<PZ[6] pin */
/**
* @brief EXTI7 configuration
*/
#define EXTI_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
#define EXTI_EXTICR2_EXTI7_PB_Pos (24U)
#define EXTI_EXTICR2_EXTI7_PB_Msk (0x1U << EXTI_EXTICR2_EXTI7_PB_Pos) /*!< 0x01000000 */
#define EXTI_EXTICR2_EXTI7_PB EXTI_EXTICR2_EXTI7_PB_Msk /*!<PB[7] pin */
#define EXTI_EXTICR2_EXTI7_PC_Pos (25U)
#define EXTI_EXTICR2_EXTI7_PC_Msk (0x1U << EXTI_EXTICR2_EXTI7_PC_Pos) /*!< 0x02000000 */
#define EXTI_EXTICR2_EXTI7_PC EXTI_EXTICR2_EXTI7_PC_Msk /*!<PC[7] pin */
#define EXTI_EXTICR2_EXTI7_PD_Pos (24U)
#define EXTI_EXTICR2_EXTI7_PD_Msk (0x3U << EXTI_EXTICR2_EXTI7_PD_Pos) /*!< 0x03000000 */
#define EXTI_EXTICR2_EXTI7_PD EXTI_EXTICR2_EXTI7_PD_Msk /*!<PD[7] pin */
#define EXTI_EXTICR2_EXTI7_PE_Pos (26U)
#define EXTI_EXTICR2_EXTI7_PE_Msk (0x1U << EXTI_EXTICR2_EXTI7_PE_Pos) /*!< 0x04000000 */
#define EXTI_EXTICR2_EXTI7_PE EXTI_EXTICR2_EXTI7_PE_Msk /*!<PE[7] pin */
#define EXTI_EXTICR2_EXTI7_PF_Pos (24U)
#define EXTI_EXTICR2_EXTI7_PF_Msk (0x5U << EXTI_EXTICR2_EXTI7_PF_Pos) /*!< 0x05000000 */
#define EXTI_EXTICR2_EXTI7_PF EXTI_EXTICR2_EXTI7_PF_Msk /*!<PF[7] pin */
#define EXTI_EXTICR2_EXTI7_PG_Pos (25U)
#define EXTI_EXTICR2_EXTI7_PG_Msk (0x3U << EXTI_EXTICR2_EXTI7_PG_Pos) /*!< 0x06000000 */
#define EXTI_EXTICR2_EXTI7_PG EXTI_EXTICR2_EXTI7_PG_Msk /*!<PG[7] pin */
#define EXTI_EXTICR2_EXTI7_PH_Pos (24U)
#define EXTI_EXTICR2_EXTI7_PH_Msk (0x7U << EXTI_EXTICR2_EXTI7_PH_Pos) /*!< 0x07000000 */
#define EXTI_EXTICR2_EXTI7_PH EXTI_EXTICR2_EXTI7_PH_Msk /*!<PH[7] pin */
#define EXTI_EXTICR2_EXTI7_PI_Pos (27U)
#define EXTI_EXTICR2_EXTI7_PI_Msk (0x1U << EXTI_EXTICR2_EXTI7_PI_Pos) /*!< 0x08000000 */
#define EXTI_EXTICR2_EXTI7_PI EXTI_EXTICR2_EXTI7_PI_Msk /*!<PI[7] pin */
#define EXTI_EXTICR2_EXTI7_PJ_Pos (24U)
#define EXTI_EXTICR2_EXTI7_PJ_Msk (0x9U << EXTI_EXTICR2_EXTI7_PJ_Pos) /*!< 0x09000000 */
#define EXTI_EXTICR2_EXTI7_PJ EXTI_EXTICR2_EXTI7_PJ_Msk /*!<PJ[7] pin */
#define EXTI_EXTICR2_EXTI7_PK_Pos (25U)
#define EXTI_EXTICR2_EXTI7_PK_Msk (0x5U << EXTI_EXTICR2_EXTI7_PK_Pos) /*!< 0x0A000000 */
#define EXTI_EXTICR2_EXTI7_PK EXTI_EXTICR2_EXTI7_PK_Msk /*!<PK[7] pin */
#define EXTI_EXTICR2_EXTI7_PZ_Pos (24U)
#define EXTI_EXTICR2_EXTI7_PZ_Msk (0xBU << EXTI_EXTICR2_EXTI7_PZ_Pos) /*!< 0x0B000000 */
#define EXTI_EXTICR2_EXTI7_PZ EXTI_EXTICR2_EXTI7_PZ_Msk /*!<PZ[7] pin */
/***************** Bit definition for EXTI_EXTICR3 register ***************/
#define EXTI_EXTICR3_EXTI8_Pos (0U)
#define EXTI_EXTICR3_EXTI8_Msk (0x0FU << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
#define EXTI_EXTICR3_EXTI9_Pos (8U)
#define EXTI_EXTICR3_EXTI9_Msk (0x0FU << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000F00 */
#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
#define EXTI_EXTICR3_EXTI10_Pos (16U)
#define EXTI_EXTICR3_EXTI10_Msk (0x0FU << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x000F0000 */
#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
#define EXTI_EXTICR3_EXTI11_Pos (24U)
#define EXTI_EXTICR3_EXTI11_Msk (0x0FU << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x0F000000 */
#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
/**
* @brief EXTI8 configuration
*/
#define EXTI_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
#define EXTI_EXTICR3_EXTI8_PB_Pos (0U)
#define EXTI_EXTICR3_EXTI8_PB_Msk (0x1U << EXTI_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
#define EXTI_EXTICR3_EXTI8_PB EXTI_EXTICR3_EXTI8_PB_Msk /*!<PB[8] pin */
#define EXTI_EXTICR3_EXTI8_PC_Pos (1U)
#define EXTI_EXTICR3_EXTI8_PC_Msk (0x1U << EXTI_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
#define EXTI_EXTICR3_EXTI8_PC EXTI_EXTICR3_EXTI8_PC_Msk /*!<PC[8] pin */
#define EXTI_EXTICR3_EXTI8_PD_Pos (0U)
#define EXTI_EXTICR3_EXTI8_PD_Msk (0x3U << EXTI_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
#define EXTI_EXTICR3_EXTI8_PD EXTI_EXTICR3_EXTI8_PD_Msk /*!<PD[8] pin */
#define EXTI_EXTICR3_EXTI8_PE_Pos (2U)
#define EXTI_EXTICR3_EXTI8_PE_Msk (0x1U << EXTI_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
#define EXTI_EXTICR3_EXTI8_PE EXTI_EXTICR3_EXTI8_PE_Msk /*!<PE[8] pin */
#define EXTI_EXTICR3_EXTI8_PF_Pos (0U)
#define EXTI_EXTICR3_EXTI8_PF_Msk (0x5U << EXTI_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
#define EXTI_EXTICR3_EXTI8_PF EXTI_EXTICR3_EXTI8_PF_Msk /*!<PF[8] pin */
#define EXTI_EXTICR3_EXTI8_PG_Pos (1U)
#define EXTI_EXTICR3_EXTI8_PG_Msk (0x3U << EXTI_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
#define EXTI_EXTICR3_EXTI8_PG EXTI_EXTICR3_EXTI8_PG_Msk /*!<PG[8] pin */
#define EXTI_EXTICR3_EXTI8_PH_Pos (0U)
#define EXTI_EXTICR3_EXTI8_PH_Msk (0x7U << EXTI_EXTICR3_EXTI8_PH_Pos) /*!< 0x00000007 */
#define EXTI_EXTICR3_EXTI8_PH EXTI_EXTICR3_EXTI8_PH_Msk /*!<PH[8] pin */
#define EXTI_EXTICR3_EXTI8_PI_Pos (3U)
#define EXTI_EXTICR3_EXTI8_PI_Msk (0x1U << EXTI_EXTICR3_EXTI8_PI_Pos) /*!< 0x00000008 */
#define EXTI_EXTICR3_EXTI8_PI EXTI_EXTICR3_EXTI8_PI_Msk /*!<PI[8] pin */
#define EXTI_EXTICR3_EXTI8_PJ_Pos (0U)
#define EXTI_EXTICR3_EXTI8_PJ_Msk (0x9U << EXTI_EXTICR3_EXTI8_PJ_Pos) /*!< 0x00000009 */
#define EXTI_EXTICR3_EXTI8_PJ EXTI_EXTICR3_EXTI8_PJ_Msk /*!<PJ[8] pin */
/**
* @brief EXTI9 configuration
*/
#define EXTI_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
#define EXTI_EXTICR3_EXTI9_PB_Pos (8U)
#define EXTI_EXTICR3_EXTI9_PB_Msk (0x1U << EXTI_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000100 */
#define EXTI_EXTICR3_EXTI9_PB EXTI_EXTICR3_EXTI9_PB_Msk /*!<PB[9] pin */
#define EXTI_EXTICR3_EXTI9_PC_Pos (9U)
#define EXTI_EXTICR3_EXTI9_PC_Msk (0x1U << EXTI_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000200 */
#define EXTI_EXTICR3_EXTI9_PC EXTI_EXTICR3_EXTI9_PC_Msk /*!<PC[9] pin */
#define EXTI_EXTICR3_EXTI9_PD_Pos (8U)
#define EXTI_EXTICR3_EXTI9_PD_Msk (0x3U << EXTI_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000300 */
#define EXTI_EXTICR3_EXTI9_PD EXTI_EXTICR3_EXTI9_PD_Msk /*!<PD[9] pin */
#define EXTI_EXTICR3_EXTI9_PE_Pos (10U)
#define EXTI_EXTICR3_EXTI9_PE_Msk (0x1U << EXTI_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000400 */
#define EXTI_EXTICR3_EXTI9_PE EXTI_EXTICR3_EXTI9_PE_Msk /*!<PE[9] pin */
#define EXTI_EXTICR3_EXTI9_PF_Pos (8U)
#define EXTI_EXTICR3_EXTI9_PF_Msk (0x5U << EXTI_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000500 */
#define EXTI_EXTICR3_EXTI9_PF EXTI_EXTICR3_EXTI9_PF_Msk /*!<PF[9] pin */
#define EXTI_EXTICR3_EXTI9_PG_Pos (9U)
#define EXTI_EXTICR3_EXTI9_PG_Msk (0x3U << EXTI_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000600 */
#define EXTI_EXTICR3_EXTI9_PG EXTI_EXTICR3_EXTI9_PG_Msk /*!<PG[9] pin */
#define EXTI_EXTICR3_EXTI9_PH_Pos (8U)
#define EXTI_EXTICR3_EXTI9_PH_Msk (0x7U << EXTI_EXTICR3_EXTI9_PH_Pos) /*!< 0x00000700 */
#define EXTI_EXTICR3_EXTI9_PH EXTI_EXTICR3_EXTI9_PH_Msk /*!<PH[9] pin */
#define EXTI_EXTICR3_EXTI9_PI_Pos (11U)
#define EXTI_EXTICR3_EXTI9_PI_Msk (0x1U << EXTI_EXTICR3_EXTI9_PI_Pos) /*!< 0x00000800 */
#define EXTI_EXTICR3_EXTI9_PI EXTI_EXTICR3_EXTI9_PI_Msk /*!<PI[9] pin */
#define EXTI_EXTICR3_EXTI9_PJ_Pos (8U)
#define EXTI_EXTICR3_EXTI9_PJ_Msk (0x9U << EXTI_EXTICR3_EXTI9_PJ_Pos) /*!< 0x00000900 */
#define EXTI_EXTICR3_EXTI9_PJ EXTI_EXTICR3_EXTI9_PJ_Msk /*!<PJ[9] pin */
/**
* @brief EXTI10 configuration
*/
#define EXTI_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
#define EXTI_EXTICR3_EXTI10_PB_Pos (16U)
#define EXTI_EXTICR3_EXTI10_PB_Msk (0x1U << EXTI_EXTICR3_EXTI10_PB_Pos) /*!< 0x00010000 */
#define EXTI_EXTICR3_EXTI10_PB EXTI_EXTICR3_EXTI10_PB_Msk /*!<PB[10] pin */
#define EXTI_EXTICR3_EXTI10_PC_Pos (17U)
#define EXTI_EXTICR3_EXTI10_PC_Msk (0x1U << EXTI_EXTICR3_EXTI10_PC_Pos) /*!< 0x00020000 */
#define EXTI_EXTICR3_EXTI10_PC EXTI_EXTICR3_EXTI10_PC_Msk /*!<PC[10] pin */
#define EXTI_EXTICR3_EXTI10_PD_Pos (16U)
#define EXTI_EXTICR3_EXTI10_PD_Msk (0x3U << EXTI_EXTICR3_EXTI10_PD_Pos) /*!< 0x00030000 */
#define EXTI_EXTICR3_EXTI10_PD EXTI_EXTICR3_EXTI10_PD_Msk /*!<PD[10] pin */
#define EXTI_EXTICR3_EXTI10_PE_Pos (18U)
#define EXTI_EXTICR3_EXTI10_PE_Msk (0x1U << EXTI_EXTICR3_EXTI10_PE_Pos) /*!< 0x00040000 */
#define EXTI_EXTICR3_EXTI10_PE EXTI_EXTICR3_EXTI10_PE_Msk /*!<PE[10] pin */
#define EXTI_EXTICR3_EXTI10_PF_Pos (16U)
#define EXTI_EXTICR3_EXTI10_PF_Msk (0x5U << EXTI_EXTICR3_EXTI10_PF_Pos) /*!< 0x00050000 */
#define EXTI_EXTICR3_EXTI10_PF EXTI_EXTICR3_EXTI10_PF_Msk /*!<PF[10] pin */
#define EXTI_EXTICR3_EXTI10_PG_Pos (17U)
#define EXTI_EXTICR3_EXTI10_PG_Msk (0x3U << EXTI_EXTICR3_EXTI10_PG_Pos) /*!< 0x00060000 */
#define EXTI_EXTICR3_EXTI10_PG EXTI_EXTICR3_EXTI10_PG_Msk /*!<PG[10] pin */
#define EXTI_EXTICR3_EXTI10_PH_Pos (16U)
#define EXTI_EXTICR3_EXTI10_PH_Msk (0x7U << EXTI_EXTICR3_EXTI10_PH_Pos) /*!< 0x00070000 */
#define EXTI_EXTICR3_EXTI10_PH EXTI_EXTICR3_EXTI10_PH_Msk /*!<PH[10] pin */
#define EXTI_EXTICR3_EXTI10_PI_Pos (19U)
#define EXTI_EXTICR3_EXTI10_PI_Msk (0x1U << EXTI_EXTICR3_EXTI10_PI_Pos) /*!< 0x00080000 */
#define EXTI_EXTICR3_EXTI10_PI EXTI_EXTICR3_EXTI10_PI_Msk /*!<PI[10] pin */
#define EXTI_EXTICR3_EXTI10_PJ_Pos (16U)
#define EXTI_EXTICR3_EXTI10_PJ_Msk (0x9U << EXTI_EXTICR3_EXTI10_PJ_Pos) /*!< 0x00090000 */
#define EXTI_EXTICR3_EXTI10_PJ EXTI_EXTICR3_EXTI10_PJ_Msk /*!<PJ[10] pin */
/**
* @brief EXTI11 configuration
*/
#define EXTI_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
#define EXTI_EXTICR3_EXTI11_PB_Pos (24U)
#define EXTI_EXTICR3_EXTI11_PB_Msk (0x1U << EXTI_EXTICR3_EXTI11_PB_Pos) /*!< 0x01000000 */
#define EXTI_EXTICR3_EXTI11_PB EXTI_EXTICR3_EXTI11_PB_Msk /*!<PB[11] pin */
#define EXTI_EXTICR3_EXTI11_PC_Pos (25U)
#define EXTI_EXTICR3_EXTI11_PC_Msk (0x1U << EXTI_EXTICR3_EXTI11_PC_Pos) /*!< 0x02000000 */
#define EXTI_EXTICR3_EXTI11_PC EXTI_EXTICR3_EXTI11_PC_Msk /*!<PC[11] pin */
#define EXTI_EXTICR3_EXTI11_PD_Pos (24U)
#define EXTI_EXTICR3_EXTI11_PD_Msk (0x3U << EXTI_EXTICR3_EXTI11_PD_Pos) /*!< 0x03000000 */
#define EXTI_EXTICR3_EXTI11_PD EXTI_EXTICR3_EXTI11_PD_Msk /*!<PD[11] pin */
#define EXTI_EXTICR3_EXTI11_PE_Pos (26U)
#define EXTI_EXTICR3_EXTI11_PE_Msk (0x1U << EXTI_EXTICR3_EXTI11_PE_Pos) /*!< 0x04000000 */
#define EXTI_EXTICR3_EXTI11_PE EXTI_EXTICR3_EXTI11_PE_Msk /*!<PE[11] pin */
#define EXTI_EXTICR3_EXTI11_PF_Pos (24U)
#define EXTI_EXTICR3_EXTI11_PF_Msk (0x5U << EXTI_EXTICR3_EXTI11_PF_Pos) /*!< 0x05000000 */
#define EXTI_EXTICR3_EXTI11_PF EXTI_EXTICR3_EXTI11_PF_Msk /*!<PF[11] pin */
#define EXTI_EXTICR3_EXTI11_PG_Pos (25U)
#define EXTI_EXTICR3_EXTI11_PG_Msk (0x3U << EXTI_EXTICR3_EXTI11_PG_Pos) /*!< 0x06000000 */
#define EXTI_EXTICR3_EXTI11_PG EXTI_EXTICR3_EXTI11_PG_Msk /*!<PG[11] pin */
#define EXTI_EXTICR3_EXTI11_PH_Pos (24U)
#define EXTI_EXTICR3_EXTI11_PH_Msk (0x7U << EXTI_EXTICR3_EXTI11_PH_Pos) /*!< 0x07000000 */
#define EXTI_EXTICR3_EXTI11_PH EXTI_EXTICR3_EXTI11_PH_Msk /*!<PH[11] pin */
#define EXTI_EXTICR3_EXTI11_PI_Pos (27U)
#define EXTI_EXTICR3_EXTI11_PI_Msk (0x1U << EXTI_EXTICR3_EXTI11_PI_Pos) /*!< 0x08000000 */
#define EXTI_EXTICR3_EXTI11_PI EXTI_EXTICR3_EXTI11_PI_Msk /*!<PI[11] pin */
#define EXTI_EXTICR3_EXTI11_PJ_Pos (24U)
#define EXTI_EXTICR3_EXTI11_PJ_Msk (0x9U << EXTI_EXTICR3_EXTI11_PJ_Pos) /*!< 0x09000000 */
#define EXTI_EXTICR3_EXTI11_PJ EXTI_EXTICR3_EXTI11_PJ_Msk /*!<PJ[11] pin */
/***************** Bit definition for EXTI_EXTICR4 register ***************/
#define EXTI_EXTICR4_EXTI12_Pos (0U)
#define EXTI_EXTICR4_EXTI12_Msk (0x0FU << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
#define EXTI_EXTICR4_EXTI13_Pos (8U)
#define EXTI_EXTICR4_EXTI13_Msk (0x0FU << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000F00 */
#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
#define EXTI_EXTICR4_EXTI14_Pos (16U)
#define EXTI_EXTICR4_EXTI14_Msk (0x0FU << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x000F0000 */
#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
#define EXTI_EXTICR4_EXTI15_Pos (24U)
#define EXTI_EXTICR4_EXTI15_Msk (0x0FU << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x0F000000 */
#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
#define EXTI_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
#define EXTI_EXTICR4_EXTI12_PB_Pos (0U)
#define EXTI_EXTICR4_EXTI12_PB_Msk (0x1U << EXTI_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
#define EXTI_EXTICR4_EXTI12_PB EXTI_EXTICR4_EXTI12_PB_Msk /*!<PB[12] pin */
#define EXTI_EXTICR4_EXTI12_PC_Pos (1U)
#define EXTI_EXTICR4_EXTI12_PC_Msk (0x1U << EXTI_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
#define EXTI_EXTICR4_EXTI12_PC EXTI_EXTICR4_EXTI12_PC_Msk /*!<PC[12] pin */
#define EXTI_EXTICR4_EXTI12_PD_Pos (0U)
#define EXTI_EXTICR4_EXTI12_PD_Msk (0x3U << EXTI_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
#define EXTI_EXTICR4_EXTI12_PD EXTI_EXTICR4_EXTI12_PD_Msk /*!<PD[12] pin */
#define EXTI_EXTICR4_EXTI12_PE_Pos (2U)
#define EXTI_EXTICR4_EXTI12_PE_Msk (0x1U << EXTI_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
#define EXTI_EXTICR4_EXTI12_PE EXTI_EXTICR4_EXTI12_PE_Msk /*!<PE[12] pin */
#define EXTI_EXTICR4_EXTI12_PF_Pos (0U)
#define EXTI_EXTICR4_EXTI12_PF_Msk (0x5U << EXTI_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
#define EXTI_EXTICR4_EXTI12_PF EXTI_EXTICR4_EXTI12_PF_Msk /*!<PF[12] pin */
#define EXTI_EXTICR4_EXTI12_PG_Pos (1U)
#define EXTI_EXTICR4_EXTI12_PG_Msk (0x3U << EXTI_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
#define EXTI_EXTICR4_EXTI12_PG EXTI_EXTICR4_EXTI12_PG_Msk /*!<PG[12] pin */
#define EXTI_EXTICR4_EXTI12_PH_Pos (0U)
#define EXTI_EXTICR4_EXTI12_PH_Msk (0x7U << EXTI_EXTICR4_EXTI12_PH_Pos) /*!< 0x00000007 */
#define EXTI_EXTICR4_EXTI12_PH EXTI_EXTICR4_EXTI12_PH_Msk /*!<PH[12] pin */
#define EXTI_EXTICR4_EXTI12_PI_Pos (3U)
#define EXTI_EXTICR4_EXTI12_PI_Msk (0x1U << EXTI_EXTICR4_EXTI12_PI_Pos) /*!< 0x00000008 */
#define EXTI_EXTICR4_EXTI12_PI EXTI_EXTICR4_EXTI12_PI_Msk /*!<PI[12] pin */
#define EXTI_EXTICR4_EXTI12_PJ_Pos (0U)
#define EXTI_EXTICR4_EXTI12_PJ_Msk (0x9U << EXTI_EXTICR4_EXTI12_PJ_Pos) /*!< 0x00000009 */
#define EXTI_EXTICR4_EXTI12_PJ EXTI_EXTICR4_EXTI12_PJ_Msk /*!<PJ[12] pin */
/**
* @brief EXTI13 configuration
*/
#define EXTI_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
#define EXTI_EXTICR4_EXTI13_PB_Pos (8U)
#define EXTI_EXTICR4_EXTI13_PB_Msk (0x1U << EXTI_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000100 */
#define EXTI_EXTICR4_EXTI13_PB EXTI_EXTICR4_EXTI13_PB_Msk /*!<PB[13] pin */
#define EXTI_EXTICR4_EXTI13_PC_Pos (9U)
#define EXTI_EXTICR4_EXTI13_PC_Msk (0x1U << EXTI_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000200 */
#define EXTI_EXTICR4_EXTI13_PC EXTI_EXTICR4_EXTI13_PC_Msk /*!<PC[13] pin */
#define EXTI_EXTICR4_EXTI13_PD_Pos (8U)
#define EXTI_EXTICR4_EXTI13_PD_Msk (0x3U << EXTI_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000300 */
#define EXTI_EXTICR4_EXTI13_PD EXTI_EXTICR4_EXTI13_PD_Msk /*!<PD[13] pin */
#define EXTI_EXTICR4_EXTI13_PE_Pos (10U)
#define EXTI_EXTICR4_EXTI13_PE_Msk (0x1U << EXTI_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000400 */
#define EXTI_EXTICR4_EXTI13_PE EXTI_EXTICR4_EXTI13_PE_Msk /*!<PE[13] pin */
#define EXTI_EXTICR4_EXTI13_PF_Pos (8U)
#define EXTI_EXTICR4_EXTI13_PF_Msk (0x5U << EXTI_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000500 */
#define EXTI_EXTICR4_EXTI13_PF EXTI_EXTICR4_EXTI13_PF_Msk /*!<PF[13] pin */
#define EXTI_EXTICR4_EXTI13_PG_Pos (9U)
#define EXTI_EXTICR4_EXTI13_PG_Msk (0x3U << EXTI_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000600 */
#define EXTI_EXTICR4_EXTI13_PG EXTI_EXTICR4_EXTI13_PG_Msk /*!<PG[13] pin */
#define EXTI_EXTICR4_EXTI13_PH_Pos (8U)
#define EXTI_EXTICR4_EXTI13_PH_Msk (0x7U << EXTI_EXTICR4_EXTI13_PH_Pos) /*!< 0x00000700 */
#define EXTI_EXTICR4_EXTI13_PH EXTI_EXTICR4_EXTI13_PH_Msk /*!<PH[13] pin */
#define EXTI_EXTICR4_EXTI13_PI_Pos (11U)
#define EXTI_EXTICR4_EXTI13_PI_Msk (0x1U << EXTI_EXTICR4_EXTI13_PI_Pos) /*!< 0x00000800 */
#define EXTI_EXTICR4_EXTI13_PI EXTI_EXTICR4_EXTI13_PI_Msk /*!<PI[13] pin */
#define EXTI_EXTICR4_EXTI13_PJ_Pos (8U)
#define EXTI_EXTICR4_EXTI13_PJ_Msk (0x9U << EXTI_EXTICR4_EXTI13_PJ_Pos) /*!< 0x00000900 */
#define EXTI_EXTICR4_EXTI13_PJ EXTI_EXTICR4_EXTI13_PJ_Msk /*!<PJ[13] pin */
/**
* @brief EXTI14 configuration
*/
#define EXTI_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
#define EXTI_EXTICR4_EXTI14_PB_Pos (16U)
#define EXTI_EXTICR4_EXTI14_PB_Msk (0x1U << EXTI_EXTICR4_EXTI14_PB_Pos) /*!< 0x00010000 */
#define EXTI_EXTICR4_EXTI14_PB EXTI_EXTICR4_EXTI14_PB_Msk /*!<PB[14] pin */
#define EXTI_EXTICR4_EXTI14_PC_Pos (17U)
#define EXTI_EXTICR4_EXTI14_PC_Msk (0x1U << EXTI_EXTICR4_EXTI14_PC_Pos) /*!< 0x00020000 */
#define EXTI_EXTICR4_EXTI14_PC EXTI_EXTICR4_EXTI14_PC_Msk /*!<PC[14] pin */
#define EXTI_EXTICR4_EXTI14_PD_Pos (16U)
#define EXTI_EXTICR4_EXTI14_PD_Msk (0x3U << EXTI_EXTICR4_EXTI14_PD_Pos) /*!< 0x00030000 */
#define EXTI_EXTICR4_EXTI14_PD EXTI_EXTICR4_EXTI14_PD_Msk /*!<PD[14] pin */
#define EXTI_EXTICR4_EXTI14_PE_Pos (18U)
#define EXTI_EXTICR4_EXTI14_PE_Msk (0x1U << EXTI_EXTICR4_EXTI14_PE_Pos) /*!< 0x00040000 */
#define EXTI_EXTICR4_EXTI14_PE EXTI_EXTICR4_EXTI14_PE_Msk /*!<PE[14] pin */
#define EXTI_EXTICR4_EXTI14_PF_Pos (16U)
#define EXTI_EXTICR4_EXTI14_PF_Msk (0x5U << EXTI_EXTICR4_EXTI14_PF_Pos) /*!< 0x00050000 */
#define EXTI_EXTICR4_EXTI14_PF EXTI_EXTICR4_EXTI14_PF_Msk /*!<PF[14] pin */
#define EXTI_EXTICR4_EXTI14_PG_Pos (17U)
#define EXTI_EXTICR4_EXTI14_PG_Msk (0x3U << EXTI_EXTICR4_EXTI14_PG_Pos) /*!< 0x00060000 */
#define EXTI_EXTICR4_EXTI14_PG EXTI_EXTICR4_EXTI14_PG_Msk /*!<PG[14] pin */
#define EXTI_EXTICR4_EXTI14_PH_Pos (16U)
#define EXTI_EXTICR4_EXTI14_PH_Msk (0x7U << EXTI_EXTICR4_EXTI14_PH_Pos) /*!< 0x00070000 */
#define EXTI_EXTICR4_EXTI14_PH EXTI_EXTICR4_EXTI14_PH_Msk /*!<PH[14] pin */
#define EXTI_EXTICR4_EXTI14_PI_Pos (19U)
#define EXTI_EXTICR4_EXTI14_PI_Msk (0x1U << EXTI_EXTICR4_EXTI14_PI_Pos) /*!< 0x00080000 */
#define EXTI_EXTICR4_EXTI14_PI EXTI_EXTICR4_EXTI14_PI_Msk /*!<PI[14] pin */
#define EXTI_EXTICR4_EXTI14_PJ_Pos (16U)
#define EXTI_EXTICR4_EXTI14_PJ_Msk (0x9U << EXTI_EXTICR4_EXTI14_PJ_Pos) /*!< 0x00090000 */
#define EXTI_EXTICR4_EXTI14_PJ EXTI_EXTICR4_EXTI14_PJ_Msk /*!<PJ[14] pin */
/**
* @brief EXTI15 configuration
*/
#define EXTI_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
#define EXTI_EXTICR4_EXTI15_PB_Pos (24U)
#define EXTI_EXTICR4_EXTI15_PB_Msk (0x1U << EXTI_EXTICR4_EXTI15_PB_Pos) /*!< 0x01000000 */
#define EXTI_EXTICR4_EXTI15_PB EXTI_EXTICR4_EXTI15_PB_Msk /*!<PB[15] pin */
#define EXTI_EXTICR4_EXTI15_PC_Pos (25U)
#define EXTI_EXTICR4_EXTI15_PC_Msk (0x1U << EXTI_EXTICR4_EXTI15_PC_Pos) /*!< 0x02000000 */
#define EXTI_EXTICR4_EXTI15_PC EXTI_EXTICR4_EXTI15_PC_Msk /*!<PC[15] pin */
#define EXTI_EXTICR4_EXTI15_PD_Pos (24U)
#define EXTI_EXTICR4_EXTI15_PD_Msk (0x3U << EXTI_EXTICR4_EXTI15_PD_Pos) /*!< 0x03000000 */
#define EXTI_EXTICR4_EXTI15_PD EXTI_EXTICR4_EXTI15_PD_Msk /*!<PD[15] pin */
#define EXTI_EXTICR4_EXTI15_PE_Pos (26U)
#define EXTI_EXTICR4_EXTI15_PE_Msk (0x1U << EXTI_EXTICR4_EXTI15_PE_Pos) /*!< 0x04000000 */
#define EXTI_EXTICR4_EXTI15_PE EXTI_EXTICR4_EXTI15_PE_Msk /*!<PE[15] pin */
#define EXTI_EXTICR4_EXTI15_PF_Pos (24U)
#define EXTI_EXTICR4_EXTI15_PF_Msk (0x5U << EXTI_EXTICR4_EXTI15_PF_Pos) /*!< 0x05000000 */
#define EXTI_EXTICR4_EXTI15_PF EXTI_EXTICR4_EXTI15_PF_Msk /*!<PF[15] pin */
#define EXTI_EXTICR4_EXTI15_PG_Pos (25U)
#define EXTI_EXTICR4_EXTI15_PG_Msk (0x3U << EXTI_EXTICR4_EXTI15_PG_Pos) /*!< 0x06000000 */
#define EXTI_EXTICR4_EXTI15_PG EXTI_EXTICR4_EXTI15_PG_Msk /*!<PG[15] pin */
#define EXTI_EXTICR4_EXTI15_PH_Pos (24U)
#define EXTI_EXTICR4_EXTI15_PH_Msk (0x7U << EXTI_EXTICR4_EXTI15_PH_Pos) /*!< 0x07000000 */
#define EXTI_EXTICR4_EXTI15_PH EXTI_EXTICR4_EXTI15_PH_Msk /*!<PH[15] pin */
#define EXTI_EXTICR4_EXTI15_PI_Pos (27U)
#define EXTI_EXTICR4_EXTI15_PI_Msk (0x1U << EXTI_EXTICR4_EXTI15_PI_Pos) /*!< 0x08000000 */
#define EXTI_EXTICR4_EXTI15_PI EXTI_EXTICR4_EXTI15_PI_Msk /*!<PI[15] pin */
#define EXTI_EXTICR4_EXTI15_PJ_Pos (24U)
#define EXTI_EXTICR4_EXTI15_PJ_Msk (0x9U << EXTI_EXTICR4_EXTI15_PJ_Pos) /*!< 0x09000000 */
#define EXTI_EXTICR4_EXTI15_PJ EXTI_EXTICR4_EXTI15_PJ_Msk /*!<PJ[15] pin */
/********************** Bit definition for EXTI_HWCFGR1 register ***************/
#define EXTI_HWCFGR1_NBEVENTS_Pos (0U)
#define EXTI_HWCFGR1_NBEVENTS_Msk (0xFFU << EXTI_HWCFGR1_NBEVENTS_Pos) /*!< 0x000000FF */
#define EXTI_HWCFGR1_NBEVENTS EXTI_HWCFGR1_NBEVENTS_Msk /*!< Number of EVENT */
#define EXTI_HWCFGR1_NBCPUS_Pos (8U)
#define EXTI_HWCFGR1_NBCPUS_Msk (0xFU << EXTI_HWCFGR1_NBCPUS_Pos) /*!< 0x00000F00 */
#define EXTI_HWCFGR1_NBCPUS EXTI_HWCFGR1_NBCPUS_Msk /*!< Number of CPUs */
#define EXTI_HWCFGR1_CPUEVTEN_Pos (12U)
#define EXTI_HWCFGR1_CPUEVTEN_Msk (0xFU << EXTI_HWCFGR1_CPUEVTEN_Pos) /*!< 0x0000F000 */
#define EXTI_HWCFGR1_CPUEVTEN EXTI_HWCFGR1_CPUEVTEN_Msk /*!< CPU(m) event output enable */
#define EXTI_HWCFGR1_NBIOPORT_Pos (16U)
#define EXTI_HWCFGR1_NBIOPORT_Msk (0xFFU << EXTI_HWCFGR1_NBIOPORT_Pos) /*!< 0x00FF0000 */
#define EXTI_HWCFGR1_NBIOPORT EXTI_HWCFGR1_NBIOPORT_Msk /*!< Number of IO ports on EXTI */
/********************** Bit definition for EXTI_VERR register *****************/
#define EXTI_VERR_MINREV_Pos (0U)
#define EXTI_VERR_MINREV_Msk (0xFU << EXTI_VERR_MINREV_Pos) /*!< 0x0000000F */
#define EXTI_VERR_MINREV EXTI_VERR_MINREV_Msk /*!< Minor Revision number */
#define EXTI_VERR_MAJREV_Pos (4U)
#define EXTI_VERR_MAJREV_Msk (0xFU << EXTI_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define EXTI_VERR_MAJREV EXTI_VERR_MAJREV_Msk /*!< Major Revision number */
/********************** Bit definition for EXTI_IPIDR register ****************/
#define EXTI_IPIDR_IPID_Pos (0U)
#define EXTI_IPIDR_IPID_Msk (0xFFFFFFFFU << EXTI_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
#define EXTI_IPIDR_IPID EXTI_IPIDR_IPID_Msk /*!< IP Identification */
/********************** Bit definition for EXTI_SIDR register *****************/
#define EXTI_SIDR_SID_Pos (0U)
#define EXTI_SIDR_SID_Msk (0xFFFFFFFFU << EXTI_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define EXTI_SIDR_SID EXTI_SIDR_SID_Msk /*!< IP size identification */
/******************************************************************************/
/* */
/* FDCAN Controller */
/* */
/******************************************************************************/
/******************* Bit definition for FDCAN_CCCR register *****************/
#define FDCAN_CCCR_INIT_Pos (0U)
#define FDCAN_CCCR_INIT_Msk (0x1U << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!< Initialization bit */
#define FDCAN_CCCR_CCCE_Pos (1U)
#define FDCAN_CCCR_CCCE_Msk (0x1U << FDCAN_CCCR_CCCE_Pos) /*!< 0x00000002 */
#define FDCAN_CCCR_CCCE FDCAN_CCCR_CCCE_Msk /*!< Configuration Change Enable bit */
/******************************************************************************/
/* */
/* Flexible Memory Controller */
/* */
/******************************************************************************/
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_MBKEN_Pos (0U)
#define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
#define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
#define FMC_BCR1_MUXEN_Pos (1U)
#define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
#define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
#define FMC_BCR1_MTYP_Pos (2U)
#define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
#define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
#define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
#define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
#define FMC_BCR1_MWID_Pos (4U)
#define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
#define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
#define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
#define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
#define FMC_BCR1_FACCEN_Pos (6U)
#define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
#define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
#define FMC_BCR1_BURSTEN_Pos (8U)
#define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
#define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
#define FMC_BCR1_WAITPOL_Pos (9U)
#define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
#define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
#define FMC_BCR1_WRAPMOD_Pos (10U)
#define FMC_BCR1_WRAPMOD_Msk (0x1U << FMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */
#define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */
#define FMC_BCR1_WAITCFG_Pos (11U)
#define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
#define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
#define FMC_BCR1_WREN_Pos (12U)
#define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
#define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
#define FMC_BCR1_WAITEN_Pos (13U)
#define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
#define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
#define FMC_BCR1_EXTMOD_Pos (14U)
#define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
#define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
#define FMC_BCR1_ASYNCWAIT_Pos (15U)
#define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
#define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
#define FMC_BCR1_CPSIZE_Pos (16U)
#define FMC_BCR1_CPSIZE_Msk (0x7U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
#define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<PSIZE[2:0] bits CRAM Page Size */
#define FMC_BCR1_CPSIZE_0 (0x1U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
#define FMC_BCR1_CPSIZE_1 (0x2U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
#define FMC_BCR1_CPSIZE_2 (0x4U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
#define FMC_BCR1_CBURSTRW_Pos (19U)
#define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
#define FMC_BCR1_NBLSET_Pos (22U)
#define FMC_BCR1_NBLSET_Msk (0x3U << FMC_BCR1_NBLSET_Pos) /*!< 0x00C00000 */
#define FMC_BCR1_NBLSET FMC_BCR1_NBLSET_Msk /*!< NBLSET[1:0] bits Byte lane (NBL) SETUP */
#define FMC_BCR1_NBLSET_0 (0x1U << FMC_BCR1_NBLSET_Pos) /*!< 0x00400000 */
#define FMC_BCR1_NBLSET_1 (0x2U << FMC_BCR1_NBLSET_Pos) /*!< 0x00800000 */
#define FMC_BCR1_FMCEN_Pos (31U)
#define FMC_BCR1_FMCEN_Msk (0x1UL << FMC_BCR1_FMCEN_Pos) /*!< 0x80000000 */
#define FMC_BCR1_FMCEN FMC_BCR1_FMCEN_Msk /*!<FMC controller enable*/
/****************** Bit definition for FMC_BCR2 register *******************/
#define FMC_BCR2_MBKEN_Pos (0U)
#define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
#define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
#define FMC_BCR2_MUXEN_Pos (1U)
#define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
#define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
#define FMC_BCR2_MTYP_Pos (2U)
#define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
#define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
#define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
#define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
#define FMC_BCR2_MWID_Pos (4U)
#define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
#define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
#define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
#define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
#define FMC_BCR2_FACCEN_Pos (6U)
#define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
#define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
#define FMC_BCR2_BURSTEN_Pos (8U)
#define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
#define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
#define FMC_BCR2_WAITPOL_Pos (9U)
#define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
#define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
#define FMC_BCR2_WRAPMOD_Pos (10U)
#define FMC_BCR2_WRAPMOD_Msk (0x1U << FMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */
#define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */
#define FMC_BCR2_WAITCFG_Pos (11U)
#define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
#define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
#define FMC_BCR2_WREN_Pos (12U)
#define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
#define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
#define FMC_BCR2_WAITEN_Pos (13U)
#define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
#define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
#define FMC_BCR2_EXTMOD_Pos (14U)
#define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
#define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
#define FMC_BCR2_ASYNCWAIT_Pos (15U)
#define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
#define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
#define FMC_BCR2_PSIZE_Pos (16U)
#define FMC_BCR2_PSIZE_Msk (0x7U << FMC_BCR2_PSIZE_Pos) /*!< 0x00070000 */
#define FMC_BCR2_PSIZE FMC_BCR2_PSIZE_Msk /*!<PSIZE[2:0] bits CRAM Page Size */
#define FMC_BCR2_PSIZE_0 (0x1U << FMC_BCR2_PSIZE_Pos) /*!< 0x00010000 */
#define FMC_BCR2_PSIZE_1 (0x2U << FMC_BCR2_PSIZE_Pos) /*!< 0x00020000 */
#define FMC_BCR2_PSIZE_2 (0x4U << FMC_BCR2_PSIZE_Pos) /*!< 0x00040000 */
#define FMC_BCR2_CBURSTRW_Pos (19U)
#define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
#define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
#define FMC_BCR2_NBLSET_Pos (22U)
#define FMC_BCR2_NBLSET_Msk (0x3U << FMC_BCR1_NBLSET_Pos) /*!< 0x00C00000 */
#define FMC_BCR2_NBLSET FMC_BCR1_NBLSET_Msk /*!< NBLSET[1:0] bits Byte lane (NBL) SETUP */
#define FMC_BCR2_NBLSET_0 (0x1U << FMC_BCR1_NBLSET_Pos) /*!< 0x00400000 */
#define FMC_BCR2_NBLSET_1 (0x2U << FMC_BCR1_NBLSET_Pos) /*!< 0x00800000 */
/****************** Bit definition for FMC_BCR3 register *******************/
#define FMC_BCR3_MBKEN_Pos (0U)
#define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
#define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
#define FMC_BCR3_MUXEN_Pos (1U)
#define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
#define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
#define FMC_BCR3_MTYP_Pos (2U)
#define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
#define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
#define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
#define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
#define FMC_BCR3_MWID_Pos (4U)
#define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
#define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
#define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
#define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
#define FMC_BCR3_FACCEN_Pos (6U)
#define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
#define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
#define FMC_BCR3_BURSTEN_Pos (8U)
#define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
#define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
#define FMC_BCR3_WAITPOL_Pos (9U)
#define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
#define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
#define FMC_BCR3_WRAPMOD_Pos (10U)
#define FMC_BCR3_WRAPMOD_Msk (0x1U << FMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */
#define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */
#define FMC_BCR3_WAITCFG_Pos (11U)
#define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
#define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
#define FMC_BCR3_WREN_Pos (12U)
#define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
#define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
#define FMC_BCR3_WAITEN_Pos (13U)
#define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
#define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
#define FMC_BCR3_EXTMOD_Pos (14U)
#define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
#define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
#define FMC_BCR3_ASYNCWAIT_Pos (15U)
#define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
#define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
#define FMC_BCR3_PSIZE_Pos (16U)
#define FMC_BCR3_PSIZE_Msk (0x7U << FMC_BCR3_PSIZE_Pos) /*!< 0x00070000 */
#define FMC_BCR3_PSIZE FMC_BCR3_PSIZE_Msk /*!<PSIZE[2:0] bits CRAM Page Size */
#define FMC_BCR3_PSIZE_0 (0x1U << FMC_BCR3_PSIZE_Pos) /*!< 0x00010000 */
#define FMC_BCR3_PSIZE_1 (0x2U << FMC_BCR3_PSIZE_Pos) /*!< 0x00020000 */
#define FMC_BCR3_PSIZE_2 (0x4U << FMC_BCR3_PSIZE_Pos) /*!< 0x00040000 */
#define FMC_BCR3_CBURSTRW_Pos (19U)
#define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
#define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
#define FMC_BCR3_NBLSET_Pos (22U)
#define FMC_BCR3_NBLSET_Msk (0x3U << FMC_BCR1_NBLSET_Pos) /*!< 0x00C00000 */
#define FMC_BCR3_NBLSET FMC_BCR1_NBLSET_Msk /*!< NBLSET[1:0] bits Byte lane (NBL) SETUP */
#define FMC_BCR3_NBLSET_0 (0x1U << FMC_BCR1_NBLSET_Pos) /*!< 0x00400000 */
#define FMC_BCR3_NBLSET_1 (0x2U << FMC_BCR1_NBLSET_Pos) /*!< 0x00800000 */
/****************** Bit definition for FMC_BCR4 register *******************/
#define FMC_BCR4_MBKEN_Pos (0U)
#define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
#define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
#define FMC_BCR4_MUXEN_Pos (1U)
#define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
#define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
#define FMC_BCR4_MTYP_Pos (2U)
#define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
#define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
#define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
#define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
#define FMC_BCR4_MWID_Pos (4U)
#define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
#define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
#define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
#define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
#define FMC_BCR4_FACCEN_Pos (6U)
#define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
#define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
#define FMC_BCR4_BURSTEN_Pos (8U)
#define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
#define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
#define FMC_BCR4_WAITPOL_Pos (9U)
#define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
#define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
#define FMC_BCR4_WRAPMOD_Pos (10U)
#define FMC_BCR4_WRAPMOD_Msk (0x1U << FMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */
#define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */
#define FMC_BCR4_WAITCFG_Pos (11U)
#define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
#define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
#define FMC_BCR4_WREN_Pos (12U)
#define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
#define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
#define FMC_BCR4_WAITEN_Pos (13U)
#define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
#define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
#define FMC_BCR4_EXTMOD_Pos (14U)
#define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
#define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
#define FMC_BCR4_ASYNCWAIT_Pos (15U)
#define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
#define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
#define FMC_BCR4_PSIZE_Pos (16U)
#define FMC_BCR4_PSIZE_Msk (0x7U << FMC_BCR4_PSIZE_Pos) /*!< 0x00070000 */
#define FMC_BCR4_PSIZE FMC_BCR4_PSIZE_Msk /*!<PSIZE[2:0] bits CRAM Page Size */
#define FMC_BCR4_PSIZE_0 (0x1U << FMC_BCR4_PSIZE_Pos) /*!< 0x00010000 */
#define FMC_BCR4_PSIZE_1 (0x2U << FMC_BCR4_PSIZE_Pos) /*!< 0x00020000 */
#define FMC_BCR4_PSIZE_2 (0x4U << FMC_BCR4_PSIZE_Pos) /*!< 0x00040000 */
#define FMC_BCR4_CBURSTRW_Pos (19U)
#define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
#define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
#define FMC_BCR4_NBLSET_Pos (22U)
#define FMC_BCR4_NBLSET_Msk (0x3U << FMC_BCR1_NBLSET_Pos) /*!< 0x00C00000 */
#define FMC_BCR4_NBLSET FMC_BCR1_NBLSET_Msk /*!< NBLSET[1:0] bits Byte lane (NBL) SETUP */
#define FMC_BCR4_NBLSET_0 (0x1U << FMC_BCR1_NBLSET_Pos) /*!< 0x00400000 */
#define FMC_BCR4_NBLSET_1 (0x2U << FMC_BCR1_NBLSET_Pos) /*!< 0x00800000 */
/****************** Bit definition for FMC_BTR1 register ******************/
#define FMC_BTR1_ADDSET_Pos (0U)
#define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BTR1_ADDHLD_Pos (4U)
#define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BTR1_DATAST_Pos (8U)
#define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BTR1_BUSTURN_Pos (16U)
#define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
#define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
#define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
#define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
#define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
#define FMC_BTR1_CLKDIV_Pos (20U)
#define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
#define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
#define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
#define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
#define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
#define FMC_BTR1_DATLAT_Pos (24U)
#define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
#define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
#define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
#define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
#define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
#define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
#define FMC_BTR1_ACCMOD_Pos (28U)
#define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
#define FMC_BTR1_DATAHLD_Pos (30U)
#define FMC_BTR1_DATAHLD_Msk (0x3U << FMC_BTR1_DATAHLD_Pos) /*!< 0xC0000000 */
#define FMC_BTR1_DATAHLD FMC_BTR1_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data Hold phase duration) */
#define FMC_BTR1_DATAHLD_0 (0x1U << FMC_BTR1_DATAHLD_Pos) /*!< 0x40000000 */
#define FMC_BTR1_DATAHLD_1 (0x2U << FMC_BTR1_DATAHLD_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_BTR2 register *******************/
#define FMC_BTR2_ADDSET_Pos (0U)
#define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BTR2_ADDHLD_Pos (4U)
#define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BTR2_DATAST_Pos (8U)
#define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BTR2_BUSTURN_Pos (16U)
#define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
#define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
#define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
#define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
#define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
#define FMC_BTR2_CLKDIV_Pos (20U)
#define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
#define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
#define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
#define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
#define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
#define FMC_BTR2_DATLAT_Pos (24U)
#define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
#define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
#define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
#define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
#define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
#define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
#define FMC_BTR2_ACCMOD_Pos (28U)
#define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
#define FMC_BTR2_DATAHLD_Pos (30U)
#define FMC_BTR2_DATAHLD_Msk (0x3U << FMC_BTR2_DATAHLD_Pos) /*!< 0xC0000000 */
#define FMC_BTR2_DATAHLD FMC_BTR2_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data Hold phase duration) */
#define FMC_BTR2_DATAHLD_0 (0x1U << FMC_BTR2_DATAHLD_Pos) /*!< 0x40000000 */
#define FMC_BTR2_DATAHLD_1 (0x2U << FMC_BTR2_DATAHLD_Pos) /*!< 0x80000000 */
/******************* Bit definition for FMC_BTR3 register *******************/
#define FMC_BTR3_ADDSET_Pos (0U)
#define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BTR3_ADDHLD_Pos (4U)
#define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BTR3_DATAST_Pos (8U)
#define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BTR3_BUSTURN_Pos (16U)
#define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
#define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
#define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
#define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
#define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
#define FMC_BTR3_CLKDIV_Pos (20U)
#define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
#define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
#define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
#define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
#define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
#define FMC_BTR3_DATLAT_Pos (24U)
#define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
#define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
#define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
#define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
#define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
#define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
#define FMC_BTR3_ACCMOD_Pos (28U)
#define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
#define FMC_BTR3_DATAHLD_Pos (30U)
#define FMC_BTR3_DATAHLD_Msk (0x3U << FMC_BTR3_DATAHLD_Pos) /*!< 0xC0000000 */
#define FMC_BTR3_DATAHLD FMC_BTR3_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data Hold phase duration) */
#define FMC_BTR3_DATAHLD_0 (0x1U << FMC_BTR3_DATAHLD_Pos) /*!< 0x40000000 */
#define FMC_BTR3_DATAHLD_1 (0x2U << FMC_BTR3_DATAHLD_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_BTR4 register *******************/
#define FMC_BTR4_ADDSET_Pos (0U)
#define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BTR4_ADDHLD_Pos (4U)
#define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BTR4_DATAST_Pos (8U)
#define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BTR4_BUSTURN_Pos (16U)
#define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
#define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
#define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
#define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
#define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
#define FMC_BTR4_CLKDIV_Pos (20U)
#define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
#define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
#define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
#define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
#define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
#define FMC_BTR4_DATLAT_Pos (24U)
#define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
#define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
#define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
#define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
#define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
#define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
#define FMC_BTR4_ACCMOD_Pos (28U)
#define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
#define FMC_BTR4_DATAHLD_Pos (30U)
#define FMC_BTR4_DATAHLD_Msk (0x3U << FMC_BTR4_DATAHLD_Pos) /*!< 0xC0000000 */
#define FMC_BTR4_DATAHLD FMC_BTR4_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data Hold phase duration) */
#define FMC_BTR4_DATAHLD_0 (0x1U << FMC_BTR4_DATAHLD_Pos) /*!< 0x40000000 */
#define FMC_BTR4_DATAHLD_1 (0x2U << FMC_BTR4_DATAHLD_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_PCSCNTR register *****************/
#define FMC_PCSCNTR_CSCOUNT_Pos (0U)
#define FMC_PCSCNTR_CSCOUNT_Msk (0xFFFFU << FMC_PCSCNTR_CSCOUNT_Pos) /*!< 0x0000FFFF */
#define FMC_PCSCNTR_CSCOUNT FMC_PCSCNTR_CSCOUNT_Msk /*!<CSCOUNT[15:0] bits Chip Select (CS) counter */
#define FMC_PCSCNTR_CNTB1EN_Pos (16U)
#define FMC_PCSCNTR_CNTB1EN_Msk (0x1U << FMC_PCSCNTR_CNTB1EN_Pos) /*!< 0x00010000 */
#define FMC_PCSCNTR_CNTB1EN FMC_PCSCNTR_CNTB1EN_Msk /*!<CNTB1EN bit Counter Bank1 enable */
#define FMC_PCSCNTR_CNTB2EN_Pos (17U)
#define FMC_PCSCNTR_CNTB2EN_Msk (0x1U << FMC_PCSCNTR_CNTB2EN_Pos) /*!< 0x00020000 */
#define FMC_PCSCNTR_CNTB2EN FMC_PCSCNTR_CNTB2EN_Msk /*!<CNTB2EN bit Counter Bank2 enable */
#define FMC_PCSCNTR_CNTB3EN_Pos (18U)
#define FMC_PCSCNTR_CNTB3EN_Msk (0x1U << FMC_PCSCNTR_CNTB3EN_Pos) /*!< 0x00040000 */
#define FMC_PCSCNTR_CNTB3EN FMC_PCSCNTR_CNTB3EN_Msk /*!<CNTB3EN bit Counter Bank3 enable */
#define FMC_PCSCNTR_CNTB4EN_Pos (19U)
#define FMC_PCSCNTR_CNTB4EN_Msk (0x1U << FMC_PCSCNTR_CNTB4EN_Pos) /*!< 0x00080000 */
#define FMC_PCSCNTR_CNTB4EN FMC_PCSCNTR_CNTB4EN_Msk /*!<CNTB4EN bit Counter Bank4 enable */
/****************** Bit definition for FMC_BWTR1 register ******************/
#define FMC_BWTR1_ADDSET_Pos (0U)
#define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BWTR1_ADDHLD_Pos (4U)
#define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BWTR1_DATAST_Pos (8U)
#define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BWTR1_CLKDIV_Pos (20U)
#define FMC_BWTR1_CLKDIV_Msk (0xFU << FMC_BWTR1_CLKDIV_Pos) /*!< 0x00F00000 */
#define FMC_BWTR1_CLKDIV FMC_BWTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BWTR1_CLKDIV_0 (0x1U << FMC_BWTR1_CLKDIV_Pos) /*!< 0x00100000 */
#define FMC_BWTR1_CLKDIV_1 (0x2U << FMC_BWTR1_CLKDIV_Pos) /*!< 0x00200000 */
#define FMC_BWTR1_CLKDIV_2 (0x4U << FMC_BWTR1_CLKDIV_Pos) /*!< 0x00400000 */
#define FMC_BWTR1_CLKDIV_3 (0x8U << FMC_BWTR1_CLKDIV_Pos) /*!< 0x00800000 */
#define FMC_BWTR1_DATLAT_Pos (24U)
#define FMC_BWTR1_DATLAT_Msk (0xFU << FMC_BWTR1_DATLAT_Pos) /*!< 0x0F000000 */
#define FMC_BWTR1_DATLAT FMC_BWTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
#define FMC_BWTR1_DATLAT_0 (0x1U << FMC_BWTR1_DATLAT_Pos) /*!< 0x01000000 */
#define FMC_BWTR1_DATLAT_1 (0x2U << FMC_BWTR1_DATLAT_Pos) /*!< 0x02000000 */
#define FMC_BWTR1_DATLAT_2 (0x4U << FMC_BWTR1_DATLAT_Pos) /*!< 0x04000000 */
#define FMC_BWTR1_DATLAT_3 (0x8U << FMC_BWTR1_DATLAT_Pos) /*!< 0x08000000 */
#define FMC_BWTR1_BUSTURN_Pos (16U)
#define FMC_BWTR1_BUSTURN_Msk (0xFU << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
#define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FMC_BWTR1_BUSTURN_0 (0x1U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
#define FMC_BWTR1_BUSTURN_1 (0x2U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
#define FMC_BWTR1_BUSTURN_2 (0x4U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
#define FMC_BWTR1_BUSTURN_3 (0x8U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
#define FMC_BWTR1_ACCMOD_Pos (28U)
#define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
#define FMC_BWTR1_DATAHLD_Pos (30U)
#define FMC_BWTR1_DATAHLD_Msk (0x3U << FMC_BWTR1_DATAHLD_Pos) /*!< 0xC0000000 */
#define FMC_BWTR1_DATAHLD FMC_BWTR1_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data Hold phase duration) */
#define FMC_BWTR1_DATAHLD_0 (0x1U << FMC_BWTR1_DATAHLD_Pos) /*!< 0x40000000 */
#define FMC_BWTR1_DATAHLD_1 (0x2U << FMC_BWTR1_DATAHLD_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_BWTR2 register ******************/
#define FMC_BWTR2_ADDSET_Pos (0U)
#define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BWTR2_ADDHLD_Pos (4U)
#define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BWTR2_DATAST_Pos (8U)
#define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BWTR2_CLKDIV_Pos (20U)
#define FMC_BWTR2_CLKDIV_Msk (0xFU << FMC_BWTR2_CLKDIV_Pos) /*!< 0x00F00000 */
#define FMC_BWTR2_CLKDIV FMC_BWTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BWTR2_CLKDIV_0 (0x1U << FMC_BWTR2_CLKDIV_Pos) /*!< 0x00100000 */
#define FMC_BWTR2_CLKDIV_1 (0x2U << FMC_BWTR2_CLKDIV_Pos) /*!< 0x00200000 */
#define FMC_BWTR2_CLKDIV_2 (0x4U << FMC_BWTR2_CLKDIV_Pos) /*!< 0x00400000 */
#define FMC_BWTR2_CLKDIV_3 (0x8U << FMC_BWTR2_CLKDIV_Pos) /*!< 0x00800000 */
#define FMC_BWTR2_DATLAT_Pos (24U)
#define FMC_BWTR2_DATLAT_Msk (0xFU << FMC_BWTR2_DATLAT_Pos) /*!< 0x0F000000 */
#define FMC_BWTR2_DATLAT FMC_BWTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
#define FMC_BWTR2_DATLAT_0 (0x1U << FMC_BWTR2_DATLAT_Pos) /*!< 0x01000000 */
#define FMC_BWTR2_DATLAT_1 (0x2U << FMC_BWTR2_DATLAT_Pos) /*!< 0x02000000 */
#define FMC_BWTR2_DATLAT_2 (0x4U << FMC_BWTR2_DATLAT_Pos) /*!< 0x04000000 */
#define FMC_BWTR2_DATLAT_3 (0x8U << FMC_BWTR2_DATLAT_Pos) /*!< 0x08000000 */
#define FMC_BWTR2_ACCMOD_Pos (28U)
#define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
#define FMC_BWTR2_DATAHLD_Pos (30U)
#define FMC_BWTR2_DATAHLD_Msk (0x3U << FMC_BWTR2_DATAHLD_Pos) /*!< 0xC0000000 */
#define FMC_BWTR2_DATAHLD FMC_BWTR2_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data Hold phase duration) */
#define FMC_BWTR2_DATAHLD_0 (0x1U << FMC_BWTR2_DATAHLD_Pos) /*!< 0x40000000 */
#define FMC_BWTR2_DATAHLD_1 (0x2U << FMC_BWTR2_DATAHLD_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_BWTR3 register ******************/
#define FMC_BWTR3_ADDSET_Pos (0U)
#define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BWTR3_ADDHLD_Pos (4U)
#define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BWTR3_DATAST_Pos (8U)
#define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BWTR3_CLKDIV_Pos (20U)
#define FMC_BWTR3_CLKDIV_Msk (0xFU << FMC_BWTR3_CLKDIV_Pos) /*!< 0x00F00000 */
#define FMC_BWTR3_CLKDIV FMC_BWTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BWTR3_CLKDIV_0 (0x1U << FMC_BWTR3_CLKDIV_Pos) /*!< 0x00100000 */
#define FMC_BWTR3_CLKDIV_1 (0x2U << FMC_BWTR3_CLKDIV_Pos) /*!< 0x00200000 */
#define FMC_BWTR3_CLKDIV_2 (0x4U << FMC_BWTR3_CLKDIV_Pos) /*!< 0x00400000 */
#define FMC_BWTR3_CLKDIV_3 (0x8U << FMC_BWTR3_CLKDIV_Pos) /*!< 0x00800000 */
#define FMC_BWTR3_DATLAT_Pos (24U)
#define FMC_BWTR3_DATLAT_Msk (0xFU << FMC_BWTR3_DATLAT_Pos) /*!< 0x0F000000 */
#define FMC_BWTR3_DATLAT FMC_BWTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
#define FMC_BWTR3_DATLAT_0 (0x1U << FMC_BWTR3_DATLAT_Pos) /*!< 0x01000000 */
#define FMC_BWTR3_DATLAT_1 (0x2U << FMC_BWTR3_DATLAT_Pos) /*!< 0x02000000 */
#define FMC_BWTR3_DATLAT_2 (0x4U << FMC_BWTR3_DATLAT_Pos) /*!< 0x04000000 */
#define FMC_BWTR3_DATLAT_3 (0x8U << FMC_BWTR3_DATLAT_Pos) /*!< 0x08000000 */
#define FMC_BWTR3_ACCMOD_Pos (28U)
#define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
#define FMC_BWTR3_DATAHLD_Pos (30U)
#define FMC_BWTR3_DATAHLD_Msk (0x3U << FMC_BWTR3_DATAHLD_Pos) /*!< 0xC0000000 */
#define FMC_BWTR3_DATAHLD FMC_BWTR3_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data Hold phase duration) */
#define FMC_BWTR3_DATAHLD_0 (0x1U << FMC_BWTR3_DATAHLD_Pos) /*!< 0x40000000 */
#define FMC_BWTR3_DATAHLD_1 (0x2U << FMC_BWTR3_DATAHLD_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_BWTR4 register ******************/
#define FMC_BWTR4_ADDSET_Pos (0U)
#define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BWTR4_ADDHLD_Pos (4U)
#define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BWTR4_DATAST_Pos (8U)
#define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BWTR4_CLKDIV_Pos (20U)
#define FMC_BWTR4_CLKDIV_Msk (0xFU << FMC_BWTR4_CLKDIV_Pos) /*!< 0x00F00000 */
#define FMC_BWTR4_CLKDIV FMC_BWTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BWTR4_CLKDIV_0 (0x1U << FMC_BWTR4_CLKDIV_Pos) /*!< 0x00100000 */
#define FMC_BWTR4_CLKDIV_1 (0x2U << FMC_BWTR4_CLKDIV_Pos) /*!< 0x00200000 */
#define FMC_BWTR4_CLKDIV_2 (0x4U << FMC_BWTR4_CLKDIV_Pos) /*!< 0x00400000 */
#define FMC_BWTR4_CLKDIV_3 (0x8U << FMC_BWTR4_CLKDIV_Pos) /*!< 0x00800000 */
#define FMC_BWTR4_DATLAT_Pos (24U)
#define FMC_BWTR4_DATLAT_Msk (0xFU << FMC_BWTR4_DATLAT_Pos) /*!< 0x0F000000 */
#define FMC_BWTR4_DATLAT FMC_BWTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
#define FMC_BWTR4_DATLAT_0 (0x1U << FMC_BWTR4_DATLAT_Pos) /*!< 0x01000000 */
#define FMC_BWTR4_DATLAT_1 (0x2U << FMC_BWTR4_DATLAT_Pos) /*!< 0x02000000 */
#define FMC_BWTR4_DATLAT_2 (0x4U << FMC_BWTR4_DATLAT_Pos) /*!< 0x04000000 */
#define FMC_BWTR4_DATLAT_3 (0x8U << FMC_BWTR4_DATLAT_Pos) /*!< 0x08000000 */
#define FMC_BWTR4_ACCMOD_Pos (28U)
#define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
#define FMC_BWTR4_DATAHLD_Pos (30U)
#define FMC_BWTR4_DATAHLD_Msk (0x3U << FMC_BWTR4_DATAHLD_Pos) /*!< 0xC0000000 */
#define FMC_BWTR4_DATAHLD FMC_BWTR4_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data Hold phase duration) */
#define FMC_BWTR4_DATAHLD_0 (0x1U << FMC_BWTR4_DATAHLD_Pos) /*!< 0x40000000 */
#define FMC_BWTR4_DATAHLD_1 (0x2U << FMC_BWTR4_DATAHLD_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_PCR register *******************/
#define FMC_PCR_PWAITEN_Pos (1U)
#define FMC_PCR_PWAITEN_Msk (0x1U << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
#define FMC_PCR_PBKEN_Pos (2U)
#define FMC_PCR_PBKEN_Msk (0x1U << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<NAND Flash memory bank enable bit */
#define FMC_PCR_PWID_Pos (4U)
#define FMC_PCR_PWID_Msk (0x3U << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
#define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
#define FMC_PCR_PWID_0 (0x1U << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
#define FMC_PCR_PWID_1 (0x2U << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
#define FMC_PCR_ECCEN_Pos (6U)
#define FMC_PCR_ECCEN_Msk (0x1U << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
#define FMC_PCR_ECCALG_Pos (8U)
#define FMC_PCR_ECCALG_Msk (0x1U << FMC_PCR_ECCALG_Pos) /*!< 0x00000100 */
#define FMC_PCR_ECCALG FMC_PCR_ECCEN_Msk /*!<ECC algorithm */
#define FMC_PCR_TCLR_Pos (9U)
#define FMC_PCR_TCLR_Msk (0xFU << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
#define FMC_PCR_TCLR_0 (0x1U << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
#define FMC_PCR_TCLR_1 (0x2U << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
#define FMC_PCR_TCLR_2 (0x4U << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
#define FMC_PCR_TCLR_3 (0x8U << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
#define FMC_PCR_TAR_Pos (13U)
#define FMC_PCR_TAR_Msk (0xFU << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
#define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
#define FMC_PCR_TAR_0 (0x1U << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
#define FMC_PCR_TAR_1 (0x2U << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
#define FMC_PCR_TAR_2 (0x4U << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
#define FMC_PCR_TAR_3 (0x8U << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
#define FMC_PCR_ECCSS_Pos (17U)
#define FMC_PCR_ECCSS_Msk (0x7U << FMC_PCR_ECCSS_Pos) /*!< 0x000E0000 */
#define FMC_PCR_ECCSS FMC_PCR_ECCSS_Msk /*!<ECCSS[1:0] bits (ECC sector size) */
#define FMC_PCR_ECCSS_0 (0x1U << FMC_PCR_ECCSS_Pos) /*!< 0x00020000 */
#define FMC_PCR_ECCSS_1 (0x2U << FMC_PCR_ECCSS_Pos) /*!< 0x00040000 */
#define FMC_PCR_ECCSS_2 (0x4U << FMC_PCR_ECCSS_Pos) /*!< 0x00080000 */
#define FMC_PCR_TCEH_Pos (20U)
#define FMC_PCR_TCEH_Msk (0xFU << FMC_PCR_TCEH_Pos) /*!< 0x00F00000 */
#define FMC_PCR_TCEH FMC_PCR_TCEH_Msk /*!<TCEH[3:0] bits (Chip select high timing) */
#define FMC_PCR_BCHECC_Pos (24U)
#define FMC_PCR_BCHECC_Msk (0x1U << FMC_PCR_BCHECC_Pos) /*!< 0x01000000 */
#define FMC_PCR_BCHECC FMC_PCR_BCHECC_Msk /*!<BCHECC bit (BCH error correction capability) */
#define FMC_PCR_WEN_Pos (25U)
#define FMC_PCR_WEN_Msk (0x1U << FMC_PCR_WEN_Pos) /*!< 0x02000000 */
#define FMC_PCR_WEN FMC_PCR_WEN_Msk /*!<WEN bit (Write enable) */
/******************* Bit definition for FMC_SR register *******************/
#define FMC_SR_ISOST_Pos (0U)
#define FMC_SR_ISOST_Msk (0x3U << FMC_SR_ISOST_Pos) /*!< 0x00000003 */
#define FMC_SR_ISOST FMC_SR_ISOST_Msk /*!<ISOST[1:0] bits (FMC isolation state with respect to the AXI interface) */
#define FMC_SR_PEF_Pos (4U)
#define FMC_SR_PEF_Msk (0x1U << FMC_SR_PEF_Pos) /*!< 0x00000010 */
#define FMC_SR_PEF FMC_SR_PEF_Msk /*!<Pipe Empty Flag */
#define FMC_SR_NWRF_Pos (6U)
#define FMC_SR_NWRF_Msk (0x1U << FMC_SR_NWRF_Pos) /*!< 0x00000040 */
#define FMC_SR_NWRF FMC_SR_NWRF_Msk /*!<NAND write request flag */
/****************** Bit definition for FMC_PMEM register ******************/
#define FMC_PMEM_MEMSET3_Pos (0U)
#define FMC_PMEM_MEMSET3_Msk (0xFFU << FMC_PMEM_MEMSET3_Pos) /*!< 0x000000FF */
#define FMC_PMEM_MEMSET3 FMC_PMEM_MEMSET3_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
#define FMC_PMEM_MEMSET3_0 (0x01U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000001 */
#define FMC_PMEM_MEMSET3_1 (0x02U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000002 */
#define FMC_PMEM_MEMSET3_2 (0x04U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000004 */
#define FMC_PMEM_MEMSET3_3 (0x08U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000008 */
#define FMC_PMEM_MEMSET3_4 (0x10U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000010 */
#define FMC_PMEM_MEMSET3_5 (0x20U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000020 */
#define FMC_PMEM_MEMSET3_6 (0x40U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000040 */
#define FMC_PMEM_MEMSET3_7 (0x80U << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000080 */
#define FMC_PMEM_MEMWAIT3_Pos (8U)
#define FMC_PMEM_MEMWAIT3_Msk (0xFFU << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x0000FF00 */
#define FMC_PMEM_MEMWAIT3 FMC_PMEM_MEMWAIT3_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
#define FMC_PMEM_MEMWAIT3_0 (0x01U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000100 */
#define FMC_PMEM_MEMWAIT3_1 (0x02U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000200 */
#define FMC_PMEM_MEMWAIT3_2 (0x04U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000400 */
#define FMC_PMEM_MEMWAIT3_3 (0x08U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000800 */
#define FMC_PMEM_MEMWAIT3_4 (0x10U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00001000 */
#define FMC_PMEM_MEMWAIT3_5 (0x20U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00002000 */
#define FMC_PMEM_MEMWAIT3_6 (0x40U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00004000 */
#define FMC_PMEM_MEMWAIT3_7 (0x80U << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00008000 */
#define FMC_PMEM_MEMHOLD3_Pos (16U)
#define FMC_PMEM_MEMHOLD3_Msk (0xFFU << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00FF0000 */
#define FMC_PMEM_MEMHOLD3 FMC_PMEM_MEMHOLD3_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
#define FMC_PMEM_MEMHOLD3_0 (0x01U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00010000 */
#define FMC_PMEM_MEMHOLD3_1 (0x02U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00020000 */
#define FMC_PMEM_MEMHOLD3_2 (0x04U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00040000 */
#define FMC_PMEM_MEMHOLD3_3 (0x08U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00080000 */
#define FMC_PMEM_MEMHOLD3_4 (0x10U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00100000 */
#define FMC_PMEM_MEMHOLD3_5 (0x20U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00200000 */
#define FMC_PMEM_MEMHOLD3_6 (0x40U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00400000 */
#define FMC_PMEM_MEMHOLD3_7 (0x80U << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00800000 */
#define FMC_PMEM_MEMHIZ3_Pos (24U)
#define FMC_PMEM_MEMHIZ3_Msk (0xFFU << FMC_PMEM_MEMHIZ3_Pos) /*!< 0xFF000000 */
#define FMC_PMEM_MEMHIZ3 FMC_PMEM_MEMHIZ3_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
#define FMC_PMEM_MEMHIZ3_0 (0x01U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x01000000 */
#define FMC_PMEM_MEMHIZ3_1 (0x02U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x02000000 */
#define FMC_PMEM_MEMHIZ3_2 (0x04U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x04000000 */
#define FMC_PMEM_MEMHIZ3_3 (0x08U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x08000000 */
#define FMC_PMEM_MEMHIZ3_4 (0x10U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x10000000 */
#define FMC_PMEM_MEMHIZ3_5 (0x20U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x20000000 */
#define FMC_PMEM_MEMHIZ3_6 (0x40U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x40000000 */
#define FMC_PMEM_MEMHIZ3_7 (0x80U << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_PATT register ******************/
#define FMC_PATT_ATTSET3_Pos (0U)
#define FMC_PATT_ATTSET3_Msk (0xFFU << FMC_PATT_ATTSET3_Pos) /*!< 0x000000FF */
#define FMC_PATT_ATTSET3 FMC_PATT_ATTSET3_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
#define FMC_PATT_ATTSET3_0 (0x01U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000001 */
#define FMC_PATT_ATTSET3_1 (0x02U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000002 */
#define FMC_PATT_ATTSET3_2 (0x04U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000004 */
#define FMC_PATT_ATTSET3_3 (0x08U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000008 */
#define FMC_PATT_ATTSET3_4 (0x10U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000010 */
#define FMC_PATT_ATTSET3_5 (0x20U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000020 */
#define FMC_PATT_ATTSET3_6 (0x40U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000040 */
#define FMC_PATT_ATTSET3_7 (0x80U << FMC_PATT_ATTSET3_Pos) /*!< 0x00000080 */
#define FMC_PATT_ATTWAIT3_Pos (8U)
#define FMC_PATT_ATTWAIT3_Msk (0xFFU << FMC_PATT_ATTWAIT3_Pos) /*!< 0x0000FF00 */
#define FMC_PATT_ATTWAIT3 FMC_PATT_ATTWAIT3_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
#define FMC_PATT_ATTWAIT3_0 (0x01U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000100 */
#define FMC_PATT_ATTWAIT3_1 (0x02U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000200 */
#define FMC_PATT_ATTWAIT3_2 (0x04U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000400 */
#define FMC_PATT_ATTWAIT3_3 (0x08U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000800 */
#define FMC_PATT_ATTWAIT3_4 (0x10U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00001000 */
#define FMC_PATT_ATTWAIT3_5 (0x20U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00002000 */
#define FMC_PATT_ATTWAIT3_6 (0x40U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00004000 */
#define FMC_PATT_ATTWAIT3_7 (0x80U << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00008000 */
#define FMC_PATT_ATTHOLD3_Pos (16U)
#define FMC_PATT_ATTHOLD3_Msk (0xFFU << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00FF0000 */
#define FMC_PATT_ATTHOLD3 FMC_PATT_ATTHOLD3_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
#define FMC_PATT_ATTHOLD3_0 (0x01U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00010000 */
#define FMC_PATT_ATTHOLD3_1 (0x02U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00020000 */
#define FMC_PATT_ATTHOLD3_2 (0x04U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00040000 */
#define FMC_PATT_ATTHOLD3_3 (0x08U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00080000 */
#define FMC_PATT_ATTHOLD3_4 (0x10U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00100000 */
#define FMC_PATT_ATTHOLD3_5 (0x20U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00200000 */
#define FMC_PATT_ATTHOLD3_6 (0x40U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00400000 */
#define FMC_PATT_ATTHOLD3_7 (0x80U << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00800000 */
#define FMC_PATT_ATTHIZ3_Pos (24U)
#define FMC_PATT_ATTHIZ3_Msk (0xFFU << FMC_PATT_ATTHIZ3_Pos) /*!< 0xFF000000 */
#define FMC_PATT_ATTHIZ3 FMC_PATT_ATTHIZ3_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
#define FMC_PATT_ATTHIZ3_0 (0x01U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x01000000 */
#define FMC_PATT_ATTHIZ3_1 (0x02U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x02000000 */
#define FMC_PATT_ATTHIZ3_2 (0x04U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x04000000 */
#define FMC_PATT_ATTHIZ3_3 (0x08U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x08000000 */
#define FMC_PATT_ATTHIZ3_4 (0x10U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x10000000 */
#define FMC_PATT_ATTHIZ3_5 (0x20U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x20000000 */
#define FMC_PATT_ATTHIZ3_6 (0x40U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x40000000 */
#define FMC_PATT_ATTHIZ3_7 (0x80U << FMC_PATT_ATTHIZ3_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_PIO4 register *******************/
#define FMC_PIO4_IOSET4_Pos (0U)
#define FMC_PIO4_IOSET4_Msk (0xFFU << FMC_PIO4_IOSET4_Pos) /*!< 0x000000FF */
#define FMC_PIO4_IOSET4 FMC_PIO4_IOSET4_Msk /*!<IOSET4[7:0] bits (I/O 4 setup time) */
#define FMC_PIO4_IOSET4_0 (0x01U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000001 */
#define FMC_PIO4_IOSET4_1 (0x02U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000002 */
#define FMC_PIO4_IOSET4_2 (0x04U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000004 */
#define FMC_PIO4_IOSET4_3 (0x08U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000008 */
#define FMC_PIO4_IOSET4_4 (0x10U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000010 */
#define FMC_PIO4_IOSET4_5 (0x20U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000020 */
#define FMC_PIO4_IOSET4_6 (0x40U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000040 */
#define FMC_PIO4_IOSET4_7 (0x80U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000080 */
#define FMC_PIO4_IOWAIT4_Pos (8U)
#define FMC_PIO4_IOWAIT4_Msk (0xFFU << FMC_PIO4_IOWAIT4_Pos) /*!< 0x0000FF00 */
#define FMC_PIO4_IOWAIT4 FMC_PIO4_IOWAIT4_Msk /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
#define FMC_PIO4_IOWAIT4_0 (0x01U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000100 */
#define FMC_PIO4_IOWAIT4_1 (0x02U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000200 */
#define FMC_PIO4_IOWAIT4_2 (0x04U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000400 */
#define FMC_PIO4_IOWAIT4_3 (0x08U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000800 */
#define FMC_PIO4_IOWAIT4_4 (0x10U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00001000 */
#define FMC_PIO4_IOWAIT4_5 (0x20U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00002000 */
#define FMC_PIO4_IOWAIT4_6 (0x40U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00004000 */
#define FMC_PIO4_IOWAIT4_7 (0x80U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00008000 */
#define FMC_PIO4_IOHOLD4_Pos (16U)
#define FMC_PIO4_IOHOLD4_Msk (0xFFU << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00FF0000 */
#define FMC_PIO4_IOHOLD4 FMC_PIO4_IOHOLD4_Msk /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
#define FMC_PIO4_IOHOLD4_0 (0x01U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00010000 */
#define FMC_PIO4_IOHOLD4_1 (0x02U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00020000 */
#define FMC_PIO4_IOHOLD4_2 (0x04U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00040000 */
#define FMC_PIO4_IOHOLD4_3 (0x08U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00080000 */
#define FMC_PIO4_IOHOLD4_4 (0x10U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00100000 */
#define FMC_PIO4_IOHOLD4_5 (0x20U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00200000 */
#define FMC_PIO4_IOHOLD4_6 (0x40U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00400000 */
#define FMC_PIO4_IOHOLD4_7 (0x80U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00800000 */
#define FMC_PIO4_IOHIZ4_Pos (24U)
#define FMC_PIO4_IOHIZ4_Msk (0xFFU << FMC_PIO4_IOHIZ4_Pos) /*!< 0xFF000000 */
#define FMC_PIO4_IOHIZ4 FMC_PIO4_IOHIZ4_Msk /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
#define FMC_PIO4_IOHIZ4_0 (0x01U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x01000000 */
#define FMC_PIO4_IOHIZ4_1 (0x02U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x02000000 */
#define FMC_PIO4_IOHIZ4_2 (0x04U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x04000000 */
#define FMC_PIO4_IOHIZ4_3 (0x08U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x08000000 */
#define FMC_PIO4_IOHIZ4_4 (0x10U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x10000000 */
#define FMC_PIO4_IOHIZ4_5 (0x20U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x20000000 */
#define FMC_PIO4_IOHIZ4_6 (0x40U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x40000000 */
#define FMC_PIO4_IOHIZ4_7 (0x80U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x80000000 */
/********************** Bit definition for FMC_VERR register *****************/
#define FMC_VERR_MINREV_Pos (0U)
#define FMC_VERR_MINREV_Msk (0xFU << FMC_VERR_MINREV_Pos) /*!< 0x0000000F */
#define FMC_VERR_MINREV FMC_VERR_MINREV_Msk /*!< Minor Revision number */
#define FMC_VERR_MAJREV_Pos (4U)
#define FMC_VERR_MAJREV_Msk (0xFU << FMC_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define FMC_VERR_MAJREV FMC_VERR_MAJREV_Msk /*!< Major Revision number */
/********************** Bit definition for FMC_IPIDR register ****************/
#define FMC_IPIDR_IPID_Pos (0U)
#define FMC_IPIDR_IPID_Msk (0xFFFFFFFFU << FMC_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
#define FMC_IPIDR_IPID FMC_IPIDR_IPID_Msk /*!< IP Identification */
/********************** Bit definition for FMC_SIDR register *****************/
#define FMC_SIDR_SID_Pos (0U)
#define FMC_SIDR_SID_Msk (0xFFFFFFFFU << FMC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define FMC_SIDR_SID FMC_SIDR_SID_Msk /*!< IP size identification */
/******************************************************************************/
/* */
/* General Purpose I/O */
/* */
/******************************************************************************/
/****************** Bits definition for GPIO_MODER register *****************/
#define GPIO_MODER_MODER0_Pos (0U)
#define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
#define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
#define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
#define GPIO_MODER_MODER1_Pos (2U)
#define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
#define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
#define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
#define GPIO_MODER_MODER2_Pos (4U)
#define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
#define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
#define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
#define GPIO_MODER_MODER3_Pos (6U)
#define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
#define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
#define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
#define GPIO_MODER_MODER4_Pos (8U)
#define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
#define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
#define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
#define GPIO_MODER_MODER5_Pos (10U)
#define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
#define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
#define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
#define GPIO_MODER_MODER6_Pos (12U)
#define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
#define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
#define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
#define GPIO_MODER_MODER7_Pos (14U)
#define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
#define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
#define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
#define GPIO_MODER_MODER8_Pos (16U)
#define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
#define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
#define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
#define GPIO_MODER_MODER9_Pos (18U)
#define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
#define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
#define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
#define GPIO_MODER_MODER10_Pos (20U)
#define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
#define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
#define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
#define GPIO_MODER_MODER11_Pos (22U)
#define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
#define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
#define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
#define GPIO_MODER_MODER12_Pos (24U)
#define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
#define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
#define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
#define GPIO_MODER_MODER13_Pos (26U)
#define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
#define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
#define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
#define GPIO_MODER_MODER14_Pos (28U)
#define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
#define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
#define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
#define GPIO_MODER_MODER15_Pos (30U)
#define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
#define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
#define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_OTYPER register ****************/
#define GPIO_OTYPER_OT0_Pos (0U)
#define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
#define GPIO_OTYPER_OT1_Pos (1U)
#define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
#define GPIO_OTYPER_OT2_Pos (2U)
#define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
#define GPIO_OTYPER_OT3_Pos (3U)
#define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
#define GPIO_OTYPER_OT4_Pos (4U)
#define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
#define GPIO_OTYPER_OT5_Pos (5U)
#define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
#define GPIO_OTYPER_OT6_Pos (6U)
#define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
#define GPIO_OTYPER_OT7_Pos (7U)
#define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
#define GPIO_OTYPER_OT8_Pos (8U)
#define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
#define GPIO_OTYPER_OT9_Pos (9U)
#define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
#define GPIO_OTYPER_OT10_Pos (10U)
#define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
#define GPIO_OTYPER_OT11_Pos (11U)
#define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
#define GPIO_OTYPER_OT12_Pos (12U)
#define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
#define GPIO_OTYPER_OT13_Pos (13U)
#define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
#define GPIO_OTYPER_OT14_Pos (14U)
#define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
#define GPIO_OTYPER_OT15_Pos (15U)
#define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
/****************** Bits definition for GPIO_OSPEEDR register ***************/
#define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)
#define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk
#define GPIO_OSPEEDR_OSPEEDR0_0 (0x1U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDR_OSPEEDR0_1 (0x2U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)
#define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk
#define GPIO_OSPEEDR_OSPEEDR1_0 (0x1U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDR_OSPEEDR1_1 (0x2U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)
#define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk
#define GPIO_OSPEEDR_OSPEEDR2_0 (0x1U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDR_OSPEEDR2_1 (0x2U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)
#define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk
#define GPIO_OSPEEDR_OSPEEDR3_0 (0x1U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDR_OSPEEDR3_1 (0x2U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)
#define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk
#define GPIO_OSPEEDR_OSPEEDR4_0 (0x1U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDR_OSPEEDR4_1 (0x2U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)
#define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk
#define GPIO_OSPEEDR_OSPEEDR5_0 (0x1U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDR_OSPEEDR5_1 (0x2U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)
#define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk
#define GPIO_OSPEEDR_OSPEEDR6_0 (0x1U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDR_OSPEEDR6_1 (0x2U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)
#define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk
#define GPIO_OSPEEDR_OSPEEDR7_0 (0x1U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDR_OSPEEDR7_1 (0x2U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)
#define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk
#define GPIO_OSPEEDR_OSPEEDR8_0 (0x1U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDR_OSPEEDR8_1 (0x2U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)
#define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk
#define GPIO_OSPEEDR_OSPEEDR9_0 (0x1U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDR_OSPEEDR9_1 (0x2U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)
#define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk
#define GPIO_OSPEEDR_OSPEEDR10_0 (0x1U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDR_OSPEEDR10_1 (0x2U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)
#define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk
#define GPIO_OSPEEDR_OSPEEDR11_0 (0x1U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDR_OSPEEDR11_1 (0x2U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)
#define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk
#define GPIO_OSPEEDR_OSPEEDR12_0 (0x1U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDR_OSPEEDR12_1 (0x2U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)
#define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk
#define GPIO_OSPEEDR_OSPEEDR13_0 (0x1U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDR_OSPEEDR13_1 (0x2U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)
#define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk
#define GPIO_OSPEEDR_OSPEEDR14_0 (0x1U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDR_OSPEEDR14_1 (0x2U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)
#define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk
#define GPIO_OSPEEDR_OSPEEDR15_0 (0x1U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDR_OSPEEDR15_1 (0x2U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_PUPDR register *****************/
#define GPIO_PUPDR_PUPDR0_Pos (0U)
#define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */
#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
#define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */
#define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */
#define GPIO_PUPDR_PUPDR1_Pos (2U)
#define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */
#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
#define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */
#define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */
#define GPIO_PUPDR_PUPDR2_Pos (4U)
#define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */
#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
#define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */
#define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */
#define GPIO_PUPDR_PUPDR3_Pos (6U)
#define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */
#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
#define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */
#define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */
#define GPIO_PUPDR_PUPDR4_Pos (8U)
#define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */
#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
#define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */
#define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */
#define GPIO_PUPDR_PUPDR5_Pos (10U)
#define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */
#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
#define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */
#define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */
#define GPIO_PUPDR_PUPDR6_Pos (12U)
#define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */
#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
#define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */
#define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */
#define GPIO_PUPDR_PUPDR7_Pos (14U)
#define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */
#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
#define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */
#define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */
#define GPIO_PUPDR_PUPDR8_Pos (16U)
#define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */
#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
#define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */
#define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */
#define GPIO_PUPDR_PUPDR9_Pos (18U)
#define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */
#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
#define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */
#define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */
#define GPIO_PUPDR_PUPDR10_Pos (20U)
#define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */
#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
#define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */
#define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */
#define GPIO_PUPDR_PUPDR11_Pos (22U)
#define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */
#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
#define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */
#define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */
#define GPIO_PUPDR_PUPDR12_Pos (24U)
#define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */
#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
#define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */
#define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */
#define GPIO_PUPDR_PUPDR13_Pos (26U)
#define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */
#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
#define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */
#define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */
#define GPIO_PUPDR_PUPDR14_Pos (28U)
#define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */
#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
#define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */
#define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */
#define GPIO_PUPDR_PUPDR15_Pos (30U)
#define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */
#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
#define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */
#define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_IDR register *******************/
#define GPIO_IDR_IDR0_Pos (0U)
#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */
#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk
#define GPIO_IDR_IDR1_Pos (1U)
#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */
#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk
#define GPIO_IDR_IDR2_Pos (2U)
#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */
#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk
#define GPIO_IDR_IDR3_Pos (3U)
#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */
#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk
#define GPIO_IDR_IDR4_Pos (4U)
#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */
#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk
#define GPIO_IDR_IDR5_Pos (5U)
#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */
#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk
#define GPIO_IDR_IDR6_Pos (6U)
#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */
#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk
#define GPIO_IDR_IDR7_Pos (7U)
#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */
#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk
#define GPIO_IDR_IDR8_Pos (8U)
#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */
#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk
#define GPIO_IDR_IDR9_Pos (9U)
#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */
#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk
#define GPIO_IDR_IDR10_Pos (10U)
#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */
#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk
#define GPIO_IDR_IDR11_Pos (11U)
#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */
#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk
#define GPIO_IDR_IDR12_Pos (12U)
#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */
#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk
#define GPIO_IDR_IDR13_Pos (13U)
#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */
#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk
#define GPIO_IDR_IDR14_Pos (14U)
#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */
#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk
#define GPIO_IDR_IDR15_Pos (15U)
#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */
#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk
/****************** Bits definition for GPIO_ODR register *******************/
#define GPIO_ODR_ODR0_Pos (0U)
#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */
#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk
#define GPIO_ODR_ODR1_Pos (1U)
#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */
#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk
#define GPIO_ODR_ODR2_Pos (2U)
#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */
#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk
#define GPIO_ODR_ODR3_Pos (3U)
#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */
#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk
#define GPIO_ODR_ODR4_Pos (4U)
#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */
#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk
#define GPIO_ODR_ODR5_Pos (5U)
#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */
#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk
#define GPIO_ODR_ODR6_Pos (6U)
#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */
#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk
#define GPIO_ODR_ODR7_Pos (7U)
#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */
#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk
#define GPIO_ODR_ODR8_Pos (8U)
#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */
#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk
#define GPIO_ODR_ODR9_Pos (9U)
#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */
#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk
#define GPIO_ODR_ODR10_Pos (10U)
#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */
#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk
#define GPIO_ODR_ODR11_Pos (11U)
#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */
#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk
#define GPIO_ODR_ODR12_Pos (12U)
#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */
#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk
#define GPIO_ODR_ODR13_Pos (13U)
#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */
#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk
#define GPIO_ODR_ODR14_Pos (14U)
#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */
#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk
#define GPIO_ODR_ODR15_Pos (15U)
#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */
#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk
/****************** Bits definition for GPIO_BSRR register ******************/
#define GPIO_BSRR_BS0_Pos (0U)
#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
#define GPIO_BSRR_BS1_Pos (1U)
#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
#define GPIO_BSRR_BS2_Pos (2U)
#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
#define GPIO_BSRR_BS3_Pos (3U)
#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
#define GPIO_BSRR_BS4_Pos (4U)
#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
#define GPIO_BSRR_BS5_Pos (5U)
#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
#define GPIO_BSRR_BS6_Pos (6U)
#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
#define GPIO_BSRR_BS7_Pos (7U)
#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
#define GPIO_BSRR_BS8_Pos (8U)
#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
#define GPIO_BSRR_BS9_Pos (9U)
#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
#define GPIO_BSRR_BS10_Pos (10U)
#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
#define GPIO_BSRR_BS11_Pos (11U)
#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
#define GPIO_BSRR_BS12_Pos (12U)
#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
#define GPIO_BSRR_BS13_Pos (13U)
#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
#define GPIO_BSRR_BS14_Pos (14U)
#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
#define GPIO_BSRR_BS15_Pos (15U)
#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
#define GPIO_BSRR_BR0_Pos (16U)
#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
#define GPIO_BSRR_BR1_Pos (17U)
#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
#define GPIO_BSRR_BR2_Pos (18U)
#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
#define GPIO_BSRR_BR3_Pos (19U)
#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
#define GPIO_BSRR_BR4_Pos (20U)
#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
#define GPIO_BSRR_BR5_Pos (21U)
#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
#define GPIO_BSRR_BR6_Pos (22U)
#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
#define GPIO_BSRR_BR7_Pos (23U)
#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
#define GPIO_BSRR_BR8_Pos (24U)
#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
#define GPIO_BSRR_BR9_Pos (25U)
#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
#define GPIO_BSRR_BR10_Pos (26U)
#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
#define GPIO_BSRR_BR11_Pos (27U)
#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
#define GPIO_BSRR_BR12_Pos (28U)
#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
#define GPIO_BSRR_BR13_Pos (29U)
#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
#define GPIO_BSRR_BR14_Pos (30U)
#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
#define GPIO_BSRR_BR15_Pos (31U)
#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0_Pos (0U)
#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
#define GPIO_LCKR_LCK1_Pos (1U)
#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
#define GPIO_LCKR_LCK2_Pos (2U)
#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
#define GPIO_LCKR_LCK3_Pos (3U)
#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
#define GPIO_LCKR_LCK4_Pos (4U)
#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
#define GPIO_LCKR_LCK5_Pos (5U)
#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
#define GPIO_LCKR_LCK6_Pos (6U)
#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
#define GPIO_LCKR_LCK7_Pos (7U)
#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
#define GPIO_LCKR_LCK8_Pos (8U)
#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
#define GPIO_LCKR_LCK9_Pos (9U)
#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
#define GPIO_LCKR_LCK10_Pos (10U)
#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
#define GPIO_LCKR_LCK11_Pos (11U)
#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
#define GPIO_LCKR_LCK12_Pos (12U)
#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
#define GPIO_LCKR_LCK13_Pos (13U)
#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
#define GPIO_LCKR_LCK14_Pos (14U)
#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
#define GPIO_LCKR_LCK15_Pos (15U)
#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
#define GPIO_LCKR_LCKK_Pos (16U)
#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
/****************** Bit definition for GPIO_AFRL register *********************/
#define GPIO_AFRL_AFR0_Pos (0U)
#define GPIO_AFRL_AFR0_Msk (0xFU << GPIO_AFRL_AFR0_Pos) /*!< 0x0000000F */
#define GPIO_AFRL_AFR0 GPIO_AFRL_AFR0_Msk
#define GPIO_AFRL_AFR0_0 (0x1U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000001 */
#define GPIO_AFRL_AFR0_1 (0x2U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000002 */
#define GPIO_AFRL_AFR0_2 (0x4U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000004 */
#define GPIO_AFRL_AFR0_3 (0x8U << GPIO_AFRL_AFR0_Pos) /*!< 0x00000008 */
#define GPIO_AFRL_AFR1_Pos (4U)
#define GPIO_AFRL_AFR1_Msk (0xFU << GPIO_AFRL_AFR1_Pos) /*!< 0x000000F0 */
#define GPIO_AFRL_AFR1 GPIO_AFRL_AFR1_Msk
#define GPIO_AFRL_AFR1_0 (0x1U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000010 */
#define GPIO_AFRL_AFR1_1 (0x2U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000020 */
#define GPIO_AFRL_AFR1_2 (0x4U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000040 */
#define GPIO_AFRL_AFR1_3 (0x8U << GPIO_AFRL_AFR1_Pos) /*!< 0x00000080 */
#define GPIO_AFRL_AFR2_Pos (8U)
#define GPIO_AFRL_AFR2_Msk (0xFU << GPIO_AFRL_AFR2_Pos) /*!< 0x00000F00 */
#define GPIO_AFRL_AFR2 GPIO_AFRL_AFR2_Msk
#define GPIO_AFRL_AFR2_0 (0x1U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000100 */
#define GPIO_AFRL_AFR2_1 (0x2U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000200 */
#define GPIO_AFRL_AFR2_2 (0x4U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000400 */
#define GPIO_AFRL_AFR2_3 (0x8U << GPIO_AFRL_AFR2_Pos) /*!< 0x00000800 */
#define GPIO_AFRL_AFR3_Pos (12U)
#define GPIO_AFRL_AFR3_Msk (0xFU << GPIO_AFRL_AFR3_Pos) /*!< 0x0000F000 */
#define GPIO_AFRL_AFR3 GPIO_AFRL_AFR3_Msk
#define GPIO_AFRL_AFR3_0 (0x1U << GPIO_AFRL_AFR3_Pos) /*!< 0x00001000 */
#define GPIO_AFRL_AFR3_1 (0x2U << GPIO_AFRL_AFR3_Pos) /*!< 0x00002000 */
#define GPIO_AFRL_AFR3_2 (0x4U << GPIO_AFRL_AFR3_Pos) /*!< 0x00004000 */
#define GPIO_AFRL_AFR3_3 (0x8U << GPIO_AFRL_AFR3_Pos) /*!< 0x00008000 */
#define GPIO_AFRL_AFR4_Pos (16U)
#define GPIO_AFRL_AFR4_Msk (0xFU << GPIO_AFRL_AFR4_Pos) /*!< 0x000F0000 */
#define GPIO_AFRL_AFR4 GPIO_AFRL_AFR4_Msk
#define GPIO_AFRL_AFR4_0 (0x1U << GPIO_AFRL_AFR4_Pos) /*!< 0x00010000 */
#define GPIO_AFRL_AFR4_1 (0x2U << GPIO_AFRL_AFR4_Pos) /*!< 0x00020000 */
#define GPIO_AFRL_AFR4_2 (0x4U << GPIO_AFRL_AFR4_Pos) /*!< 0x00040000 */
#define GPIO_AFRL_AFR4_3 (0x8U << GPIO_AFRL_AFR4_Pos) /*!< 0x00080000 */
#define GPIO_AFRL_AFR5_Pos (20U)
#define GPIO_AFRL_AFR5_Msk (0xFU << GPIO_AFRL_AFR5_Pos) /*!< 0x00F00000 */
#define GPIO_AFRL_AFR5 GPIO_AFRL_AFR5_Msk
#define GPIO_AFRL_AFR5_0 (0x1U << GPIO_AFRL_AFR5_Pos) /*!< 0x00100000 */
#define GPIO_AFRL_AFR5_1 (0x2U << GPIO_AFRL_AFR5_Pos) /*!< 0x00200000 */
#define GPIO_AFRL_AFR5_2 (0x4U << GPIO_AFRL_AFR5_Pos) /*!< 0x00400000 */
#define GPIO_AFRL_AFR5_3 (0x8U << GPIO_AFRL_AFR5_Pos) /*!< 0x00800000 */
#define GPIO_AFRL_AFR6_Pos (24U)
#define GPIO_AFRL_AFR6_Msk (0xFU << GPIO_AFRL_AFR6_Pos) /*!< 0x0F000000 */
#define GPIO_AFRL_AFR6 GPIO_AFRL_AFR6_Msk
#define GPIO_AFRL_AFR6_0 (0x1U << GPIO_AFRL_AFR6_Pos) /*!< 0x01000000 */
#define GPIO_AFRL_AFR6_1 (0x2U << GPIO_AFRL_AFR6_Pos) /*!< 0x02000000 */
#define GPIO_AFRL_AFR6_2 (0x4U << GPIO_AFRL_AFR6_Pos) /*!< 0x04000000 */
#define GPIO_AFRL_AFR6_3 (0x8U << GPIO_AFRL_AFR6_Pos) /*!< 0x08000000 */
#define GPIO_AFRL_AFR7_Pos (28U)
#define GPIO_AFRL_AFR7_Msk (0xFU << GPIO_AFRL_AFR7_Pos) /*!< 0xF0000000 */
#define GPIO_AFRL_AFR7 GPIO_AFRL_AFR7_Msk
#define GPIO_AFRL_AFR7_0 (0x1U << GPIO_AFRL_AFR7_Pos) /*!< 0x10000000 */
#define GPIO_AFRL_AFR7_1 (0x2U << GPIO_AFRL_AFR7_Pos) /*!< 0x20000000 */
#define GPIO_AFRL_AFR7_2 (0x4U << GPIO_AFRL_AFR7_Pos) /*!< 0x40000000 */
#define GPIO_AFRL_AFR7_3 (0x8U << GPIO_AFRL_AFR7_Pos) /*!< 0x80000000 */
/****************** Bit definition for GPIO_AFRH register *********************/
#define GPIO_AFRH_AFR8_Pos (0U)
#define GPIO_AFRH_AFR8_Msk (0xFU << GPIO_AFRH_AFR8_Pos) /*!< 0x0000000F */
#define GPIO_AFRH_AFR8 GPIO_AFRH_AFR8_Msk
#define GPIO_AFRH_AFR8_0 (0x1U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000001 */
#define GPIO_AFRH_AFR8_1 (0x2U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000002 */
#define GPIO_AFRH_AFR8_2 (0x4U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000004 */
#define GPIO_AFRH_AFR8_3 (0x8U << GPIO_AFRH_AFR8_Pos) /*!< 0x00000008 */
#define GPIO_AFRH_AFR9_Pos (4U)
#define GPIO_AFRH_AFR9_Msk (0xFU << GPIO_AFRH_AFR9_Pos) /*!< 0x000000F0 */
#define GPIO_AFRH_AFR9 GPIO_AFRH_AFR9_Msk
#define GPIO_AFRH_AFR9_0 (0x1U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000010 */
#define GPIO_AFRH_AFR9_1 (0x2U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000020 */
#define GPIO_AFRH_AFR9_2 (0x4U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000040 */
#define GPIO_AFRH_AFR9_3 (0x8U << GPIO_AFRH_AFR9_Pos) /*!< 0x00000080 */
#define GPIO_AFRH_AFR10_Pos (8U)
#define GPIO_AFRH_AFR10_Msk (0xFU << GPIO_AFRH_AFR10_Pos) /*!< 0x00000F00 */
#define GPIO_AFRH_AFR10 GPIO_AFRH_AFR10_Msk
#define GPIO_AFRH_AFR10_0 (0x1U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000100 */
#define GPIO_AFRH_AFR10_1 (0x2U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000200 */
#define GPIO_AFRH_AFR10_2 (0x4U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000400 */
#define GPIO_AFRH_AFR10_3 (0x8U << GPIO_AFRH_AFR10_Pos) /*!< 0x00000800 */
#define GPIO_AFRH_AFR11_Pos (12U)
#define GPIO_AFRH_AFR11_Msk (0xFU << GPIO_AFRH_AFR11_Pos) /*!< 0x0000F000 */
#define GPIO_AFRH_AFR11 GPIO_AFRH_AFR11_Msk
#define GPIO_AFRH_AFR11_0 (0x1U << GPIO_AFRH_AFR11_Pos) /*!< 0x00001000 */
#define GPIO_AFRH_AFR11_1 (0x2U << GPIO_AFRH_AFR11_Pos) /*!< 0x00002000 */
#define GPIO_AFRH_AFR11_2 (0x4U << GPIO_AFRH_AFR11_Pos) /*!< 0x00004000 */
#define GPIO_AFRH_AFR11_3 (0x8U << GPIO_AFRH_AFR11_Pos) /*!< 0x00008000 */
#define GPIO_AFRH_AFR12_Pos (16U)
#define GPIO_AFRH_AFR12_Msk (0xFU << GPIO_AFRH_AFR12_Pos) /*!< 0x000F0000 */
#define GPIO_AFRH_AFR12 GPIO_AFRH_AFR12_Msk
#define GPIO_AFRH_AFR12_0 (0x1U << GPIO_AFRH_AFR12_Pos) /*!< 0x00010000 */
#define GPIO_AFRH_AFR12_1 (0x2U << GPIO_AFRH_AFR12_Pos) /*!< 0x00020000 */
#define GPIO_AFRH_AFR12_2 (0x4U << GPIO_AFRH_AFR12_Pos) /*!< 0x00040000 */
#define GPIO_AFRH_AFR12_3 (0x8U << GPIO_AFRH_AFR12_Pos) /*!< 0x00080000 */
#define GPIO_AFRH_AFR13_Pos (20U)
#define GPIO_AFRH_AFR13_Msk (0xFU << GPIO_AFRH_AFR13_Pos) /*!< 0x00F00000 */
#define GPIO_AFRH_AFR13 GPIO_AFRH_AFR13_Msk
#define GPIO_AFRH_AFR13_0 (0x1U << GPIO_AFRH_AFR13_Pos) /*!< 0x00100000 */
#define GPIO_AFRH_AFR13_1 (0x2U << GPIO_AFRH_AFR13_Pos) /*!< 0x00200000 */
#define GPIO_AFRH_AFR13_2 (0x4U << GPIO_AFRH_AFR13_Pos) /*!< 0x00400000 */
#define GPIO_AFRH_AFR13_3 (0x8U << GPIO_AFRH_AFR13_Pos) /*!< 0x00800000 */
#define GPIO_AFRH_AFR14_Pos (24U)
#define GPIO_AFRH_AFR14_Msk (0xFU << GPIO_AFRH_AFR14_Pos) /*!< 0x0F000000 */
#define GPIO_AFRH_AFR14 GPIO_AFRH_AFR14_Msk
#define GPIO_AFRH_AFR14_0 (0x1U << GPIO_AFRH_AFR14_Pos) /*!< 0x01000000 */
#define GPIO_AFRH_AFR14_1 (0x2U << GPIO_AFRH_AFR14_Pos) /*!< 0x02000000 */
#define GPIO_AFRH_AFR14_2 (0x4U << GPIO_AFRH_AFR14_Pos) /*!< 0x04000000 */
#define GPIO_AFRH_AFR14_3 (0x8U << GPIO_AFRH_AFR14_Pos) /*!< 0x08000000 */
#define GPIO_AFRH_AFR15_Pos (28U)
#define GPIO_AFRH_AFR15_Msk (0xFU << GPIO_AFRH_AFR15_Pos) /*!< 0xF0000000 */
#define GPIO_AFRH_AFR15 GPIO_AFRH_AFR15_Msk
#define GPIO_AFRH_AFR15_0 (0x1U << GPIO_AFRH_AFR15_Pos) /*!< 0x10000000 */
#define GPIO_AFRH_AFR15_1 (0x2U << GPIO_AFRH_AFR15_Pos) /*!< 0x20000000 */
#define GPIO_AFRH_AFR15_2 (0x4U << GPIO_AFRH_AFR15_Pos) /*!< 0x40000000 */
#define GPIO_AFRH_AFR15_3 (0x8U << GPIO_AFRH_AFR15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_BRR register ******************/
#define GPIO_BRR_BR0_Pos (0U)
#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
#define GPIO_BRR_BR1_Pos (1U)
#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
#define GPIO_BRR_BR2_Pos (2U)
#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
#define GPIO_BRR_BR3_Pos (3U)
#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
#define GPIO_BRR_BR4_Pos (4U)
#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
#define GPIO_BRR_BR5_Pos (5U)
#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
#define GPIO_BRR_BR6_Pos (6U)
#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
#define GPIO_BRR_BR7_Pos (7U)
#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
#define GPIO_BRR_BR8_Pos (8U)
#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
#define GPIO_BRR_BR9_Pos (9U)
#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
#define GPIO_BRR_BR10_Pos (10U)
#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
#define GPIO_BRR_BR11_Pos (11U)
#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
#define GPIO_BRR_BR12_Pos (12U)
#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
#define GPIO_BRR_BR13_Pos (13U)
#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
#define GPIO_BRR_BR14_Pos (14U)
#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
#define GPIO_BRR_BR15_Pos (15U)
#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
/****************** Bits definition for GPIO_SECCFGR register ******************/
#define GPIO_SECCFGR_SEC0_Pos (0U)
#define GPIO_SECCFGR_SEC0_Msk (0x1U << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */
#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk
#define GPIO_SECCFGR_SEC1_Pos (1U)
#define GPIO_SECCFGR_SEC1_Msk (0x1U << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */
#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk
#define GPIO_SECCFGR_SEC2_Pos (2U)
#define GPIO_SECCFGR_SEC2_Msk (0x1U << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */
#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk
#define GPIO_SECCFGR_SEC3_Pos (3U)
#define GPIO_SECCFGR_SEC3_Msk (0x1U << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */
#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk
#define GPIO_SECCFGR_SEC4_Pos (4U)
#define GPIO_SECCFGR_SEC4_Msk (0x1U << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */
#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk
#define GPIO_SECCFGR_SEC5_Pos (5U)
#define GPIO_SECCFGR_SEC5_Msk (0x1U << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */
#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk
#define GPIO_SECCFGR_SEC6_Pos (6U)
#define GPIO_SECCFGR_SEC6_Msk (0x1U << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */
#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk
#define GPIO_SECCFGR_SEC7_Pos (7U)
#define GPIO_SECCFGR_SEC7_Msk (0x1U << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */
#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk
/*************** Bit definition for GPIO_HWCFGR10 register ****************/
#define GPIO_HWCFGR10_AHB_IOP_Pos (0U)
#define GPIO_HWCFGR10_AHB_IOP_Msk (0xFU << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x0000000F */
#define GPIO_HWCFGR10_AHB_IOP GPIO_HWCFGR10_AHB_IOP_Msk /*!< Bus interface configuration */
#define GPIO_HWCFGR10_AHB_IOP_0 (0x1U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000001 */
#define GPIO_HWCFGR10_AHB_IOP_1 (0x2U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000002 */
#define GPIO_HWCFGR10_AHB_IOP_2 (0x4U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000004 */
#define GPIO_HWCFGR10_AHB_IOP_3 (0x8U << GPIO_HWCFGR10_AHB_IOP_Pos) /*!< 0x00000008 */
#define GPIO_HWCFGR10_AF_SIZE_Pos (4U)
#define GPIO_HWCFGR10_AF_SIZE_Msk (0xFU << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x000000F0 */
#define GPIO_HWCFGR10_AF_SIZE GPIO_HWCFGR10_AF_SIZE_Msk /*!< Number of AF available for each I/O */
#define GPIO_HWCFGR10_AF_SIZE_0 (0x1U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000010 */
#define GPIO_HWCFGR10_AF_SIZE_1 (0x2U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000020 */
#define GPIO_HWCFGR10_AF_SIZE_2 (0x4U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000040 */
#define GPIO_HWCFGR10_AF_SIZE_3 (0x8U << GPIO_HWCFGR10_AF_SIZE_Pos) /*!< 0x00000080 */
#define GPIO_HWCFGR10_SPEED_CFG_Pos (8U)
#define GPIO_HWCFGR10_SPEED_CFG_Msk (0xFU << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000F00 */
#define GPIO_HWCFGR10_SPEED_CFG GPIO_HWCFGR10_SPEED_CFG_Msk /*!< Number of speed lines for each I/O */
#define GPIO_HWCFGR10_SPEED_CFG_0 (0x1U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000100 */
#define GPIO_HWCFGR10_SPEED_CFG_1 (0x2U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000200 */
#define GPIO_HWCFGR10_SPEED_CFG_2 (0x4U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000400 */
#define GPIO_HWCFGR10_SPEED_CFG_3 (0x8U << GPIO_HWCFGR10_SPEED_CFG_Pos) /*!< 0x00000800 */
#define GPIO_HWCFGR10_LOCK_CFG_Pos (12U)
#define GPIO_HWCFGR10_LOCK_CFG_Msk (0xFU << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x0000F000 */
#define GPIO_HWCFGR10_LOCK_CFG GPIO_HWCFGR10_LOCK_CFG_Msk /*!< Lock mechanism activation */
#define GPIO_HWCFGR10_LOCK_CFG_0 (0x1U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00001000 */
#define GPIO_HWCFGR10_LOCK_CFG_1 (0x2U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00002000 */
#define GPIO_HWCFGR10_LOCK_CFG_2 (0x4U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00004000 */
#define GPIO_HWCFGR10_LOCK_CFG_3 (0x8U << GPIO_HWCFGR10_LOCK_CFG_Pos) /*!< 0x00008000 */
#define GPIO_HWCFGR10_SEC_CFG_Pos (16U)
#define GPIO_HWCFGR10_SEC_CFG_Msk (0xFU << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x000F0000 */
#define GPIO_HWCFGR10_SEC_CFG GPIO_HWCFGR10_SEC_CFG_Msk /*!< Security mechanism activation */
#define GPIO_HWCFGR10_SEC_CFG_0 (0x1U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00010000 */
#define GPIO_HWCFGR10_SEC_CFG_1 (0x2U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00020000 */
#define GPIO_HWCFGR10_SEC_CFG_2 (0x4U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00040000 */
#define GPIO_HWCFGR10_SEC_CFG_3 (0x8U << GPIO_HWCFGR10_SEC_CFG_Pos) /*!< 0x00080000 */
#define GPIO_HWCFGR10_OR_CFG_Pos (20U)
#define GPIO_HWCFGR10_OR_CFG_Msk (0xFU << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00F00000 */
#define GPIO_HWCFGR10_OR_CFG GPIO_HWCFGR10_OR_CFG_Msk /*!< Option register configuration */
#define GPIO_HWCFGR10_OR_CFG_0 (0x1U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00100000 */
#define GPIO_HWCFGR10_OR_CFG_1 (0x2U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00200000 */
#define GPIO_HWCFGR10_OR_CFG_2 (0x4U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00400000 */
#define GPIO_HWCFGR10_OR_CFG_3 (0x8U << GPIO_HWCFGR10_OR_CFG_Pos) /*!< 0x00800000 */
/**************** Bit definition for GPIO_HWCFGR9 register ****************/
#define GPIO_HWCFGR9_EN_IO_Pos (0U)
#define GPIO_HWCFGR9_EN_IO_Msk (0xFFFFU << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x0000FFFF */
#define GPIO_HWCFGR9_EN_IO GPIO_HWCFGR9_EN_IO_Msk /*!< Presence granularity, each bit indicate the presence of the IO */
#define GPIO_HWCFGR9_EN_IO_0 (0x1U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000001 */
#define GPIO_HWCFGR9_EN_IO_1 (0x2U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000002 */
#define GPIO_HWCFGR9_EN_IO_2 (0x4U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000004 */
#define GPIO_HWCFGR9_EN_IO_3 (0x8U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000008 */
#define GPIO_HWCFGR9_EN_IO_4 (0x10U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000010 */
#define GPIO_HWCFGR9_EN_IO_5 (0x20U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000020 */
#define GPIO_HWCFGR9_EN_IO_6 (0x40U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000040 */
#define GPIO_HWCFGR9_EN_IO_7 (0x80U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000080 */
#define GPIO_HWCFGR9_EN_IO_8 (0x100U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000100 */
#define GPIO_HWCFGR9_EN_IO_9 (0x200U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000200 */
#define GPIO_HWCFGR9_EN_IO_10 (0x400U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000400 */
#define GPIO_HWCFGR9_EN_IO_11 (0x800U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00000800 */
#define GPIO_HWCFGR9_EN_IO_12 (0x1000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00001000 */
#define GPIO_HWCFGR9_EN_IO_13 (0x2000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00002000 */
#define GPIO_HWCFGR9_EN_IO_14 (0x4000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00004000 */
#define GPIO_HWCFGR9_EN_IO_15 (0x8000U << GPIO_HWCFGR9_EN_IO_Pos) /*!< 0x00008000 */
/**************** Bit definition for GPIO_HWCFGR8 register ****************/
#define GPIO_HWCFGR8_AF_PRIO8_Pos (0U)
#define GPIO_HWCFGR8_AF_PRIO8_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x0000000F */
#define GPIO_HWCFGR8_AF_PRIO8 GPIO_HWCFGR8_AF_PRIO8_Msk /*!< Indicate the priority AF for I/O8 (0 to F) */
#define GPIO_HWCFGR8_AF_PRIO8_0 (0x1U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000001 */
#define GPIO_HWCFGR8_AF_PRIO8_1 (0x2U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000002 */
#define GPIO_HWCFGR8_AF_PRIO8_2 (0x4U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000004 */
#define GPIO_HWCFGR8_AF_PRIO8_3 (0x8U << GPIO_HWCFGR8_AF_PRIO8_Pos) /*!< 0x00000008 */
#define GPIO_HWCFGR8_AF_PRIO9_Pos (4U)
#define GPIO_HWCFGR8_AF_PRIO9_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x000000F0 */
#define GPIO_HWCFGR8_AF_PRIO9 GPIO_HWCFGR8_AF_PRIO9_Msk /*!< Indicate the priority AF for I/O9 (0 to F) */
#define GPIO_HWCFGR8_AF_PRIO9_0 (0x1U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000010 */
#define GPIO_HWCFGR8_AF_PRIO9_1 (0x2U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000020 */
#define GPIO_HWCFGR8_AF_PRIO9_2 (0x4U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000040 */
#define GPIO_HWCFGR8_AF_PRIO9_3 (0x8U << GPIO_HWCFGR8_AF_PRIO9_Pos) /*!< 0x00000080 */
#define GPIO_HWCFGR8_AF_PRIO10_Pos (8U)
#define GPIO_HWCFGR8_AF_PRIO10_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000F00 */
#define GPIO_HWCFGR8_AF_PRIO10 GPIO_HWCFGR8_AF_PRIO10_Msk /*!< Indicate the priority AF for I/O10 (0 to F) */
#define GPIO_HWCFGR8_AF_PRIO10_0 (0x1U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000100 */
#define GPIO_HWCFGR8_AF_PRIO10_1 (0x2U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000200 */
#define GPIO_HWCFGR8_AF_PRIO10_2 (0x4U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000400 */
#define GPIO_HWCFGR8_AF_PRIO10_3 (0x8U << GPIO_HWCFGR8_AF_PRIO10_Pos) /*!< 0x00000800 */
#define GPIO_HWCFGR8_AF_PRIO11_Pos (12U)
#define GPIO_HWCFGR8_AF_PRIO11_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x0000F000 */
#define GPIO_HWCFGR8_AF_PRIO11 GPIO_HWCFGR8_AF_PRIO11_Msk /*!< Indicate the priority AF for I/O11 (0 to F) */
#define GPIO_HWCFGR8_AF_PRIO11_0 (0x1U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00001000 */
#define GPIO_HWCFGR8_AF_PRIO11_1 (0x2U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00002000 */
#define GPIO_HWCFGR8_AF_PRIO11_2 (0x4U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00004000 */
#define GPIO_HWCFGR8_AF_PRIO11_3 (0x8U << GPIO_HWCFGR8_AF_PRIO11_Pos) /*!< 0x00008000 */
#define GPIO_HWCFGR8_AF_PRIO12_Pos (16U)
#define GPIO_HWCFGR8_AF_PRIO12_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x000F0000 */
#define GPIO_HWCFGR8_AF_PRIO12 GPIO_HWCFGR8_AF_PRIO12_Msk /*!< Indicate the priority AF for I/O12 (0 to F) */
#define GPIO_HWCFGR8_AF_PRIO12_0 (0x1U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00010000 */
#define GPIO_HWCFGR8_AF_PRIO12_1 (0x2U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00020000 */
#define GPIO_HWCFGR8_AF_PRIO12_2 (0x4U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00040000 */
#define GPIO_HWCFGR8_AF_PRIO12_3 (0x8U << GPIO_HWCFGR8_AF_PRIO12_Pos) /*!< 0x00080000 */
#define GPIO_HWCFGR8_AF_PRIO13_Pos (20U)
#define GPIO_HWCFGR8_AF_PRIO13_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00F00000 */
#define GPIO_HWCFGR8_AF_PRIO13 GPIO_HWCFGR8_AF_PRIO13_Msk /*!< Indicate the priority AF for I/O13 (0 to F) */
#define GPIO_HWCFGR8_AF_PRIO13_0 (0x1U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00100000 */
#define GPIO_HWCFGR8_AF_PRIO13_1 (0x2U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00200000 */
#define GPIO_HWCFGR8_AF_PRIO13_2 (0x4U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00400000 */
#define GPIO_HWCFGR8_AF_PRIO13_3 (0x8U << GPIO_HWCFGR8_AF_PRIO13_Pos) /*!< 0x00800000 */
#define GPIO_HWCFGR8_AF_PRIO14_Pos (24U)
#define GPIO_HWCFGR8_AF_PRIO14_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x0F000000 */
#define GPIO_HWCFGR8_AF_PRIO14 GPIO_HWCFGR8_AF_PRIO14_Msk /*!< Indicate the priority AF for I/O14 (0 to F) */
#define GPIO_HWCFGR8_AF_PRIO14_0 (0x1U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x01000000 */
#define GPIO_HWCFGR8_AF_PRIO14_1 (0x2U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x02000000 */
#define GPIO_HWCFGR8_AF_PRIO14_2 (0x4U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x04000000 */
#define GPIO_HWCFGR8_AF_PRIO14_3 (0x8U << GPIO_HWCFGR8_AF_PRIO14_Pos) /*!< 0x08000000 */
#define GPIO_HWCFGR8_AF_PRIO15_Pos (28U)
#define GPIO_HWCFGR8_AF_PRIO15_Msk (0xFU << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0xF0000000 */
#define GPIO_HWCFGR8_AF_PRIO15 GPIO_HWCFGR8_AF_PRIO15_Msk /*!< Indicate the priority AF for I/O15 (0 to F) */
#define GPIO_HWCFGR8_AF_PRIO15_0 (0x1U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x10000000 */
#define GPIO_HWCFGR8_AF_PRIO15_1 (0x2U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x20000000 */
#define GPIO_HWCFGR8_AF_PRIO15_2 (0x4U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x40000000 */
#define GPIO_HWCFGR8_AF_PRIO15_3 (0x8U << GPIO_HWCFGR8_AF_PRIO15_Pos) /*!< 0x80000000 */
/**************** Bit definition for GPIO_HWCFGR7 register ****************/
#define GPIO_HWCFGR7_AF_PRIO0_Pos (0U)
#define GPIO_HWCFGR7_AF_PRIO0_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x0000000F */
#define GPIO_HWCFGR7_AF_PRIO0 GPIO_HWCFGR7_AF_PRIO0_Msk /*!< Indicate the priority AF for I/O0 (0 to F) */
#define GPIO_HWCFGR7_AF_PRIO0_0 (0x1U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000001 */
#define GPIO_HWCFGR7_AF_PRIO0_1 (0x2U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000002 */
#define GPIO_HWCFGR7_AF_PRIO0_2 (0x4U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000004 */
#define GPIO_HWCFGR7_AF_PRIO0_3 (0x8U << GPIO_HWCFGR7_AF_PRIO0_Pos) /*!< 0x00000008 */
#define GPIO_HWCFGR7_AF_PRIO1_Pos (4U)
#define GPIO_HWCFGR7_AF_PRIO1_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x000000F0 */
#define GPIO_HWCFGR7_AF_PRIO1 GPIO_HWCFGR7_AF_PRIO1_Msk /*!< Indicate the priority AF for I/O1 (0 to F) */
#define GPIO_HWCFGR7_AF_PRIO1_0 (0x1U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000010 */
#define GPIO_HWCFGR7_AF_PRIO1_1 (0x2U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000020 */
#define GPIO_HWCFGR7_AF_PRIO1_2 (0x4U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000040 */
#define GPIO_HWCFGR7_AF_PRIO1_3 (0x8U << GPIO_HWCFGR7_AF_PRIO1_Pos) /*!< 0x00000080 */
#define GPIO_HWCFGR7_AF_PRIO2_Pos (8U)
#define GPIO_HWCFGR7_AF_PRIO2_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000F00 */
#define GPIO_HWCFGR7_AF_PRIO2 GPIO_HWCFGR7_AF_PRIO2_Msk /*!< Indicate the priority AF for I/O2 (0 to F) */
#define GPIO_HWCFGR7_AF_PRIO2_0 (0x1U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000100 */
#define GPIO_HWCFGR7_AF_PRIO2_1 (0x2U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000200 */
#define GPIO_HWCFGR7_AF_PRIO2_2 (0x4U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000400 */
#define GPIO_HWCFGR7_AF_PRIO2_3 (0x8U << GPIO_HWCFGR7_AF_PRIO2_Pos) /*!< 0x00000800 */
#define GPIO_HWCFGR7_AF_PRIO3_Pos (12U)
#define GPIO_HWCFGR7_AF_PRIO3_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x0000F000 */
#define GPIO_HWCFGR7_AF_PRIO3 GPIO_HWCFGR7_AF_PRIO3_Msk /*!< Indicate the priority AF for I/O3 (0 to F) */
#define GPIO_HWCFGR7_AF_PRIO3_0 (0x1U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00001000 */
#define GPIO_HWCFGR7_AF_PRIO3_1 (0x2U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00002000 */
#define GPIO_HWCFGR7_AF_PRIO3_2 (0x4U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00004000 */
#define GPIO_HWCFGR7_AF_PRIO3_3 (0x8U << GPIO_HWCFGR7_AF_PRIO3_Pos) /*!< 0x00008000 */
#define GPIO_HWCFGR7_AF_PRIO4_Pos (16U)
#define GPIO_HWCFGR7_AF_PRIO4_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x000F0000 */
#define GPIO_HWCFGR7_AF_PRIO4 GPIO_HWCFGR7_AF_PRIO4_Msk /*!< Indicate the priority AF for I/O4 (0 to F) */
#define GPIO_HWCFGR7_AF_PRIO4_0 (0x1U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00010000 */
#define GPIO_HWCFGR7_AF_PRIO4_1 (0x2U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00020000 */
#define GPIO_HWCFGR7_AF_PRIO4_2 (0x4U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00040000 */
#define GPIO_HWCFGR7_AF_PRIO4_3 (0x8U << GPIO_HWCFGR7_AF_PRIO4_Pos) /*!< 0x00080000 */
#define GPIO_HWCFGR7_AF_PRIO5_Pos (20U)
#define GPIO_HWCFGR7_AF_PRIO5_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00F00000 */
#define GPIO_HWCFGR7_AF_PRIO5 GPIO_HWCFGR7_AF_PRIO5_Msk /*!< Indicate the priority AF for I/O5 (0 to F) */
#define GPIO_HWCFGR7_AF_PRIO5_0 (0x1U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00100000 */
#define GPIO_HWCFGR7_AF_PRIO5_1 (0x2U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00200000 */
#define GPIO_HWCFGR7_AF_PRIO5_2 (0x4U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00400000 */
#define GPIO_HWCFGR7_AF_PRIO5_3 (0x8U << GPIO_HWCFGR7_AF_PRIO5_Pos) /*!< 0x00800000 */
#define GPIO_HWCFGR7_AF_PRIO6_Pos (24U)
#define GPIO_HWCFGR7_AF_PRIO6_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x0F000000 */
#define GPIO_HWCFGR7_AF_PRIO6 GPIO_HWCFGR7_AF_PRIO6_Msk /*!< Indicate the priority AF for I/O6 (0 to F) */
#define GPIO_HWCFGR7_AF_PRIO6_0 (0x1U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x01000000 */
#define GPIO_HWCFGR7_AF_PRIO6_1 (0x2U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x02000000 */
#define GPIO_HWCFGR7_AF_PRIO6_2 (0x4U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x04000000 */
#define GPIO_HWCFGR7_AF_PRIO6_3 (0x8U << GPIO_HWCFGR7_AF_PRIO6_Pos) /*!< 0x08000000 */
#define GPIO_HWCFGR7_AF_PRIO7_Pos (28U)
#define GPIO_HWCFGR7_AF_PRIO7_Msk (0xFU << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0xF0000000 */
#define GPIO_HWCFGR7_AF_PRIO7 GPIO_HWCFGR7_AF_PRIO7_Msk /*!< Indicate the priority AF for I/O7 (0 to F) */
#define GPIO_HWCFGR7_AF_PRIO7_0 (0x1U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x10000000 */
#define GPIO_HWCFGR7_AF_PRIO7_1 (0x2U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x20000000 */
#define GPIO_HWCFGR7_AF_PRIO7_2 (0x4U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x40000000 */
#define GPIO_HWCFGR7_AF_PRIO7_3 (0x8U << GPIO_HWCFGR7_AF_PRIO7_Pos) /*!< 0x80000000 */
/**************** Bit definition for GPIO_HWCFGR6 register ****************/
#define GPIO_HWCFGR6_MODER_RES_Pos (0U)
#define GPIO_HWCFGR6_MODER_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0xFFFFFFFF */
#define GPIO_HWCFGR6_MODER_RES GPIO_HWCFGR6_MODER_RES_Msk /*!< MODER register reset value */
#define GPIO_HWCFGR6_MODER_RES_0 (0x1U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000001 */
#define GPIO_HWCFGR6_MODER_RES_1 (0x2U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000002 */
#define GPIO_HWCFGR6_MODER_RES_2 (0x4U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000004 */
#define GPIO_HWCFGR6_MODER_RES_3 (0x8U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000008 */
#define GPIO_HWCFGR6_MODER_RES_4 (0x10U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000010 */
#define GPIO_HWCFGR6_MODER_RES_5 (0x20U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000020 */
#define GPIO_HWCFGR6_MODER_RES_6 (0x40U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000040 */
#define GPIO_HWCFGR6_MODER_RES_7 (0x80U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000080 */
#define GPIO_HWCFGR6_MODER_RES_8 (0x100U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000100 */
#define GPIO_HWCFGR6_MODER_RES_9 (0x200U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000200 */
#define GPIO_HWCFGR6_MODER_RES_10 (0x400U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000400 */
#define GPIO_HWCFGR6_MODER_RES_11 (0x800U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00000800 */
#define GPIO_HWCFGR6_MODER_RES_12 (0x1000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00001000 */
#define GPIO_HWCFGR6_MODER_RES_13 (0x2000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00002000 */
#define GPIO_HWCFGR6_MODER_RES_14 (0x4000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00004000 */
#define GPIO_HWCFGR6_MODER_RES_15 (0x8000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00008000 */
#define GPIO_HWCFGR6_MODER_RES_16 (0x10000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00010000 */
#define GPIO_HWCFGR6_MODER_RES_17 (0x20000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00020000 */
#define GPIO_HWCFGR6_MODER_RES_18 (0x40000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00040000 */
#define GPIO_HWCFGR6_MODER_RES_19 (0x80000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00080000 */
#define GPIO_HWCFGR6_MODER_RES_20 (0x100000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00100000 */
#define GPIO_HWCFGR6_MODER_RES_21 (0x200000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00200000 */
#define GPIO_HWCFGR6_MODER_RES_22 (0x400000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00400000 */
#define GPIO_HWCFGR6_MODER_RES_23 (0x800000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x00800000 */
#define GPIO_HWCFGR6_MODER_RES_24 (0x1000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x01000000 */
#define GPIO_HWCFGR6_MODER_RES_25 (0x2000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x02000000 */
#define GPIO_HWCFGR6_MODER_RES_26 (0x4000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x04000000 */
#define GPIO_HWCFGR6_MODER_RES_27 (0x8000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x08000000 */
#define GPIO_HWCFGR6_MODER_RES_28 (0x10000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x10000000 */
#define GPIO_HWCFGR6_MODER_RES_29 (0x20000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x20000000 */
#define GPIO_HWCFGR6_MODER_RES_30 (0x40000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x40000000 */
#define GPIO_HWCFGR6_MODER_RES_31 (0x80000000U << GPIO_HWCFGR6_MODER_RES_Pos) /*!< 0x80000000 */
/**************** Bit definition for GPIO_HWCFGR5 register ****************/
#define GPIO_HWCFGR5_PUPDR_RES_Pos (0U)
#define GPIO_HWCFGR5_PUPDR_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0xFFFFFFFF */
#define GPIO_HWCFGR5_PUPDR_RES GPIO_HWCFGR5_PUPDR_RES_Msk /*!< Pull-up / pull-down register reset value */
#define GPIO_HWCFGR5_PUPDR_RES_0 (0x1U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000001 */
#define GPIO_HWCFGR5_PUPDR_RES_1 (0x2U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000002 */
#define GPIO_HWCFGR5_PUPDR_RES_2 (0x4U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000004 */
#define GPIO_HWCFGR5_PUPDR_RES_3 (0x8U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000008 */
#define GPIO_HWCFGR5_PUPDR_RES_4 (0x10U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000010 */
#define GPIO_HWCFGR5_PUPDR_RES_5 (0x20U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000020 */
#define GPIO_HWCFGR5_PUPDR_RES_6 (0x40U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000040 */
#define GPIO_HWCFGR5_PUPDR_RES_7 (0x80U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000080 */
#define GPIO_HWCFGR5_PUPDR_RES_8 (0x100U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000100 */
#define GPIO_HWCFGR5_PUPDR_RES_9 (0x200U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000200 */
#define GPIO_HWCFGR5_PUPDR_RES_10 (0x400U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000400 */
#define GPIO_HWCFGR5_PUPDR_RES_11 (0x800U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00000800 */
#define GPIO_HWCFGR5_PUPDR_RES_12 (0x1000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00001000 */
#define GPIO_HWCFGR5_PUPDR_RES_13 (0x2000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00002000 */
#define GPIO_HWCFGR5_PUPDR_RES_14 (0x4000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00004000 */
#define GPIO_HWCFGR5_PUPDR_RES_15 (0x8000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00008000 */
#define GPIO_HWCFGR5_PUPDR_RES_16 (0x10000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00010000 */
#define GPIO_HWCFGR5_PUPDR_RES_17 (0x20000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00020000 */
#define GPIO_HWCFGR5_PUPDR_RES_18 (0x40000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00040000 */
#define GPIO_HWCFGR5_PUPDR_RES_19 (0x80000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00080000 */
#define GPIO_HWCFGR5_PUPDR_RES_20 (0x100000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00100000 */
#define GPIO_HWCFGR5_PUPDR_RES_21 (0x200000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00200000 */
#define GPIO_HWCFGR5_PUPDR_RES_22 (0x400000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00400000 */
#define GPIO_HWCFGR5_PUPDR_RES_23 (0x800000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x00800000 */
#define GPIO_HWCFGR5_PUPDR_RES_24 (0x1000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x01000000 */
#define GPIO_HWCFGR5_PUPDR_RES_25 (0x2000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x02000000 */
#define GPIO_HWCFGR5_PUPDR_RES_26 (0x4000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x04000000 */
#define GPIO_HWCFGR5_PUPDR_RES_27 (0x8000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x08000000 */
#define GPIO_HWCFGR5_PUPDR_RES_28 (0x10000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x10000000 */
#define GPIO_HWCFGR5_PUPDR_RES_29 (0x20000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x20000000 */
#define GPIO_HWCFGR5_PUPDR_RES_30 (0x40000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x40000000 */
#define GPIO_HWCFGR5_PUPDR_RES_31 (0x80000000U << GPIO_HWCFGR5_PUPDR_RES_Pos) /*!< 0x80000000 */
/**************** Bit definition for GPIO_HWCFGR4 register ****************/
#define GPIO_HWCFGR4_OSPEED_RES_Pos (0U)
#define GPIO_HWCFGR4_OSPEED_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0xFFFFFFFF */
#define GPIO_HWCFGR4_OSPEED_RES GPIO_HWCFGR4_OSPEED_RES_Msk /*!< OSPEED register reset value */
#define GPIO_HWCFGR4_OSPEED_RES_0 (0x1U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000001 */
#define GPIO_HWCFGR4_OSPEED_RES_1 (0x2U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000002 */
#define GPIO_HWCFGR4_OSPEED_RES_2 (0x4U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000004 */
#define GPIO_HWCFGR4_OSPEED_RES_3 (0x8U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000008 */
#define GPIO_HWCFGR4_OSPEED_RES_4 (0x10U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000010 */
#define GPIO_HWCFGR4_OSPEED_RES_5 (0x20U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000020 */
#define GPIO_HWCFGR4_OSPEED_RES_6 (0x40U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000040 */
#define GPIO_HWCFGR4_OSPEED_RES_7 (0x80U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000080 */
#define GPIO_HWCFGR4_OSPEED_RES_8 (0x100U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000100 */
#define GPIO_HWCFGR4_OSPEED_RES_9 (0x200U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000200 */
#define GPIO_HWCFGR4_OSPEED_RES_10 (0x400U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000400 */
#define GPIO_HWCFGR4_OSPEED_RES_11 (0x800U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00000800 */
#define GPIO_HWCFGR4_OSPEED_RES_12 (0x1000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00001000 */
#define GPIO_HWCFGR4_OSPEED_RES_13 (0x2000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00002000 */
#define GPIO_HWCFGR4_OSPEED_RES_14 (0x4000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00004000 */
#define GPIO_HWCFGR4_OSPEED_RES_15 (0x8000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00008000 */
#define GPIO_HWCFGR4_OSPEED_RES_16 (0x10000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00010000 */
#define GPIO_HWCFGR4_OSPEED_RES_17 (0x20000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00020000 */
#define GPIO_HWCFGR4_OSPEED_RES_18 (0x40000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00040000 */
#define GPIO_HWCFGR4_OSPEED_RES_19 (0x80000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00080000 */
#define GPIO_HWCFGR4_OSPEED_RES_20 (0x100000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00100000 */
#define GPIO_HWCFGR4_OSPEED_RES_21 (0x200000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00200000 */
#define GPIO_HWCFGR4_OSPEED_RES_22 (0x400000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00400000 */
#define GPIO_HWCFGR4_OSPEED_RES_23 (0x800000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x00800000 */
#define GPIO_HWCFGR4_OSPEED_RES_24 (0x1000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x01000000 */
#define GPIO_HWCFGR4_OSPEED_RES_25 (0x2000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x02000000 */
#define GPIO_HWCFGR4_OSPEED_RES_26 (0x4000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x04000000 */
#define GPIO_HWCFGR4_OSPEED_RES_27 (0x8000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x08000000 */
#define GPIO_HWCFGR4_OSPEED_RES_28 (0x10000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x10000000 */
#define GPIO_HWCFGR4_OSPEED_RES_29 (0x20000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x20000000 */
#define GPIO_HWCFGR4_OSPEED_RES_30 (0x40000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x40000000 */
#define GPIO_HWCFGR4_OSPEED_RES_31 (0x80000000U << GPIO_HWCFGR4_OSPEED_RES_Pos) /*!< 0x80000000 */
/**************** Bit definition for GPIO_HWCFGR3 register ****************/
#define GPIO_HWCFGR3_ODR_RES_Pos (0U)
#define GPIO_HWCFGR3_ODR_RES_Msk (0xFFFFU << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x0000FFFF */
#define GPIO_HWCFGR3_ODR_RES GPIO_HWCFGR3_ODR_RES_Msk /*!< Output data register reset value */
#define GPIO_HWCFGR3_ODR_RES_0 (0x1U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000001 */
#define GPIO_HWCFGR3_ODR_RES_1 (0x2U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000002 */
#define GPIO_HWCFGR3_ODR_RES_2 (0x4U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000004 */
#define GPIO_HWCFGR3_ODR_RES_3 (0x8U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000008 */
#define GPIO_HWCFGR3_ODR_RES_4 (0x10U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000010 */
#define GPIO_HWCFGR3_ODR_RES_5 (0x20U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000020 */
#define GPIO_HWCFGR3_ODR_RES_6 (0x40U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000040 */
#define GPIO_HWCFGR3_ODR_RES_7 (0x80U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000080 */
#define GPIO_HWCFGR3_ODR_RES_8 (0x100U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000100 */
#define GPIO_HWCFGR3_ODR_RES_9 (0x200U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000200 */
#define GPIO_HWCFGR3_ODR_RES_10 (0x400U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000400 */
#define GPIO_HWCFGR3_ODR_RES_11 (0x800U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00000800 */
#define GPIO_HWCFGR3_ODR_RES_12 (0x1000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00001000 */
#define GPIO_HWCFGR3_ODR_RES_13 (0x2000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00002000 */
#define GPIO_HWCFGR3_ODR_RES_14 (0x4000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00004000 */
#define GPIO_HWCFGR3_ODR_RES_15 (0x8000U << GPIO_HWCFGR3_ODR_RES_Pos) /*!< 0x00008000 */
#define GPIO_HWCFGR3_OTYPER_RES_Pos (16U)
#define GPIO_HWCFGR3_OTYPER_RES_Msk (0xFFFFU << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0xFFFF0000 */
#define GPIO_HWCFGR3_OTYPER_RES GPIO_HWCFGR3_OTYPER_RES_Msk /*!< Output type register reset value */
#define GPIO_HWCFGR3_OTYPER_RES_0 (0x1U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00010000 */
#define GPIO_HWCFGR3_OTYPER_RES_1 (0x2U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00020000 */
#define GPIO_HWCFGR3_OTYPER_RES_2 (0x4U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00040000 */
#define GPIO_HWCFGR3_OTYPER_RES_3 (0x8U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00080000 */
#define GPIO_HWCFGR3_OTYPER_RES_4 (0x10U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00100000 */
#define GPIO_HWCFGR3_OTYPER_RES_5 (0x20U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00200000 */
#define GPIO_HWCFGR3_OTYPER_RES_6 (0x40U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00400000 */
#define GPIO_HWCFGR3_OTYPER_RES_7 (0x80U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x00800000 */
#define GPIO_HWCFGR3_OTYPER_RES_8 (0x100U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x01000000 */
#define GPIO_HWCFGR3_OTYPER_RES_9 (0x200U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x02000000 */
#define GPIO_HWCFGR3_OTYPER_RES_10 (0x400U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x04000000 */
#define GPIO_HWCFGR3_OTYPER_RES_11 (0x800U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x08000000 */
#define GPIO_HWCFGR3_OTYPER_RES_12 (0x1000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x10000000 */
#define GPIO_HWCFGR3_OTYPER_RES_13 (0x2000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x20000000 */
#define GPIO_HWCFGR3_OTYPER_RES_14 (0x4000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x40000000 */
#define GPIO_HWCFGR3_OTYPER_RES_15 (0x8000U << GPIO_HWCFGR3_OTYPER_RES_Pos) /*!< 0x80000000 */
/**************** Bit definition for GPIO_HWCFGR2 register ****************/
#define GPIO_HWCFGR2_AFRL_RES_Pos (0U)
#define GPIO_HWCFGR2_AFRL_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0xFFFFFFFF */
#define GPIO_HWCFGR2_AFRL_RES GPIO_HWCFGR2_AFRL_RES_Msk /*!< AF register low reset value */
#define GPIO_HWCFGR2_AFRL_RES_0 (0x1U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000001 */
#define GPIO_HWCFGR2_AFRL_RES_1 (0x2U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000002 */
#define GPIO_HWCFGR2_AFRL_RES_2 (0x4U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000004 */
#define GPIO_HWCFGR2_AFRL_RES_3 (0x8U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000008 */
#define GPIO_HWCFGR2_AFRL_RES_4 (0x10U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000010 */
#define GPIO_HWCFGR2_AFRL_RES_5 (0x20U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000020 */
#define GPIO_HWCFGR2_AFRL_RES_6 (0x40U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000040 */
#define GPIO_HWCFGR2_AFRL_RES_7 (0x80U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000080 */
#define GPIO_HWCFGR2_AFRL_RES_8 (0x100U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000100 */
#define GPIO_HWCFGR2_AFRL_RES_9 (0x200U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000200 */
#define GPIO_HWCFGR2_AFRL_RES_10 (0x400U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000400 */
#define GPIO_HWCFGR2_AFRL_RES_11 (0x800U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00000800 */
#define GPIO_HWCFGR2_AFRL_RES_12 (0x1000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00001000 */
#define GPIO_HWCFGR2_AFRL_RES_13 (0x2000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00002000 */
#define GPIO_HWCFGR2_AFRL_RES_14 (0x4000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00004000 */
#define GPIO_HWCFGR2_AFRL_RES_15 (0x8000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00008000 */
#define GPIO_HWCFGR2_AFRL_RES_16 (0x10000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00010000 */
#define GPIO_HWCFGR2_AFRL_RES_17 (0x20000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00020000 */
#define GPIO_HWCFGR2_AFRL_RES_18 (0x40000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00040000 */
#define GPIO_HWCFGR2_AFRL_RES_19 (0x80000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00080000 */
#define GPIO_HWCFGR2_AFRL_RES_20 (0x100000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00100000 */
#define GPIO_HWCFGR2_AFRL_RES_21 (0x200000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00200000 */
#define GPIO_HWCFGR2_AFRL_RES_22 (0x400000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00400000 */
#define GPIO_HWCFGR2_AFRL_RES_23 (0x800000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x00800000 */
#define GPIO_HWCFGR2_AFRL_RES_24 (0x1000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x01000000 */
#define GPIO_HWCFGR2_AFRL_RES_25 (0x2000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x02000000 */
#define GPIO_HWCFGR2_AFRL_RES_26 (0x4000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x04000000 */
#define GPIO_HWCFGR2_AFRL_RES_27 (0x8000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x08000000 */
#define GPIO_HWCFGR2_AFRL_RES_28 (0x10000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x10000000 */
#define GPIO_HWCFGR2_AFRL_RES_29 (0x20000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x20000000 */
#define GPIO_HWCFGR2_AFRL_RES_30 (0x40000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x40000000 */
#define GPIO_HWCFGR2_AFRL_RES_31 (0x80000000U << GPIO_HWCFGR2_AFRL_RES_Pos) /*!< 0x80000000 */
/**************** Bit definition for GPIO_HWCFGR1 register ****************/
#define GPIO_HWCFGR1_AFRH_RES_Pos (0U)
#define GPIO_HWCFGR1_AFRH_RES_Msk (0xFFFFFFFFU << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0xFFFFFFFF */
#define GPIO_HWCFGR1_AFRH_RES GPIO_HWCFGR1_AFRH_RES_Msk /*!< AF register high reset value */
#define GPIO_HWCFGR1_AFRH_RES_0 (0x1U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000001 */
#define GPIO_HWCFGR1_AFRH_RES_1 (0x2U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000002 */
#define GPIO_HWCFGR1_AFRH_RES_2 (0x4U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000004 */
#define GPIO_HWCFGR1_AFRH_RES_3 (0x8U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000008 */
#define GPIO_HWCFGR1_AFRH_RES_4 (0x10U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000010 */
#define GPIO_HWCFGR1_AFRH_RES_5 (0x20U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000020 */
#define GPIO_HWCFGR1_AFRH_RES_6 (0x40U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000040 */
#define GPIO_HWCFGR1_AFRH_RES_7 (0x80U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000080 */
#define GPIO_HWCFGR1_AFRH_RES_8 (0x100U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000100 */
#define GPIO_HWCFGR1_AFRH_RES_9 (0x200U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000200 */
#define GPIO_HWCFGR1_AFRH_RES_10 (0x400U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000400 */
#define GPIO_HWCFGR1_AFRH_RES_11 (0x800U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00000800 */
#define GPIO_HWCFGR1_AFRH_RES_12 (0x1000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00001000 */
#define GPIO_HWCFGR1_AFRH_RES_13 (0x2000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00002000 */
#define GPIO_HWCFGR1_AFRH_RES_14 (0x4000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00004000 */
#define GPIO_HWCFGR1_AFRH_RES_15 (0x8000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00008000 */
#define GPIO_HWCFGR1_AFRH_RES_16 (0x10000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00010000 */
#define GPIO_HWCFGR1_AFRH_RES_17 (0x20000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00020000 */
#define GPIO_HWCFGR1_AFRH_RES_18 (0x40000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00040000 */
#define GPIO_HWCFGR1_AFRH_RES_19 (0x80000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00080000 */
#define GPIO_HWCFGR1_AFRH_RES_20 (0x100000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00100000 */
#define GPIO_HWCFGR1_AFRH_RES_21 (0x200000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00200000 */
#define GPIO_HWCFGR1_AFRH_RES_22 (0x400000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00400000 */
#define GPIO_HWCFGR1_AFRH_RES_23 (0x800000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x00800000 */
#define GPIO_HWCFGR1_AFRH_RES_24 (0x1000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x01000000 */
#define GPIO_HWCFGR1_AFRH_RES_25 (0x2000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x02000000 */
#define GPIO_HWCFGR1_AFRH_RES_26 (0x4000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x04000000 */
#define GPIO_HWCFGR1_AFRH_RES_27 (0x8000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x08000000 */
#define GPIO_HWCFGR1_AFRH_RES_28 (0x10000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x10000000 */
#define GPIO_HWCFGR1_AFRH_RES_29 (0x20000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x20000000 */
#define GPIO_HWCFGR1_AFRH_RES_30 (0x40000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x40000000 */
#define GPIO_HWCFGR1_AFRH_RES_31 (0x80000000U << GPIO_HWCFGR1_AFRH_RES_Pos) /*!< 0x80000000 */
/**************** Bit definition for GPIO_HWCFGR0 register ****************/
#define GPIO_HWCFGR0_OR_RES_Pos (0U)
#define GPIO_HWCFGR0_OR_RES_Msk (0xFFFFU << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x0000FFFF */
#define GPIO_HWCFGR0_OR_RES GPIO_HWCFGR0_OR_RES_Msk /*!< Option register reset value */
#define GPIO_HWCFGR0_OR_RES_0 (0x1U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000001 */
#define GPIO_HWCFGR0_OR_RES_1 (0x2U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000002 */
#define GPIO_HWCFGR0_OR_RES_2 (0x4U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000004 */
#define GPIO_HWCFGR0_OR_RES_3 (0x8U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000008 */
#define GPIO_HWCFGR0_OR_RES_4 (0x10U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000010 */
#define GPIO_HWCFGR0_OR_RES_5 (0x20U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000020 */
#define GPIO_HWCFGR0_OR_RES_6 (0x40U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000040 */
#define GPIO_HWCFGR0_OR_RES_7 (0x80U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000080 */
#define GPIO_HWCFGR0_OR_RES_8 (0x100U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000100 */
#define GPIO_HWCFGR0_OR_RES_9 (0x200U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000200 */
#define GPIO_HWCFGR0_OR_RES_10 (0x400U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000400 */
#define GPIO_HWCFGR0_OR_RES_11 (0x800U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00000800 */
#define GPIO_HWCFGR0_OR_RES_12 (0x1000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00001000 */
#define GPIO_HWCFGR0_OR_RES_13 (0x2000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00002000 */
#define GPIO_HWCFGR0_OR_RES_14 (0x4000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00004000 */
#define GPIO_HWCFGR0_OR_RES_15 (0x8000U << GPIO_HWCFGR0_OR_RES_Pos) /*!< 0x00008000 */
/********************** Bit definition for GPIO_VERR register *****************/
#define GPIO_VERR_MINREV_Pos (0U)
#define GPIO_VERR_MINREV_Msk (0xFU << GPIO_VERR_MINREV_Pos) /*!< 0x0000000F */
#define GPIO_VERR_MINREV GPIO_VERR_MINREV_Msk /*!< Minor Revision number */
#define GPIO_VERR_MAJREV_Pos (4U)
#define GPIO_VERR_MAJREV_Msk (0xFU << GPIO_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define GPIO_VERR_MAJREV GPIO_VERR_MAJREV_Msk /*!< Major Revision number */
/********************** Bit definition for GPIO_IPIDR register ****************/
#define GPIO_IPIDR_IPID_Pos (0U)
#define GPIO_IPIDR_IPID_Msk (0xFFFFFFFFU << GPIO_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
#define GPIO_IPIDR_IPID GPIO_IPIDR_IPID_Msk /*!< IP Identification */
/********************** Bit definition for GPIO_SIDR register *****************/
#define GPIO_SIDR_SID_Pos (0U)
#define GPIO_SIDR_SID_Msk (0xFFFFFFFFU << GPIO_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define GPIO_SIDR_SID GPIO_SIDR_SID_Msk /*!< IP size identification */
/******************************************************************************/
/* */
/* HSEM HW Semaphore */
/* */
/******************************************************************************/
/******************** Bit definition for HSEM_R register ********************/
#define HSEM_R_PROCID_Pos (0U)
#define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) /*!< 0x000000FF */
#define HSEM_R_PROCID HSEM_R_PROCID_Msk /*!<Semaphore ProcessID */
#define HSEM_R_COREID_Pos (8U)
#define HSEM_R_COREID_Msk (0xFFUL << HSEM_R_COREID_Pos) /*!< 0x0000FF00 */
#define HSEM_R_COREID HSEM_R_COREID_Msk /*!<Semaphore CoreID. */
#define HSEM_R_LOCK_Pos (31U)
#define HSEM_R_LOCK_Msk (0x1UL << HSEM_R_LOCK_Pos) /*!< 0x80000000 */
#define HSEM_R_LOCK HSEM_R_LOCK_Msk /*!<Lock indication. */
/******************** Bit definition for HSEM_RLR register ******************/
#define HSEM_RLR_PROCID_Pos (0U)
#define HSEM_RLR_PROCID_Msk (0xFFUL << HSEM_RLR_PROCID_Pos) /*!< 0x000000FF */
#define HSEM_RLR_PROCID HSEM_RLR_PROCID_Msk /*!<Semaphore ProcessID */
#define HSEM_RLR_COREID_Pos (8U)
#define HSEM_RLR_COREID_Msk (0xFFUL << HSEM_RLR_COREID_Pos) /*!< 0x0000FF00 */
#define HSEM_RLR_COREID HSEM_RLR_COREID_Msk /*!<Semaphore CoreID. */
#define HSEM_RLR_LOCK_Pos (31U)
#define HSEM_RLR_LOCK_Msk (0x1UL << HSEM_RLR_LOCK_Pos) /*!< 0x80000000 */
#define HSEM_RLR_LOCK HSEM_RLR_LOCK_Msk /*!<Lock indication. */
/******************** Bit definition for HSEM_C1IER register *****************/
#define HSEM_C1IER_ISE0_Pos (0U)
#define HSEM_C1IER_ISE0_Msk (0x1UL << HSEM_C1IER_ISE0_Pos) /*!< 0x00000001 */
#define HSEM_C1IER_ISE0 HSEM_C1IER_ISE0_Msk /*!<semaphore 0 , interrupt 0 enable bit. */
#define HSEM_C1IER_ISE1_Pos (1U)
#define HSEM_C1IER_ISE1_Msk (0x1UL << HSEM_C1IER_ISE1_Pos) /*!< 0x00000002 */
#define HSEM_C1IER_ISE1 HSEM_C1IER_ISE1_Msk /*!<semaphore 1 , interrupt 0 enable bit. */
#define HSEM_C1IER_ISE2_Pos (2U)
#define HSEM_C1IER_ISE2_Msk (0x1UL << HSEM_C1IER_ISE2_Pos) /*!< 0x00000004 */
#define HSEM_C1IER_ISE2 HSEM_C1IER_ISE2_Msk /*!<semaphore 2 , interrupt 0 enable bit. */
#define HSEM_C1IER_ISE3_Pos (3U)
#define HSEM_C1IER_ISE3_Msk (0x1UL << HSEM_C1IER_ISE3_Pos) /*!< 0x00000008 */
#define HSEM_C1IER_ISE3 HSEM_C1IER_ISE3_Msk /*!<semaphore 3 , interrupt 0 enable bit. */
#define HSEM_C1IER_ISE4_Pos (4U)
#define HSEM_C1IER_ISE4_Msk (0x1UL << HSEM_C1IER_ISE4_Pos) /*!< 0x00000010 */
#define HSEM_C1IER_ISE4 HSEM_C1IER_ISE4_Msk /*!<semaphore 4 , interrupt 0 enable bit. */
#define HSEM_C1IER_ISE5_Pos (5U)
#define HSEM_C1IER_ISE5_Msk (0x1UL << HSEM_C1IER_ISE5_Pos) /*!< 0x00000020 */
#define HSEM_C1IER_ISE5 HSEM_C1IER_ISE5_Msk /*!<semaphore 5 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE6_Pos (6U)
#define HSEM_C1IER_ISE6_Msk (0x1UL << HSEM_C1IER_ISE6_Pos) /*!< 0x00000040 */
#define HSEM_C1IER_ISE6 HSEM_C1IER_ISE6_Msk /*!<semaphore 6 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE7_Pos (7U)
#define HSEM_C1IER_ISE7_Msk (0x1UL << HSEM_C1IER_ISE7_Pos) /*!< 0x00000080 */
#define HSEM_C1IER_ISE7 HSEM_C1IER_ISE7_Msk /*!<semaphore 7 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE8_Pos (8U)
#define HSEM_C1IER_ISE8_Msk (0x1UL << HSEM_C1IER_ISE8_Pos) /*!< 0x00000100 */
#define HSEM_C1IER_ISE8 HSEM_C1IER_ISE8_Msk /*!<semaphore 8 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE9_Pos (9U)
#define HSEM_C1IER_ISE9_Msk (0x1UL << HSEM_C1IER_ISE9_Pos) /*!< 0x00000200 */
#define HSEM_C1IER_ISE9 HSEM_C1IER_ISE9_Msk /*!<semaphore 9 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE10_Pos (10U)
#define HSEM_C1IER_ISE10_Msk (0x1UL << HSEM_C1IER_ISE10_Pos) /*!< 0x00000400 */
#define HSEM_C1IER_ISE10 HSEM_C1IER_ISE10_Msk /*!<semaphore 10 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE11_Pos (11U)
#define HSEM_C1IER_ISE11_Msk (0x1UL << HSEM_C1IER_ISE11_Pos) /*!< 0x00000800 */
#define HSEM_C1IER_ISE11 HSEM_C1IER_ISE11_Msk /*!<semaphore 11 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE12_Pos (12U)
#define HSEM_C1IER_ISE12_Msk (0x1UL << HSEM_C1IER_ISE12_Pos) /*!< 0x00001000 */
#define HSEM_C1IER_ISE12 HSEM_C1IER_ISE12_Msk /*!<semaphore 12 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE13_Pos (13U)
#define HSEM_C1IER_ISE13_Msk (0x1UL << HSEM_C1IER_ISE13_Pos) /*!< 0x00002000 */
#define HSEM_C1IER_ISE13 HSEM_C1IER_ISE13_Msk /*!<semaphore 13 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE14_Pos (14U)
#define HSEM_C1IER_ISE14_Msk (0x1UL << HSEM_C1IER_ISE14_Pos) /*!< 0x00004000 */
#define HSEM_C1IER_ISE14 HSEM_C1IER_ISE14_Msk /*!<semaphore 14 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE15_Pos (15U)
#define HSEM_C1IER_ISE15_Msk (0x1UL << HSEM_C1IER_ISE15_Pos) /*!< 0x00008000 */
#define HSEM_C1IER_ISE15 HSEM_C1IER_ISE15_Msk /*!<semaphore 15 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE16_Pos (16U)
#define HSEM_C1IER_ISE16_Msk (0x1UL << HSEM_C1IER_ISE16_Pos) /*!< 0x00010000 */
#define HSEM_C1IER_ISE16 HSEM_C1IER_ISE16_Msk /*!<semaphore 16 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE17_Pos (17U)
#define HSEM_C1IER_ISE17_Msk (0x1UL << HSEM_C1IER_ISE17_Pos) /*!< 0x00020000 */
#define HSEM_C1IER_ISE17 HSEM_C1IER_ISE17_Msk /*!<semaphore 17 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE18_Pos (18U)
#define HSEM_C1IER_ISE18_Msk (0x1UL << HSEM_C1IER_ISE18_Pos) /*!< 0x00040000 */
#define HSEM_C1IER_ISE18 HSEM_C1IER_ISE18_Msk /*!<semaphore 18 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE19_Pos (19U)
#define HSEM_C1IER_ISE19_Msk (0x1UL << HSEM_C1IER_ISE19_Pos) /*!< 0x00080000 */
#define HSEM_C1IER_ISE19 HSEM_C1IER_ISE19_Msk /*!<semaphore 19 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE20_Pos (20U)
#define HSEM_C1IER_ISE20_Msk (0x1UL << HSEM_C1IER_ISE20_Pos) /*!< 0x00100000 */
#define HSEM_C1IER_ISE20 HSEM_C1IER_ISE20_Msk /*!<semaphore 20 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE21_Pos (21U)
#define HSEM_C1IER_ISE21_Msk (0x1UL << HSEM_C1IER_ISE21_Pos) /*!< 0x00200000 */
#define HSEM_C1IER_ISE21 HSEM_C1IER_ISE21_Msk /*!<semaphore 21 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE22_Pos (22U)
#define HSEM_C1IER_ISE22_Msk (0x1UL << HSEM_C1IER_ISE22_Pos) /*!< 0x00400000 */
#define HSEM_C1IER_ISE22 HSEM_C1IER_ISE22_Msk /*!<semaphore 22 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE23_Pos (23U)
#define HSEM_C1IER_ISE23_Msk (0x1UL << HSEM_C1IER_ISE23_Pos) /*!< 0x00800000 */
#define HSEM_C1IER_ISE23 HSEM_C1IER_ISE23_Msk /*!<semaphore 23 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE24_Pos (24U)
#define HSEM_C1IER_ISE24_Msk (0x1UL << HSEM_C1IER_ISE24_Pos) /*!< 0x01000000 */
#define HSEM_C1IER_ISE24 HSEM_C1IER_ISE24_Msk /*!<semaphore 24 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE25_Pos (25U)
#define HSEM_C1IER_ISE25_Msk (0x1UL << HSEM_C1IER_ISE25_Pos) /*!< 0x02000000 */
#define HSEM_C1IER_ISE25 HSEM_C1IER_ISE25_Msk /*!<semaphore 25 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE26_Pos (26U)
#define HSEM_C1IER_ISE26_Msk (0x1UL << HSEM_C1IER_ISE26_Pos) /*!< 0x04000000 */
#define HSEM_C1IER_ISE26 HSEM_C1IER_ISE26_Msk /*!<semaphore 26 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE27_Pos (27U)
#define HSEM_C1IER_ISE27_Msk (0x1UL << HSEM_C1IER_ISE27_Pos) /*!< 0x08000000 */
#define HSEM_C1IER_ISE27 HSEM_C1IER_ISE27_Msk /*!<semaphore 27 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE28_Pos (28U)
#define HSEM_C1IER_ISE28_Msk (0x1UL << HSEM_C1IER_ISE28_Pos) /*!< 0x10000000 */
#define HSEM_C1IER_ISE28 HSEM_C1IER_ISE28_Msk /*!<semaphore 28 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE29_Pos (29U)
#define HSEM_C1IER_ISE29_Msk (0x1UL << HSEM_C1IER_ISE29_Pos) /*!< 0x20000000 */
#define HSEM_C1IER_ISE29 HSEM_C1IER_ISE29_Msk /*!<semaphore 29 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE30_Pos (30U)
#define HSEM_C1IER_ISE30_Msk (0x1UL << HSEM_C1IER_ISE30_Pos) /*!< 0x40000000 */
#define HSEM_C1IER_ISE30 HSEM_C1IER_ISE30_Msk /*!<semaphore 30 interrupt 0 enable bit. */
#define HSEM_C1IER_ISE31_Pos (31U)
#define HSEM_C1IER_ISE31_Msk (0x1UL << HSEM_C1IER_ISE31_Pos) /*!< 0x80000000 */
#define HSEM_C1IER_ISE31 HSEM_C1IER_ISE31_Msk /*!<semaphore 31 interrupt 0 enable bit. */
/******************** Bit definition for HSEM_C1ICR register *****************/
#define HSEM_C1ICR_ISC0_Pos (0U)
#define HSEM_C1ICR_ISC0_Msk (0x1UL << HSEM_C1ICR_ISC0_Pos) /*!< 0x00000001 */
#define HSEM_C1ICR_ISC0 HSEM_C1ICR_ISC0_Msk /*!<semaphore 0 , interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC1_Pos (1U)
#define HSEM_C1ICR_ISC1_Msk (0x1UL << HSEM_C1ICR_ISC1_Pos) /*!< 0x00000002 */
#define HSEM_C1ICR_ISC1 HSEM_C1ICR_ISC1_Msk /*!<semaphore 1 , interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC2_Pos (2U)
#define HSEM_C1ICR_ISC2_Msk (0x1UL << HSEM_C1ICR_ISC2_Pos) /*!< 0x00000004 */
#define HSEM_C1ICR_ISC2 HSEM_C1ICR_ISC2_Msk /*!<semaphore 2 , interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC3_Pos (3U)
#define HSEM_C1ICR_ISC3_Msk (0x1UL << HSEM_C1ICR_ISC3_Pos) /*!< 0x00000008 */
#define HSEM_C1ICR_ISC3 HSEM_C1ICR_ISC3_Msk /*!<semaphore 3 , interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC4_Pos (4U)
#define HSEM_C1ICR_ISC4_Msk (0x1UL << HSEM_C1ICR_ISC4_Pos) /*!< 0x00000010 */
#define HSEM_C1ICR_ISC4 HSEM_C1ICR_ISC4_Msk /*!<semaphore 4 , interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC5_Pos (5U)
#define HSEM_C1ICR_ISC5_Msk (0x1UL << HSEM_C1ICR_ISC5_Pos) /*!< 0x00000020 */
#define HSEM_C1ICR_ISC5 HSEM_C1ICR_ISC5_Msk /*!<semaphore 5 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC6_Pos (6U)
#define HSEM_C1ICR_ISC6_Msk (0x1UL << HSEM_C1ICR_ISC6_Pos) /*!< 0x00000040 */
#define HSEM_C1ICR_ISC6 HSEM_C1ICR_ISC6_Msk /*!<semaphore 6 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC7_Pos (7U)
#define HSEM_C1ICR_ISC7_Msk (0x1UL << HSEM_C1ICR_ISC7_Pos) /*!< 0x00000080 */
#define HSEM_C1ICR_ISC7 HSEM_C1ICR_ISC7_Msk /*!<semaphore 7 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC8_Pos (8U)
#define HSEM_C1ICR_ISC8_Msk (0x1UL << HSEM_C1ICR_ISC8_Pos) /*!< 0x00000100 */
#define HSEM_C1ICR_ISC8 HSEM_C1ICR_ISC8_Msk /*!<semaphore 8 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC9_Pos (9U)
#define HSEM_C1ICR_ISC9_Msk (0x1UL << HSEM_C1ICR_ISC9_Pos) /*!< 0x00000200 */
#define HSEM_C1ICR_ISC9 HSEM_C1ICR_ISC9_Msk /*!<semaphore 9 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC10_Pos (10U)
#define HSEM_C1ICR_ISC10_Msk (0x1UL << HSEM_C1ICR_ISC10_Pos) /*!< 0x00000400 */
#define HSEM_C1ICR_ISC10 HSEM_C1ICR_ISC10_Msk /*!<semaphore 10 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC11_Pos (11U)
#define HSEM_C1ICR_ISC11_Msk (0x1UL << HSEM_C1ICR_ISC11_Pos) /*!< 0x00000800 */
#define HSEM_C1ICR_ISC11 HSEM_C1ICR_ISC11_Msk /*!<semaphore 11 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC12_Pos (12U)
#define HSEM_C1ICR_ISC12_Msk (0x1UL << HSEM_C1ICR_ISC12_Pos) /*!< 0x00001000 */
#define HSEM_C1ICR_ISC12 HSEM_C1ICR_ISC12_Msk /*!<semaphore 12 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC13_Pos (13U)
#define HSEM_C1ICR_ISC13_Msk (0x1UL << HSEM_C1ICR_ISC13_Pos) /*!< 0x00002000 */
#define HSEM_C1ICR_ISC13 HSEM_C1ICR_ISC13_Msk /*!<semaphore 13 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC14_Pos (14U)
#define HSEM_C1ICR_ISC14_Msk (0x1UL << HSEM_C1ICR_ISC14_Pos) /*!< 0x00004000 */
#define HSEM_C1ICR_ISC14 HSEM_C1ICR_ISC14_Msk /*!<semaphore 14 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC15_Pos (15U)
#define HSEM_C1ICR_ISC15_Msk (0x1UL << HSEM_C1ICR_ISC15_Pos) /*!< 0x00008000 */
#define HSEM_C1ICR_ISC15 HSEM_C1ICR_ISC15_Msk /*!<semaphore 15 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC16_Pos (16U)
#define HSEM_C1ICR_ISC16_Msk (0x1UL << HSEM_C1ICR_ISC16_Pos) /*!< 0x00010000 */
#define HSEM_C1ICR_ISC16 HSEM_C1ICR_ISC16_Msk /*!<semaphore 16 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC17_Pos (17U)
#define HSEM_C1ICR_ISC17_Msk (0x1UL << HSEM_C1ICR_ISC17_Pos) /*!< 0x00020000 */
#define HSEM_C1ICR_ISC17 HSEM_C1ICR_ISC17_Msk /*!<semaphore 17 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC18_Pos (18U)
#define HSEM_C1ICR_ISC18_Msk (0x1UL << HSEM_C1ICR_ISC18_Pos) /*!< 0x00040000 */
#define HSEM_C1ICR_ISC18 HSEM_C1ICR_ISC18_Msk /*!<semaphore 18 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC19_Pos (19U)
#define HSEM_C1ICR_ISC19_Msk (0x1UL << HSEM_C1ICR_ISC19_Pos) /*!< 0x00080000 */
#define HSEM_C1ICR_ISC19 HSEM_C1ICR_ISC19_Msk /*!<semaphore 19 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC20_Pos (20U)
#define HSEM_C1ICR_ISC20_Msk (0x1UL << HSEM_C1ICR_ISC20_Pos) /*!< 0x00100000 */
#define HSEM_C1ICR_ISC20 HSEM_C1ICR_ISC20_Msk /*!<semaphore 20 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC21_Pos (21U)
#define HSEM_C1ICR_ISC21_Msk (0x1UL << HSEM_C1ICR_ISC21_Pos) /*!< 0x00200000 */
#define HSEM_C1ICR_ISC21 HSEM_C1ICR_ISC21_Msk /*!<semaphore 21 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC22_Pos (22U)
#define HSEM_C1ICR_ISC22_Msk (0x1UL << HSEM_C1ICR_ISC22_Pos) /*!< 0x00400000 */
#define HSEM_C1ICR_ISC22 HSEM_C1ICR_ISC22_Msk /*!<semaphore 22 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC23_Pos (23U)
#define HSEM_C1ICR_ISC23_Msk (0x1UL << HSEM_C1ICR_ISC23_Pos) /*!< 0x00800000 */
#define HSEM_C1ICR_ISC23 HSEM_C1ICR_ISC23_Msk /*!<semaphore 23 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC24_Pos (24U)
#define HSEM_C1ICR_ISC24_Msk (0x1UL << HSEM_C1ICR_ISC24_Pos) /*!< 0x01000000 */
#define HSEM_C1ICR_ISC24 HSEM_C1ICR_ISC24_Msk /*!<semaphore 24 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC25_Pos (25U)
#define HSEM_C1ICR_ISC25_Msk (0x1UL << HSEM_C1ICR_ISC25_Pos) /*!< 0x02000000 */
#define HSEM_C1ICR_ISC25 HSEM_C1ICR_ISC25_Msk /*!<semaphore 25 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC26_Pos (26U)
#define HSEM_C1ICR_ISC26_Msk (0x1UL << HSEM_C1ICR_ISC26_Pos) /*!< 0x04000000 */
#define HSEM_C1ICR_ISC26 HSEM_C1ICR_ISC26_Msk /*!<semaphore 26 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC27_Pos (27U)
#define HSEM_C1ICR_ISC27_Msk (0x1UL << HSEM_C1ICR_ISC27_Pos) /*!< 0x08000000 */
#define HSEM_C1ICR_ISC27 HSEM_C1ICR_ISC27_Msk /*!<semaphore 27 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC28_Pos (28U)
#define HSEM_C1ICR_ISC28_Msk (0x1UL << HSEM_C1ICR_ISC28_Pos) /*!< 0x10000000 */
#define HSEM_C1ICR_ISC28 HSEM_C1ICR_ISC28_Msk /*!<semaphore 28 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC29_Pos (29U)
#define HSEM_C1ICR_ISC29_Msk (0x1UL << HSEM_C1ICR_ISC29_Pos) /*!< 0x20000000 */
#define HSEM_C1ICR_ISC29 HSEM_C1ICR_ISC29_Msk /*!<semaphore 29 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC30_Pos (30U)
#define HSEM_C1ICR_ISC30_Msk (0x1UL << HSEM_C1ICR_ISC30_Pos) /*!< 0x40000000 */
#define HSEM_C1ICR_ISC30 HSEM_C1ICR_ISC30_Msk /*!<semaphore 30 interrupt 0 clear bit. */
#define HSEM_C1ICR_ISC31_Pos (31U)
#define HSEM_C1ICR_ISC31_Msk (0x1UL << HSEM_C1ICR_ISC31_Pos) /*!< 0x80000000 */
#define HSEM_C1ICR_ISC31 HSEM_C1ICR_ISC31_Msk /*!<semaphore 31 interrupt 0 clear bit. */
/******************** Bit definition for HSEM_C1ISR register *****************/
#define HSEM_C1ISR_ISF0_Pos (0U)
#define HSEM_C1ISR_ISF0_Msk (0x1UL << HSEM_C1ISR_ISF0_Pos) /*!< 0x00000001 */
#define HSEM_C1ISR_ISF0 HSEM_C1ISR_ISF0_Msk /*!<semaphore 0 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF1_Pos (1U)
#define HSEM_C1ISR_ISF1_Msk (0x1UL << HSEM_C1ISR_ISF1_Pos) /*!< 0x00000002 */
#define HSEM_C1ISR_ISF1 HSEM_C1ISR_ISF1_Msk /*!<semaphore 1 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF2_Pos (2U)
#define HSEM_C1ISR_ISF2_Msk (0x1UL << HSEM_C1ISR_ISF2_Pos) /*!< 0x00000004 */
#define HSEM_C1ISR_ISF2 HSEM_C1ISR_ISF2_Msk /*!<semaphore 2 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF3_Pos (3U)
#define HSEM_C1ISR_ISF3_Msk (0x1UL << HSEM_C1ISR_ISF3_Pos) /*!< 0x00000008 */
#define HSEM_C1ISR_ISF3 HSEM_C1ISR_ISF3_Msk /*!<semaphore 3 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF4_Pos (4U)
#define HSEM_C1ISR_ISF4_Msk (0x1UL << HSEM_C1ISR_ISF4_Pos) /*!< 0x00000010 */
#define HSEM_C1ISR_ISF4 HSEM_C1ISR_ISF4_Msk /*!<semaphore 4 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF5_Pos (5U)
#define HSEM_C1ISR_ISF5_Msk (0x1UL << HSEM_C1ISR_ISF5_Pos) /*!< 0x00000020 */
#define HSEM_C1ISR_ISF5 HSEM_C1ISR_ISF5_Msk /*!<semaphore 5 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF6_Pos (6U)
#define HSEM_C1ISR_ISF6_Msk (0x1UL << HSEM_C1ISR_ISF6_Pos) /*!< 0x00000040 */
#define HSEM_C1ISR_ISF6 HSEM_C1ISR_ISF6_Msk /*!<semaphore 6 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF7_Pos (7U)
#define HSEM_C1ISR_ISF7_Msk (0x1UL << HSEM_C1ISR_ISF7_Pos) /*!< 0x00000080 */
#define HSEM_C1ISR_ISF7 HSEM_C1ISR_ISF7_Msk /*!<semaphore 7 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF8_Pos (8U)
#define HSEM_C1ISR_ISF8_Msk (0x1UL << HSEM_C1ISR_ISF8_Pos) /*!< 0x00000100 */
#define HSEM_C1ISR_ISF8 HSEM_C1ISR_ISF8_Msk /*!<semaphore 8 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF9_Pos (9U)
#define HSEM_C1ISR_ISF9_Msk (0x1UL << HSEM_C1ISR_ISF9_Pos) /*!< 0x00000200 */
#define HSEM_C1ISR_ISF9 HSEM_C1ISR_ISF9_Msk /*!<semaphore 9 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF10_Pos (10U)
#define HSEM_C1ISR_ISF10_Msk (0x1UL << HSEM_C1ISR_ISF10_Pos) /*!< 0x00000400 */
#define HSEM_C1ISR_ISF10 HSEM_C1ISR_ISF10_Msk /*!<semaphore 10 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF11_Pos (11U)
#define HSEM_C1ISR_ISF11_Msk (0x1UL << HSEM_C1ISR_ISF11_Pos) /*!< 0x00000800 */
#define HSEM_C1ISR_ISF11 HSEM_C1ISR_ISF11_Msk /*!<semaphore 11 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF12_Pos (12U)
#define HSEM_C1ISR_ISF12_Msk (0x1UL << HSEM_C1ISR_ISF12_Pos) /*!< 0x00001000 */
#define HSEM_C1ISR_ISF12 HSEM_C1ISR_ISF12_Msk /*!<semaphore 12 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF13_Pos (13U)
#define HSEM_C1ISR_ISF13_Msk (0x1UL << HSEM_C1ISR_ISF13_Pos) /*!< 0x00002000 */
#define HSEM_C1ISR_ISF13 HSEM_C1ISR_ISF13_Msk /*!<semaphore 13 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF14_Pos (14U)
#define HSEM_C1ISR_ISF14_Msk (0x1UL << HSEM_C1ISR_ISF14_Pos) /*!< 0x00004000 */
#define HSEM_C1ISR_ISF14 HSEM_C1ISR_ISF14_Msk /*!<semaphore 14 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF15_Pos (15U)
#define HSEM_C1ISR_ISF15_Msk (0x1UL << HSEM_C1ISR_ISF15_Pos) /*!< 0x00008000 */
#define HSEM_C1ISR_ISF15 HSEM_C1ISR_ISF15_Msk /*!<semaphore 15 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF16_Pos (16U)
#define HSEM_C1ISR_ISF16_Msk (0x1UL << HSEM_C1ISR_ISF16_Pos) /*!< 0x00010000 */
#define HSEM_C1ISR_ISF16 HSEM_C1ISR_ISF16_Msk /*!<semaphore 16 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF17_Pos (17U)
#define HSEM_C1ISR_ISF17_Msk (0x1UL << HSEM_C1ISR_ISF17_Pos) /*!< 0x00020000 */
#define HSEM_C1ISR_ISF17 HSEM_C1ISR_ISF17_Msk /*!<semaphore 17 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF18_Pos (18U)
#define HSEM_C1ISR_ISF18_Msk (0x1UL << HSEM_C1ISR_ISF18_Pos) /*!< 0x00040000 */
#define HSEM_C1ISR_ISF18 HSEM_C1ISR_ISF18_Msk /*!<semaphore 18 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF19_Pos (19U)
#define HSEM_C1ISR_ISF19_Msk (0x1UL << HSEM_C1ISR_ISF19_Pos) /*!< 0x00080000 */
#define HSEM_C1ISR_ISF19 HSEM_C1ISR_ISF19_Msk /*!<semaphore 19 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF20_Pos (20U)
#define HSEM_C1ISR_ISF20_Msk (0x1UL << HSEM_C1ISR_ISF20_Pos) /*!< 0x00100000 */
#define HSEM_C1ISR_ISF20 HSEM_C1ISR_ISF20_Msk /*!<semaphore 20 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF21_Pos (21U)
#define HSEM_C1ISR_ISF21_Msk (0x1UL << HSEM_C1ISR_ISF21_Pos) /*!< 0x00200000 */
#define HSEM_C1ISR_ISF21 HSEM_C1ISR_ISF21_Msk /*!<semaphore 21 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF22_Pos (22U)
#define HSEM_C1ISR_ISF22_Msk (0x1UL << HSEM_C1ISR_ISF22_Pos) /*!< 0x00400000 */
#define HSEM_C1ISR_ISF22 HSEM_C1ISR_ISF22_Msk /*!<semaphore 22 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF23_Pos (23U)
#define HSEM_C1ISR_ISF23_Msk (0x1UL << HSEM_C1ISR_ISF23_Pos) /*!< 0x00800000 */
#define HSEM_C1ISR_ISF23 HSEM_C1ISR_ISF23_Msk /*!<semaphore 23 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF24_Pos (24U)
#define HSEM_C1ISR_ISF24_Msk (0x1UL << HSEM_C1ISR_ISF24_Pos) /*!< 0x01000000 */
#define HSEM_C1ISR_ISF24 HSEM_C1ISR_ISF24_Msk /*!<semaphore 24 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF25_Pos (25U)
#define HSEM_C1ISR_ISF25_Msk (0x1UL << HSEM_C1ISR_ISF25_Pos) /*!< 0x02000000 */
#define HSEM_C1ISR_ISF25 HSEM_C1ISR_ISF25_Msk /*!<semaphore 25 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF26_Pos (26U)
#define HSEM_C1ISR_ISF26_Msk (0x1UL << HSEM_C1ISR_ISF26_Pos) /*!< 0x04000000 */
#define HSEM_C1ISR_ISF26 HSEM_C1ISR_ISF26_Msk /*!<semaphore 26 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF27_Pos (27U)
#define HSEM_C1ISR_ISF27_Msk (0x1UL << HSEM_C1ISR_ISF27_Pos) /*!< 0x08000000 */
#define HSEM_C1ISR_ISF27 HSEM_C1ISR_ISF27_Msk /*!<semaphore 27 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF28_Pos (28U)
#define HSEM_C1ISR_ISF28_Msk (0x1UL << HSEM_C1ISR_ISF28_Pos) /*!< 0x10000000 */
#define HSEM_C1ISR_ISF28 HSEM_C1ISR_ISF28_Msk /*!<semaphore 28 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF29_Pos (29U)
#define HSEM_C1ISR_ISF29_Msk (0x1UL << HSEM_C1ISR_ISF29_Pos) /*!< 0x20000000 */
#define HSEM_C1ISR_ISF29 HSEM_C1ISR_ISF29_Msk /*!<semaphore 29 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF30_Pos (30U)
#define HSEM_C1ISR_ISF30_Msk (0x1UL << HSEM_C1ISR_ISF30_Pos) /*!< 0x40000000 */
#define HSEM_C1ISR_ISF30 HSEM_C1ISR_ISF30_Msk /*!<semaphore 30 interrupt 0 status bit. */
#define HSEM_C1ISR_ISF31_Pos (31U)
#define HSEM_C1ISR_ISF31_Msk (0x1UL << HSEM_C1ISR_ISF31_Pos) /*!< 0x80000000 */
#define HSEM_C1ISR_ISF31 HSEM_C1ISR_ISF31_Msk /*!<semaphore 31 interrupt 0 status bit. */
/******************** Bit definition for HSEM_C1MISR register *****************/
#define HSEM_C1MISR_MISF0_Pos (0U)
#define HSEM_C1MISR_MISF0_Msk (0x1UL << HSEM_C1MISR_MISF0_Pos) /*!< 0x00000001 */
#define HSEM_C1MISR_MISF0 HSEM_C1MISR_MISF0_Msk /*!<semaphore 0 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF1_Pos (1U)
#define HSEM_C1MISR_MISF1_Msk (0x1UL << HSEM_C1MISR_MISF1_Pos) /*!< 0x00000002 */
#define HSEM_C1MISR_MISF1 HSEM_C1MISR_MISF1_Msk /*!<semaphore 1 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF2_Pos (2U)
#define HSEM_C1MISR_MISF2_Msk (0x1UL << HSEM_C1MISR_MISF2_Pos) /*!< 0x00000004 */
#define HSEM_C1MISR_MISF2 HSEM_C1MISR_MISF2_Msk /*!<semaphore 2 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF3_Pos (3U)
#define HSEM_C1MISR_MISF3_Msk (0x1UL << HSEM_C1MISR_MISF3_Pos) /*!< 0x00000008 */
#define HSEM_C1MISR_MISF3 HSEM_C1MISR_MISF3_Msk /*!<semaphore 3 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF4_Pos (4U)
#define HSEM_C1MISR_MISF4_Msk (0x1UL << HSEM_C1MISR_MISF4_Pos) /*!< 0x00000010 */
#define HSEM_C1MISR_MISF4 HSEM_C1MISR_MISF4_Msk /*!<semaphore 4 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF5_Pos (5U)
#define HSEM_C1MISR_MISF5_Msk (0x1UL << HSEM_C1MISR_MISF5_Pos) /*!< 0x00000020 */
#define HSEM_C1MISR_MISF5 HSEM_C1MISR_MISF5_Msk /*!<semaphore 5 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF6_Pos (6U)
#define HSEM_C1MISR_MISF6_Msk (0x1UL << HSEM_C1MISR_MISF6_Pos) /*!< 0x00000040 */
#define HSEM_C1MISR_MISF6 HSEM_C1MISR_MISF6_Msk /*!<semaphore 6 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF7_Pos (7U)
#define HSEM_C1MISR_MISF7_Msk (0x1UL << HSEM_C1MISR_MISF7_Pos) /*!< 0x00000080 */
#define HSEM_C1MISR_MISF7 HSEM_C1MISR_MISF7_Msk /*!<semaphore 7 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF8_Pos (8U)
#define HSEM_C1MISR_MISF8_Msk (0x1UL << HSEM_C1MISR_MISF8_Pos) /*!< 0x00000100 */
#define HSEM_C1MISR_MISF8 HSEM_C1MISR_MISF8_Msk /*!<semaphore 8 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF9_Pos (9U)
#define HSEM_C1MISR_MISF9_Msk (0x1UL << HSEM_C1MISR_MISF9_Pos) /*!< 0x00000200 */
#define HSEM_C1MISR_MISF9 HSEM_C1MISR_MISF9_Msk /*!<semaphore 9 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF10_Pos (10U)
#define HSEM_C1MISR_MISF10_Msk (0x1UL << HSEM_C1MISR_MISF10_Pos) /*!< 0x00000400 */
#define HSEM_C1MISR_MISF10 HSEM_C1MISR_MISF10_Msk /*!<semaphore 10 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF11_Pos (11U)
#define HSEM_C1MISR_MISF11_Msk (0x1UL << HSEM_C1MISR_MISF11_Pos) /*!< 0x00000800 */
#define HSEM_C1MISR_MISF11 HSEM_C1MISR_MISF11_Msk /*!<semaphore 11 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF12_Pos (12U)
#define HSEM_C1MISR_MISF12_Msk (0x1UL << HSEM_C1MISR_MISF12_Pos) /*!< 0x00001000 */
#define HSEM_C1MISR_MISF12 HSEM_C1MISR_MISF12_Msk /*!<semaphore 12 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF13_Pos (13U)
#define HSEM_C1MISR_MISF13_Msk (0x1UL << HSEM_C1MISR_MISF13_Pos) /*!< 0x00002000 */
#define HSEM_C1MISR_MISF13 HSEM_C1MISR_MISF13_Msk /*!<semaphore 13 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF14_Pos (14U)
#define HSEM_C1MISR_MISF14_Msk (0x1UL << HSEM_C1MISR_MISF14_Pos) /*!< 0x00004000 */
#define HSEM_C1MISR_MISF14 HSEM_C1MISR_MISF14_Msk /*!<semaphore 14 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF15_Pos (15U)
#define HSEM_C1MISR_MISF15_Msk (0x1UL << HSEM_C1MISR_MISF15_Pos) /*!< 0x00008000 */
#define HSEM_C1MISR_MISF15 HSEM_C1MISR_MISF15_Msk /*!<semaphore 15 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF16_Pos (16U)
#define HSEM_C1MISR_MISF16_Msk (0x1UL << HSEM_C1MISR_MISF16_Pos) /*!< 0x00010000 */
#define HSEM_C1MISR_MISF16 HSEM_C1MISR_MISF16_Msk /*!<semaphore 16 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF17_Pos (17U)
#define HSEM_C1MISR_MISF17_Msk (0x1UL << HSEM_C1MISR_MISF17_Pos) /*!< 0x00020000 */
#define HSEM_C1MISR_MISF17 HSEM_C1MISR_MISF17_Msk /*!<semaphore 17 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF18_Pos (18U)
#define HSEM_C1MISR_MISF18_Msk (0x1UL << HSEM_C1MISR_MISF18_Pos) /*!< 0x00040000 */
#define HSEM_C1MISR_MISF18 HSEM_C1MISR_MISF18_Msk /*!<semaphore 18 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF19_Pos (19U)
#define HSEM_C1MISR_MISF19_Msk (0x1UL << HSEM_C1MISR_MISF19_Pos) /*!< 0x00080000 */
#define HSEM_C1MISR_MISF19 HSEM_C1MISR_MISF19_Msk /*!<semaphore 19 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF20_Pos (20U)
#define HSEM_C1MISR_MISF20_Msk (0x1UL << HSEM_C1MISR_MISF20_Pos) /*!< 0x00100000 */
#define HSEM_C1MISR_MISF20 HSEM_C1MISR_MISF20_Msk /*!<semaphore 20 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF21_Pos (21U)
#define HSEM_C1MISR_MISF21_Msk (0x1UL << HSEM_C1MISR_MISF21_Pos) /*!< 0x00200000 */
#define HSEM_C1MISR_MISF21 HSEM_C1MISR_MISF21_Msk /*!<semaphore 21 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF22_Pos (22U)
#define HSEM_C1MISR_MISF22_Msk (0x1UL << HSEM_C1MISR_MISF22_Pos) /*!< 0x00400000 */
#define HSEM_C1MISR_MISF22 HSEM_C1MISR_MISF22_Msk /*!<semaphore 22 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF23_Pos (23U)
#define HSEM_C1MISR_MISF23_Msk (0x1UL << HSEM_C1MISR_MISF23_Pos) /*!< 0x00800000 */
#define HSEM_C1MISR_MISF23 HSEM_C1MISR_MISF23_Msk /*!<semaphore 23 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF24_Pos (24U)
#define HSEM_C1MISR_MISF24_Msk (0x1UL << HSEM_C1MISR_MISF24_Pos) /*!< 0x01000000 */
#define HSEM_C1MISR_MISF24 HSEM_C1MISR_MISF24_Msk /*!<semaphore 24 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF25_Pos (25U)
#define HSEM_C1MISR_MISF25_Msk (0x1UL << HSEM_C1MISR_MISF25_Pos) /*!< 0x02000000 */
#define HSEM_C1MISR_MISF25 HSEM_C1MISR_MISF25_Msk /*!<semaphore 25 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF26_Pos (26U)
#define HSEM_C1MISR_MISF26_Msk (0x1UL << HSEM_C1MISR_MISF26_Pos) /*!< 0x04000000 */
#define HSEM_C1MISR_MISF26 HSEM_C1MISR_MISF26_Msk /*!<semaphore 26 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF27_Pos (27U)
#define HSEM_C1MISR_MISF27_Msk (0x1UL << HSEM_C1MISR_MISF27_Pos) /*!< 0x08000000 */
#define HSEM_C1MISR_MISF27 HSEM_C1MISR_MISF27_Msk /*!<semaphore 27 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF28_Pos (28U)
#define HSEM_C1MISR_MISF28_Msk (0x1UL << HSEM_C1MISR_MISF28_Pos) /*!< 0x10000000 */
#define HSEM_C1MISR_MISF28 HSEM_C1MISR_MISF28_Msk /*!<semaphore 28 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF29_Pos (29U)
#define HSEM_C1MISR_MISF29_Msk (0x1UL << HSEM_C1MISR_MISF29_Pos) /*!< 0x20000000 */
#define HSEM_C1MISR_MISF29 HSEM_C1MISR_MISF29_Msk /*!<semaphore 29 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF30_Pos (30U)
#define HSEM_C1MISR_MISF30_Msk (0x1UL << HSEM_C1MISR_MISF30_Pos) /*!< 0x40000000 */
#define HSEM_C1MISR_MISF30 HSEM_C1MISR_MISF30_Msk /*!<semaphore 30 interrupt 0 masked status bit. */
#define HSEM_C1MISR_MISF31_Pos (31U)
#define HSEM_C1MISR_MISF31_Msk (0x1UL << HSEM_C1MISR_MISF31_Pos) /*!< 0x80000000 */
#define HSEM_C1MISR_MISF31 HSEM_C1MISR_MISF31_Msk /*!<semaphore 31 interrupt 0 masked status bit. */
/******************** Bit definition for HSEM_CR register *****************/
#define HSEM_CR_COREID_Pos (8U)
#define HSEM_CR_COREID_Msk (0xFFUL << HSEM_CR_COREID_Pos) /*!< 0x0000FF00 */
#define HSEM_CR_COREID HSEM_CR_COREID_Msk /*!<CoreID of semaphores to be cleared. */
#define HSEM_CR_KEY_Pos (16U)
#define HSEM_CR_KEY_Msk (0xFFFFUL << HSEM_CR_KEY_Pos) /*!< 0xFFFF0000 */
#define HSEM_CR_KEY HSEM_CR_KEY_Msk /*!<semaphores clear key. */
/******************** Bit definition for HSEM_KEYR register *****************/
#define HSEM_KEYR_KEY_Pos (16U)
#define HSEM_KEYR_KEY_Msk (0xFFFFUL << HSEM_KEYR_KEY_Pos) /*!< 0xFFFF0000 */
#define HSEM_KEYR_KEY HSEM_KEYR_KEY_Msk /*!<semaphores clear key. */
/********************** Bit definition for HSEM_HWCFGR2 register ***************/
#define HSEM_HWCFGR2_MASTERID1_Pos (0U)
#define HSEM_HWCFGR2_MASTERID1_Msk (0xFU << HSEM_HWCFGR2_MASTERID1_Pos) /*!< 0x0000000F */
#define HSEM_HWCFGR2_MASTERID1 HSEM_HWCFGR2_MASTERID1_Msk /*!< HW Config valid bus masters ID1 */
#define HSEM_HWCFGR2_MASTERID2_Pos (4U)
#define HSEM_HWCFGR2_MASTERID2_Msk (0xFU << HSEM_HWCFGR2_MASTERID2_Pos) /*!< 0x000000F0 */
#define HSEM_HWCFGR2_MASTERID2 HSEM_HWCFGR2_MASTERID2_Msk /*!< HW Config valid bus masters ID2 */
#define HSEM_HWCFGR2_MASTERID3_Pos (8U)
#define HSEM_HWCFGR2_MASTERID3_Msk (0xFU << HSEM_HWCFGR2_MASTERID3_Pos) /*!< 0x00000F00 */
#define HSEM_HWCFGR2_MASTERID3 HSEM_HWCFGR2_MASTERID3_Msk /*!< HW Config valid bus masters ID3 */
#define HSEM_HWCFGR2_MASTERID4_Pos (12U)
#define HSEM_HWCFGR2_MASTERID4_Msk (0xFU << HSEM_HWCFGR2_MASTERID4_Pos) /*!< 0x0000F000 */
#define HSEM_HWCFGR2_MASTERID4 HSEM_HWCFGR2_MASTERID4_Msk /*!< HW Config valid bus masters ID4 */
/********************** Bit definition for HSEM_HWCFGR1 register ***************/
#define HSEM_HWCFGR1_NBSEM_Pos (0U)
#define HSEM_HWCFGR1_NBSEM_Msk (0xFFU << HSEM_HWCFGR1_NBSEM_Pos) /*!< 0x000000FF */
#define HSEM_HWCFGR1_NBSEM HSEM_HWCFGR1_NBSEM_Msk /*!< HW Config number of semaphores */
#define HSEM_HWCFGR1_NBINT_Pos (8U)
#define HSEM_HWCFGR1_NBINT_Msk (0xFU << HSEM_HWCFGR1_NBINT_Pos) /*!< 0x00000F00 */
#define HSEM_HWCFGR1_NBINT HSEM_HWCFGR1_NBINT_Msk /*!< HW Config number of interrupts/ supported number of master IDs */
/********************** Bit definition for HSEM_VERR register *****************/
#define HSEM_VERR_MINREV_Pos (0U)
#define HSEM_VERR_MINREV_Msk (0xFU << HSEM_VERR_MINREV_Pos) /*!< 0x0000000F */
#define HSEM_VERR_MINREV HSEM_VERR_MINREV_Msk /*!< Minor Revision number */
#define HSEM_VERR_MAJREV_Pos (4U)
#define HSEM_VERR_MAJREV_Msk (0xFU << HSEM_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define HSEM_VERR_MAJREV HSEM_VERR_MAJREV_Msk /*!< Major Revision number */
/********************** Bit definition for HSEM_IPIDR register ****************/
#define HSEM_IPIDR_IPID_Pos (0U)
#define HSEM_IPIDR_IPID_Msk (0xFFFFFFFFU << HSEM_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
#define HSEM_IPIDR_IPID HSEM_IPIDR_IPID_Msk /*!< IP Identification */
/********************** Bit definition for HSEM_SIDR register *****************/
#define HSEM_SIDR_SID_Pos (0U)
#define HSEM_SIDR_SID_Msk (0xFFFFFFFFU << HSEM_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define HSEM_SIDR_SID HSEM_SIDR_SID_Msk /*!< IP size identification */
/******************************************************************************/
/* */
/* HASH */
/* */
/******************************************************************************/
/****************** Bits definition for HASH_CR register ********************/
#define HASH_CR_INIT_Pos (2U)
#define HASH_CR_INIT_Msk (0x1U << HASH_CR_INIT_Pos) /*!< 0x00000004 */
#define HASH_CR_INIT HASH_CR_INIT_Msk
#define HASH_CR_DMAE_Pos (3U)
#define HASH_CR_DMAE_Msk (0x1U << HASH_CR_DMAE_Pos) /*!< 0x00000008 */
#define HASH_CR_DMAE HASH_CR_DMAE_Msk
#define HASH_CR_DATATYPE_Pos (4U)
#define HASH_CR_DATATYPE_Msk (0x3U << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */
#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk
#define HASH_CR_DATATYPE_0 (0x1U << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */
#define HASH_CR_DATATYPE_1 (0x2U << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */
#define HASH_CR_MODE_Pos (6U)
#define HASH_CR_MODE_Msk (0x1U << HASH_CR_MODE_Pos) /*!< 0x00000040 */
#define HASH_CR_MODE HASH_CR_MODE_Msk
#define HASH_CR_ALGO_Pos (7U)
#define HASH_CR_ALGO_Msk (0x801U << HASH_CR_ALGO_Pos) /*!< 0x00040080 */
#define HASH_CR_ALGO HASH_CR_ALGO_Msk
#define HASH_CR_ALGO_0 (0x001U << HASH_CR_ALGO_Pos) /*!< 0x00000080 */
#define HASH_CR_ALGO_1 (0x800U << HASH_CR_ALGO_Pos) /*!< 0x00040000 */
#define HASH_CR_NBW_Pos (8U)
#define HASH_CR_NBW_Msk (0xFU << HASH_CR_NBW_Pos) /*!< 0x00000F00 */
#define HASH_CR_NBW HASH_CR_NBW_Msk
#define HASH_CR_NBW_0 (0x1U << HASH_CR_NBW_Pos) /*!< 0x00000100 */
#define HASH_CR_NBW_1 (0x2U << HASH_CR_NBW_Pos) /*!< 0x00000200 */
#define HASH_CR_NBW_2 (0x4U << HASH_CR_NBW_Pos) /*!< 0x00000400 */
#define HASH_CR_NBW_3 (0x8U << HASH_CR_NBW_Pos) /*!< 0x00000800 */
#define HASH_CR_DINNE_Pos (12U)
#define HASH_CR_DINNE_Msk (0x1U << HASH_CR_DINNE_Pos) /*!< 0x00001000 */
#define HASH_CR_DINNE HASH_CR_DINNE_Msk
#define HASH_CR_MDMAT_Pos (13U)
#define HASH_CR_MDMAT_Msk (0x1U << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */
#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk
#define HASH_CR_DMAA_Pos (14U)
#define HASH_CR_DMAA_Msk (0x1U << HASH_CR_DMAA_Pos) /*!< 0x00004000 */
#define HASH_CR_DMAA HASH_CR_DMAA_Msk
#define HASH_CR_LKEY_Pos (16U)
#define HASH_CR_LKEY_Msk (0x1U << HASH_CR_LKEY_Pos) /*!< 0x00010000 */
#define HASH_CR_LKEY HASH_CR_LKEY_Msk
/****************** Bits definition for HASH_STR register *******************/
#define HASH_STR_NBLW_Pos (0U)
#define HASH_STR_NBLW_Msk (0x1FU << HASH_STR_NBLW_Pos) /*!< 0x0000001F */
#define HASH_STR_NBLW HASH_STR_NBLW_Msk
#define HASH_STR_NBLW_0 (0x01U << HASH_STR_NBLW_Pos) /*!< 0x00000001 */
#define HASH_STR_NBLW_1 (0x02U << HASH_STR_NBLW_Pos) /*!< 0x00000002 */
#define HASH_STR_NBLW_2 (0x04U << HASH_STR_NBLW_Pos) /*!< 0x00000004 */
#define HASH_STR_NBLW_3 (0x08U << HASH_STR_NBLW_Pos) /*!< 0x00000008 */
#define HASH_STR_NBLW_4 (0x10U << HASH_STR_NBLW_Pos) /*!< 0x00000010 */
#define HASH_STR_DCAL_Pos (8U)
#define HASH_STR_DCAL_Msk (0x1U << HASH_STR_DCAL_Pos) /*!< 0x00000100 */
#define HASH_STR_DCAL HASH_STR_DCAL_Msk
/****************** Bits definition for HASH_IMR register *******************/
#define HASH_IMR_DINIE_Pos (0U)
#define HASH_IMR_DINIE_Msk (0x1U << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */
#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk
#define HASH_IMR_DCIE_Pos (1U)
#define HASH_IMR_DCIE_Msk (0x1U << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */
#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk
/****************** Bits definition for HASH_SR register ********************/
#define HASH_SR_DINIS_Pos (0U)
#define HASH_SR_DINIS_Msk (0x1U << HASH_SR_DINIS_Pos) /*!< 0x00000001 */
#define HASH_SR_DINIS HASH_SR_DINIS_Msk
#define HASH_SR_DCIS_Pos (1U)
#define HASH_SR_DCIS_Msk (0x1U << HASH_SR_DCIS_Pos) /*!< 0x00000002 */
#define HASH_SR_DCIS HASH_SR_DCIS_Msk
#define HASH_SR_DMAS_Pos (2U)
#define HASH_SR_DMAS_Msk (0x1U << HASH_SR_DMAS_Pos) /*!< 0x00000004 */
#define HASH_SR_DMAS HASH_SR_DMAS_Msk
#define HASH_SR_BUSY_Pos (3U)
#define HASH_SR_BUSY_Msk (0x1U << HASH_SR_BUSY_Pos) /*!< 0x00000008 */
#define HASH_SR_BUSY HASH_SR_BUSY_Msk
/********************** Bit definition for HASH_HWCFGR register ***************/
#define HASH_HWCFGR_CFG1_Pos (0U)
#define HASH_HWCFGR_CFG1_Msk (0xFU << HASH_HWCFGR_CFG1_Pos) /*!< 0x0000000F */
#define HASH_HWCFGR_CFG1 HASH_HWCFGR_CFG1_Msk /*!< use_mdma generic value (0x1) */
/********************** Bit definition for HASH_VERR register *****************/
#define HASH_VERR_VER_Pos (0U)
#define HASH_VERR_VER_Msk (0xFFU << HASH_VERR_VER_Pos) /*!< 0x0000000FF */
#define HASH_VERR_VER HASH_VERR_VER_Msk /*!< Revision number */
/********************** Bit definition for HASH_IPIDR register ****************/
#define HASH_IPIDR_IPID_Pos (0U)
#define HASH_IPIDR_IPID_Msk (0xFFFFFFFFU << HASH_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
#define HASH_IPIDR_IPID HASH_IPIDR_IPID_Msk /*!< IP Identification */
/********************** Bit definition for HASH_SIDR register *****************/
#define HASH_MID_MID_Pos (0U)
#define HASH_MID_MID_Msk (0xFFFFFFFFU << HASH_MID_MID_Pos) /*!< 0xFFFFFFFF */
#define HASH_MID_MID HASH_MID_MID_Msk /*!< Magic identification */
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface (I2C) */
/* */
/******************************************************************************/
/******************* Bit definition for I2C_CR1 register *******************/
#define I2C_CR1_PE_Pos (0U)
#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
#define I2C_CR1_TXIE_Pos (1U)
#define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
#define I2C_CR1_RXIE_Pos (2U)
#define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
#define I2C_CR1_ADDRIE_Pos (3U)
#define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
#define I2C_CR1_NACKIE_Pos (4U)
#define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
#define I2C_CR1_STOPIE_Pos (5U)
#define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE_Pos (6U)
#define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE_Pos (7U)
#define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
#define I2C_CR1_DNF_Pos (8U)
#define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
#define I2C_CR1_ANFOFF_Pos (12U)
#define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST_Pos (13U)
#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
#define I2C_CR1_TXDMAEN_Pos (14U)
#define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
#define I2C_CR1_RXDMAEN_Pos (15U)
#define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
#define I2C_CR1_SBC_Pos (16U)
#define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
#define I2C_CR1_NOSTRETCH_Pos (17U)
#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
#define I2C_CR1_WUPEN_Pos (18U)
#define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
#define I2C_CR1_GCEN_Pos (19U)
#define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
#define I2C_CR1_SMBHEN_Pos (20U)
#define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
#define I2C_CR1_SMBDEN_Pos (21U)
#define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
#define I2C_CR1_ALERTEN_Pos (22U)
#define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
#define I2C_CR1_PECEN_Pos (23U)
#define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
/****************** Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_SADD_Pos (0U)
#define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN_Pos (10U)
#define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
#define I2C_CR2_ADD10_Pos (11U)
#define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
#define I2C_CR2_HEAD10R_Pos (12U)
#define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
#define I2C_CR2_START_Pos (13U)
#define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
#define I2C_CR2_STOP_Pos (14U)
#define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
#define I2C_CR2_NACK_Pos (15U)
#define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
#define I2C_CR2_NBYTES_Pos (16U)
#define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
#define I2C_CR2_RELOAD_Pos (24U)
#define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
#define I2C_CR2_AUTOEND_Pos (25U)
#define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
#define I2C_CR2_PECBYTE_Pos (26U)
#define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
/******************* Bit definition for I2C_OAR1 register ******************/
#define I2C_OAR1_OA1_Pos (0U)
#define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
#define I2C_OAR1_OA1MODE_Pos (10U)
#define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
#define I2C_OAR1_OA1EN_Pos (15U)
#define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register ******************/
#define I2C_OAR2_OA2_Pos (1U)
#define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
#define I2C_OAR2_OA2MSK_Pos (8U)
#define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
#define I2C_OAR2_OA2NOMASK 0x00000000UL /*!< No mask */
#define I2C_OAR2_OA2MASK01_Pos (8U)
#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
#define I2C_OAR2_OA2MASK02_Pos (9U)
#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
#define I2C_OAR2_OA2MASK03_Pos (8U)
#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
#define I2C_OAR2_OA2MASK04_Pos (10U)
#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
#define I2C_OAR2_OA2MASK05_Pos (8U)
#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
#define I2C_OAR2_OA2MASK06_Pos (9U)
#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
#define I2C_OAR2_OA2MASK07_Pos (8U)
#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
#define I2C_OAR2_OA2EN_Pos (15U)
#define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register *******************/
#define I2C_TIMINGR_SCLL_Pos (0U)
#define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
#define I2C_TIMINGR_SCLH_Pos (8U)
#define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
#define I2C_TIMINGR_SDADEL_Pos (16U)
#define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
#define I2C_TIMINGR_SCLDEL_Pos (20U)
#define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
#define I2C_TIMINGR_PRESC_Pos (28U)
#define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
/******************* Bit definition for I2C_TIMEOUTR register *******************/
#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
#define I2C_TIMEOUTR_TIDLE_Pos (12U)
#define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
#define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
/****************** Bit definition for I2C_ISR register *********************/
#define I2C_ISR_TXE_Pos (0U)
#define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
#define I2C_ISR_TXIS_Pos (1U)
#define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
#define I2C_ISR_RXNE_Pos (2U)
#define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
#define I2C_ISR_ADDR_Pos (3U)
#define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
#define I2C_ISR_NACKF_Pos (4U)
#define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
#define I2C_ISR_STOPF_Pos (5U)
#define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
#define I2C_ISR_TC_Pos (6U)
#define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
#define I2C_ISR_TCR_Pos (7U)
#define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
#define I2C_ISR_BERR_Pos (8U)
#define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
#define I2C_ISR_ARLO_Pos (9U)
#define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
#define I2C_ISR_OVR_Pos (10U)
#define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
#define I2C_ISR_PECERR_Pos (11U)
#define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
#define I2C_ISR_TIMEOUT_Pos (12U)
#define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
#define I2C_ISR_ALERT_Pos (13U)
#define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
#define I2C_ISR_BUSY_Pos (15U)
#define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
#define I2C_ISR_DIR_Pos (16U)
#define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
#define I2C_ISR_ADDCODE_Pos (17U)
#define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
/****************** Bit definition for I2C_ICR register *********************/
#define I2C_ICR_ADDRCF_Pos (3U)
#define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
#define I2C_ICR_NACKCF_Pos (4U)
#define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
#define I2C_ICR_STOPCF_Pos (5U)
#define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
#define I2C_ICR_BERRCF_Pos (8U)
#define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
#define I2C_ICR_ARLOCF_Pos (9U)
#define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
#define I2C_ICR_OVRCF_Pos (10U)
#define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
#define I2C_ICR_PECCF_Pos (11U)
#define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
#define I2C_ICR_TIMOUTCF_Pos (12U)
#define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
#define I2C_ICR_ALERTCF_Pos (13U)
#define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
/****************** Bit definition for I2C_PECR register *********************/
#define I2C_PECR_PEC_Pos (0U)
#define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
/****************** Bit definition for I2C_RXDR register *********************/
#define I2C_RXDR_RXDATA_Pos (0U)
#define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
/****************** Bit definition for I2C_TXDR register *********************/
#define I2C_TXDR_TXDATA_Pos (0U)
#define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
/********************** Bit definition for I2C_HWCFGR register ***************/
#define I2C_HWCFGR_SMBUS_Pos (0U)
#define I2C_HWCFGR_SMBUS_Msk (0xFU << I2C_HWCFGR_SMBUS_Pos) /*!< 0x0000000F */
#define I2C_HWCFGR_SMBUS I2C_HWCFGR_SMBUS_Msk /*!< SMBus mode */
#define I2C_HWCFGR_ASYN_Pos (4U)
#define I2C_HWCFGR_ASYN_Msk (0xFU << I2C_HWCFGR_ASYN_Pos) /*!< 0x000000F0 */
#define I2C_HWCFGR_ASYN I2C_HWCFGR_ASYN_Msk /*!< Independent kernel clock */
#define I2C_HWCFGR_WKP_Pos (8U)
#define I2C_HWCFGR_WKP_Msk (0xFU << I2C_HWCFGR_WKP_Pos) /*!< 0x00000F00 */
#define I2C_HWCFGR_WKP I2C_HWCFGR_WKP_Msk /*!< Wakeup from Stop mode */
/******************** Bit definition for I2C_VERR register***********************/
#define I2C_VERR_MINREV_Pos (0U)
#define I2C_VERR_MINREV_Msk (0xFU << I2C_VERR_MINREV_Pos) /*!< 0x0000000F */
#define I2C_VERR_MINREV I2C_VERR_MINREV_Msk /*Minor Revision of the IP*/
#define I2C_VERR_MAJREV_Pos (4U)
#define I2C_VERR_MAJREV_Msk (0xFU << I2C_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define I2C_VERR_MAJREV I2C_VERR_MAJREV_Msk /*Major Revision of the IP*/
/******************** Bit definition for I2C_IPIDR register**********************/
#define I2C_IPIDR_ID_Pos (0U)
#define I2C_IPIDR_ID_Msk (0xFFFFFFFFU << I2C_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
#define I2C_IPIDR_ID I2C_IPIDR_ID_Msk /*IP Identifier*/
/******************** Bit definition for I2C_SIDR register**********************/
#define I2C_SIDR_SID_Pos (0U)
#define I2C_SIDR_SID_Msk (0xFFFFFFFFU << I2C_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define I2C_SIDR_SID I2C_SIDR_SID_Msk /*Size Identifier*/
/******************************************************************************/
/* */
/* Independent WATCHDOG (IWDG) */
/* */
/******************************************************************************/
/******************* Bit definition for IWDG_KR register ********************/
#define IWDG_KR_KEY_Pos (0U)
#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
/******************* Bit definition for IWDG_PR register ********************/
#define IWDG_PR_PR_Pos (0U)
#define IWDG_PR_PR_Msk (0xFU << IWDG_PR_PR_Pos) /*!< 0x00000007 */
#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
#define IWDG_PR_PR_3 (0x8U << IWDG_PR_PR_Pos) /*!< 0x00000008 */
/******************* Bit definition for IWDG_RLR register *******************/
#define IWDG_RLR_RL_Pos (0U)
#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
/******************* Bit definition for IWDG_SR register ********************/
#define IWDG_SR_PVU_Pos (0U)
#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
#define IWDG_SR_RVU_Pos (1U)
#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
#define IWDG_SR_WVU_Pos (2U)
#define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
#define IWDG_SR_EWU_Pos (3U)
#define IWDG_SR_EWU_Msk (0x1U << IWDG_SR_EWU_Pos) /*!< 0x00000008 */
#define IWDG_SR_EWU IWDG_SR_EWU_Msk /*!< Watchdog interrupt comparator value update */
#define IWDG_SR_EWIF_Pos (14U)
#define IWDG_SR_EWIF_Msk (0x1U << IWDG_SR_EWIF_Pos) /*!< 0x00004000 */
#define IWDG_SR_EWIF IWDG_SR_EWIF_Msk /*!< Watchdog early interrupt flag */
/******************* Bit definition for IWDG_KR register ********************/
#define IWDG_WINR_WIN_Pos (0U)
#define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
/******************* Bit definition for IWDG_EWCR register ********************/
#define IWDG_EWCR_EWIT_Pos (0U)
#define IWDG_EWCR_EWIT_Msk (0xFFFU << IWDG_EWCR_EWIT_Pos) /*!< 0x00000FFF */
#define IWDG_EWCR_EWIT IWDG_EWCR_EWIT_Msk /*!< Watchdog early wakeup comparator value */
#define IWDG_EWCR_EWIC_Pos (14U)
#define IWDG_EWCR_EWIC_Msk (0x1U << IWDG_EWCR_EWIC_Pos) /*!< 0x00004000 */
#define IWDG_EWCR_EWIC IWDG_EWCR_EWIC_Msk /*!< Watchdog early interrupt acknowledge */
#define IWDG_EWCR_EWIE_Pos (15U)
#define IWDG_EWCR_EWIE_Msk (0x1U << IWDG_EWCR_EWIE_Pos) /*!< 0x00008000 */
#define IWDG_EWCR_EWIE IWDG_EWCR_EWIE_Msk /*!< Watchdog early interrupt enable */
/********************** Bit definition for IWDG_HWCFGR register ***************/
#define IWDG_HWCFGR_WINDOW_Pos (0U)
#define IWDG_HWCFGR_WINDOW_Msk (0xFU << IWDG_HWCFGR_WINDOW_Pos) /*!< 0x0000000F */
#define IWDG_HWCFGR_WINDOW IWDG_HWCFGR_WINDOW_Msk /*!< Support of Window function */
#define IWDG_HWCFGR_PR_DEFAULT_Pos (4U)
#define IWDG_HWCFGR_PR_DEFAULT_Msk (0xFU << IWDG_HWCFGR_PR_DEFAULT_Pos) /*!< 0x000000F0 */
#define IWDG_HWCFGR_PR_DEFAULT IWDG_HWCFGR_PR_DEFAULT_Msk /*!< Prescaler default value */
/********************** Bit definition for IWDG_VERR register *****************/
#define IWDG_VERR_MINREV_Pos (0U)
#define IWDG_VERR_MINREV_Msk (0xFU << IWDG_VERR_MINREV_Pos) /*!< 0x0000000F */
#define IWDG_VERR_MINREV IWDG_VERR_MINREV_Msk /*!< Minor Revision number */
#define IWDG_VERR_MAJREV_Pos (4U)
#define IWDG_VERR_MAJREV_Msk (0xFU << IWDG_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define IWDG_VERR_MAJREV IWDG_VERR_MAJREV_Msk /*!< Major Revision number */
/********************** Bit definition for IWDG_IDR register ****************/
#define IWDG_IDR_IPID_Pos (0U)
#define IWDG_IDR_IPID_Msk (0xFFFFFFFFU << IWDG_IDR_IPID_Pos) /*!< 0xFFFFFFFF */
#define IWDG_IDR_IPID IWDG_IDR_IPID_Msk /*!< IP Identification */
/********************** Bit definition for IWDG_SIDR register *****************/
#define IWDG_SIDR_SID_Pos (0U)
#define IWDG_SIDR_SID_Msk (0xFFFFFFFFU << IWDG_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define IWDG_SIDR_SID IWDG_SIDR_SID_Msk /*!< IP size identification */
/******************************************************************************/
/* */
/* LCD-TFT Display Controller (LTDC) */
/* */
/******************************************************************************/
/******************** Bit definition for LTDC_SSCR register *****************/
#define LTDC_SSCR_VSH_Pos (0U)
#define LTDC_SSCR_VSH_Msk (0x7FFU << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
#define LTDC_SSCR_HSW_Pos (16U)
#define LTDC_SSCR_HSW_Msk (0xFFFU << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
/******************** Bit definition for LTDC_BPCR register *****************/
#define LTDC_BPCR_AVBP_Pos (0U)
#define LTDC_BPCR_AVBP_Msk (0x7FFU << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
#define LTDC_BPCR_AHBP_Pos (16U)
#define LTDC_BPCR_AHBP_Msk (0xFFFU << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
/******************** Bit definition for LTDC_AWCR register *****************/
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFU << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFU << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
/******************** Bit definition for LTDC_TWCR register *****************/
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFU << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFU << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
/******************** Bit definition for LTDC_GCR register ******************/
#define LTDC_GCR_LTDCEN_Pos (0U)
#define LTDC_GCR_LTDCEN_Msk (0x1U << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
#define LTDC_GCR_DBW_Pos (4U)
#define LTDC_GCR_DBW_Msk (0x7U << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
#define LTDC_GCR_DGW_Pos (8U)
#define LTDC_GCR_DGW_Msk (0x7U << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
#define LTDC_GCR_DRW_Pos (12U)
#define LTDC_GCR_DRW_Msk (0x7U << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
#define LTDC_GCR_DEN_Pos (16U)
#define LTDC_GCR_DEN_Msk (0x1U << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
#define LTDC_GCR_PCPOL_Pos (28U)
#define LTDC_GCR_PCPOL_Msk (0x1U << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
#define LTDC_GCR_DEPOL_Pos (29U)
#define LTDC_GCR_DEPOL_Msk (0x1U << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
#define LTDC_GCR_VSPOL_Pos (30U)
#define LTDC_GCR_VSPOL_Msk (0x1U << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
#define LTDC_GCR_HSPOL_Pos (31U)
#define LTDC_GCR_HSPOL_Msk (0x1U << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
/******************** Bit definition for LTDC_SRCR register *****************/
#define LTDC_SRCR_IMR_Pos (0U)
#define LTDC_SRCR_IMR_Msk (0x1U << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
#define LTDC_SRCR_VBR_Pos (1U)
#define LTDC_SRCR_VBR_Msk (0x1U << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
/******************** Bit definition for LTDC_BCCR register *****************/
#define LTDC_BCCR_BCBLUE_Pos (0U)
#define LTDC_BCCR_BCBLUE_Msk (0xFFU << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
#define LTDC_BCCR_BCGREEN_Pos (8U)
#define LTDC_BCCR_BCGREEN_Msk (0xFFU << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
#define LTDC_BCCR_BCRED_Pos (16U)
#define LTDC_BCCR_BCRED_Msk (0xFFU << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
/******************** Bit definition for LTDC_IER register ******************/
#define LTDC_IER_LIE_Pos (0U)
#define LTDC_IER_LIE_Msk (0x1U << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
#define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
#define LTDC_IER_FUIE_Pos (1U)
#define LTDC_IER_FUIE_Msk (0x1U << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
#define LTDC_IER_TERRIE_Pos (2U)
#define LTDC_IER_TERRIE_Msk (0x1U << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
#define LTDC_IER_RRIE_Pos (3U)
#define LTDC_IER_RRIE_Msk (0x1U << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
/******************** Bit definition for LTDC_ISR register ******************/
#define LTDC_ISR_LIF_Pos (0U)
#define LTDC_ISR_LIF_Msk (0x1U << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
#define LTDC_ISR_FUIF_Pos (1U)
#define LTDC_ISR_FUIF_Msk (0x1U << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
#define LTDC_ISR_TERRIF_Pos (2U)
#define LTDC_ISR_TERRIF_Msk (0x1U << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
#define LTDC_ISR_RRIF_Pos (3U)
#define LTDC_ISR_RRIF_Msk (0x1U << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
/******************** Bit definition for LTDC_ICR register ******************/
#define LTDC_ICR_CLIF_Pos (0U)
#define LTDC_ICR_CLIF_Msk (0x1U << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
#define LTDC_ICR_CFUIF_Pos (1U)
#define LTDC_ICR_CFUIF_Msk (0x1U << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
#define LTDC_ICR_CTERRIF_Pos (2U)
#define LTDC_ICR_CTERRIF_Msk (0x1U << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
#define LTDC_ICR_CRRIF_Pos (3U)
#define LTDC_ICR_CRRIF_Msk (0x1U << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
/******************** Bit definition for LTDC_LIPCR register ****************/
#define LTDC_LIPCR_LIPOS_Pos (0U)
#define LTDC_LIPCR_LIPOS_Msk (0x7FFU << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
/******************** Bit definition for LTDC_CPSR register *****************/
#define LTDC_CPSR_CYPOS_Pos (0U)
#define LTDC_CPSR_CYPOS_Msk (0xFFFFU << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
#define LTDC_CPSR_CXPOS_Pos (16U)
#define LTDC_CPSR_CXPOS_Msk (0xFFFFU << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
/******************** Bit definition for LTDC_CDSR register *****************/
#define LTDC_CDSR_VDES_Pos (0U)
#define LTDC_CDSR_VDES_Msk (0x1U << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
#define LTDC_CDSR_HDES_Pos (1U)
#define LTDC_CDSR_HDES_Msk (0x1U << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
#define LTDC_CDSR_VSYNCS_Pos (2U)
#define LTDC_CDSR_VSYNCS_Msk (0x1U << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
#define LTDC_CDSR_HSYNCS_Pos (3U)
#define LTDC_CDSR_HSYNCS_Msk (0x1U << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
/******************** Bit definition for LTDC_LxCR register *****************/
#define LTDC_LxCR_LEN_Pos (0U)
#define LTDC_LxCR_LEN_Msk (0x1U << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
#define LTDC_LxCR_COLKEN_Pos (1U)
#define LTDC_LxCR_COLKEN_Msk (0x1U << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
#define LTDC_LxCR_CLUTEN_Pos (4U)
#define LTDC_LxCR_CLUTEN_Msk (0x1U << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
/******************** Bit definition for LTDC_LxWHPCR register **************/
#define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
#define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFU << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */
#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
/******************** Bit definition for LTDC_LxWVPCR register **************/
#define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
#define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFU << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */
#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
/******************** Bit definition for LTDC_LxCKCR register ***************/
#define LTDC_LxCKCR_CKBLUE_Pos (0U)
#define LTDC_LxCKCR_CKBLUE_Msk (0xFFU << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
#define LTDC_LxCKCR_CKGREEN_Pos (8U)
#define LTDC_LxCKCR_CKGREEN_Msk (0xFFU << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
#define LTDC_LxCKCR_CKRED_Pos (16U)
#define LTDC_LxCKCR_CKRED_Msk (0xFFU << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
/******************** Bit definition for LTDC_LxPFCR register ***************/
#define LTDC_LxPFCR_PF_Pos (0U)
#define LTDC_LxPFCR_PF_Msk (0x7U << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
/******************** Bit definition for LTDC_LxCACR register ***************/
#define LTDC_LxCACR_CONSTA_Pos (0U)
#define LTDC_LxCACR_CONSTA_Msk (0xFFU << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
/******************** Bit definition for LTDC_LxDCCR register ***************/
#define LTDC_LxDCCR_DCBLUE_Pos (0U)
#define LTDC_LxDCCR_DCBLUE_Msk (0xFFU << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
#define LTDC_LxDCCR_DCGREEN_Pos (8U)
#define LTDC_LxDCCR_DCGREEN_Msk (0xFFU << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
#define LTDC_LxDCCR_DCRED_Pos (16U)
#define LTDC_LxDCCR_DCRED_Msk (0xFFU << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
#define LTDC_LxDCCR_DCALPHA_Pos (24U)
#define LTDC_LxDCCR_DCALPHA_Msk (0xFFU << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
/******************** Bit definition for LTDC_LxBFCR register ***************/
#define LTDC_LxBFCR_BF2_Pos (0U)
#define LTDC_LxBFCR_BF2_Msk (0x7U << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
#define LTDC_LxBFCR_BF1_Pos (8U)
#define LTDC_LxBFCR_BF1_Msk (0x7U << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
/******************** Bit definition for LTDC_LxCFBAR register **************/
#define LTDC_LxCFBAR_CFBADD_Pos (0U)
#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
/******************** Bit definition for LTDC_LxCFBLR register **************/
#define LTDC_LxCFBLR_CFBLL_Pos (0U)
#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
#define LTDC_LxCFBLR_CFBP_Pos (16U)
#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
/******************** Bit definition for LTDC_LxCFBLNR register *************/
#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
/******************** Bit definition for LTDC_LxCLUTWR register *************/
#define LTDC_LxCLUTWR_BLUE_Pos (0U)
#define LTDC_LxCLUTWR_BLUE_Msk (0xFFU << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
#define LTDC_LxCLUTWR_GREEN_Pos (8U)
#define LTDC_LxCLUTWR_GREEN_Msk (0xFFU << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
#define LTDC_LxCLUTWR_RED_Pos (16U)
#define LTDC_LxCLUTWR_RED_Msk (0xFFU << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
#define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
/******************************************************************************/
/* */
/* Inter-Processor Communication Controller (IPCC) */
/* */
/******************************************************************************/
/********************** Bit definition for IPCC_C1CR register ***************/
#define IPCC_C1CR_RXOIE_Pos (0U)
#define IPCC_C1CR_RXOIE_Msk (0x1U << IPCC_C1CR_RXOIE_Pos) /*!< 0x00000001 */
#define IPCC_C1CR_RXOIE IPCC_C1CR_RXOIE_Msk /*!< Processor M4 Receive channel occupied interrupt enable */
#define IPCC_C1CR_TXFIE_Pos (16U)
#define IPCC_C1CR_TXFIE_Msk (0x1U << IPCC_C1CR_TXFIE_Pos) /*!< 0x00010000 */
#define IPCC_C1CR_TXFIE IPCC_C1CR_TXFIE_Msk /*!< Processor M4 Transmit channel free interrupt enable */
/********************** Bit definition for IPCC_C1MR register **************/
#define IPCC_C1MR_CH1OM_Pos (0U)
#define IPCC_C1MR_CH1OM_Msk (0x1U << IPCC_C1MR_CH1OM_Pos) /*!< 0x00000001 */
#define IPCC_C1MR_CH1OM IPCC_C1MR_CH1OM_Msk /*!< M4 Channel1 occupied interrupt mask */
#define IPCC_C1MR_CH2OM_Pos (1U)
#define IPCC_C1MR_CH2OM_Msk (0x1U << IPCC_C1MR_CH2OM_Pos) /*!< 0x00000002 */
#define IPCC_C1MR_CH2OM IPCC_C1MR_CH2OM_Msk /*!< M4 Channel2 occupied interrupt mask */
#define IPCC_C1MR_CH3OM_Pos (2U)
#define IPCC_C1MR_CH3OM_Msk (0x1U << IPCC_C1MR_CH3OM_Pos) /*!< 0x00000004 */
#define IPCC_C1MR_CH3OM IPCC_C1MR_CH3OM_Msk /*!< M4 Channel3 occupied interrupt mask */
#define IPCC_C1MR_CH4OM_Pos (3U)
#define IPCC_C1MR_CH4OM_Msk (0x1U << IPCC_C1MR_CH4OM_Pos) /*!< 0x00000008 */
#define IPCC_C1MR_CH4OM IPCC_C1MR_CH4OM_Msk /*!< M4 Channel4 occupied interrupt mask */
#define IPCC_C1MR_CH5OM_Pos (4U)
#define IPCC_C1MR_CH5OM_Msk (0x1U << IPCC_C1MR_CH5OM_Pos) /*!< 0x00000010 */
#define IPCC_C1MR_CH5OM IPCC_C1MR_CH5OM_Msk /*!< M4 Channel5 occupied interrupt mask */
#define IPCC_C1MR_CH6OM_Pos (5U)
#define IPCC_C1MR_CH6OM_Msk (0x1U << IPCC_C1MR_CH6OM_Pos) /*!< 0x00000020 */
#define IPCC_C1MR_CH6OM IPCC_C1MR_CH6OM_Msk /*!< M4 Channel6 occupied interrupt mask */
#define IPCC_C1MR_CH1FM_Pos (16U)
#define IPCC_C1MR_CH1FM_Msk (0x1U << IPCC_C1MR_CH1FM_Pos) /*!< 0x00010000 */
#define IPCC_C1MR_CH1FM IPCC_C1MR_CH1FM_Msk /*!< M4 Transmit Channel1 free interrupt mask */
#define IPCC_C1MR_CH2FM_Pos (17U)
#define IPCC_C1MR_CH2FM_Msk (0x1U << IPCC_C1MR_CH2FM_Pos) /*!< 0x00020000 */
#define IPCC_C1MR_CH2FM IPCC_C1MR_CH2FM_Msk /*!< M4 Transmit Channel2 free interrupt mask */
#define IPCC_C1MR_CH3FM_Pos (18U)
#define IPCC_C1MR_CH3FM_Msk (0x1U << IPCC_C1MR_CH3FM_Pos) /*!< 0x00040000 */
#define IPCC_C1MR_CH3FM IPCC_C1MR_CH3FM_Msk /*!< M4 Transmit Channel3 free interrupt mask */
#define IPCC_C1MR_CH4FM_Pos (19U)
#define IPCC_C1MR_CH4FM_Msk (0x1U << IPCC_C1MR_CH4FM_Pos) /*!< 0x00080000 */
#define IPCC_C1MR_CH4FM IPCC_C1MR_CH4FM_Msk /*!< M4 Transmit Channel4 free interrupt mask */
#define IPCC_C1MR_CH5FM_Pos (20U)
#define IPCC_C1MR_CH5FM_Msk (0x1U << IPCC_C1MR_CH5FM_Pos) /*!< 0x00100000 */
#define IPCC_C1MR_CH5FM IPCC_C1MR_CH5FM_Msk /*!< M4 Transmit Channel5 free interrupt mask */
#define IPCC_C1MR_CH6FM_Pos (21U)
#define IPCC_C1MR_CH6FM_Msk (0x1U << IPCC_C1MR_CH6FM_Pos) /*!< 0x00200000 */
#define IPCC_C1MR_CH6FM IPCC_C1MR_CH6FM_Msk /*!< M4 Transmit Channel6 free interrupt mask */
/********************** Bit definition for IPCC_C1SCR register ***************/
#define IPCC_C1SCR_CH1C_Pos (0U)
#define IPCC_C1SCR_CH1C_Msk (0x1U << IPCC_C1SCR_CH1C_Pos) /*!< 0x00000001 */
#define IPCC_C1SCR_CH1C IPCC_C1SCR_CH1C_Msk /*!< M4 receive Channel1 status clear */
#define IPCC_C1SCR_CH2C_Pos (1U)
#define IPCC_C1SCR_CH2C_Msk (0x1U << IPCC_C1SCR_CH2C_Pos) /*!< 0x00000002 */
#define IPCC_C1SCR_CH2C IPCC_C1SCR_CH2C_Msk /*!< M4 receive Channel2 status clear */
#define IPCC_C1SCR_CH3C_Pos (2U)
#define IPCC_C1SCR_CH3C_Msk (0x1U << IPCC_C1SCR_CH3C_Pos) /*!< 0x00000004 */
#define IPCC_C1SCR_CH3C IPCC_C1SCR_CH3C_Msk /*!< M4 receive Channel3 status clear */
#define IPCC_C1SCR_CH4C_Pos (3U)
#define IPCC_C1SCR_CH4C_Msk (0x1U << IPCC_C1SCR_CH4C_Pos) /*!< 0x00000008 */
#define IPCC_C1SCR_CH4C IPCC_C1SCR_CH4C_Msk /*!< M4 receive Channel4 status clear */
#define IPCC_C1SCR_CH5C_Pos (4U)
#define IPCC_C1SCR_CH5C_Msk (0x1U << IPCC_C1SCR_CH5C_Pos) /*!< 0x00000010 */
#define IPCC_C1SCR_CH5C IPCC_C1SCR_CH5C_Msk /*!< M4 receive Channel5 status clear */
#define IPCC_C1SCR_CH6C_Pos (5U)
#define IPCC_C1SCR_CH6C_Msk (0x1U << IPCC_C1SCR_CH6C_Pos) /*!< 0x00000020 */
#define IPCC_C1SCR_CH6C IPCC_C1SCR_CH6C_Msk /*!< M4 receive Channel6 status clear */
#define IPCC_C1SCR_CH1S_Pos (16U)
#define IPCC_C1SCR_CH1S_Msk (0x1U << IPCC_C1SCR_CH1S_Pos) /*!< 0x00010000 */
#define IPCC_C1SCR_CH1S IPCC_C1SCR_CH1S_Msk /*!< M4 transmit Channel1 status set */
#define IPCC_C1SCR_CH2S_Pos (17U)
#define IPCC_C1SCR_CH2S_Msk (0x1U << IPCC_C1SCR_CH2S_Pos) /*!< 0x00020000 */
#define IPCC_C1SCR_CH2S IPCC_C1SCR_CH2S_Msk /*!< M4 transmit Channel2 status set */
#define IPCC_C1SCR_CH3S_Pos (18U)
#define IPCC_C1SCR_CH3S_Msk (0x1U << IPCC_C1SCR_CH3S_Pos) /*!< 0x00040000 */
#define IPCC_C1SCR_CH3S IPCC_C1SCR_CH3S_Msk /*!< M4 transmit Channel3 status set */
#define IPCC_C1SCR_CH4S_Pos (19U)
#define IPCC_C1SCR_CH4S_Msk (0x1U << IPCC_C1SCR_CH4S_Pos) /*!< 0x00080000 */
#define IPCC_C1SCR_CH4S IPCC_C1SCR_CH4S_Msk /*!< M4 transmit Channel4 status set */
#define IPCC_C1SCR_CH5S_Pos (20U)
#define IPCC_C1SCR_CH5S_Msk (0x1U << IPCC_C1SCR_CH5S_Pos) /*!< 0x00100000 */
#define IPCC_C1SCR_CH5S IPCC_C1SCR_CH5S_Msk /*!< M4 transmit Channel5 status set */
#define IPCC_C1SCR_CH6S_Pos (21U)
#define IPCC_C1SCR_CH6S_Msk (0x1U << IPCC_C1SCR_CH6S_Pos) /*!< 0x00200000 */
#define IPCC_C1SCR_CH6S IPCC_C1SCR_CH6S_Msk /*!< M4 transmit Channel6 status set */
/********************** Bit definition for IPCC_C1TOC2SR register ***************/
#define IPCC_C1TOC2SR_CH1F_Pos (0U)
#define IPCC_C1TOC2SR_CH1F_Msk (0x1U << IPCC_C1TOC2SR_CH1F_Pos) /*!< 0x00000001 */
#define IPCC_C1TOC2SR_CH1F IPCC_C1TOC2SR_CH1F_Msk /*!< M4 transmit to M4 receive Channel1 status flag before masking */
#define IPCC_C1TOC2SR_CH2F_Pos (1U)
#define IPCC_C1TOC2SR_CH2F_Msk (0x1U << IPCC_C1TOC2SR_CH2F_Pos) /*!< 0x00000002 */
#define IPCC_C1TOC2SR_CH2F IPCC_C1TOC2SR_CH2F_Msk /*!< M4 transmit to M4 receive Channel2 status flag before masking */
#define IPCC_C1TOC2SR_CH3F_Pos (2U)
#define IPCC_C1TOC2SR_CH3F_Msk (0x1U << IPCC_C1TOC2SR_CH3F_Pos) /*!< 0x00000004 */
#define IPCC_C1TOC2SR_CH3F IPCC_C1TOC2SR_CH3F_Msk /*!< M4 transmit to M4 receive Channel3 status flag before masking */
#define IPCC_C1TOC2SR_CH4F_Pos (3U)
#define IPCC_C1TOC2SR_CH4F_Msk (0x1U << IPCC_C1TOC2SR_CH4F_Pos) /*!< 0x00000008 */
#define IPCC_C1TOC2SR_CH4F IPCC_C1TOC2SR_CH4F_Msk /*!< M4 transmit to M4 receive Channel4 status flag before masking */
#define IPCC_C1TOC2SR_CH5F_Pos (4U)
#define IPCC_C1TOC2SR_CH5F_Msk (0x1U << IPCC_C1TOC2SR_CH5F_Pos) /*!< 0x00000010 */
#define IPCC_C1TOC2SR_CH5F IPCC_C1TOC2SR_CH5F_Msk /*!< M4 transmit to M4 receive Channel5 status flag before masking */
#define IPCC_C1TOC2SR_CH6F_Pos (5U)
#define IPCC_C1TOC2SR_CH6F_Msk (0x1U << IPCC_C1TOC2SR_CH6F_Pos) /*!< 0x00000020 */
#define IPCC_C1TOC2SR_CH6F IPCC_C1TOC2SR_CH6F_Msk /*!< M4 transmit to M4 receive Channel6 status flag before masking */
/********************** Bit definition for IPCC_C2CR register ***************/
#define IPCC_C2CR_RXOIE_Pos (0U)
#define IPCC_C2CR_RXOIE_Msk (0x1U << IPCC_C2CR_RXOIE_Pos) /*!< 0x00000001 */
#define IPCC_C2CR_RXOIE IPCC_C2CR_RXOIE_Msk /*!< Processor M0+ Receive channel occupied interrupt enable */
#define IPCC_C2CR_TXFIE_Pos (16U)
#define IPCC_C2CR_TXFIE_Msk (0x1U << IPCC_C2CR_TXFIE_Pos) /*!< 0x00010000 */
#define IPCC_C2CR_TXFIE IPCC_C2CR_TXFIE_Msk /*!< Processor M0+ Transmit channel free interrupt enable */
/********************** Bit definition for IPCC_C2MR register ***************/
#define IPCC_C2MR_CH1OM_Pos (0U)
#define IPCC_C2MR_CH1OM_Msk (0x1U << IPCC_C2MR_CH1OM_Pos) /*!< 0x00000001 */
#define IPCC_C2MR_CH1OM IPCC_C2MR_CH1OM_Msk /*!< M0+ Channel1 occupied interrupt mask */
#define IPCC_C2MR_CH2OM_Pos (1U)
#define IPCC_C2MR_CH2OM_Msk (0x1U << IPCC_C2MR_CH2OM_Pos) /*!< 0x00000002 */
#define IPCC_C2MR_CH2OM IPCC_C2MR_CH2OM_Msk /*!< M0+ Channel2 occupied interrupt mask */
#define IPCC_C2MR_CH3OM_Pos (2U)
#define IPCC_C2MR_CH3OM_Msk (0x1U << IPCC_C2MR_CH3OM_Pos) /*!< 0x00000004 */
#define IPCC_C2MR_CH3OM IPCC_C2MR_CH3OM_Msk /*!< M0+ Channel3 occupied interrupt mask */
#define IPCC_C2MR_CH4OM_Pos (3U)
#define IPCC_C2MR_CH4OM_Msk (0x1U << IPCC_C2MR_CH4OM_Pos) /*!< 0x00000008 */
#define IPCC_C2MR_CH4OM IPCC_C2MR_CH4OM_Msk /*!< M0+ Channel4 occupied interrupt mask */
#define IPCC_C2MR_CH5OM_Pos (4U)
#define IPCC_C2MR_CH5OM_Msk (0x1U << IPCC_C2MR_CH5OM_Pos) /*!< 0x00000010 */
#define IPCC_C2MR_CH5OM IPCC_C2MR_CH5OM_Msk /*!< M0+ Channel5 occupied interrupt mask */
#define IPCC_C2MR_CH6OM_Pos (5U)
#define IPCC_C2MR_CH6OM_Msk (0x1U << IPCC_C2MR_CH6OM_Pos) /*!< 0x00000020 */
#define IPCC_C2MR_CH6OM IPCC_C2MR_CH6OM_Msk /*!< M0+ Channel6 occupied interrupt mask */
#define IPCC_C2MR_CH1FM_Pos (16U)
#define IPCC_C2MR_CH1FM_Msk (0x1U << IPCC_C2MR_CH1FM_Pos) /*!< 0x00010000 */
#define IPCC_C2MR_CH1FM IPCC_C2MR_CH1FM_Msk /*!< M0+ Transmit Channel1 free interrupt mask */
#define IPCC_C2MR_CH2FM_Pos (17U)
#define IPCC_C2MR_CH2FM_Msk (0x1U << IPCC_C2MR_CH2FM_Pos) /*!< 0x00020000 */
#define IPCC_C2MR_CH2FM IPCC_C2MR_CH2FM_Msk /*!< M0+ Transmit Channel2 free interrupt mask */
#define IPCC_C2MR_CH3FM_Pos (18U)
#define IPCC_C2MR_CH3FM_Msk (0x1U << IPCC_C2MR_CH3FM_Pos) /*!< 0x00040000 */
#define IPCC_C2MR_CH3FM IPCC_C2MR_CH3FM_Msk /*!< M0+ Transmit Channel3 free interrupt mask */
#define IPCC_C2MR_CH4FM_Pos (19U)
#define IPCC_C2MR_CH4FM_Msk (0x1U << IPCC_C2MR_CH4FM_Pos) /*!< 0x00080000 */
#define IPCC_C2MR_CH4FM IPCC_C2MR_CH4FM_Msk /*!< M0+ Transmit Channel4 free interrupt mask */
#define IPCC_C2MR_CH5FM_Pos (20U)
#define IPCC_C2MR_CH5FM_Msk (0x1U << IPCC_C2MR_CH5FM_Pos) /*!< 0x00100000 */
#define IPCC_C2MR_CH5FM IPCC_C2MR_CH5FM_Msk /*!< M0+ Transmit Channel5 free interrupt mask */
#define IPCC_C2MR_CH6FM_Pos (21U)
#define IPCC_C2MR_CH6FM_Msk (0x1U << IPCC_C2MR_CH6FM_Pos) /*!< 0x00200000 */
#define IPCC_C2MR_CH6FM IPCC_C2MR_CH6FM_Msk /*!< M0+ Transmit Channel6 free interrupt mask */
/********************** Bit definition for IPCC_C2SCR register ***************/
#define IPCC_C2SCR_CH1C_Pos (0U)
#define IPCC_C2SCR_CH1C_Msk (0x1U << IPCC_C2SCR_CH1C_Pos) /*!< 0x00000001 */
#define IPCC_C2SCR_CH1C IPCC_C2SCR_CH1C_Msk /*!< M0+ receive Channel1 status clear */
#define IPCC_C2SCR_CH2C_Pos (1U)
#define IPCC_C2SCR_CH2C_Msk (0x1U << IPCC_C2SCR_CH2C_Pos) /*!< 0x00000002 */
#define IPCC_C2SCR_CH2C IPCC_C2SCR_CH2C_Msk /*!< M0+ receive Channel2 status clear */
#define IPCC_C2SCR_CH3C_Pos (2U)
#define IPCC_C2SCR_CH3C_Msk (0x1U << IPCC_C2SCR_CH3C_Pos) /*!< 0x00000004 */
#define IPCC_C2SCR_CH3C IPCC_C2SCR_CH3C_Msk /*!< M0+ receive Channel3 status clear */
#define IPCC_C2SCR_CH4C_Pos (3U)
#define IPCC_C2SCR_CH4C_Msk (0x1U << IPCC_C2SCR_CH4C_Pos) /*!< 0x00000008 */
#define IPCC_C2SCR_CH4C IPCC_C2SCR_CH4C_Msk /*!< M0+ receive Channel4 status clear */
#define IPCC_C2SCR_CH5C_Pos (4U)
#define IPCC_C2SCR_CH5C_Msk (0x1U << IPCC_C2SCR_CH5C_Pos) /*!< 0x00000010 */
#define IPCC_C2SCR_CH5C IPCC_C2SCR_CH5C_Msk /*!< M0+ receive Channel5 status clear */
#define IPCC_C2SCR_CH6C_Pos (5U)
#define IPCC_C2SCR_CH6C_Msk (0x1U << IPCC_C2SCR_CH6C_Pos) /*!< 0x00000020 */
#define IPCC_C2SCR_CH6C IPCC_C2SCR_CH6C_Msk /*!< M0+ receive Channel6 status clear */
#define IPCC_C2SCR_CH1S_Pos (16U)
#define IPCC_C2SCR_CH1S_Msk (0x1U << IPCC_C2SCR_CH1S_Pos) /*!< 0x00010000 */
#define IPCC_C2SCR_CH1S IPCC_C2SCR_CH1S_Msk /*!< M0+ transmit Channel1 status set */
#define IPCC_C2SCR_CH2S_Pos (17U)
#define IPCC_C2SCR_CH2S_Msk (0x1U << IPCC_C2SCR_CH2S_Pos) /*!< 0x00020000 */
#define IPCC_C2SCR_CH2S IPCC_C2SCR_CH2S_Msk /*!< M0+ transmit Channel2 status set */
#define IPCC_C2SCR_CH3S_Pos (18U)
#define IPCC_C2SCR_CH3S_Msk (0x1U << IPCC_C2SCR_CH3S_Pos) /*!< 0x00040000 */
#define IPCC_C2SCR_CH3S IPCC_C2SCR_CH3S_Msk /*!< M0+ transmit Channel3 status set */
#define IPCC_C2SCR_CH4S_Pos (19U)
#define IPCC_C2SCR_CH4S_Msk (0x1U << IPCC_C2SCR_CH4S_Pos) /*!< 0x00080000 */
#define IPCC_C2SCR_CH4S IPCC_C2SCR_CH4S_Msk /*!< M0+ transmit Channel4 status set */
#define IPCC_C2SCR_CH5S_Pos (20U)
#define IPCC_C2SCR_CH5S_Msk (0x1U << IPCC_C2SCR_CH5S_Pos) /*!< 0x00100000 */
#define IPCC_C2SCR_CH5S IPCC_C2SCR_CH5S_Msk /*!< M0+ transmit Channel5 status set */
#define IPCC_C2SCR_CH6S_Pos (21U)
#define IPCC_C2SCR_CH6S_Msk (0x1U << IPCC_C2SCR_CH6S_Pos) /*!< 0x00200000 */
#define IPCC_C2SCR_CH6S IPCC_C2SCR_CH6S_Msk /*!< M0+ transmit Channel6 status set */
/********************** Bit definition for IPCC_C2TOC1SR register ***************/
#define IPCC_C2TOC1SR_CH1F_Pos (0U)
#define IPCC_C2TOC1SR_CH1F_Msk (0x1U << IPCC_C2TOC1SR_CH1F_Pos) /*!< 0x00000001 */
#define IPCC_C2TOC1SR_CH1F IPCC_C2TOC1SR_CH1F_Msk /*!< M0+ transmit to M0 receive Channel1 status flag before masking */
#define IPCC_C2TOC1SR_CH2F_Pos (1U)
#define IPCC_C2TOC1SR_CH2F_Msk (0x1U << IPCC_C2TOC1SR_CH2F_Pos) /*!< 0x00000002 */
#define IPCC_C2TOC1SR_CH2F IPCC_C2TOC1SR_CH2F_Msk /*!< M0+ transmit to M0 receive Channel2 status flag before masking */
#define IPCC_C2TOC1SR_CH3F_Pos (2U)
#define IPCC_C2TOC1SR_CH3F_Msk (0x1U << IPCC_C2TOC1SR_CH3F_Pos) /*!< 0x00000004 */
#define IPCC_C2TOC1SR_CH3F IPCC_C2TOC1SR_CH3F_Msk /*!< M0+ transmit to M0 receive Channel3 status flag before masking */
#define IPCC_C2TOC1SR_CH4F_Pos (3U)
#define IPCC_C2TOC1SR_CH4F_Msk (0x1U << IPCC_C2TOC1SR_CH4F_Pos) /*!< 0x00000008 */
#define IPCC_C2TOC1SR_CH4F IPCC_C2TOC1SR_CH4F_Msk /*!< M0+ transmit to M0 receive Channel4 status flag before masking */
#define IPCC_C2TOC1SR_CH5F_Pos (4U)
#define IPCC_C2TOC1SR_CH5F_Msk (0x1U << IPCC_C2TOC1SR_CH5F_Pos) /*!< 0x00000010 */
#define IPCC_C2TOC1SR_CH5F IPCC_C2TOC1SR_CH5F_Msk /*!< M0+ transmit to M0 receive Channel5 status flag before masking */
#define IPCC_C2TOC1SR_CH6F_Pos (5U)
#define IPCC_C2TOC1SR_CH6F_Msk (0x1U << IPCC_C2TOC1SR_CH6F_Pos) /*!< 0x00000020 */
#define IPCC_C2TOC1SR_CH6F IPCC_C2TOC1SR_CH6F_Msk /*!< M0+ transmit to M0 receive Channel6 status flag before masking */
/********************** Bit definition for IPCC_HWCFGR register ***************/
#define IPCC_HWCFGR_CHANNELS_Pos (0U)
#define IPCC_HWCFGR_CHANNELS_Msk (0xFFU << IPCC_HWCFGR_CHANNELS_Pos) /*!< 0x000000FF */
#define IPCC_HWCFGR_CHANNELS IPCC_HWCFGR_CHANNELS_Msk /*!< Number of channels per CPU */
/********************** Bit definition for IPCC_VERR register *****************/
#define IPCC_VERR_MINREV_Pos (0U)
#define IPCC_VERR_MINREV_Msk (0xFU << IPCC_VERR_MINREV_Pos) /*!< 0x0000000F */
#define IPCC_VERR_MINREV IPCC_VERR_MINREV_Msk /*!< Minor Revision number */
#define IPCC_VERR_MAJREV_Pos (4U)
#define IPCC_VERR_MAJREV_Msk (0xFU << IPCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define IPCC_VERR_MAJREV IPCC_VERR_MAJREV_Msk /*!< Major Revision number */
/********************** Bit definition for IPCC_IPIDR register ****************/
#define IPCC_IPIDR_IPID_Pos (0U)
#define IPCC_IPIDR_IPID_Msk (0xFFFFFFFFU << IPCC_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
#define IPCC_IPIDR_IPID IPCC_IPIDR_IPID_Msk /*!< IP Identification */
/********************** Bit definition for IPCC_SIDR register *****************/
#define IPCC_SIDR_SID_Pos (0U)
#define IPCC_SIDR_SID_Msk (0xFFFFFFFFU << IPCC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define IPCC_SIDR_SID IPCC_SIDR_SID_Msk /*!< IP size identification */
/********************** Bit definition for IPCC_C1CR register ***************/
#define IPCC_CR_RXOIE_Pos IPCC_C1CR_RXOIE_Pos
#define IPCC_CR_RXOIE_Msk IPCC_C1CR_RXOIE_Msk
#define IPCC_CR_RXOIE IPCC_C1CR_RXOIE
#define IPCC_CR_TXFIE_Pos IPCC_C1CR_TXFIE_Pos
#define IPCC_CR_TXFIE_Msk IPCC_C1CR_TXFIE_Msk
#define IPCC_CR_TXFIE IPCC_C1CR_TXFIE
/********************** Bit definition for IPCC_C1MR register **************/
#define IPCC_MR_CH1OM_Pos IPCC_C1MR_CH1OM_Pos
#define IPCC_MR_CH1OM_Msk IPCC_C1MR_CH1OM_Msk
#define IPCC_MR_CH1OM IPCC_C1MR_CH1OM
#define IPCC_MR_CH2OM_Pos IPCC_C1MR_CH2OM_Pos
#define IPCC_MR_CH2OM_Msk IPCC_C1MR_CH2OM_Msk
#define IPCC_MR_CH2OM IPCC_C1MR_CH2OM
#define IPCC_MR_CH3OM_Pos IPCC_C1MR_CH3OM_Pos
#define IPCC_MR_CH3OM_Msk IPCC_C1MR_CH3OM_Msk
#define IPCC_MR_CH3OM IPCC_C1MR_CH3OM
#define IPCC_MR_CH4OM_Pos IPCC_C1MR_CH4OM_Pos
#define IPCC_MR_CH4OM_Msk IPCC_C1MR_CH4OM_Msk
#define IPCC_MR_CH4OM IPCC_C1MR_CH4OM
#define IPCC_MR_CH5OM_Pos IPCC_C1MR_CH5OM_Pos
#define IPCC_MR_CH5OM_Msk IPCC_C1MR_CH5OM_Msk
#define IPCC_MR_CH5OM IPCC_C1MR_CH5OM
#define IPCC_MR_CH6OM_Pos IPCC_C1MR_CH6OM_Pos
#define IPCC_MR_CH6OM_Msk IPCC_C1MR_CH6OM_Msk
#define IPCC_MR_CH6OM IPCC_C1MR_CH6OM
#define IPCC_MR_CH1FM_Pos IPCC_C1MR_CH1FM_Pos
#define IPCC_MR_CH1FM_Msk IPCC_C1MR_CH1FM_Msk
#define IPCC_MR_CH1FM IPCC_C1MR_CH1FM
#define IPCC_MR_CH2FM_Pos IPCC_C1MR_CH2FM_Pos
#define IPCC_MR_CH2FM_Msk IPCC_C1MR_CH2FM_Msk
#define IPCC_MR_CH2FM IPCC_C1MR_CH2FM
#define IPCC_MR_CH3FM_Pos IPCC_C1MR_CH3FM_Pos
#define IPCC_MR_CH3FM_Msk IPCC_C1MR_CH3FM_Msk
#define IPCC_MR_CH3FM IPCC_C1MR_CH3FM
#define IPCC_MR_CH4FM_Pos IPCC_C1MR_CH4FM_Pos
#define IPCC_MR_CH4FM_Msk IPCC_C1MR_CH4FM_Msk
#define IPCC_MR_CH4FM IPCC_C1MR_CH4FM
#define IPCC_MR_CH5FM_Pos IPCC_C1MR_CH5FM_Pos
#define IPCC_MR_CH5FM_Msk IPCC_C1MR_CH5FM_Msk
#define IPCC_MR_CH5FM IPCC_C1MR_CH5FM
#define IPCC_MR_CH6FM_Pos IPCC_C1MR_CH6FM_Pos
#define IPCC_MR_CH6FM_Msk IPCC_C1MR_CH6FM_Msk
#define IPCC_MR_CH6FM IPCC_C1MR_CH6FM
/********************** Bit definition for IPCC_C1SCR register ***************/
#define IPCC_SCR_CH1C_Pos IPCC_C1SCR_CH1C_Pos
#define IPCC_SCR_CH1C_Msk IPCC_C1SCR_CH1C_Msk
#define IPCC_SCR_CH1C IPCC_C1SCR_CH1C
#define IPCC_SCR_CH2C_Pos IPCC_C1SCR_CH2C_Pos
#define IPCC_SCR_CH2C_Msk IPCC_C1SCR_CH2C_Msk
#define IPCC_SCR_CH2C IPCC_C1SCR_CH2C
#define IPCC_SCR_CH3C_Pos IPCC_C1SCR_CH3C_Pos
#define IPCC_SCR_CH3C_Msk IPCC_C1SCR_CH3C_Msk
#define IPCC_SCR_CH3C IPCC_C1SCR_CH3C
#define IPCC_SCR_CH4C_Pos IPCC_C1SCR_CH4C_Pos
#define IPCC_SCR_CH4C_Msk IPCC_C1SCR_CH4C_Msk
#define IPCC_SCR_CH4C IPCC_C1SCR_CH4C
#define IPCC_SCR_CH5C_Pos IPCC_C1SCR_CH5C_Pos
#define IPCC_SCR_CH5C_Msk IPCC_C1SCR_CH5C_Msk
#define IPCC_SCR_CH5C IPCC_C1SCR_CH5C
#define IPCC_SCR_CH6C_Pos IPCC_C1SCR_CH6C_Pos
#define IPCC_SCR_CH6C_Msk IPCC_C1SCR_CH6C_Msk
#define IPCC_SCR_CH6C IPCC_C1SCR_CH6C
#define IPCC_SCR_CH1S_Pos IPCC_C1SCR_CH1S_Pos
#define IPCC_SCR_CH1S_Msk IPCC_C1SCR_CH1S_Msk
#define IPCC_SCR_CH1S IPCC_C1SCR_CH1S
#define IPCC_SCR_CH2S_Pos IPCC_C1SCR_CH2S_Pos
#define IPCC_SCR_CH2S_Msk IPCC_C1SCR_CH2S_Msk
#define IPCC_SCR_CH2S IPCC_C1SCR_CH2S
#define IPCC_SCR_CH3S_Pos IPCC_C1SCR_CH3S_Pos
#define IPCC_SCR_CH3S_Msk IPCC_C1SCR_CH3S_Msk
#define IPCC_SCR_CH3S IPCC_C1SCR_CH3S
#define IPCC_SCR_CH4S_Pos IPCC_C1SCR_CH4S_Pos
#define IPCC_SCR_CH4S_Msk IPCC_C1SCR_CH4S_Msk
#define IPCC_SCR_CH4S IPCC_C1SCR_CH4S
#define IPCC_SCR_CH5S_Pos IPCC_C1SCR_CH5S_Pos
#define IPCC_SCR_CH5S_Msk IPCC_C1SCR_CH5S_Msk
#define IPCC_SCR_CH5S IPCC_C1SCR_CH5S
#define IPCC_SCR_CH6S_Pos IPCC_C1SCR_CH6S_Pos
#define IPCC_SCR_CH6S_Msk IPCC_C1SCR_CH6S_Msk
#define IPCC_SCR_CH6S IPCC_C1SCR_CH6S
/********************** Bit definition for IPCC_C1TOC2SR register ***************/
#define IPCC_SR_CH1F_Pos IPCC_C1TOC2SR_CH1F_Pos
#define IPCC_SR_CH1F_Msk IPCC_C1TOC2SR_CH1F_Msk
#define IPCC_SR_CH1F IPCC_C1TOC2SR_CH1F
#define IPCC_SR_CH2F_Pos IPCC_C1TOC2SR_CH2F_Pos
#define IPCC_SR_CH2F_Msk IPCC_C1TOC2SR_CH2F_Msk
#define IPCC_SR_CH2F IPCC_C1TOC2SR_CH2F
#define IPCC_SR_CH3F_Pos IPCC_C1TOC2SR_CH3F_Pos
#define IPCC_SR_CH3F_Msk IPCC_C1TOC2SR_CH3F_Msk
#define IPCC_SR_CH3F IPCC_C1TOC2SR_CH3F
#define IPCC_SR_CH4F_Pos IPCC_C1TOC2SR_CH4F_Pos
#define IPCC_SR_CH4F_Msk IPCC_C1TOC2SR_CH4F_Msk
#define IPCC_SR_CH4F IPCC_C1TOC2SR_CH4F
#define IPCC_SR_CH5F_Pos IPCC_C1TOC2SR_CH5F_Pos
#define IPCC_SR_CH5F_Msk IPCC_C1TOC2SR_CH5F_Msk
#define IPCC_SR_CH5F IPCC_C1TOC2SR_CH5F
#define IPCC_SR_CH6F_Pos IPCC_C1TOC2SR_CH6F_Pos
#define IPCC_SR_CH6F_Msk IPCC_C1TOC2SR_CH6F_Msk
#define IPCC_SR_CH6F IPCC_C1TOC2SR_CH6F
/******************** Number of IPCC channels ******************************/
#define IPCC_CHANNEL_NUMBER 6U
/******************************************************************************/
/* */
/* MDMA */
/* */
/******************************************************************************/
/******************** Bit definition for MDMA_GISR0 register ****************/
#define MDMA_GISR0_GIF0_Pos (0U)
#define MDMA_GISR0_GIF0_Msk (0x1U << MDMA_GISR0_GIF0_Pos) /*!< 0x00000001 */
#define MDMA_GISR0_GIF0 MDMA_GISR0_GIF0_Msk /*!< Channel 0 global interrupt flag */
#define MDMA_GISR0_GIF1_Pos (1U)
#define MDMA_GISR0_GIF1_Msk (0x1U << MDMA_GISR0_GIF1_Pos) /*!< 0x00000002 */
#define MDMA_GISR0_GIF1 MDMA_GISR0_GIF1_Msk /*!< Channel 1 global interrupt flag */
#define MDMA_GISR0_GIF2_Pos (2U)
#define MDMA_GISR0_GIF2_Msk (0x1U << MDMA_GISR0_GIF2_Pos) /*!< 0x00000004 */
#define MDMA_GISR0_GIF2 MDMA_GISR0_GIF2_Msk /*!< Channel 2 global interrupt flag */
#define MDMA_GISR0_GIF3_Pos (3U)
#define MDMA_GISR0_GIF3_Msk (0x1U << MDMA_GISR0_GIF3_Pos) /*!< 0x00000008 */
#define MDMA_GISR0_GIF3 MDMA_GISR0_GIF3_Msk /*!< Channel 3 global interrupt flag */
#define MDMA_GISR0_GIF4_Pos (4U)
#define MDMA_GISR0_GIF4_Msk (0x1U << MDMA_GISR0_GIF4_Pos) /*!< 0x00000010 */
#define MDMA_GISR0_GIF4 MDMA_GISR0_GIF4_Msk /*!< Channel 4 global interrupt flag */
#define MDMA_GISR0_GIF5_Pos (5U)
#define MDMA_GISR0_GIF5_Msk (0x1U << MDMA_GISR0_GIF5_Pos) /*!< 0x00000020 */
#define MDMA_GISR0_GIF5 MDMA_GISR0_GIF5_Msk /*!< Channel 5 global interrupt flag */
#define MDMA_GISR0_GIF6_Pos (6U)
#define MDMA_GISR0_GIF6_Msk (0x1U << MDMA_GISR0_GIF6_Pos) /*!< 0x00000040 */
#define MDMA_GISR0_GIF6 MDMA_GISR0_GIF6_Msk /*!< Channel 6 global interrupt flag */
#define MDMA_GISR0_GIF7_Pos (7U)
#define MDMA_GISR0_GIF7_Msk (0x1U << MDMA_GISR0_GIF7_Pos) /*!< 0x00000080 */
#define MDMA_GISR0_GIF7 MDMA_GISR0_GIF7_Msk /*!< Channel 7 global interrupt flag */
#define MDMA_GISR0_GIF8_Pos (8U)
#define MDMA_GISR0_GIF8_Msk (0x1U << MDMA_GISR0_GIF8_Pos) /*!< 0x00000100 */
#define MDMA_GISR0_GIF8 MDMA_GISR0_GIF8_Msk /*!< Channel 8 global interrupt flag */
#define MDMA_GISR0_GIF9_Pos (9U)
#define MDMA_GISR0_GIF9_Msk (0x1U << MDMA_GISR0_GIF9_Pos) /*!< 0x00000200 */
#define MDMA_GISR0_GIF9 MDMA_GISR0_GIF9_Msk /*!< Channel 9 global interrupt flag */
#define MDMA_GISR0_GIF10_Pos (10U)
#define MDMA_GISR0_GIF10_Msk (0x1U << MDMA_GISR0_GIF10_Pos) /*!< 0x00000400 */
#define MDMA_GISR0_GIF10 MDMA_GISR0_GIF10_Msk /*!< Channel 10 global interrupt flag */
#define MDMA_GISR0_GIF11_Pos (11U)
#define MDMA_GISR0_GIF11_Msk (0x1U << MDMA_GISR0_GIF11_Pos) /*!< 0x00000800 */
#define MDMA_GISR0_GIF11 MDMA_GISR0_GIF11_Msk /*!< Channel 11 global interrupt flag */
#define MDMA_GISR0_GIF12_Pos (12U)
#define MDMA_GISR0_GIF12_Msk (0x1U << MDMA_GISR0_GIF12_Pos) /*!< 0x00001000 */
#define MDMA_GISR0_GIF12 MDMA_GISR0_GIF12_Msk /*!< Channel 12 global interrupt flag */
#define MDMA_GISR0_GIF13_Pos (13U)
#define MDMA_GISR0_GIF13_Msk (0x1U << MDMA_GISR0_GIF13_Pos) /*!< 0x00002000 */
#define MDMA_GISR0_GIF13 MDMA_GISR0_GIF13_Msk /*!< Channel 13 global interrupt flag */
#define MDMA_GISR0_GIF14_Pos (14U)
#define MDMA_GISR0_GIF14_Msk (0x1U << MDMA_GISR0_GIF14_Pos) /*!< 0x00004000 */
#define MDMA_GISR0_GIF14 MDMA_GISR0_GIF14_Msk /*!< Channel 14 global interrupt flag */
#define MDMA_GISR0_GIF15_Pos (15U)
#define MDMA_GISR0_GIF15_Msk (0x1U << MDMA_GISR0_GIF15_Pos) /*!< 0x00008000 */
#define MDMA_GISR0_GIF15 MDMA_GISR0_GIF15_Msk /*!< Channel 15 global interrupt flag */
#define MDMA_GISR0_GIF16_Pos (16U)
#define MDMA_GISR0_GIF16_Msk (0x1U << MDMA_GISR0_GIF16_Pos) /*!< 0x00010000 */
#define MDMA_GISR0_GIF16 MDMA_GISR0_GIF16_Msk /*!< Channel 16 global interrupt flag */
#define MDMA_GISR0_GIF17_Pos (17U)
#define MDMA_GISR0_GIF17_Msk (0x1U << MDMA_GISR0_GIF17_Pos) /*!< 0x00020000 */
#define MDMA_GISR0_GIF17 MDMA_GISR0_GIF17_Msk /*!< Channel 17 global interrupt flag */
#define MDMA_GISR0_GIF18_Pos (18U)
#define MDMA_GISR0_GIF18_Msk (0x1U << MDMA_GISR0_GIF18_Pos) /*!< 0x00040000 */
#define MDMA_GISR0_GIF18 MDMA_GISR0_GIF18_Msk /*!< Channel 18 global interrupt flag */
#define MDMA_GISR0_GIF19_Pos (19U)
#define MDMA_GISR0_GIF19_Msk (0x1U << MDMA_GISR0_GIF19_Pos) /*!< 0x00080000 */
#define MDMA_GISR0_GIF19 MDMA_GISR0_GIF19_Msk /*!< Channel 19 global interrupt flag */
#define MDMA_GISR0_GIF20_Pos (20U)
#define MDMA_GISR0_GIF20_Msk (0x1U << MDMA_GISR0_GIF20_Pos) /*!< 0x00100000 */
#define MDMA_GISR0_GIF20 MDMA_GISR0_GIF20_Msk /*!< Channel 20 global interrupt flag */
#define MDMA_GISR0_GIF21_Pos (21U)
#define MDMA_GISR0_GIF21_Msk (0x1U << MDMA_GISR0_GIF21_Pos) /*!< 0x00200000 */
#define MDMA_GISR0_GIF21 MDMA_GISR0_GIF21_Msk /*!< Channel 21 global interrupt flag */
#define MDMA_GISR0_GIF22_Pos (22U)
#define MDMA_GISR0_GIF22_Msk (0x1U << MDMA_GISR0_GIF22_Pos) /*!< 0x00400000 */
#define MDMA_GISR0_GIF22 MDMA_GISR0_GIF22_Msk /*!< Channel 22 global interrupt flag */
#define MDMA_GISR0_GIF23_Pos (23U)
#define MDMA_GISR0_GIF23_Msk (0x1U << MDMA_GISR0_GIF23_Pos) /*!< 0x00800000 */
#define MDMA_GISR0_GIF23 MDMA_GISR0_GIF23_Msk /*!< Channel 23 global interrupt flag */
#define MDMA_GISR0_GIF24_Pos (24U)
#define MDMA_GISR0_GIF24_Msk (0x1U << MDMA_GISR0_GIF24_Pos) /*!< 0x01000000 */
#define MDMA_GISR0_GIF24 MDMA_GISR0_GIF24_Msk /*!< Channel 24 global interrupt flag */
#define MDMA_GISR0_GIF25_Pos (25U)
#define MDMA_GISR0_GIF25_Msk (0x1U << MDMA_GISR0_GIF25_Pos) /*!< 0x02000000 */
#define MDMA_GISR0_GIF25 MDMA_GISR0_GIF25_Msk /*!< Channel 25 global interrupt flag */
#define MDMA_GISR0_GIF26_Pos (26U)
#define MDMA_GISR0_GIF26_Msk (0x1U << MDMA_GISR0_GIF26_Pos) /*!< 0x04000000 */
#define MDMA_GISR0_GIF26 MDMA_GISR0_GIF26_Msk /*!< Channel 26 global interrupt flag */
#define MDMA_GISR0_GIF27_Pos (27U)
#define MDMA_GISR0_GIF27_Msk (0x1U << MDMA_GISR0_GIF27_Pos) /*!< 0x08000000 */
#define MDMA_GISR0_GIF27 MDMA_GISR0_GIF27_Msk /*!< Channel 27 global interrupt flag */
#define MDMA_GISR0_GIF28_Pos (28U)
#define MDMA_GISR0_GIF28_Msk (0x1U << MDMA_GISR0_GIF28_Pos) /*!< 0x10000000 */
#define MDMA_GISR0_GIF28 MDMA_GISR0_GIF28_Msk /*!< Channel 28 global interrupt flag */
#define MDMA_GISR0_GIF29_Pos (29U)
#define MDMA_GISR0_GIF29_Msk (0x1U << MDMA_GISR0_GIF29_Pos) /*!< 0x20000000 */
#define MDMA_GISR0_GIF29 MDMA_GISR0_GIF29_Msk /*!< Channel 29 global interrupt flag */
#define MDMA_GISR0_GIF30_Pos (30U)
#define MDMA_GISR0_GIF30_Msk (0x1U << MDMA_GISR0_GIF30_Pos) /*!< 0x40000000 */
#define MDMA_GISR0_GIF30 MDMA_GISR0_GIF30_Msk /*!< Channel 30 global interrupt flag */
#define MDMA_GISR0_GIF31_Pos (31U)
#define MDMA_GISR0_GIF31_Msk (0x1U << MDMA_GISR0_GIF31_Pos) /*!< 0x80000000 */
#define MDMA_GISR0_GIF31 MDMA_GISR0_GIF31_Msk /*!< Channel 31 global interrupt flag */
/******************** Bit definition for MDMA_GISR1 register ****************/
#define MDMA_GISR1_GIF32_Pos (0U)
#define MDMA_GISR1_GIF32_Msk (0x1U << MDMA_GISR1_GIF32_Pos) /*!< 0x00000001 */
#define MDMA_GISR1_GIF32 MDMA_GISR1_GIF32_Msk /*!< Channel 32 global interrupt flag */
#define MDMA_GISR1_GIF33_Pos (1U)
#define MDMA_GISR1_GIF33_Msk (0x1U << MDMA_GISR1_GIF33_Pos) /*!< 0x00000002 */
#define MDMA_GISR1_GIF33 MDMA_GISR1_GIF33_Msk /*!< Channel 33 global interrupt flag */
#define MDMA_GISR1_GIF34_Pos (2U)
#define MDMA_GISR1_GIF34_Msk (0x1U << MDMA_GISR1_GIF34_Pos) /*!< 0x00000004 */
#define MDMA_GISR1_GIF34 MDMA_GISR1_GIF34_Msk /*!< Channel 34 global interrupt flag */
#define MDMA_GISR1_GIF35_Pos (3U)
#define MDMA_GISR1_GIF35_Msk (0x1U << MDMA_GISR1_GIF35_Pos) /*!< 0x00000008 */
#define MDMA_GISR1_GIF35 MDMA_GISR1_GIF35_Msk /*!< Channel 35 global interrupt flag */
#define MDMA_GISR1_GIF36_Pos (4U)
#define MDMA_GISR1_GIF36_Msk (0x1U << MDMA_GISR1_GIF36_Pos) /*!< 0x00000010 */
#define MDMA_GISR1_GIF36 MDMA_GISR1_GIF36_Msk /*!< Channel 36 global interrupt flag */
#define MDMA_GISR1_GIF37_Pos (5U)
#define MDMA_GISR1_GIF37_Msk (0x1U << MDMA_GISR1_GIF37_Pos) /*!< 0x00000020 */
#define MDMA_GISR1_GIF37 MDMA_GISR1_GIF37_Msk /*!< Channel 37 global interrupt flag */
#define MDMA_GISR1_GIF38_Pos (6U)
#define MDMA_GISR1_GIF38_Msk (0x1U << MDMA_GISR1_GIF38_Pos) /*!< 0x00000040 */
#define MDMA_GISR1_GIF38 MDMA_GISR1_GIF38_Msk /*!< Channel 38 global interrupt flag */
#define MDMA_GISR1_GIF39_Pos (7U)
#define MDMA_GISR1_GIF39_Msk (0x1U << MDMA_GISR1_GIF39_Pos) /*!< 0x00000080 */
#define MDMA_GISR1_GIF39 MDMA_GISR1_GIF39_Msk /*!< Channel 39 global interrupt flag */
#define MDMA_GISR1_GIF40_Pos (8U)
#define MDMA_GISR1_GIF40_Msk (0x1U << MDMA_GISR1_GIF40_Pos) /*!< 0x00000100 */
#define MDMA_GISR1_GIF40 MDMA_GISR1_GIF40_Msk /*!< Channel 40 global interrupt flag */
#define MDMA_GISR1_GIF41_Pos (9U)
#define MDMA_GISR1_GIF41_Msk (0x1U << MDMA_GISR1_GIF41_Pos) /*!< 0x00000200 */
#define MDMA_GISR1_GIF41 MDMA_GISR1_GIF41_Msk /*!< Channel 41 global interrupt flag */
#define MDMA_GISR1_GIF42_Pos (10U)
#define MDMA_GISR1_GIF42_Msk (0x1U << MDMA_GISR1_GIF42_Pos) /*!< 0x00000400 */
#define MDMA_GISR1_GIF42 MDMA_GISR1_GIF42_Msk /*!< Channel 42 global interrupt flag */
#define MDMA_GISR1_GIF43_Pos (11U)
#define MDMA_GISR1_GIF43_Msk (0x1U << MDMA_GISR1_GIF43_Pos) /*!< 0x00000800 */
#define MDMA_GISR1_GIF43 MDMA_GISR1_GIF43_Msk /*!< Channel 43 global interrupt flag */
#define MDMA_GISR1_GIF44_Pos (12U)
#define MDMA_GISR1_GIF44_Msk (0x1U << MDMA_GISR1_GIF44_Pos) /*!< 0x00001000 */
#define MDMA_GISR1_GIF44 MDMA_GISR1_GIF44_Msk /*!< Channel 44 global interrupt flag */
#define MDMA_GISR1_GIF45_Pos (13U)
#define MDMA_GISR1_GIF45_Msk (0x1U << MDMA_GISR1_GIF45_Pos) /*!< 0x00002000 */
#define MDMA_GISR1_GIF45 MDMA_GISR1_GIF45_Msk /*!< Channel 45 global interrupt flag */
#define MDMA_GISR1_GIF46_Pos (14U)
#define MDMA_GISR1_GIF46_Msk (0x1U << MDMA_GISR1_GIF46_Pos) /*!< 0x00004000 */
#define MDMA_GISR1_GIF46 MDMA_GISR1_GIF46_Msk /*!< Channel 46 global interrupt flag */
#define MDMA_GISR1_GIF47_Pos (15U)
#define MDMA_GISR1_GIF47_Msk (0x1U << MDMA_GISR1_GIF47_Pos) /*!< 0x00008000 */
#define MDMA_GISR1_GIF47 MDMA_GISR1_GIF47_Msk /*!< Channel 47 global interrupt flag */
#define MDMA_GISR1_GIF48_Pos (16U)
#define MDMA_GISR1_GIF48_Msk (0x1U << MDMA_GISR1_GIF48_Pos) /*!< 0x00010000 */
#define MDMA_GISR1_GIF48 MDMA_GISR1_GIF48_Msk /*!< Channel 48 global interrupt flag */
#define MDMA_GISR1_GIF49_Pos (17U)
#define MDMA_GISR1_GIF49_Msk (0x1U << MDMA_GISR1_GIF49_Pos) /*!< 0x00020000 */
#define MDMA_GISR1_GIF49 MDMA_GISR1_GIF49_Msk /*!< Channel 49 global interrupt flag */
#define MDMA_GISR1_GIF50_Pos (18U)
#define MDMA_GISR1_GIF50_Msk (0x1U << MDMA_GISR1_GIF50_Pos) /*!< 0x00040000 */
#define MDMA_GISR1_GIF50 MDMA_GISR1_GIF50_Msk /*!< Channel 50 global interrupt flag */
#define MDMA_GISR1_GIF51_Pos (19U)
#define MDMA_GISR1_GIF51_Msk (0x1U << MDMA_GISR1_GIF51_Pos) /*!< 0x00080000 */
#define MDMA_GISR1_GIF51 MDMA_GISR1_GIF51_Msk /*!< Channel 51 global interrupt flag */
#define MDMA_GISR1_GIF52_Pos (20U)
#define MDMA_GISR1_GIF52_Msk (0x1U << MDMA_GISR1_GIF52_Pos) /*!< 0x00100000 */
#define MDMA_GISR1_GIF52 MDMA_GISR1_GIF52_Msk /*!< Channel 52 global interrupt flag */
#define MDMA_GISR1_GIF53_Pos (21U)
#define MDMA_GISR1_GIF53_Msk (0x1U << MDMA_GISR1_GIF53_Pos) /*!< 0x00200000 */
#define MDMA_GISR1_GIF53 MDMA_GISR1_GIF53_Msk /*!< Channel 53 global interrupt flag */
#define MDMA_GISR1_GIF54_Pos (22U)
#define MDMA_GISR1_GIF54_Msk (0x1U << MDMA_GISR1_GIF54_Pos) /*!< 0x00400000 */
#define MDMA_GISR1_GIF54 MDMA_GISR1_GIF54_Msk /*!< Channel 54 global interrupt flag */
#define MDMA_GISR1_GIF55_Pos (23U)
#define MDMA_GISR1_GIF55_Msk (0x1U << MDMA_GISR1_GIF55_Pos) /*!< 0x00800000 */
#define MDMA_GISR1_GIF55 MDMA_GISR1_GIF55_Msk /*!< Channel 55 global interrupt flag */
#define MDMA_GISR1_GIF56_Pos (24U)
#define MDMA_GISR1_GIF56_Msk (0x1U << MDMA_GISR1_GIF56_Pos) /*!< 0x01000000 */
#define MDMA_GISR1_GIF56 MDMA_GISR1_GIF56_Msk /*!< Channel 56 global interrupt flag */
#define MDMA_GISR1_GIF57_Pos (25U)
#define MDMA_GISR1_GIF57_Msk (0x1U << MDMA_GISR1_GIF57_Pos) /*!< 0x02000000 */
#define MDMA_GISR1_GIF57 MDMA_GISR1_GIF57_Msk /*!< Channel 57 global interrupt flag */
#define MDMA_GISR1_GIF58_Pos (26U)
#define MDMA_GISR1_GIF58_Msk (0x1U << MDMA_GISR1_GIF58_Pos) /*!< 0x04000000 */
#define MDMA_GISR1_GIF58 MDMA_GISR1_GIF58_Msk /*!< Channel 58 global interrupt flag */
#define MDMA_GISR1_GIF59_Pos (27U)
#define MDMA_GISR1_GIF59_Msk (0x1U << MDMA_GISR1_GIF59_Pos) /*!< 0x08000000 */
#define MDMA_GISR1_GIF59 MDMA_GISR1_GIF59_Msk /*!< Channel 59 global interrupt flag */
#define MDMA_GISR1_GIF60_Pos (28U)
#define MDMA_GISR1_GIF60_Msk (0x1U << MDMA_GISR1_GIF60_Pos) /*!< 0x10000000 */
#define MDMA_GISR1_GIF60 MDMA_GISR1_GIF60_Msk /*!< Channel 60 global interrupt flag */
#define MDMA_GISR1_GIF61_Pos (29U)
#define MDMA_GISR1_GIF61_Msk (0x1U << MDMA_GISR1_GIF61_Pos) /*!< 0x20000000 */
#define MDMA_GISR1_GIF61 MDMA_GISR1_GIF61_Msk /*!< Channel 61 global interrupt flag */
#define MDMA_GISR1_GIF62_Pos (30U)
#define MDMA_GISR1_GIF62_Msk (0x1U << MDMA_GISR1_GIF62_Pos) /*!< 0x40000000 */
#define MDMA_GISR1_GIF62 MDMA_GISR1_GIF62_Msk /*!< Channel 62 global interrupt flag */
/******************** Bit definition for MDMA_CxISR register ****************/
#define MDMA_CISR_TEIF_Pos (0U)
#define MDMA_CISR_TEIF_Msk (0x1U << MDMA_CISR_TEIF_Pos) /*!< 0x00000001 */
#define MDMA_CISR_TEIF MDMA_CISR_TEIF_Msk /*!< Channel x transfer error interrupt flag */
#define MDMA_CISR_CTCIF_Pos (1U)
#define MDMA_CISR_CTCIF_Msk (0x1U << MDMA_CISR_CTCIF_Pos) /*!< 0x00000002 */
#define MDMA_CISR_CTCIF MDMA_CISR_CTCIF_Msk /*!< Channel x Channel Transfer Complete interrupt flag */
#define MDMA_CISR_BRTIF_Pos (2U)
#define MDMA_CISR_BRTIF_Msk (0x1U << MDMA_CISR_BRTIF_Pos) /*!< 0x00000004 */
#define MDMA_CISR_BRTIF MDMA_CISR_BRTIF_Msk /*!< Channel x block repeat transfer complete interrupt flag */
#define MDMA_CISR_BTIF_Pos (3U)
#define MDMA_CISR_BTIF_Msk (0x1U << MDMA_CISR_BTIF_Pos) /*!< 0x00000008 */
#define MDMA_CISR_BTIF MDMA_CISR_BTIF_Msk /*!< Channel x block transfer complete interrupt flag */
#define MDMA_CISR_TCIF_Pos (4U)
#define MDMA_CISR_TCIF_Msk (0x1U << MDMA_CISR_TCIF_Pos) /*!< 0x00000010 */
#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
#define MDMA_CISR_CRQA_Pos (16U)
#define MDMA_CISR_CRQA_Msk (0x1U << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
/******************** Bit definition for MDMA_CxIFCR register ****************/
#define MDMA_CIFCR_CTEIF_Pos (0U)
#define MDMA_CIFCR_CTEIF_Msk (0x1U << MDMA_CIFCR_CTEIF_Pos) /*!< 0x00000001 */
#define MDMA_CIFCR_CTEIF MDMA_CIFCR_CTEIF_Msk /*!< Channel x clear transfer error interrupt flag */
#define MDMA_CIFCR_CCTCIF_Pos (1U)
#define MDMA_CIFCR_CCTCIF_Msk (0x1U << MDMA_CIFCR_CCTCIF_Pos) /*!< 0x00000002 */
#define MDMA_CIFCR_CCTCIF MDMA_CIFCR_CCTCIF_Msk /*!< Clear Channel transfer complete interrupt flag for channel x */
#define MDMA_CIFCR_CBRTIF_Pos (2U)
#define MDMA_CIFCR_CBRTIF_Msk (0x1U << MDMA_CIFCR_CBRTIF_Pos) /*!< 0x00000004 */
#define MDMA_CIFCR_CBRTIF MDMA_CIFCR_CBRTIF_Msk /*!< Channel x clear block repeat transfer complete interrupt flag */
#define MDMA_CIFCR_CBTIF_Pos (3U)
#define MDMA_CIFCR_CBTIF_Msk (0x1U << MDMA_CIFCR_CBTIF_Pos) /*!< 0x00000008 */
#define MDMA_CIFCR_CBTIF MDMA_CIFCR_CBTIF_Msk /*!< Channel x Clear block transfer complete interrupt flag */
#define MDMA_CIFCR_CLTCIF_Pos (4U)
#define MDMA_CIFCR_CLTCIF_Msk (0x1U << MDMA_CIFCR_CLTCIF_Pos) /*!< 0x00000010 */
#define MDMA_CIFCR_CLTCIF MDMA_CIFCR_CLTCIF_Msk /*!< CLear Transfer buffer Complete Interrupt Flag for channel */
/******************** Bit definition for MDMA_CxESR register ****************/
#define MDMA_CESR_TEA_Pos (0U)
#define MDMA_CESR_TEA_Msk (0x7FU << MDMA_CESR_TEA_Pos) /*!< 0x0000007F */
#define MDMA_CESR_TEA MDMA_CESR_TEA_Msk /*!< Transfer Error Address */
#define MDMA_CESR_TED_Pos (7U)
#define MDMA_CESR_TED_Msk (0x1U << MDMA_CESR_TED_Pos) /*!< 0x00000080 */
#define MDMA_CESR_TED MDMA_CESR_TED_Msk /*!< Transfer Error Direction */
#define MDMA_CESR_TELD_Pos (8U)
#define MDMA_CESR_TELD_Msk (0x1U << MDMA_CESR_TELD_Pos) /*!< 0x00000100 */
#define MDMA_CESR_TELD MDMA_CESR_TELD_Msk /*!< Transfer Error Link Data */
#define MDMA_CESR_TEMD_Pos (9U)
#define MDMA_CESR_TEMD_Msk (0x1U << MDMA_CESR_TEMD_Pos) /*!< 0x00000200 */
#define MDMA_CESR_TEMD MDMA_CESR_TEMD_Msk /*!< Transfer Error Mask Data */
#define MDMA_CESR_ASE_Pos (10U)
#define MDMA_CESR_ASE_Msk (0x1U << MDMA_CESR_ASE_Pos) /*!< 0x00000400 */
#define MDMA_CESR_ASE MDMA_CESR_ASE_Msk /*!< Address/Size Error */
#define MDMA_CESR_BSE_Pos (11U)
#define MDMA_CESR_BSE_Msk (0x1U << MDMA_CESR_BSE_Pos) /*!< 0x00000800 */
#define MDMA_CESR_BSE MDMA_CESR_BSE_Msk /*!< Block Size Error */
/******************** Bit definition for MDMA_CxCR register ****************/
#define MDMA_CCR_EN_Pos (0U)
#define MDMA_CCR_EN_Msk (0x1U << MDMA_CCR_EN_Pos) /*!< 0x00000001 */
#define MDMA_CCR_EN MDMA_CCR_EN_Msk /*!< Channel enable / flag channel ready when read low */
#define MDMA_CCR_TEIE_Pos (1U)
#define MDMA_CCR_TEIE_Msk (0x1U << MDMA_CCR_TEIE_Pos) /*!< 0x00000002 */
#define MDMA_CCR_TEIE MDMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
#define MDMA_CCR_CTCIE_Pos (2U)
#define MDMA_CCR_CTCIE_Msk (0x1U << MDMA_CCR_CTCIE_Pos) /*!< 0x00000004 */
#define MDMA_CCR_CTCIE MDMA_CCR_CTCIE_Msk /*!< Channel Transfer Complete interrupt enable */
#define MDMA_CCR_BRTIE_Pos (3U)
#define MDMA_CCR_BRTIE_Msk (0x1U << MDMA_CCR_BRTIE_Pos) /*!< 0x00000008 */
#define MDMA_CCR_BRTIE MDMA_CCR_BRTIE_Msk /*!< Block Repeat transfer interrupt enable */
#define MDMA_CCR_BTIE_Pos (4U)
#define MDMA_CCR_BTIE_Msk (0x1U << MDMA_CCR_BTIE_Pos) /*!< 0x00000010 */
#define MDMA_CCR_BTIE MDMA_CCR_BTIE_Msk /*!< Block Transfer interrupt enable */
#define MDMA_CCR_TCIE_Pos (5U)
#define MDMA_CCR_TCIE_Msk (0x1U << MDMA_CCR_TCIE_Pos) /*!< 0x00000020 */
#define MDMA_CCR_TCIE MDMA_CCR_TCIE_Msk /*!< buffer Transfer Complete interrupt enable */
#define MDMA_CCR_PL_Pos (6U)
#define MDMA_CCR_PL_Msk (0x3U << MDMA_CCR_PL_Pos) /*!< 0x000000C0 */
#define MDMA_CCR_PL MDMA_CCR_PL_Msk /*!< Priority level */
#define MDMA_CCR_PL_0 (0x1U << MDMA_CCR_PL_Pos) /*!< 0x00000040 */
#define MDMA_CCR_PL_1 (0x2U << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
#define MDMA_CCR_SM_Pos (8U)
#define MDMA_CCR_SM_Msk (0x1U << MDMA_CCR_SM_Pos) /*!< 0x00000100 */
#define MDMA_CCR_SM MDMA_CCR_SM_Msk /*!< Secure Mode Eanble */
#define MDMA_CCR_BEX_Pos (12U)
#define MDMA_CCR_BEX_Msk (0x1U << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
#define MDMA_CCR_HEX_Pos (13U)
#define MDMA_CCR_HEX_Msk (0x1U << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
#define MDMA_CCR_WEX_Pos (14U)
#define MDMA_CCR_WEX_Msk (0x1U << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
#define MDMA_CCR_SWRQ_Pos (16U)
#define MDMA_CCR_SWRQ_Msk (0x1U << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
/******************** Bit definition for MDMA_CxTCR register ****************/
#define MDMA_CTCR_SINC_Pos (0U)
#define MDMA_CTCR_SINC_Msk (0x3U << MDMA_CTCR_SINC_Pos) /*!< 0x00000003 */
#define MDMA_CTCR_SINC MDMA_CTCR_SINC_Msk /*!< Source increment mode */
#define MDMA_CTCR_SINC_0 (0x1U << MDMA_CTCR_SINC_Pos) /*!< 0x00000001 */
#define MDMA_CTCR_SINC_1 (0x2U << MDMA_CTCR_SINC_Pos) /*!< 0x00000002 */
#define MDMA_CTCR_DINC_Pos (2U)
#define MDMA_CTCR_DINC_Msk (0x3U << MDMA_CTCR_DINC_Pos) /*!< 0x0000000C */
#define MDMA_CTCR_DINC MDMA_CTCR_DINC_Msk /*!< Source increment mode */
#define MDMA_CTCR_DINC_0 (0x1U << MDMA_CTCR_DINC_Pos) /*!< 0x00000004 */
#define MDMA_CTCR_DINC_1 (0x2U << MDMA_CTCR_DINC_Pos) /*!< 0x00000008 */
#define MDMA_CTCR_SSIZE_Pos (4U)
#define MDMA_CTCR_SSIZE_Msk (0x3U << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000030 */
#define MDMA_CTCR_SSIZE MDMA_CTCR_SSIZE_Msk /*!< Source data size */
#define MDMA_CTCR_SSIZE_0 (0x1U << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000010 */
#define MDMA_CTCR_SSIZE_1 (0x2U << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000020 */
#define MDMA_CTCR_DSIZE_Pos (6U)
#define MDMA_CTCR_DSIZE_Msk (0x3U << MDMA_CTCR_DSIZE_Pos) /*!< 0x000000C0 */
#define MDMA_CTCR_DSIZE MDMA_CTCR_DSIZE_Msk /*!< Destination data size */
#define MDMA_CTCR_DSIZE_0 (0x1U << MDMA_CTCR_DSIZE_Pos) /*!< 0x00000040 */
#define MDMA_CTCR_DSIZE_1 (0x2U << MDMA_CTCR_DSIZE_Pos) /*!< 0x00000080 */
#define MDMA_CTCR_SINCOS_Pos (8U)
#define MDMA_CTCR_SINCOS_Msk (0x3U << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000300 */
#define MDMA_CTCR_SINCOS MDMA_CTCR_SINCOS_Msk /*!< Source increment offset size */
#define MDMA_CTCR_SINCOS_0 (0x1U << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000100 */
#define MDMA_CTCR_SINCOS_1 (0x2U << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000200 */
#define MDMA_CTCR_DINCOS_Pos (10U)
#define MDMA_CTCR_DINCOS_Msk (0x3U << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000C00 */
#define MDMA_CTCR_DINCOS MDMA_CTCR_DINCOS_Msk /*!< Destination increment offset size */
#define MDMA_CTCR_DINCOS_0 (0x1U << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000400 */
#define MDMA_CTCR_DINCOS_1 (0x2U << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000800 */
#define MDMA_CTCR_SBURST_Pos (12U)
#define MDMA_CTCR_SBURST_Msk (0x7U << MDMA_CTCR_SBURST_Pos) /*!< 0x00007000 */
#define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */
#define MDMA_CTCR_SBURST_0 (0x1U << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */
#define MDMA_CTCR_SBURST_1 (0x2U << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */
#define MDMA_CTCR_SBURST_2 (0x3U << MDMA_CTCR_SBURST_Pos) /*!< 0x00003000 */
#define MDMA_CTCR_DBURST_Pos (15U)
#define MDMA_CTCR_DBURST_Msk (0x7U << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */
#define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */
#define MDMA_CTCR_DBURST_0 (0x1U << MDMA_CTCR_DBURST_Pos) /*!< 0x00008000 */
#define MDMA_CTCR_DBURST_1 (0x2U << MDMA_CTCR_DBURST_Pos) /*!< 0x00010000 */
#define MDMA_CTCR_DBURST_2 (0x4U << MDMA_CTCR_DBURST_Pos) /*!< 0x00020000 */
#define MDMA_CTCR_TLEN_Pos (18U)
#define MDMA_CTCR_TLEN_Msk (0x7FU << MDMA_CTCR_TLEN_Pos) /*!< 0x01FC0000 */
#define MDMA_CTCR_TLEN MDMA_CTCR_TLEN_Msk /*!< buffer Transfer Length (number of bytes - 1) */
#define MDMA_CTCR_PKE_Pos (25U)
#define MDMA_CTCR_PKE_Msk (0x1U << MDMA_CTCR_PKE_Pos) /*!< 0x02000000 */
#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
#define MDMA_CTCR_PAM_Pos (26U)
#define MDMA_CTCR_PAM_Msk (0x3U << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
#define MDMA_CTCR_PAM_0 (0x1U << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
#define MDMA_CTCR_PAM_1 (0x2U << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
#define MDMA_CTCR_TRGM_Pos (28U)
#define MDMA_CTCR_TRGM_Msk (0x3U << MDMA_CTCR_TRGM_Pos) /*!< 0x30000000 */
#define MDMA_CTCR_TRGM MDMA_CTCR_TRGM_Msk /*!< Trigger Mode */
#define MDMA_CTCR_TRGM_0 (0x1U << MDMA_CTCR_TRGM_Pos) /*!< 0x10000000 */
#define MDMA_CTCR_TRGM_1 (0x2U << MDMA_CTCR_TRGM_Pos) /*!< 0x20000000 */
#define MDMA_CTCR_SWRM_Pos (30U)
#define MDMA_CTCR_SWRM_Msk (0x1U << MDMA_CTCR_SWRM_Pos) /*!< 0x40000000 */
#define MDMA_CTCR_SWRM MDMA_CTCR_SWRM_Msk /*!< SW Request Mode */
#define MDMA_CTCR_BWM_Pos (31U)
#define MDMA_CTCR_BWM_Msk (0x1U << MDMA_CTCR_BWM_Pos) /*!< 0x80000000 */
#define MDMA_CTCR_BWM MDMA_CTCR_BWM_Msk /*!< Bufferable Write Mode */
/******************** Bit definition for MDMA_CxBNDTR register ****************/
#define MDMA_CBNDTR_BNDT_Pos (0U)
#define MDMA_CBNDTR_BNDT_Msk (0x1FFFFU << MDMA_CBNDTR_BNDT_Pos) /*!< 0x0001FFFF */
#define MDMA_CBNDTR_BNDT MDMA_CBNDTR_BNDT_Msk /*!< Block Number of data bytes to transfer */
#define MDMA_CBNDTR_BRSUM_Pos (18U)
#define MDMA_CBNDTR_BRSUM_Msk (0x1U << MDMA_CBNDTR_BRSUM_Pos) /*!< 0x00040000 */
#define MDMA_CBNDTR_BRSUM MDMA_CBNDTR_BRSUM_Msk /*!< Block Repeat Source address Update Mode */
#define MDMA_CBNDTR_BRDUM_Pos (19U)
#define MDMA_CBNDTR_BRDUM_Msk (0x1U << MDMA_CBNDTR_BRDUM_Pos) /*!< 0x00080000 */
#define MDMA_CBNDTR_BRDUM MDMA_CBNDTR_BRDUM_Msk /*!< Block Repeat Destination address Update Mode */
#define MDMA_CBNDTR_BRC_Pos (20U)
#define MDMA_CBNDTR_BRC_Msk (0xFFFU << MDMA_CBNDTR_BRC_Pos) /*!< 0xFFF00000 */
#define MDMA_CBNDTR_BRC MDMA_CBNDTR_BRC_Msk /*!< Block Repeat Count */
/******************** Bit definition for MDMA_CxSAR register ****************/
#define MDMA_CSAR_SAR_Pos (0U)
#define MDMA_CSAR_SAR_Msk (0xFFFFFFFFU << MDMA_CSAR_SAR_Pos) /*!< 0xFFFFFFFF */
#define MDMA_CSAR_SAR MDMA_CSAR_SAR_Msk /*!< Source address */
/******************** Bit definition for MDMA_CxDAR register ****************/
#define MDMA_CDAR_DAR_Pos (0U)
#define MDMA_CDAR_DAR_Msk (0xFFFFFFFFU << MDMA_CDAR_DAR_Pos) /*!< 0xFFFFFFFF */
#define MDMA_CDAR_DAR MDMA_CDAR_DAR_Msk /*!< Destination address */
/******************** Bit definition for MDMA_CxBRUR ************************/
#define MDMA_CBRUR_SUV_Pos (0U)
#define MDMA_CBRUR_SUV_Msk (0xFFFFU << MDMA_CBRUR_SUV_Pos) /*!< 0x0000FFFF */
#define MDMA_CBRUR_SUV MDMA_CBRUR_SUV_Msk /*!< Source address Update Value */
#define MDMA_CBRUR_DUV_Pos (16U)
#define MDMA_CBRUR_DUV_Msk (0xFFFFU << MDMA_CBRUR_DUV_Pos) /*!< 0xFFFF0000 */
#define MDMA_CBRUR_DUV MDMA_CBRUR_DUV_Msk /*!< Destination address Update Value */
/******************** Bit definition for MDMA_CxLAR *************************/
#define MDMA_CLAR_LAR_Pos (0U)
#define MDMA_CLAR_LAR_Msk (0xFFFFFFFFU << MDMA_CLAR_LAR_Pos) /*!< 0xFFFFFFFF */
#define MDMA_CLAR_LAR MDMA_CLAR_LAR_Msk /*!< Link Address Register */
/******************** Bit definition for MDMA_CxTBR) ************************/
#define MDMA_CTBR_TSEL_Pos (0U)
#define MDMA_CTBR_TSEL_Msk (0xFFU << MDMA_CTBR_TSEL_Pos) /*!< 0x000000FF */
#define MDMA_CTBR_TSEL MDMA_CTBR_TSEL_Msk /*!< Trigger SELection */
#define MDMA_CTBR_SBUS_Pos (16U)
#define MDMA_CTBR_SBUS_Msk (0x1U << MDMA_CTBR_SBUS_Pos) /*!< 0x00010000 */
#define MDMA_CTBR_SBUS MDMA_CTBR_SBUS_Msk /*!< Source BUS select */
#define MDMA_CTBR_DBUS_Pos (17U)
#define MDMA_CTBR_DBUS_Msk (0x1U << MDMA_CTBR_DBUS_Pos) /*!< 0x00020000 */
#define MDMA_CTBR_DBUS MDMA_CTBR_DBUS_Msk /*!< Destination BUS select */
/******************** Bit definition for MDMA_CxMAR) ************************/
#define MDMA_CMAR_MAR_Pos (0U)
#define MDMA_CMAR_MAR_Msk (0xFFFFFFFFU << MDMA_CMAR_MAR_Pos) /*!< 0xFFFFFFFF */
#define MDMA_CMAR_MAR MDMA_CMAR_MAR_Msk /*!< Mask address */
/******************** Bit definition for MDMA_CxMDR) ************************/
#define MDMA_CMDR_MDR_Pos (0U)
#define MDMA_CMDR_MDR_Msk (0xFFFFFFFFU << MDMA_CMDR_MDR_Pos) /*!< 0xFFFFFFFF */
#define MDMA_CMDR_MDR MDMA_CMDR_MDR_Msk /*!< Mask address */
/******************************************************************************/
/* */
/* Operational Amplifier (OPAMP) */
/* */
/******************************************************************************/
/********************* Bit definition for OPAMPx_CSR register ***************/
#define OPAMP_CSR_OPAMPxEN_Pos (0U)
#define OPAMP_CSR_OPAMPxEN_Msk (0x1U << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
#define OPAMP_CSR_FORCEVP_Pos (1U)
#define OPAMP_CSR_FORCEVP_Msk (0x1U << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */
#define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
#define OPAMP_CSR_VPSEL_Pos (2U)
#define OPAMP_CSR_VPSEL_Msk (0x3U << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */
#define OPAMP_CSR_VPSEL_0 (0x1U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
#define OPAMP_CSR_VPSEL_1 (0x2U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
#define OPAMP_CSR_VMSEL_Pos (5U)
#define OPAMP_CSR_VMSEL_Msk (0x3U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */
#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
#define OPAMP_CSR_VMSEL_0 (0x1U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */
#define OPAMP_CSR_VMSEL_1 (0x2U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */
#define OPAMP_CSR_OPAHSM_Pos (8U)
#define OPAMP_CSR_OPAHSM_Msk (0x1U << OPAMP_CSR_OPAHSM_Pos) /*!< 0x00000100 */
#define OPAMP_CSR_OPAHSM OPAMP_CSR_OPAHSM_Msk /*!< Operational amplifier high speed mode */
#define OPAMP_CSR_CALON_Pos (11U)
#define OPAMP_CSR_CALON_Msk (0x1U << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */
#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
#define OPAMP_CSR_CALSEL_Pos (12U)
#define OPAMP_CSR_CALSEL_Msk (0x3U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */
#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
#define OPAMP_CSR_CALSEL_0 (0x1U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */
#define OPAMP_CSR_CALSEL_1 (0x2U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
#define OPAMP_CSR_PGGAIN_Pos (14U)
#define OPAMP_CSR_PGGAIN_Msk (0xFU << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */
#define OPAMP_CSR_PGGAIN_0 (0x1U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */
#define OPAMP_CSR_PGGAIN_1 (0x2U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */
#define OPAMP_CSR_PGGAIN_2 (0x4U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */
#define OPAMP_CSR_PGGAIN_3 (0x8U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */
#define OPAMP_CSR_USERTRIM_Pos (18U)
#define OPAMP_CSR_USERTRIM_Msk (0x1U << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00040000 */
#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
#define OPAMP_CSR_TSTREF_Pos (29U)
#define OPAMP_CSR_TSTREF_Msk (0x1U << OPAMP_CSR_TSTREF_Pos) /*!< 0x20000000 */
#define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
#define OPAMP_CSR_CALOUT_Pos (30U)
#define OPAMP_CSR_CALOUT_Msk (0x1U << OPAMP_CSR_CALOUT_Pos) /*!< 0x40000000 */
#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier calibration output */
/********************* Bit definition for OPAMP1_CSR register ***************/
#define OPAMP1_CSR_OPAEN_Pos (0U)
#define OPAMP1_CSR_OPAEN_Msk (0x1U << OPAMP1_CSR_OPAEN_Pos) /*!< 0x00000001 */
#define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk /*!< Operational amplifier1 Enable */
#define OPAMP1_CSR_FORCEVP_Pos (1U)
#define OPAMP1_CSR_FORCEVP_Msk (0x1U << OPAMP1_CSR_FORCEVP_Pos) /*!< 0x00000002 */
#define OPAMP1_CSR_FORCEVP OPAMP1_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
#define OPAMP1_CSR_VPSEL_Pos (2U)
#define OPAMP1_CSR_VPSEL_Msk (0x3U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
#define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverted input selection */
#define OPAMP1_CSR_VPSEL_0 (0x1U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
#define OPAMP1_CSR_VPSEL_1 (0x2U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
#define OPAMP1_CSR_VMSEL_Pos (5U)
#define OPAMP1_CSR_VMSEL_Msk (0x3U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000060 */
#define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */
#define OPAMP1_CSR_VMSEL_0 (0x1U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000020 */
#define OPAMP1_CSR_VMSEL_1 (0x2U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000040 */
#define OPAMP1_CSR_OPAHSM_Pos (8U)
#define OPAMP1_CSR_OPAHSM_Msk (0x1U << OPAMP1_CSR_OPAHSM_Pos) /*!< 0x00000100 */
#define OPAMP1_CSR_OPAHSM OPAMP1_CSR_OPAHSM_Msk /*!< Operational amplifier1 high speed mode */
#define OPAMP1_CSR_CALON_Pos (11U)
#define OPAMP1_CSR_CALON_Msk (0x1U << OPAMP1_CSR_CALON_Pos) /*!< 0x00000800 */
#define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */
#define OPAMP1_CSR_CALSEL_Pos (12U)
#define OPAMP1_CSR_CALSEL_Msk (0x3U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00003000 */
#define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */
#define OPAMP1_CSR_CALSEL_0 (0x1U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00001000 */
#define OPAMP1_CSR_CALSEL_1 (0x2U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */
#define OPAMP1_CSR_PGGAIN_Pos (14U)
#define OPAMP1_CSR_PGGAIN_Msk (0xFU << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
#define OPAMP1_CSR_PGGAIN OPAMP1_CSR_PGGAIN_Msk /*!< Operational amplifier1 Programmable amplifier gain value */
#define OPAMP1_CSR_PGGAIN_0 (0x1U << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00004000 */
#define OPAMP1_CSR_PGGAIN_1 (0x2U << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00008000 */
#define OPAMP1_CSR_PGGAIN_2 (0x4U << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00010000 */
#define OPAMP1_CSR_PGGAIN_3 (0x8U << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00020000 */
#define OPAMP1_CSR_USERTRIM_Pos (18U)
#define OPAMP1_CSR_USERTRIM_Msk (0x1U << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00040000 */
#define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */
#define OPAMP1_CSR_TSTREF_Pos (29U)
#define OPAMP1_CSR_TSTREF_Msk (0x1U << OPAMP1_CSR_TSTREF_Pos) /*!< 0x20000000 */
#define OPAMP1_CSR_TSTREF OPAMP1_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
#define OPAMP1_CSR_CALOUT_Pos (30U)
#define OPAMP1_CSR_CALOUT_Msk (0x1U << OPAMP1_CSR_CALOUT_Pos) /*!< 0x40000000 */
#define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
/********************* Bit definition for OPAMP2_CSR register ***************/
#define OPAMP2_CSR_OPAEN_Pos (0U)
#define OPAMP2_CSR_OPAEN_Msk (0x1U << OPAMP2_CSR_OPAEN_Pos) /*!< 0x00000001 */
#define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk /*!< Operational amplifier2 Enable */
#define OPAMP2_CSR_FORCEVP_Pos (1U)
#define OPAMP2_CSR_FORCEVP_Msk (0x1U << OPAMP2_CSR_FORCEVP_Pos) /*!< 0x00000002 */
#define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
#define OPAMP2_CSR_VPSEL_Pos (2U)
#define OPAMP2_CSR_VPSEL_Msk (0x3U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x0000000C */
#define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverted input selection */
#define OPAMP2_CSR_VPSEL_0 (0x1U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000004 */
#define OPAMP2_CSR_VPSEL_1 (0x2U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000008 */
#define OPAMP2_CSR_VMSEL_Pos (5U)
#define OPAMP2_CSR_VMSEL_Msk (0x3U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000060 */
#define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */
#define OPAMP2_CSR_VMSEL_0 (0x1U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000020 */
#define OPAMP2_CSR_VMSEL_1 (0x2U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000040 */
#define OPAMP2_CSR_OPAHSM_Pos (8U)
#define OPAMP2_CSR_OPAHSM_Msk (0x1U << OPAMP2_CSR_OPAHSM_Pos) /*!< 0x00000100 */
#define OPAMP2_CSR_OPAHSM OPAMP2_CSR_OPAHSM_Msk /*!< Operational amplifier2 high speed mode */
#define OPAMP2_CSR_CALON_Pos (11U)
#define OPAMP2_CSR_CALON_Msk (0x1U << OPAMP2_CSR_CALON_Pos) /*!< 0x00000800 */
#define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */
#define OPAMP2_CSR_CALSEL_Pos (12U)
#define OPAMP2_CSR_CALSEL_Msk (0x3U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00003000 */
#define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */
#define OPAMP2_CSR_CALSEL_0 (0x1U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00001000 */
#define OPAMP2_CSR_CALSEL_1 (0x2U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */
#define OPAMP2_CSR_PGGAIN_Pos (14U)
#define OPAMP2_CSR_PGGAIN_Msk (0xFU << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
#define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk /*!< Operational amplifier2 Programmable amplifier gain value */
#define OPAMP2_CSR_PGGAIN_0 (0x1U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00004000 */
#define OPAMP2_CSR_PGGAIN_1 (0x2U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00008000 */
#define OPAMP2_CSR_PGGAIN_2 (0x4U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00010000 */
#define OPAMP2_CSR_PGGAIN_3 (0x8U << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00020000 */
#define OPAMP2_CSR_USERTRIM_Pos (18U)
#define OPAMP2_CSR_USERTRIM_Msk (0x1U << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00040000 */
#define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */
#define OPAMP2_CSR_TSTREF_Pos (29U)
#define OPAMP2_CSR_TSTREF_Msk (0x1U << OPAMP2_CSR_TSTREF_Pos) /*!< 0x20000000 */
#define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
#define OPAMP2_CSR_CALOUT_Pos (30U)
#define OPAMP2_CSR_CALOUT_Msk (0x1U << OPAMP2_CSR_CALOUT_Pos) /*!< 0x40000000 */
#define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk /*!< Operational amplifier2 calibration output */
/******************* Bit definition for OPAMP_OTR register ******************/
#define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
#define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
#define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
#define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
#define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
#define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
/******************* Bit definition for OPAMP1_OTR register ******************/
#define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
#define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
#define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
#define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
#define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
#define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
/******************* Bit definition for OPAMP2_OTR register ******************/
#define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
#define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
#define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
#define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
#define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
#define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
/******************* Bit definition for OPAMP_HSOTR register ****************/
#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos (0U)
#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk (0x1FU << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
#define OPAMP_HSOTR_TRIMHSOFFSETN OPAMP_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos (8U)
#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk (0x1FU << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
#define OPAMP_HSOTR_TRIMHSOFFSETP OPAMP_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
/******************* Bit definition for OPAMP1_HSOTR register ****************/
#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos (0U)
#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk (0x1FU << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
#define OPAMP1_HSOTR_TRIMHSOFFSETN OPAMP1_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos (8U)
#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk (0x1FU << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
#define OPAMP1_HSOTR_TRIMHSOFFSETP OPAMP1_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
/******************* Bit definition for OPAMP2_HSOTR register ****************/
#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos (0U)
#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk (0x1FU << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
#define OPAMP2_HSOTR_TRIMHSOFFSETN OPAMP2_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos (8U)
#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk (0x1FU << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
#define OPAMP2_HSOTR_TRIMHSOFFSETP OPAMP2_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
/******************************************************************************/
/* */
/* Power Control */
/* */
/******************************************************************************/
/******************** Bit definition for PWR_CR1 register ********************/
#define PWR_CR1_RESERVED3_Pos (19U)
#define PWR_CR1_RESERVED3_Msk (0x1FFFU << PWR_CR1_RESERVED3_Pos) /*!< 0xFFF80000 */
#define PWR_CR1_RESERVED3 PWR_CR1_RESERVED3_Msk /*!< Reserved, must be kept at reset value */
#define PWR_CR1_ALS_Pos (17U)
#define PWR_CR1_ALS_Msk (0x3U << PWR_CR1_ALS_Pos) /*!< 0x00060000 */
#define PWR_CR1_ALS PWR_CR1_ALS_Msk /*!< Analog Voltage Detector level selection */
#define PWR_CR1_AVDEN_Pos (16U)
#define PWR_CR1_AVDEN_Msk (0x1U << PWR_CR1_AVDEN_Pos) /*!< 0x00010000 */
#define PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk /*!< Peripheral Voltage Monitor on VDDA enable */
#define PWR_CR1_RESERVED2_Pos (11U)
#define PWR_CR1_RESERVED2_Msk (0x1FU << PWR_CR1_RESERVED2_Pos) /*!< 0x0000F800 */
#define PWR_CR1_RESERVED2 PWR_CR1_RESERVED2_Msk /*!< Reserved, must be kept at reset value */
#define PWR_CR1_RESERVED1_Pos (9U)
#define PWR_CR1_RESERVED1_Msk (0x1U << PWR_CR1_RESERVED1_Pos) /*!< 0x00000200 */
#define PWR_CR1_RESERVED1 PWR_CR1_RESERVED1_Msk /*!< Reserved, must be kept at reset value */
#define PWR_CR1_DBP_Pos (8U)
#define PWR_CR1_DBP_Msk (0x1U << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
#define PWR_CR1_PLS_Pos (5U)
#define PWR_CR1_PLS_Msk (0x7U << PWR_CR1_PLS_Pos) /*!< 0x000000E0 */
#define PWR_CR1_PLS PWR_CR1_PLS_Msk /*!< Programmable Voltage Detector level selection */
#define PWR_CR1_PVDEN_Pos (4U)
#define PWR_CR1_PVDEN_Msk (0x1U << PWR_CR1_PVDEN_Pos) /*!< 0x00000010 */
#define PWR_CR1_PVDEN PWR_CR1_PVDEN_Msk /*!< Programmable Voltage detector enable */
#define PWR_CR1_RESERVED0_Pos (3U)
#define PWR_CR1_RESERVED0_Msk (0x1U << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */
#define PWR_CR1_RESERVED0 PWR_CR1_RESERVED0_Msk /*!< Reserved, must be kept at reset value */
#define PWR_CR1_LVDS_Pos (2U)
#define PWR_CR1_LVDS_Msk (0x1U << PWR_CR1_LVDS_Pos) /*!< 0x00000004 */
#define PWR_CR1_LVDS PWR_CR1_LVDS_Msk /*!< Low Voltage Deepsleep LP-STOP mode selection */
#define PWR_CR1_LPCFG_Pos (1U)
#define PWR_CR1_LPCFG_Msk (0x1U << PWR_CR1_LPCFG_Pos) /*!< 0x00000002 */
#define PWR_CR1_LPCFG PWR_CR1_LPCFG_Msk /*!< PWR_ON pin configuration */
#define PWR_CR1_LPDS_Pos (0U)
#define PWR_CR1_LPDS_Msk (0x1U << PWR_CR1_LPDS_Pos) /*!< 0x00000001 */
#define PWR_CR1_LPDS PWR_CR1_LPDS_Msk /*!< Low Power Deepsleep STOP mode selection */
/*!< AVD level configuration */
#define PWR_CR1_ALS_LEV0 ((uint32_t)0x00000000) /*!< AVD level 0 */
#define PWR_CR1_ALS_LEV1_Pos (17U)
#define PWR_CR1_ALS_LEV1_Msk (0x1U << PWR_CR1_ALS_LEV1_Pos) /*!< 0x00020000 */
#define PWR_CR1_ALS_LEV1 PWR_CR1_ALS_LEV1_Msk /*!< AVD level 1 */
#define PWR_CR1_ALS_LEV2_Pos (18U)
#define PWR_CR1_ALS_LEV2_Msk (0x1U << PWR_CR1_ALS_LEV2_Pos) /*!< 0x00040000 */
#define PWR_CR1_ALS_LEV2 PWR_CR1_ALS_LEV2_Msk /*!< AVD level 2 */
#define PWR_CR1_ALS_LEV3_Pos (17U)
#define PWR_CR1_ALS_LEV3_Msk (0x3U << PWR_CR1_ALS_LEV3_Pos) /*!< 0x00060000 */
#define PWR_CR1_ALS_LEV3 PWR_CR1_ALS_LEV3_Msk /*!< AVD level 3 */
/*!< PVD level configuration */
#define PWR_CR1_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
#define PWR_CR1_PLS_LEV1_Pos (5U)
#define PWR_CR1_PLS_LEV1_Msk (0x1U << PWR_CR1_PLS_LEV1_Pos) /*!< 0x00000020 */
#define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk /*!< PVD level 1 */
#define PWR_CR1_PLS_LEV2_Pos (6U)
#define PWR_CR1_PLS_LEV2_Msk (0x1U << PWR_CR1_PLS_LEV2_Pos) /*!< 0x00000040 */
#define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk /*!< PVD level 2 */
#define PWR_CR1_PLS_LEV3_Pos (5U)
#define PWR_CR1_PLS_LEV3_Msk (0x3U << PWR_CR1_PLS_LEV3_Pos) /*!< 0x00000060 */
#define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk /*!< PVD level 3 */
#define PWR_CR1_PLS_LEV4_Pos (7U)
#define PWR_CR1_PLS_LEV4_Msk (0x1U << PWR_CR1_PLS_LEV4_Pos) /*!< 0x00000080 */
#define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk /*!< PVD level 4 */
#define PWR_CR1_PLS_LEV5_Pos (5U)
#define PWR_CR1_PLS_LEV5_Msk (0x5U << PWR_CR1_PLS_LEV5_Pos) /*!< 0x000000A0 */
#define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk /*!< PVD level 5 */
#define PWR_CR1_PLS_LEV6_Pos (6U)
#define PWR_CR1_PLS_LEV6_Msk (0x3U << PWR_CR1_PLS_LEV6_Pos) /*!< 0x000000C0 */
#define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk /*!< PVD level 6 */
#define PWR_CR1_PLS_LEV7_Pos (5U)
#define PWR_CR1_PLS_LEV7_Msk (0x7U << PWR_CR1_PLS_LEV7_Pos) /*!< 0x000000E0 */
#define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk /*!< PVD level 7 */
/******************** Bit definition for PWR_CSR1 register ********************/
#define PWR_CSR1_AVDO_Pos (16U)
#define PWR_CSR1_AVDO_Msk (0x1U << PWR_CSR1_AVDO_Pos) /*!< 0x00010000 */
#define PWR_CSR1_AVDO PWR_CSR1_AVDO_Msk /*!< Analog Voltage detector Output on VDDA */
#define PWR_CSR1_PVDO_Pos (4U)
#define PWR_CSR1_PVDO_Msk (0x1U << PWR_CSR1_PVDO_Pos) /*!< 0x00000010 */
#define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk /*!< Programmable Voltage Detect Output */
/******************** Bit definition for PWR_CR2 register ********************/
#define PWR_CR2_BREN_Pos (0U)
#define PWR_CR2_BREN_Msk (0x1U << PWR_CR2_BREN_Pos) /*!< 0x00000001 */
#define PWR_CR2_BREN PWR_CR2_BREN_Msk /*!< Backup regulator enable */
#define PWR_CR2_RREN_Pos (1U)
#define PWR_CR2_RREN_Msk (0x1U << PWR_CR2_RREN_Pos) /*!< 0x00000002 */
#define PWR_CR2_RREN PWR_CR2_RREN_Msk /*!< Retention Regulator enable */
#define PWR_CR2_MONEN_Pos (4U)
#define PWR_CR2_MONEN_Msk (0x1U << PWR_CR2_MONEN_Pos) /*!< 0x00000010 */
#define PWR_CR2_MONEN PWR_CR2_MONEN_Msk /*!< VBAT and temperature monitoring enable */
#define PWR_CR2_BRRDY_Pos (16U)
#define PWR_CR2_BRRDY_Msk (0x1U << PWR_CR2_BRRDY_Pos) /*!< 0x00010000 */
#define PWR_CR2_BRRDY PWR_CR2_BRRDY_Msk /*!< Backup Regulator ready */
#define PWR_CR2_RRRDY_Pos (17U)
#define PWR_CR2_RRRDY_Msk (0x1U << PWR_CR2_RRRDY_Pos) /*!< 0x00020000 */
#define PWR_CR2_RRRDY PWR_CR2_RRRDY_Msk /*!< Retention Regulator ready */
#define PWR_CR2_VBATL_Pos (20U)
#define PWR_CR2_VBATL_Msk (0x1U << PWR_CR2_VBATL_Pos) /*!< 0x00100000 */
#define PWR_CR2_VBATL PWR_CR2_VBATL_Msk /*!< Monitored VBAT level equal or below low threshold */
#define PWR_CR2_VBATH_Pos (21U)
#define PWR_CR2_VBATH_Msk (0x1U << PWR_CR2_VBATH_Pos) /*!< 0x00200000 */
#define PWR_CR2_VBATH PWR_CR2_VBATH_Msk /*!< Monitored VBAT level equal or above high threshold */
#define PWR_CR2_TEMPL_Pos (22U)
#define PWR_CR2_TEMPL_Msk (0x1U << PWR_CR2_TEMPL_Pos) /*!< 0x00300000 */
#define PWR_CR2_TEMPL PWR_CR2_TEMPL_Msk /*!< Monitored temperature level equal or below low threshold */
#define PWR_CR2_TEMPH_Pos (23U)
#define PWR_CR2_TEMPH_Msk (0x1U << PWR_CR2_TEMPH_Pos) /*!< 0x00400000 */
#define PWR_CR2_TEMPH PWR_CR2_TEMPH_Msk /*!< Monitored temperature level equal or below high threshold */
/******************** Bit definition for PWR_CR3 register ********************/
#define PWR_CR3_VBE_Pos (8U)
#define PWR_CR3_VBE_Msk (0x1U << PWR_CR3_VBE_Pos) /*!< 0x00000100 */
#define PWR_CR3_VBE PWR_CR3_VBE_Msk /*!< VBAT charging enable */
#define PWR_CR3_VBRS_Pos (9U)
#define PWR_CR3_VBRS_Msk (0x1U << PWR_CR3_VBRS_Pos) /*!< 0x00000200 */
#define PWR_CR3_VBRS PWR_CR3_VBRS_Msk /*!< VBAT charging resistor selection */
#define PWR_CR3_DDRSREN_Pos (10U)
#define PWR_CR3_DDRSREN_Msk (0x1U << PWR_CR3_DDRSREN_Pos) /*!< 0x00000400 */
#define PWR_CR3_DDRSREN PWR_CR3_DDRSREN_Msk /*!< DDR self-refresh in standby mode enable */
#define PWR_CR3_DDRSRDIS_Pos (11U)
#define PWR_CR3_DDRSRDIS_Msk (0x1U << PWR_CR3_DDRSRDIS_Pos) /*!< 0x00000800 */
#define PWR_CR3_DDRSRDIS PWR_CR3_DDRSRDIS_Msk /*!< DDR self-refresh retention after standby disable */
#define PWR_CR3_DDRRETEN_Pos (12U)
#define PWR_CR3_DDRRETEN_Msk (0x1U << PWR_CR3_DDRRETEN_Pos) /*!< 0x00001000 */
#define PWR_CR3_DDRRETEN PWR_CR3_DDRRETEN_Msk /*!< DDR retention enable */
#define PWR_CR3_POPL_Pos (17U)
#define PWR_CR3_POPL_Msk (0x1FU << PWR_CR3_POPL_Pos) /*!< 0x003E0000 */
#define PWR_CR3_POPL PWR_CR3_POPL_Msk /*!< PWR_ON pulse low configuration */
#define PWR_CR3_USB33DEN_Pos (24U)
#define PWR_CR3_USB33DEN_Msk (0x1U << PWR_CR3_USB33DEN_Pos) /*!< 0x01000000 */
#define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk /*!< USB33DEN: USB 3.3V voltage level detector enable */
#define PWR_CR3_USB33RDY_Pos (26U)
#define PWR_CR3_USB33RDY_Msk (0x1U << PWR_CR3_USB33RDY_Pos) /*!< 0x04000000 */
#define PWR_CR3_USB33RDY PWR_CR3_USB33RDY_Msk /*!< USB 3.3V supply ready */
#define PWR_CR3_REG18EN_Pos (28U)
#define PWR_CR3_REG18EN_Msk (0x1U << PWR_CR3_REG18EN_Pos) /*!< 0x10000000 */
#define PWR_CR3_REG18EN PWR_CR3_REG18EN_Msk /*!< 1V8 regulator enable */
#define PWR_CR3_REG18RDY_Pos (29U)
#define PWR_CR3_REG18RDY_Msk (0x1U << PWR_CR3_REG18RDY_Pos) /*!< 0x20000000 */
#define PWR_CR3_REG18RDY PWR_CR3_REG18RDY_Msk /*!< 1V8 regulator supply ready */
#define PWR_CR3_REG11EN_Pos (30U)
#define PWR_CR3_REG11EN_Msk (0x1U << PWR_CR3_REG11EN_Pos) /*!< 0x40000000 */
#define PWR_CR3_REG11EN PWR_CR3_REG11EN_Msk /*!< 1V1 regulator enable */
#define PWR_CR3_REG11RDY_Pos (31U)
#define PWR_CR3_REG11RDY_Msk (0x1U << PWR_CR3_REG11RDY_Pos) /*!< 0x80000000 */
#define PWR_CR3_REG11RDY PWR_CR3_REG11RDY_Msk /*!< 1V1 regulator supply ready */
/******************** Bit definition for PWR_MPUCR register ********************/
#define PWR_MPUCR_PDDS_Pos (0U)
#define PWR_MPUCR_PDDS_Msk (0x1U << PWR_MPUCR_PDDS_Pos) /*!< 0x00000001 */
#define PWR_MPUCR_PDDS PWR_MPUCR_PDDS_Msk /*!< System Power Down Deepsleep selection */
#define PWR_MPUCR_CSTBYDIS_Pos (3U)
#define PWR_MPUCR_CSTBYDIS_Msk (0x1U << PWR_MPUCR_CSTBYDIS_Pos) /*!< 0x00000008 */
#define PWR_MPUCR_CSTBYDIS PWR_MPUCR_CSTBYDIS_Msk /*!< MPU CStandby mode disable */
#define PWR_MPUCR_STOPF_Pos (5U)
#define PWR_MPUCR_STOPF_Msk (0x1U << PWR_MPUCR_STOPF_Pos) /*!< 0x00000020 */
#define PWR_MPUCR_STOPF PWR_MPUCR_STOPF_Msk /*!< Stop Flag */
#define PWR_MPUCR_SBF_Pos (6U)
#define PWR_MPUCR_SBF_Msk (0x1U << PWR_MPUCR_SBF_Pos) /*!< 0x00000040 */
#define PWR_MPUCR_SBF PWR_MPUCR_SBF_Msk /*!< System Standby Flag */
#define PWR_MPUCR_SBF_MPU_Pos (7U)
#define PWR_MPUCR_SBF_MPU_Msk (0x1U << PWR_MPUCR_SBF_MPU_Pos) /*!< 0x00000080 */
#define PWR_MPUCR_SBF_MPU PWR_MPUCR_SBF_MPU_Msk /*!< MPU Standby Flag */
#define PWR_MPUCR_CSSF_Pos (9U)
#define PWR_MPUCR_CSSF_Msk (0x1U << PWR_MPUCR_CSSF_Pos) /*!< 0x00000200 */
#define PWR_MPUCR_CSSF PWR_MPUCR_CSSF_Msk /*!< Clear MCU STANDBY, STOP and HOLD flags.(always read as 0) */
#define PWR_MPUCR_STANDBYWFIL2_Pos (15U)
#define PWR_MPUCR_STANDBYWFIL2_Msk (0x1U << PWR_MPUCR_STANDBYWFIL2_Pos) /*!< 0x00008000 */
#define PWR_MPUCR_STANDBYWFIL2 PWR_MPUCR_STANDBYWFIL2_Msk /*!< MPU system idle indication */
/******************** Bit definition for PWR_MCUCR register ********************/
#define PWR_MCUCR_PDDS_Pos (0U)
#define PWR_MCUCR_PDDS_Msk (0x1U << PWR_MCUCR_PDDS_Pos) /*!< 0x00000001 */
#define PWR_MCUCR_PDDS PWR_MCUCR_PDDS_Msk /*!< System Power Down Deepsleep selection */
#define PWR_MCUCR_STOPF_Pos (5U)
#define PWR_MCUCR_STOPF_Msk (0x1U << PWR_MCUCR_STOPF_Pos) /*!< 0x00000020 */
#define PWR_MCUCR_STOPF PWR_MCUCR_STOPF_Msk /*!< Stop Flag */
#define PWR_MCUCR_SBF_Pos (6U)
#define PWR_MCUCR_SBF_Msk (0x1U << PWR_MCUCR_SBF_Pos) /*!< 0x00000040 */
#define PWR_MCUCR_SBF PWR_MCUCR_SBF_Msk /*!< System Standby Flag */
#define PWR_MCUCR_CSSF_Pos (9U)
#define PWR_MCUCR_CSSF_Msk (0x1U << PWR_MCUCR_CSSF_Pos) /*!< 0x00000200 */
#define PWR_MCUCR_CSSF PWR_MCUCR_CSSF_Msk /*!< Clear MCU Standby, Stop flags */
#define PWR_MCUCR_DEEPSLEEP_Pos (15U)
#define PWR_MCUCR_DEEPSLEEP_Msk (0x1U << PWR_MCUCR_DEEPSLEEP_Pos) /*!< 0x00008000 */
#define PWR_MCUCR_DEEPSLEEP PWR_MCUCR_DEEPSLEEP_Msk /*!< MCU system idle indication */
/******************** Bit definition for PWR_WKUPCR register ********************/
#define PWR_WKUPCR_WKUPPUPD_Pos (16U)
#define PWR_WKUPCR_WKUPPUPD_Msk (0xFFFU << PWR_WKUPCR_WKUPPUPD_Pos) /*!< 0x0FFF0000 */
#define PWR_WKUPCR_WKUPPUPD PWR_WKUPCR_WKUPPUPD_Msk /*!< Wakeup Pin pull configuration mask*/
#define PWR_WKUPCR_WKUPPUPD6_Pos (26U)
#define PWR_WKUPCR_WKUPPUPD6_Msk (0x3U << PWR_WKUPCR_WKUPPUPD6_Pos) /*!< 0x0C000000 */
#define PWR_WKUPCR_WKUPPUPD6 PWR_WKUPCR_WKUPPUPD6_Msk /*!< Wakeup Pin pull configuration for WKUP6 */
#define PWR_WKUPCR_WKUPPUPD6_0 (0x1U << PWR_WKUPCR_WKUPPUPD6_Pos) /*!< 0x04000000 */
#define PWR_WKUPCR_WKUPPUPD6_1 (0x2U << PWR_WKUPCR_WKUPPUPD6_Pos) /*!< 0x08000000 */
#define PWR_WKUPCR_WKUPPUPD5_Pos (24U)
#define PWR_WKUPCR_WKUPPUPD5_Msk (0x3U << PWR_WKUPCR_WKUPPUPD5_Pos) /*!< 0x03000000 */
#define PWR_WKUPCR_WKUPPUPD5 PWR_WKUPCR_WKUPPUPD5_Msk /*!< Wakeup Pin pull configuration for WKUP5 */
#define PWR_WKUPCR_WKUPPUPD5_0 (0x1U << PWR_WKUPCR_WKUPPUPD5_Pos) /*!< 0x01000000 */
#define PWR_WKUPCR_WKUPPUPD5_1 (0x2U << PWR_WKUPCR_WKUPPUPD5_Pos) /*!< 0x02000000 */
#define PWR_WKUPCR_WKUPPUPD4_Pos (22U)
#define PWR_WKUPCR_WKUPPUPD4_Msk (0x3U << PWR_WKUPCR_WKUPPUPD4_Pos) /*!< 0x00C00000 */
#define PWR_WKUPCR_WKUPPUPD4 PWR_WKUPCR_WKUPPUPD4_Msk /*!< Wakeup Pin pull configuration for WKUP4 */
#define PWR_WKUPCR_WKUPPUPD4_0 (0x1U << PWR_WKUPCR_WKUPPUPD4_Pos) /*!< 0x00400000 */
#define PWR_WKUPCR_WKUPPUPD4_1 (0x2U << PWR_WKUPCR_WKUPPUPD4_Pos) /*!< 0x00800000 */
#define PWR_WKUPCR_WKUPPUPD3_Pos (20U)
#define PWR_WKUPCR_WKUPPUPD3_Msk (0x3U << PWR_WKUPCR_WKUPPUPD3_Pos) /*!< 0x00300000 */
#define PWR_WKUPCR_WKUPPUPD3 PWR_WKUPCR_WKUPPUPD3_Msk /*!< Wakeup Pin pull configuration for WKUP3 */
#define PWR_WKUPCR_WKUPPUPD3_0 (0x1U << PWR_WKUPCR_WKUPPUPD3_Pos) /*!< 0x00100000 */
#define PWR_WKUPCR_WKUPPUPD3_1 (0x2U << PWR_WKUPCR_WKUPPUPD3_Pos) /*!< 0x00200000 */
#define PWR_WKUPCR_WKUPPUPD2_Pos (18U)
#define PWR_WKUPCR_WKUPPUPD2_Msk (0x3U << PWR_WKUPCR_WKUPPUPD2_Pos) /*!< 0x000C0000 */
#define PWR_WKUPCR_WKUPPUPD2 PWR_WKUPCR_WKUPPUPD2_Msk /*!< Wakeup Pin pull configuration for WKUP2 */
#define PWR_WKUPCR_WKUPPUPD2_0 (0x1U << PWR_WKUPCR_WKUPPUPD2_Pos) /*!< 0x00040000 */
#define PWR_WKUPCR_WKUPPUPD2_1 (0x2U << PWR_WKUPCR_WKUPPUPD2_Pos) /*!< 0x00080000 */
#define PWR_WKUPCR_WKUPPUPD1_Pos (16U)
#define PWR_WKUPCR_WKUPPUPD1_Msk (0x3U << PWR_WKUPCR_WKUPPUPD1_Pos) /*!< 0x00030000 */
#define PWR_WKUPCR_WKUPPUPD1 PWR_WKUPCR_WKUPPUPD1_Msk /*!< Wakeup Pin pull configuration for WKUP1 */
#define PWR_WKUPCR_WKUPPUPD1_0 (0x1U << PWR_WKUPCR_WKUPPUPD1_Pos) /*!< 0x00010000 */
#define PWR_WKUPCR_WKUPPUPD1_1 (0x2U << PWR_WKUPCR_WKUPPUPD1_Pos) /*!< 0x00020000 */
#define PWR_WKUPCR_WKUPP_Pos (8U)
#define PWR_WKUPCR_WKUPP_Msk (0x3FU << PWR_WKUPCR_WKUPP_Pos) /*!< 0x00003F00 */
#define PWR_WKUPCR_WKUPP PWR_WKUPCR_WKUPP_Msk /*!< Wakeup Pin Polarity mask*/
#define PWR_WKUPCR_WKUPP_6 (0x20U << PWR_WKUPCR_WKUPP_Pos) /*!< 0x00002000 */
#define PWR_WKUPCR_WKUPP_5 (0x10U << PWR_WKUPCR_WKUPP_Pos) /*!< 0x00001000 */
#define PWR_WKUPCR_WKUPP_4 (0x08U << PWR_WKUPCR_WKUPP_Pos) /*!< 0x00000800 */
#define PWR_WKUPCR_WKUPP_3 (0x04U << PWR_WKUPCR_WKUPP_Pos) /*!< 0x00000400 */
#define PWR_WKUPCR_WKUPP_2 (0x02U << PWR_WKUPCR_WKUPP_Pos) /*!< 0x00000200 */
#define PWR_WKUPCR_WKUPP_1 (0x01U << PWR_WKUPCR_WKUPP_Pos) /*!< 0x00000100 */
#define PWR_WKUPCR_WKUPC_Pos (0U)
#define PWR_WKUPCR_WKUPC_Msk (0x3FU << PWR_WKUPCR_WKUPC_Pos) /*!< 0x0000003F */
#define PWR_WKUPCR_WKUPC PWR_WKUPCR_WKUPC_Msk /*!< Wakeup Pin Mask */
#define PWR_WKUPCR_WKUPC6_Pos (5U)
#define PWR_WKUPCR_WKUPC6_Msk (0x1U << PWR_WKUPCR_WKUPC6_Pos) /*!< 0x00000020 */
#define PWR_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6_Msk /*!< Clear Wakeup Pin Flag 6 */
#define PWR_WKUPCR_WKUPC5_Pos (4U)
#define PWR_WKUPCR_WKUPC5_Msk (0x1U << PWR_WKUPCR_WKUPC5_Pos) /*!< 0x00000010 */
#define PWR_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5_Msk /*!< Clear Wakeup Pin Flag 5 */
#define PWR_WKUPCR_WKUPC4_Pos (3U)
#define PWR_WKUPCR_WKUPC4_Msk (0x1U << PWR_WKUPCR_WKUPC4_Pos) /*!< 0x00000008 */
#define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk /*!< Clear Wakeup Pin Flag 4 */
#define PWR_WKUPCR_WKUPC3_Pos (2U)
#define PWR_WKUPCR_WKUPC3_Msk (0x1U << PWR_WKUPCR_WKUPC3_Pos) /*!< 0x00000004 */
#define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk /*!< Clear Wakeup Pin Flag 3 */
#define PWR_WKUPCR_WKUPC2_Pos (1U)
#define PWR_WKUPCR_WKUPC2_Msk (0x1U << PWR_WKUPCR_WKUPC2_Pos) /*!< 0x00000002 */
#define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk /*!< Clear Wakeup Pin Flag 2 */
#define PWR_WKUPCR_WKUPC1_Pos (0U)
#define PWR_WKUPCR_WKUPC1_Msk (0x1U << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */
#define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Pin Flag 1 */
/******************** Bit definition for PWR_WKUPFR register ********************/
#define PWR_WKUPFR_WKUPF6_Pos (5U)
#define PWR_WKUPFR_WKUPF6_Msk (0x1U << PWR_WKUPFR_WKUPF6_Pos) /*!< 0x00000020 */
#define PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6_Msk /*!< Wakeup Pin Flag 6 */
#define PWR_WKUPFR_WKUPF5_Pos (4U)
#define PWR_WKUPFR_WKUPF5_Msk (0x1U << PWR_WKUPFR_WKUPF5_Pos) /*!< 0x00000010 */
#define PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5_Msk /*!< Wakeup Pin Flag 5 */
#define PWR_WKUPFR_WKUPF4_Pos (3U)
#define PWR_WKUPFR_WKUPF4_Msk (0x1U << PWR_WKUPFR_WKUPF4_Pos) /*!< 0x00000008 */
#define PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4_Msk /*!< Wakeup Pin Flag 4 */
#define PWR_WKUPFR_WKUPF3_Pos (2U)
#define PWR_WKUPFR_WKUPF3_Msk (0x1U << PWR_WKUPFR_WKUPF3_Pos) /*!< 0x00000004 */
#define PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3_Msk /*!< Wakeup Pin Flag 3 */
#define PWR_WKUPFR_WKUPF2_Pos (1U)
#define PWR_WKUPFR_WKUPF2_Msk (0x1U << PWR_WKUPFR_WKUPF2_Pos) /*!< 0x00000002 */
#define PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2_Msk /*!< Wakeup Pin Flag 2 */
#define PWR_WKUPFR_WKUPF1_Pos (0U)
#define PWR_WKUPFR_WKUPF1_Msk (0x1U << PWR_WKUPFR_WKUPF1_Pos) /*!< 0x00000001 */
#define PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk /*!< Wakeup Pin Flag 1 */
/******************** Bit definition for PWR_MPUWKUPENR register ********************/
#define PWR_MPUWKUPENR_WKUPEN_Pos (0U)
#define PWR_MPUWKUPENR_WKUPEN_Msk (0x3FU << PWR_MPUWKUPENR_WKUPEN_Pos) /*!< 0x0000003F */
#define PWR_MPUWKUPENR_WKUPEN PWR_MPUWKUPENR_WKUPEN_Msk /*!< Enable Wakeup and interrupt for CPU1 */
#define PWR_MPUWKUPENR_WKUPEN_6 (0x20U << PWR_MPUWKUPENR_WKUPEN_Pos) /*!< 0x00000020 */
#define PWR_MPUWKUPENR_WKUPEN_5 (0x10U << PWR_MPUWKUPENR_WKUPEN_Pos) /*!< 0x00000010 */
#define PWR_MPUWKUPENR_WKUPEN_4 (0x08U << PWR_MPUWKUPENR_WKUPEN_Pos) /*!< 0x00000008 */
#define PWR_MPUWKUPENR_WKUPEN_3 (0x04U << PWR_MPUWKUPENR_WKUPEN_Pos) /*!< 0x00000004 */
#define PWR_MPUWKUPENR_WKUPEN_2 (0x02U << PWR_MPUWKUPENR_WKUPEN_Pos) /*!< 0x00000002 */
#define PWR_MPUWKUPENR_WKUPEN_1 (0x01U << PWR_MPUWKUPENR_WKUPEN_Pos) /*!< 0x00000001 */
/******************** Bit definition for PWR_MCUWKUPENR register ********************/
#define PWR_MCUWKUPENR_WKUPEN_Pos (0U)
#define PWR_MCUWKUPENR_WKUPEN_Msk (0x3FU << PWR_MCUWKUPENR_WKUPEN_Pos) /*!< 0x0000003F */
#define PWR_MCUWKUPENR_WKUPEN PWR_MCUWKUPENR_WKUPEN_Msk /*!< Enable Wakeup and interrupt for CPU2 */
#define PWR_MCUWKUPENR_WKUPEN6_Pos (5U)
#define PWR_MCUWKUPENR_WKUPEN6_Msk (0x1U << PWR_MCUWKUPENR_WKUPEN6_Pos) /*!< 0x00000020 */
#define PWR_MCUWKUPENR_WKUPEN6 PWR_MCUWKUPENR_WKUPEN6_Msk /*!< Enable Wakeup WKUP6 pin and interrupt for CPU2 */
#define PWR_MCUWKUPENR_WKUPEN5_Pos (4U)
#define PWR_MCUWKUPENR_WKUPEN5_Msk (0x1U << PWR_MCUWKUPENR_WKUPEN5_Pos) /*!< 0x00000010 */
#define PWR_MCUWKUPENR_WKUPEN5 PWR_MCUWKUPENR_WKUPEN5_Msk /*!< Enable Wakeup WKUP5 pin and interrupt for CPU2 */
#define PWR_MCUWKUPENR_WKUPEN4_Pos (3U)
#define PWR_MCUWKUPENR_WKUPEN4_Msk (0x1U << PWR_MCUWKUPENR_WKUPEN4_Pos) /*!< 0x00000008 */
#define PWR_MCUWKUPENR_WKUPEN4 PWR_MCUWKUPENR_WKUPEN4_Msk /*!< Enable Wakeup WKUP4 pin and interrupt for CPU2 */
#define PWR_MCUWKUPENR_WKUPEN3_Pos (2U)
#define PWR_MCUWKUPENR_WKUPEN3_Msk (0x1U << PWR_MCUWKUPENR_WKUPEN3_Pos) /*!< 0x00000004 */
#define PWR_MCUWKUPENR_WKUPEN3 PWR_MCUWKUPENR_WKUPEN3_Msk /*!< Enable Wakeup WKUP3 pin and interrupt for CPU2 */
#define PWR_MCUWKUPENR_WKUPEN2_Pos (1U)
#define PWR_MCUWKUPENR_WKUPEN2_Msk (0x1U << PWR_MCUWKUPENR_WKUPEN2_Pos) /*!< 0x00000002 */
#define PWR_MCUWKUPENR_WKUPEN2 PWR_MCUWKUPENR_WKUPEN2_Msk /*!< Enable Wakeup WKUP2 pin and interrupt for CPU2 */
#define PWR_MCUWKUPENR_WKUPEN1_Pos (0U)
#define PWR_MCUWKUPENR_WKUPEN1_Msk (0x1U << PWR_MCUWKUPENR_WKUPEN1_Pos) /*!< 0x00000001 */
#define PWR_MCUWKUPENR_WKUPEN1 PWR_MCUWKUPENR_WKUPEN1_Msk /*!< Enable Wakeup WKUP1 pin and interrupt for CPU2 */
/******************** Bit definition for PWR_VER register ********************/
#define PWR_VER_MAJREV_Pos (4U)
#define PWR_VER_MAJREV_Msk (0xFU << PWR_VER_MAJREV_Pos) /*!< 0x000000F0 */
#define PWR_VER_MAJREV PWR_VER_MAJREV_Msk /*!< Major Revision number */
#define PWR_VER_MINREV_Pos (0U)
#define PWR_VER_MINREV_Msk (0xFU << PWR_VER_MINREV_Pos) /*!< 0x0000000F */
#define PWR_VER_MINREV PWR_VER_MINREV_Msk /*!< Minor Revision number */
/******************** Bit definition for PWR_ID register ********************/
#define PWR_ID_IPID_Pos (0U)
#define PWR_ID_IPID_Msk (0xFFFFFFFFU << PWR_ID_IPID_Pos) /*!< 0xFFFFFFFF */
#define PWR_ID_IPID PWR_ID_IPID_Msk /*!< IP identification */
/******************** Bit definition for PWR_SID register ********************/
#define PWR_SID_SID_Pos (0U)
#define PWR_SID_SID_Msk (0xFFFFFFFFU << PWR_SID_SID_Pos) /*!< 0xFFFFFFFF */
#define PWR_SID_SID PWR_SID_SID_Msk /*!< Size identification */
/******************************************************************************/
/* */
/* Boot and Security and OTP Control (BSEC) */
/* */
/******************************************************************************/
/****************** Bit definition for BSEC_OTP_CONFIG register *****************/
#define BSEC_OTP_CONFIG_PWRUP_Pos (0U)
#define BSEC_OTP_CONFIG_PWRUP_Msk (0x1U << BSEC_OTP_CONFIG_PWRUP_Pos) /*!< 0x00000001 */
#define BSEC_OTP_CONFIG_PWRUP BSEC_OTP_CONFIG_PWRUP_Msk /*!< OTP power-up control */
#define BSEC_OTP_CONFIG_FRC_Pos (1U)
#define BSEC_OTP_CONFIG_FRC_Msk (0x3U << BSEC_OTP_CONFIG_FRC_Pos) /*!< 0x00000006 */
#define BSEC_OTP_CONFIG_FRC BSEC_OTP_CONFIG_FRC_Msk /*!< OTP clock frequency range selection */
#define BSEC_OTP_CONFIG_FRC_0 (0x1U << BSEC_OTP_CONFIG_FRC_Pos) /*!< 0x00000002 */
#define BSEC_OTP_CONFIG_FRC_1 (0x2U << BSEC_OTP_CONFIG_FRC_Pos) /*!< 0x00000004 */
#define BSEC_OTP_CONFIG_PRGWIDTH_Pos (3U)
#define BSEC_OTP_CONFIG_PRGWIDTH_Msk (0xFU << BSEC_OTP_CONFIG_PRGWIDTH_Pos) /*!< 0x00000078 */
#define BSEC_OTP_CONFIG_PRGWIDTH BSEC_OTP_CONFIG_PRGWIDTH_Msk /*!< OTP programming pulse width */
#define BSEC_OTP_CONFIG_PRGWIDTH_0 (0x1U << BSEC_OTP_CONFIG_PRGWIDTH_Pos) /*!< 0x00000008 */
#define BSEC_OTP_CONFIG_PRGWIDTH_1 (0x2U << BSEC_OTP_CONFIG_PRGWIDTH_Pos) /*!< 0x00000010 */
#define BSEC_OTP_CONFIG_PRGWIDTH_2 (0x4U << BSEC_OTP_CONFIG_PRGWIDTH_Pos) /*!< 0x00000020 */
#define BSEC_OTP_CONFIG_PRGWIDTH_3 (0x8U << BSEC_OTP_CONFIG_PRGWIDTH_Pos) /*!< 0x00000040 */
#define BSEC_OTP_CONFIG_TREAD_Pos (7U)
#define BSEC_OTP_CONFIG_TREAD_Msk (0x3U << BSEC_OTP_CONFIG_TREAD_Pos) /*!< 0x00000180 */
#define BSEC_OTP_CONFIG_TREAD BSEC_OTP_CONFIG_TREAD_Msk /*!< set OTP reading current level */
#define BSEC_OTP_CONFIG_TREAD_0 (0x1U << BSEC_OTP_CONFIG_TREAD_Pos) /*!< 0x00000080 */
#define BSEC_OTP_CONFIG_TREAD_1 (0x2U << BSEC_OTP_CONFIG_TREAD_Pos) /*!< 0x00000100 */
/****************** Bit definition for BSEC_OTP_CONTROL register ****************/
#define BSEC_OTP_CONTROL_ADDR_Pos (0U)
#define BSEC_OTP_CONTROL_ADDR_Msk (0x7FU << BSEC_OTP_CONTROL_ADDR_Pos) /*!< 0x0000007F */
#define BSEC_OTP_CONTROL_ADDR BSEC_OTP_CONTROL_ADDR_Msk /*!< OTP word address */
#define BSEC_OTP_CONTROL_PROG_Pos (8U)
#define BSEC_OTP_CONTROL_PROG_Msk (0x1U << BSEC_OTP_CONTROL_PROG_Pos) /*!< 0x00000100 */
#define BSEC_OTP_CONTROL_PROG BSEC_OTP_CONTROL_PROG_Msk /*!< OTP operation control */
#define BSEC_OTP_CONTROL_LOCK_Pos (9U)
#define BSEC_OTP_CONTROL_LOCK_Msk (0x1U << BSEC_OTP_CONTROL_LOCK_Pos) /*!< 0x00000200 */
#define BSEC_OTP_CONTROL_LOCK BSEC_OTP_CONTROL_LOCK_Msk /*!< OTP permanent word lock control */
/****************** Bit definition for BSEC_OTP_STATUS register *****************/
#define BSEC_OTP_STATUS_SECURE_Pos (0U)
#define BSEC_OTP_STATUS_SECURE_Msk (0x1U << BSEC_OTP_STATUS_SECURE_Pos) /*!< 0x00000001 */
#define BSEC_OTP_STATUS_SECURE BSEC_OTP_STATUS_SECURE_Msk /*!< OTP secured mode */
#define BSEC_OTP_STATUS_FULLDBG_Pos (1U)
#define BSEC_OTP_STATUS_FULLDBG_Msk (0x1U << BSEC_OTP_STATUS_FULLDBG_Pos) /*!< 0x00000002 */
#define BSEC_OTP_STATUS_FULLDBG BSEC_OTP_STATUS_FULLDBG_Msk /*!< OTP mode in full debug */
#define BSEC_OTP_STATUS_INVALID_Pos (2U)
#define BSEC_OTP_STATUS_INVALID_Msk (0x1U << BSEC_OTP_STATUS_INVALID_Pos) /*!< 0x00000004 */
#define BSEC_OTP_STATUS_INVALID BSEC_OTP_STATUS_INVALID_Msk /*!< OTP invalid mode */
#define BSEC_OTP_STATUS_BUSY_Pos (3U)
#define BSEC_OTP_STATUS_BUSY_Msk (0x1U << BSEC_OTP_STATUS_BUSY_Pos) /*!< 0x00000008 */
#define BSEC_OTP_STATUS_BUSY BSEC_OTP_STATUS_BUSY_Msk /*!< OTP operation status */
#define BSEC_OTP_STATUS_PROGFAIL_Pos (4U)
#define BSEC_OTP_STATUS_PROGFAIL_Msk (0x1U << BSEC_OTP_STATUS_PROGFAIL_Pos) /*!< 0x00000010 */
#define BSEC_OTP_STATUS_PROGFAIL BSEC_OTP_STATUS_PROGFAIL_Msk /*!< last programming status */
#define BSEC_OTP_STATUS_PWRON_Pos (5U)
#define BSEC_OTP_STATUS_PWRON_Msk (0x1U << BSEC_OTP_STATUS_PWRON_Pos) /*!< 0x00000020 */
#define BSEC_OTP_STATUS_PWRON BSEC_OTP_STATUS_PWRON_Msk /*!< OTP power status */
#define BSEC_OTP_STATUS_BIST1LOCK_Pos (6U)
#define BSEC_OTP_STATUS_BIST1LOCK_Msk (0x1U << BSEC_OTP_STATUS_BIST1LOCK_Pos) /*!< 0x00000040 */
#define BSEC_OTP_STATUS_BIST1LOCK BSEC_OTP_STATUS_BIST1LOCK_Msk /*!< BIST1 locked */
#define BSEC_OTP_STATUS_BIST2LOCK_Pos (7U)
#define BSEC_OTP_STATUS_BIST2LOCK_Msk (0x1U << BSEC_OTP_STATUS_BIST2LOCK_Pos) /*!< 0x00000080 */
#define BSEC_OTP_STATUS_BIST2LOCK BSEC_OTP_STATUS_BIST2LOCK_Msk /*!< BIST2 locked */
/****************** Bit definition for BSEC_OTP_LOCK register ********************/
#define BSEC_OTP_LOCK_OTP_Pos (0U)
#define BSEC_OTP_LOCK_OTP_Msk (0x1U << BSEC_OTP_LOCK_OTP_Pos) /*!< 0x00000001 */
#define BSEC_OTP_LOCK_OTP BSEC_OTP_LOCK_OTP_Msk /*!< upper OTP read lock */
#define BSEC_OTP_LOCK_DENREG_Pos (2U)
#define BSEC_OTP_LOCK_DENREG_Msk (0x1U << BSEC_OTP_LOCK_DENREG_Pos) /*!< 0x00000004 */
#define BSEC_OTP_LOCK_DENREG BSEC_OTP_LOCK_DENREG_Msk /*!< debug enable register sticky lock */
#define BSEC_OTP_LOCK_FENREG_Pos (3U)
#define BSEC_OTP_LOCK_FENREG_Msk (0x1U << BSEC_OTP_LOCK_FENREG_Pos) /*!< 0x00000008 */
#define BSEC_OTP_LOCK_FENREG BSEC_OTP_LOCK_FENREG_Msk /*!< feature enable register sticky lock */
#define BSEC_OTP_LOCK_GPLOCK_Pos (4U)
#define BSEC_OTP_LOCK_GPLOCK_Msk (0x1U << BSEC_OTP_LOCK_GPLOCK_Pos) /*!< 0x00000010 */
#define BSEC_OTP_LOCK_GPLOCK BSEC_OTP_LOCK_GPLOCK_Msk /*!< programming sticky lock */
/******************** Bit definition for BSEC_DENABLE register********************/
#define BSEC_DENABLE_DFTEN_Pos (0U)
#define BSEC_DENABLE_DFTEN_Msk (0x1U << BSEC_DENABLE_DFTEN_Pos) /*!< 0x00000001 */
#define BSEC_DENABLE_DFTEN BSEC_DENABLE_DFTEN_Msk /*!< DFT enable with signal dften */
#define BSEC_DENABLE_DBGEN_Pos (1U)
#define BSEC_DENABLE_DBGEN_Msk (0x1U << BSEC_DENABLE_DBGEN_Pos) /*!< 0x00000002 */
#define BSEC_DENABLE_DBGEN BSEC_DENABLE_DBGEN_Msk /*!< debug enable with signal dbgen */
#define BSEC_DENABLE_NIDEN_Pos (2U)
#define BSEC_DENABLE_NIDEN_Msk (0x1U << BSEC_DENABLE_NIDEN_Pos) /*!< 0x00000004 */
#define BSEC_DENABLE_NIDEN BSEC_DENABLE_NIDEN_Msk /*!< non-invasive debug enable with signal niden */
#define BSEC_DENABLE_DEVICEEN_Pos (3U)
#define BSEC_DENABLE_DEVICEEN_Msk (0x1U << BSEC_DENABLE_DEVICEEN_Pos) /*!< 0x00000008 */
#define BSEC_DENABLE_DEVICEEN BSEC_DENABLE_DEVICEEN_Msk /*!< controls access to debug component via external debug port by signal deviceen */
#define BSEC_DENABLE_HDPEN_Pos (4U)
#define BSEC_DENABLE_HDPEN_Msk (0x1U << BSEC_DENABLE_HDPEN_Pos) /*!< 0x00000010 */
#define BSEC_DENABLE_HDPEN BSEC_DENABLE_HDPEN_Msk /*!< hardware debug port enable with signal hdpen */
#define BSEC_DENABLE_SPIDEN_Pos (5U)
#define BSEC_DENABLE_SPIDEN_Msk (0x1U << BSEC_DENABLE_SPIDEN_Pos) /*!< 0x00000020 */
#define BSEC_DENABLE_SPIDEN BSEC_DENABLE_SPIDEN_Msk /*!< secure privilege invasive debug enable with signal spniden */
#define BSEC_DENABLE_SPNIDEN_Pos (6U)
#define BSEC_DENABLE_SPNIDEN_Msk (0x1U << BSEC_DENABLE_SPNIDEN_Pos) /*!< 0x00000040 */
#define BSEC_DENABLE_SPNIDEN BSEC_DENABLE_SPNIDEN_Msk /*!< secure privilege non-invasive debug enable with signal spiden */
#define BSEC_DENABLE_CP15SDISABLE_Pos (7U)
#define BSEC_DENABLE_CP15SDISABLE_Msk (0x3U << BSEC_DENABLE_CP15SDISABLE_Pos) /*!< 0x00000180 */
#define BSEC_DENABLE_CP15SDISABLE BSEC_DENABLE_CP15SDISABLE_Msk /*!< write access to some secure Cortex®-A7 CP15 registers disable CPDISABLE[0] applies to CPU0. CPDISABLE[1] applies to CPU1 */
#define BSEC_DENABLE_CP15SDISABLE_0 (0x1U << BSEC_DENABLE_CP15SDISABLE_Pos) /*!< 0x00000080 */
#define BSEC_DENABLE_CP15SDISABLE_1 (0x2U << BSEC_DENABLE_CP15SDISABLE_Pos) /*!< 0x00000100 */
#define BSEC_DENABLE_CFGSDISABLE_Pos (9U)
#define BSEC_DENABLE_CFGSDISABLE_Msk (0x1U << BSEC_DENABLE_CFGSDISABLE_Pos) /*!< 0x00000200 */
#define BSEC_DENABLE_CFGSDISABLE BSEC_DENABLE_CFGSDISABLE_Msk /*!< write access to secure GIC registers disable with signal cfgsdisable */
#define BSEC_DENABLE_DBGSWENABLE_Pos (10U)
#define BSEC_DENABLE_DBGSWENABLE_Msk (0x1U << BSEC_DENABLE_DBGSWENABLE_Pos) /*!< 0x00000400 */
#define BSEC_DENABLE_DBGSWENABLE BSEC_DENABLE_DBGSWENABLE_Msk /*!< control self hosted debug enable with signal dbgswenable */
/******************** Bit definition for BSEC_HWCFGR register ***************/
#define BSEC_HWCFGR_SIZE_Pos (0U)
#define BSEC_HWCFGR_SIZE_Msk (0xFU << BSEC_HWCFGR_SIZE_Pos) /*!< 0x0000000F */
#define BSEC_HWCFGR_SIZE BSEC_HWCFGR_SIZE_Msk /*!< OTP Block Size */
#define BSEC_HWCFGR_ECC_USE_Pos (4U)
#define BSEC_HWCFGR_ECC_USE_Msk (0xFU << BSEC_HWCFGR_ECC_USE_Pos) /*!< 0x000000F0 */
#define BSEC_HWCFGR_ECC_USE BSEC_HWCFGR_ECC_USE_Msk /*!< protection / redundancy scheme used */
/******************** Bit definition for BSEC_VERR register********************/
#define BSEC_VERR_MINREV_Pos (0U)
#define BSEC_VERR_MINREV_Msk (0xFU << BSEC_VERR_MINREV_Pos) /*!< 0x0000000F */
#define BSEC_VERR_MINREV BSEC_VERR_MINREV_Msk /*!< MAJREV[3:0] bits (Minor revision) */
#define BSEC_VERR_MAJREV_Pos (4U)
#define BSEC_VERR_MAJREV_Msk (0xFU << BSEC_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define BSEC_VERR_MAJREV BSEC_VERR_MAJREV_Msk /*!< MINREV[3:0] bits (Major revision) */
/********************** Bit definition for BSEC_IPIDR register ****************/
#define BSEC_IPIDR_IPID_Pos (0U)
#define BSEC_IPIDR_IPID_Msk (0xFFFFFFFFU << BSEC_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
#define BSEC_IPIDR_IPID BSEC_IPIDR_IPID_Msk /*!< IP Identification */
/********************** Bit definition for BSEC_SIDR register *****************/
#define BSEC_SIDR_SID_Pos (0U)
#define BSEC_SIDR_SID_Msk (0xFFFFFFFFU << BSEC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define BSEC_SIDR_SID BSEC_SIDR_SID_Msk /*!< IP size identification */
/******************************************************************************/
/* */
/* Hardware Debug Port */
/* */
/******************************************************************************/
/******************** Bit definition for HDP_CTRL register********************/
#define HDP_CTRL_EN_Pos (0U)
#define HDP_CTRL_EN_Msk (0x1U << HDP_CTRL_EN_Pos) /*!< 0x00000001 */
#define HDP_CTRL_EN HDP_CTRL_EN_Msk /*Enable HDP, valid if enabled in BSEC*/
/******************** Bit definition for HDP_MUX register*********************/
#define HDP_MUX_MUX0_Pos (0U)
#define HDP_MUX_MUX0_Msk (0xFU << HDP_MUX_MUX0_Pos) /*!< 0x0000000F */
#define HDP_MUX_MUX0 HDP_MUX_MUX0_Msk /*Select the HDP0 output among the 16 available signals*/
#define HDP_MUX_MUX0_0 (0x1U << HDP_MUX_MUX0_Pos) /*!< 0x00000001 */
#define HDP_MUX_MUX0_1 (0x2U << HDP_MUX_MUX0_Pos) /*!< 0x00000002 */
#define HDP_MUX_MUX0_2 (0x4U << HDP_MUX_MUX0_Pos) /*!< 0x00000004 */
#define HDP_MUX_MUX0_3 (0x8U << HDP_MUX_MUX0_Pos) /*!< 0x00000008 */
#define HDP_MUX_MUX1_Pos (4U)
#define HDP_MUX_MUX1_Msk (0xFU << HDP_MUX_MUX1_Pos) /*!< 0x000000F0 */
#define HDP_MUX_MUX1 HDP_MUX_MUX1_Msk /*Select the HDP1 output among the 16 available signals*/
#define HDP_MUX_MUX1_0 (0x1U << HDP_MUX_MUX1_Pos) /*!< 0x00000010 */
#define HDP_MUX_MUX1_1 (0x2U << HDP_MUX_MUX1_Pos) /*!< 0x00000020 */
#define HDP_MUX_MUX1_2 (0x4U << HDP_MUX_MUX1_Pos) /*!< 0x00000040 */
#define HDP_MUX_MUX1_3 (0x8U << HDP_MUX_MUX1_Pos) /*!< 0x00000080 */
#define HDP_MUX_MUX2_Pos (8U)
#define HDP_MUX_MUX2_Msk (0xFU << HDP_MUX_MUX2_Pos) /*!< 0x00000F00 */
#define HDP_MUX_MUX2 HDP_MUX_MUX2_Msk /*Select the HDP2 output among the 16 available signals*/
#define HDP_MUX_MUX2_0 (0x1U << HDP_MUX_MUX2_Pos) /*!< 0x00000100 */
#define HDP_MUX_MUX2_1 (0x2U << HDP_MUX_MUX2_Pos) /*!< 0x00000200 */
#define HDP_MUX_MUX2_2 (0x4U << HDP_MUX_MUX2_Pos) /*!< 0x00000400 */
#define HDP_MUX_MUX2_3 (0x8U << HDP_MUX_MUX2_Pos) /*!< 0x00000800 */
#define HDP_MUX_MUX3_Pos (12U)
#define HDP_MUX_MUX3_Msk (0xFU << HDP_MUX_MUX3_Pos) /*!< 0x0000F000 */
#define HDP_MUX_MUX3 HDP_MUX_MUX3_Msk /*Select the HDP3 output among the 16 available signals*/
#define HDP_MUX_MUX3_0 (0x1U << HDP_MUX_MUX3_Pos) /*!< 0x00001000 */
#define HDP_MUX_MUX3_1 (0x2U << HDP_MUX_MUX3_Pos) /*!< 0x00002000 */
#define HDP_MUX_MUX3_2 (0x4U << HDP_MUX_MUX3_Pos) /*!< 0x00004000 */
#define HDP_MUX_MUX3_3 (0x8U << HDP_MUX_MUX3_Pos) /*!< 0x00008000 */
#define HDP_MUX_MUX4_Pos (16U)
#define HDP_MUX_MUX4_Msk (0xFU << HDP_MUX_MUX4_Pos) /*!< 0x000F0000 */
#define HDP_MUX_MUX4 HDP_MUX_MUX4_Msk /*Select the HDP4 output among the 16 available signals*/
#define HDP_MUX_MUX4_0 (0x1U << HDP_MUX_MUX4_Pos) /*!< 0x00010000 */
#define HDP_MUX_MUX4_1 (0x2U << HDP_MUX_MUX4_Pos) /*!< 0x00020000 */
#define HDP_MUX_MUX4_2 (0x4U << HDP_MUX_MUX4_Pos) /*!< 0x00040000 */
#define HDP_MUX_MUX4_3 (0x8U << HDP_MUX_MUX4_Pos) /*!< 0x00080000 */
#define HDP_MUX_MUX5_Pos (20U)
#define HDP_MUX_MUX5_Msk (0xFU << HDP_MUX_MUX5_Pos) /*!< 0x00F00000 */
#define HDP_MUX_MUX5 HDP_MUX_MUX5_Msk /*Select the HDP5 output among the 16 available signals*/
#define HDP_MUX_MUX5_0 (0x1U << HDP_MUX_MUX5_Pos) /*!< 0x00100000 */
#define HDP_MUX_MUX5_1 (0x2U << HDP_MUX_MUX5_Pos) /*!< 0x00200000 */
#define HDP_MUX_MUX5_2 (0x4U << HDP_MUX_MUX5_Pos) /*!< 0x00400000 */
#define HDP_MUX_MUX5_3 (0x8U << HDP_MUX_MUX5_Pos) /*!< 0x00800000 */
#define HDP_MUX_MUX6_Pos (24U)
#define HDP_MUX_MUX6_Msk (0xFU << HDP_MUX_MUX6_Pos) /*!< 0x0F000000 */
#define HDP_MUX_MUX6 HDP_MUX_MUX6_Msk /*Select the HDP6 output among the 16 available signals*/
#define HDP_MUX_MUX6_0 (0x1U << HDP_MUX_MUX6_Pos) /*!< 0x01000000 */
#define HDP_MUX_MUX6_1 (0x2U << HDP_MUX_MUX6_Pos) /*!< 0x02000000 */
#define HDP_MUX_MUX6_2 (0x4U << HDP_MUX_MUX6_Pos) /*!< 0x04000000 */
#define HDP_MUX_MUX6_3 (0x8U << HDP_MUX_MUX6_Pos) /*!< 0x08000000 */
#define HDP_MUX_MUX7_Pos (28U)
#define HDP_MUX_MUX7_Msk (0xFU << HDP_MUX_MUX7_Pos) /*!< 0xF0000000 */
#define HDP_MUX_MUX7 HDP_MUX_MUX7_Msk /*Select the HDP7 output among the 16 available signals*/
#define HDP_MUX_MUX7_0 (0x1U << HDP_MUX_MUX7_Pos) /*!< 0x10000000 */
#define HDP_MUX_MUX7_1 (0x2U << HDP_MUX_MUX7_Pos) /*!< 0x20000000 */
#define HDP_MUX_MUX7_2 (0x4U << HDP_MUX_MUX7_Pos) /*!< 0x40000000 */
#define HDP_MUX_MUX7_3 (0x8U << HDP_MUX_MUX7_Pos) /*!< 0x80000000 */
/******************** Bit definition for HDP_VAL register*********************/
#define HDP_VAL_HDPVAL_Pos (0U)
#define HDP_VAL_HDPVAL_Msk (0xFFU << HDP_VAL_HDPVAL_Pos) /*!< 0x000000FF */
#define HDP_VAL_HDPVAL HDP_VAL_HDPVAL_Msk /*Provide the value of the HDP signals*/
/******************** Bit definition for HDP_GPOSET register*********************/
#define HDP_GPOSET_HDPGPOSET_Pos (0U)
#define HDP_GPOSET_HDPGPOSET_Msk (0xFFU << HDP_GPOSET_HDPGPOSET_Pos) /*!< 0x000000FF */
#define HDP_GPOSET_HDPGPOSET HDP_GPOSET_HDPGPOSET_Msk /*When a bit is written to 1, the corresponding HDP GPO is seT*/
/******************** Bit definition for HDP_GPOCLR register*********************/
#define HDP_GPOCLR_HDPGPOCLR_Pos (0U)
#define HDP_GPOCLR_HDPGPOCLR_Msk (0xFFU << HDP_GPOCLR_HDPGPOCLR_Pos) /*!< 0x000000FF */
#define HDP_GPOCLR_HDPGPOCLR HDP_GPOCLR_HDPGPOCLR_Msk /*When a bit is written to 1, the corresponding HDP GPO is cleared*/
/******************** Bit definition for HDP_GPOVAL register*********************/
#define HDP_GPOVAL_HDPGPOVAL_Pos (0U)
#define HDP_GPOVAL_HDPGPOVAL_Msk (0xFFU << HDP_GPOVAL_HDPGPOVAL_Pos) /*!< 0x000000FF */
#define HDP_GPOVAL_HDPGPOVAL HDP_GPOVAL_HDPGPOVAL_Msk /*When written, define the value of the HDP GPO*/
/******************** Bit definition for HDP_VERR register***********************/
#define HDP_VERR_MINREV_Pos (0U)
#define HDP_VERR_MINREV_Msk (0xFU << HDP_VERR_MINREV_Pos) /*!< 0x0000000F */
#define HDP_VERR_MINREV HDP_VERR_MINREV_Msk /*Minor Revision of the IP*/
#define HDP_VERR_MAJREV_Pos (4U)
#define HDP_VERR_MAJREV_Msk (0xFU << HDP_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define HDP_VERR_MAJREV HDP_VERR_MAJREV_Msk /*Major Revision of the IP*/
/******************** Bit definition for HDP_IPIDR register**********************/
#define HDP_IPIDR_ID_Pos (0U)
#define HDP_IPIDR_ID_Msk (0xFFFFFFFFU << HDP_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
#define HDP_IPIDR_ID HDP_IPIDR_ID_Msk /*IP Identifier*/
/******************** Bit definition for HDP_SIDR register**********************/
#define HDP_SIDR_SID_Pos (0U)
#define HDP_SIDR_SID_Msk (0xFFFFFFFFU << HDP_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define HDP_SIDR_SID HDP_SIDR_SID_Msk /*Size Identifier*/
/******************************************************************************/
/* */
/* Reset and Clock Control */
/* */
/******************************************************************************/
/******************** Bit definition for RCC_TZCR register********************/
#define RCC_TZCR_TZEN_Pos (0U)
#define RCC_TZCR_TZEN_Msk (0x1U << RCC_TZCR_TZEN_Pos) /*!< 0x00000001 */
#define RCC_TZCR_TZEN RCC_TZCR_TZEN_Msk /*TrustZone Enable*/
#define RCC_TZCR_MCKPROT_Pos (1U)
#define RCC_TZCR_MCKPROT_Msk (0x1U << RCC_TZCR_MCKPROT_Pos) /*!< 0x00000002 */
#define RCC_TZCR_MCKPROT RCC_TZCR_MCKPROT_Msk /*Protection of the generation of ck_mcuss Enable*/
/******************** Bit definition for RCC_OCENSETR register********************/
#define RCC_OCENSETR_HSION_Pos (0U)
#define RCC_OCENSETR_HSION_Msk (0x1U << RCC_OCENSETR_HSION_Pos) /*!< 0x00000001 */
#define RCC_OCENSETR_HSION RCC_OCENSETR_HSION_Msk /*Internal High Speed enable clock*/
#define RCC_OCENSETR_HSIKERON_Pos (1U)
#define RCC_OCENSETR_HSIKERON_Msk (0x1U << RCC_OCENSETR_HSIKERON_Pos) /*!< 0x00000002 */
#define RCC_OCENSETR_HSIKERON RCC_OCENSETR_HSIKERON_Msk /*Force HSI to ON,even in stop mode ,in order to be quickly available*/
#define RCC_OCENSETR_CSION_Pos (4U)
#define RCC_OCENSETR_CSION_Msk (0x1U << RCC_OCENSETR_CSION_Pos) /*!< 0x00000010 */
#define RCC_OCENSETR_CSION RCC_OCENSETR_CSION_Msk /*CSI enable clock*/
#define RCC_OCENSETR_CSIKERON_Pos (5U)
#define RCC_OCENSETR_CSIKERON_Msk (0x1U << RCC_OCENSETR_CSIKERON_Pos) /*!< 0x00000020 */
#define RCC_OCENSETR_CSIKERON RCC_OCENSETR_CSIKERON_Msk /*Force CSI to ON,eve in stop mode ,in order to be quickly available*/
#define RCC_OCENSETR_DIGBYP_Pos (7U)
#define RCC_OCENSETR_DIGBYP_Msk (0x1U << RCC_OCENSETR_DIGBYP_Pos) /*!< 0x00000040 */
#define RCC_OCENSETR_DIGBYP RCC_OCENSETR_DIGBYP_Msk /*Digital Bypass*/
#define RCC_OCENSETR_HSEON_Pos (8U)
#define RCC_OCENSETR_HSEON_Msk (0x1U << RCC_OCENSETR_HSEON_Pos) /*!< 0x00000100 */
#define RCC_OCENSETR_HSEON RCC_OCENSETR_HSEON_Msk /*External High Speed enable clock*/
#define RCC_OCENSETR_HSEKERON_Pos (9U)
#define RCC_OCENSETR_HSEKERON_Msk (0x1U << RCC_OCENSETR_HSEKERON_Pos) /*!< 0x00000200 */
#define RCC_OCENSETR_HSEKERON RCC_OCENSETR_HSEKERON_Msk /*Force HSE to ON,evne in stop mode ,in order to be quickly available*/
#define RCC_OCENSETR_HSEBYP_Pos (10U)
#define RCC_OCENSETR_HSEBYP_Msk (0x1U << RCC_OCENSETR_HSEBYP_Pos) /*!< 0x00000400 */
#define RCC_OCENSETR_HSEBYP RCC_OCENSETR_HSEBYP_Msk /*HSE Bypass*/
#define RCC_OCENSETR_HSECSSON_Pos (11U)
#define RCC_OCENSETR_HSECSSON_Msk (0x1U << RCC_OCENSETR_HSECSSON_Pos) /*!< 0x00000800 */
#define RCC_OCENSETR_HSECSSON RCC_OCENSETR_HSECSSON_Msk /*Clock Security System on HSE enable*/
/******************** Bit definition for RCC_OCENCLRR register********************/
#define RCC_OCENCLRR_HSION_Pos (0U)
#define RCC_OCENCLRR_HSION_Msk (0x1U << RCC_OCENCLRR_HSION_Pos) /*!< 0x00000001 */
#define RCC_OCENCLRR_HSION RCC_OCENCLRR_HSION_Msk /*clear of HSION bit*/
#define RCC_OCENCLRR_HSIKERON_Pos (1U)
#define RCC_OCENCLRR_HSIKERON_Msk (0x1U << RCC_OCENCLRR_HSIKERON_Pos) /*!< 0x00000002 */
#define RCC_OCENCLRR_HSIKERON RCC_OCENCLRR_HSIKERON_Msk /*clear of HSIKERON bit*/
#define RCC_OCENCLRR_CSION_Pos (4U)
#define RCC_OCENCLRR_CSION_Msk (0x1U << RCC_OCENCLRR_CSION_Pos) /*!< 0x00000010 */
#define RCC_OCENCLRR_CSION RCC_OCENCLRR_CSION_Msk /*clear of CSION bit*/
#define RCC_OCENCLRR_CSIKERON_Pos (5U)
#define RCC_OCENCLRR_CSIKERON_Msk (0x1U << RCC_OCENCLRR_CSIKERON_Pos) /*!< 0x00000020 */
#define RCC_OCENCLRR_CSIKERON RCC_OCENCLRR_CSIKERON_Msk /*clear of CSIKERON bit*/
#define RCC_OCENCLRR_DIGBYP_Pos (7U)
#define RCC_OCENCLRR_DIGBYP_Msk (0x1U << RCC_OCENCLRR_DIGBYP_Pos) /*!< 0x00000040 */
#define RCC_OCENCLRR_DIGBYP RCC_OCENCLRR_DIGBYP_Msk /*clear of DIGBYP bit*/
#define RCC_OCENCLRR_HSEON_Pos (8U)
#define RCC_OCENCLRR_HSEON_Msk (0x1U << RCC_OCENCLRR_HSEON_Pos) /*!< 0x00000100 */
#define RCC_OCENCLRR_HSEON RCC_OCENCLRR_HSEON_Msk /*clear of HSEON bit*/
#define RCC_OCENCLRR_HSEKERON_Pos (9U)
#define RCC_OCENCLRR_HSEKERON_Msk (0x1U << RCC_OCENCLRR_HSEKERON_Pos) /*!< 0x00000200 */
#define RCC_OCENCLRR_HSEKERON RCC_OCENCLRR_HSEKERON_Msk /*clear of HSEKERON bit*/
#define RCC_OCENCLRR_HSEBYP_Pos (10U)
#define RCC_OCENCLRR_HSEBYP_Msk (0x1U << RCC_OCENCLRR_HSEBYP_Pos) /*!< 0x00000400 */
#define RCC_OCENCLRR_HSEBYP RCC_OCENCLRR_HSEBYP_Msk /*clear the HSE Bypass bit*/
/******************** Bit definition for RCC_OCRDYR register********************/
#define RCC_OCRDYR_HSIRDY_Pos (0U)
#define RCC_OCRDYR_HSIRDY_Msk (0x1U << RCC_OCRDYR_HSIRDY_Pos) /*!< 0x00000001 */
#define RCC_OCRDYR_HSIRDY RCC_OCRDYR_HSIRDY_Msk /*HSI clock ready flag*/
#define RCC_OCRDYR_HSIDIVRDY_Pos (2U)
#define RCC_OCRDYR_HSIDIVRDY_Msk (0x1U << RCC_OCRDYR_HSIDIVRDY_Pos) /*!< 0x00000004 */
#define RCC_OCRDYR_HSIDIVRDY RCC_OCRDYR_HSIDIVRDY_Msk /*HSI divider ready flag*/
#define RCC_OCRDYR_CSIRDY_Pos (4U)
#define RCC_OCRDYR_CSIRDY_Msk (0x1U << RCC_OCRDYR_CSIRDY_Pos) /*!< 0x00000010 */
#define RCC_OCRDYR_CSIRDY RCC_OCRDYR_CSIRDY_Msk /*CSI clock ready flag*/
#define RCC_OCRDYR_HSERDY_Pos (8U)
#define RCC_OCRDYR_HSERDY_Msk (0x1U << RCC_OCRDYR_HSERDY_Pos) /*!< 0x00000100 */
#define RCC_OCRDYR_HSERDY RCC_OCRDYR_HSERDY_Msk /*HSE clock ready flag*/
#define RCC_OCRDYR_AXICKRDY_Pos (24U)
#define RCC_OCRDYR_AXICKRDY_Msk (0x1U << RCC_OCRDYR_AXICKRDY_Pos) /*!< 0x01000000 */
#define RCC_OCRDYR_AXICKRDY RCC_OCRDYR_AXICKRDY_Msk /*AXI sub-system clock ready flag*/
#define RCC_OCRDYR_CKREST_Pos (25U)
#define RCC_OCRDYR_CKREST_Msk (0x1U << RCC_OCRDYR_CKREST_Pos) /*!< 0x02000000 */
#define RCC_OCRDYR_CKREST RCC_OCRDYR_CKREST_Msk /*Clock Restore State Machine Status*/
/******************** Bit definition for RCC_DBGCFGR register********************/
#define RCC_DBGCFGR_TRACEDIV_Pos (0U)
#define RCC_DBGCFGR_TRACEDIV_Msk (0x7U << RCC_DBGCFGR_TRACEDIV_Pos) /*!< 0x00000007 */
#define RCC_DBGCFGR_TRACEDIV RCC_DBGCFGR_TRACEDIV_Msk /*clock divider for the trace clock*/
#define RCC_DBGCFGR_DBGCKEN_Pos (8U)
#define RCC_DBGCFGR_DBGCKEN_Msk (0x1U << RCC_DBGCFGR_DBGCKEN_Pos) /*!< 0x00000100 */
#define RCC_DBGCFGR_DBGCKEN RCC_DBGCFGR_DBGCKEN_Msk /*clock enable for debug function*/
#define RCC_DBGCFGR_TRACECKEN_Pos (9U)
#define RCC_DBGCFGR_TRACECKEN_Msk (0x1U << RCC_DBGCFGR_TRACECKEN_Pos) /*!< 0x00000200 */
#define RCC_DBGCFGR_TRACECKEN RCC_DBGCFGR_TRACECKEN_Msk /*clock enable for trace function*/
#define RCC_DBGCFGR_DBGRST_Pos (12U)
#define RCC_DBGCFGR_DBGRST_Msk (0x1U << RCC_DBGCFGR_DBGRST_Pos) /*!< 0x00001000 */
#define RCC_DBGCFGR_DBGRST RCC_DBGCFGR_DBGRST_Msk /*Reset of the debug function*/
/******************** Bit definition for RCC_HSICFGR register********************/
#define RCC_HSICFGR_HSIDIV_Pos (0U)
#define RCC_HSICFGR_HSIDIV_Msk (0x3U << RCC_HSICFGR_HSIDIV_Pos)
#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /* HSI clock divider*/
#define RCC_HSICFGR_HSIDIV_0 (0x0U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 1 (default after reset)*/
#define RCC_HSICFGR_HSIDIV_1 (0x1U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 2 */
#define RCC_HSICFGR_HSIDIV_2 (0x2U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 4 */
#define RCC_HSICFGR_HSIDIV_3 (0x3U << RCC_HSICFGR_HSIDIV_Pos) /* Division by 8 */
#define RCC_HSICFGR_HSITRIM_Pos (8U)
#define RCC_HSICFGR_HSITRIM_Msk (0x3FU << RCC_HSICFGR_HSITRIM_Pos)
#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*HSI clock trimming*/
#define RCC_HSICFGR_HSICAL_Pos (16U)
#define RCC_HSICFGR_HSICAL_Msk (0xFFFU << RCC_HSICFGR_HSICAL_Pos)
#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*HSI clock calibration*/
/******************** Bit definition for RCC_CSICFGR register********************/
#define RCC_CSICFGR_CSITRIM_Pos (8U)
#define RCC_CSICFGR_CSITRIM_Msk (0x1FU << RCC_CSICFGR_CSITRIM_Pos)
#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*CSI clock trimming*/
#define RCC_CSICFGR_CSICAL_Pos (16U)
#define RCC_CSICFGR_CSICAL_Msk (0xFFU << RCC_CSICFGR_CSICAL_Pos)
#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*CSI clock calibration*/
/******************** Bit definition for RCC_MCO1CFGR register********************/
#define RCC_MCO1CFGR_MCO1SEL_Pos (0U)
#define RCC_MCO1CFGR_MCO1SEL_Msk (0x7U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000007 */
#define RCC_MCO1CFGR_MCO1SEL RCC_MCO1CFGR_MCO1SEL_Msk /*MCO1 clock output selection*/
#define RCC_MCO1CFGR_MCO1SEL_0 (0x0U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000000 */
#define RCC_MCO1CFGR_MCO1SEL_1 (0x1U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000001 */
#define RCC_MCO1CFGR_MCO1SEL_2 (0x2U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000002 */
#define RCC_MCO1CFGR_MCO1SEL_3 (0x3U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000003 */
#define RCC_MCO1CFGR_MCO1SEL_4 (0x4U << RCC_MCO1CFGR_MCO1SEL_Pos) /*!< 0x00000004 */
#define RCC_MCO1CFGR_MCO1DIV_Pos (4U)
#define RCC_MCO1CFGR_MCO1DIV_Msk (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */
#define RCC_MCO1CFGR_MCO1DIV RCC_MCO1CFGR_MCO1DIV_Msk /*MCO1 prescaler*/
#define RCC_MCO1CFGR_MCO1DIV_0 (0x0U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000000 */
#define RCC_MCO1CFGR_MCO1DIV_1 (0x1U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000010 */
#define RCC_MCO1CFGR_MCO1DIV_2 (0x2U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000020 */
#define RCC_MCO1CFGR_MCO1DIV_3 (0x3U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000030 */
#define RCC_MCO1CFGR_MCO1DIV_4 (0x4U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000040 */
#define RCC_MCO1CFGR_MCO1DIV_5 (0x5U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000050 */
#define RCC_MCO1CFGR_MCO1DIV_6 (0x6U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000060 */
#define RCC_MCO1CFGR_MCO1DIV_7 (0x7U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000070 */
#define RCC_MCO1CFGR_MCO1DIV_8 (0x8U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000080 */
#define RCC_MCO1CFGR_MCO1DIV_9 (0x9U << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x00000090 */
#define RCC_MCO1CFGR_MCO1DIV_10 (0xAU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000A0 */
#define RCC_MCO1CFGR_MCO1DIV_11 (0xBU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000B0 */
#define RCC_MCO1CFGR_MCO1DIV_12 (0xCU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000C0 */
#define RCC_MCO1CFGR_MCO1DIV_13 (0xDU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000D0 */
#define RCC_MCO1CFGR_MCO1DIV_14 (0xEU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000E0 */
#define RCC_MCO1CFGR_MCO1DIV_15 (0xFU << RCC_MCO1CFGR_MCO1DIV_Pos) /*!< 0x000000F0 */
#define RCC_MCO1CFGR_MCO1ON_Pos (12U)
#define RCC_MCO1CFGR_MCO1ON_Msk (0x1U << RCC_MCO1CFGR_MCO1ON_Pos) /*!< 0x00001000 */
#define RCC_MCO1CFGR_MCO1ON RCC_MCO1CFGR_MCO1ON_Msk /*Control the MCO1 output*/
/******************** Bit definition for RCC_MCO2CFGR register********************/
#define RCC_MCO2CFGR_MCO2SEL_Pos (0U)
#define RCC_MCO2CFGR_MCO2SEL_Msk (0x7U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000007 */
#define RCC_MCO2CFGR_MCO2SEL RCC_MCO2CFGR_MCO2SEL_Msk /*MCO2 clock output selection*/
#define RCC_MCO2CFGR_MCO2SEL_0 (0x0U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000000 */
#define RCC_MCO2CFGR_MCO2SEL_1 (0x1U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000001 */
#define RCC_MCO2CFGR_MCO2SEL_2 (0x2U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000002 */
#define RCC_MCO2CFGR_MCO2SEL_3 (0x3U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000003 */
#define RCC_MCO2CFGR_MCO2SEL_4 (0x4U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000004 */
#define RCC_MCO2CFGR_MCO2SEL_5 (0x5U << RCC_MCO2CFGR_MCO2SEL_Pos) /*!< 0x00000005 */
#define RCC_MCO2CFGR_MCO2DIV_Pos (4U)
#define RCC_MCO2CFGR_MCO2DIV_Msk (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */
#define RCC_MCO2CFGR_MCO2DIV RCC_MCO2CFGR_MCO2DIV_Msk /*MCO2 prescaler*/
#define RCC_MCO2CFGR_MCO2DIV_0 (0x0U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000000 */
#define RCC_MCO2CFGR_MCO2DIV_1 (0x1U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000010 */
#define RCC_MCO2CFGR_MCO2DIV_2 (0x2U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000020 */
#define RCC_MCO2CFGR_MCO2DIV_3 (0x3U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000030 */
#define RCC_MCO2CFGR_MCO2DIV_4 (0x4U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000040 */
#define RCC_MCO2CFGR_MCO2DIV_5 (0x5U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000050 */
#define RCC_MCO2CFGR_MCO2DIV_6 (0x6U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000060 */
#define RCC_MCO2CFGR_MCO2DIV_7 (0x7U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000070 */
#define RCC_MCO2CFGR_MCO2DIV_8 (0x8U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000080 */
#define RCC_MCO2CFGR_MCO2DIV_9 (0x9U << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x00000090 */
#define RCC_MCO2CFGR_MCO2DIV_10 (0xAU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000A0 */
#define RCC_MCO2CFGR_MCO2DIV_11 (0xBU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000B0 */
#define RCC_MCO2CFGR_MCO2DIV_12 (0xCU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000C0 */
#define RCC_MCO2CFGR_MCO2DIV_13 (0xDU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000D0 */
#define RCC_MCO2CFGR_MCO2DIV_14 (0xEU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000E0 */
#define RCC_MCO2CFGR_MCO2DIV_15 (0xFU << RCC_MCO2CFGR_MCO2DIV_Pos) /*!< 0x000000F0 */
#define RCC_MCO2CFGR_MCO2ON_Pos (12U)
#define RCC_MCO2CFGR_MCO2ON_Msk (0x1U << RCC_MCO2CFGR_MCO2ON_Pos) /*!< 0x00001000 */
#define RCC_MCO2CFGR_MCO2ON RCC_MCO2CFGR_MCO2ON_Msk /*contorl the MCO2 output*/
/******************** Bit definition for RCC_MPCKSELR register********************/
#define RCC_MPCKSELR_MPUSRC_Pos (0U)
#define RCC_MPCKSELR_MPUSRC_Msk (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */
#define RCC_MPCKSELR_MPUSRC RCC_MPCKSELR_MPUSRC_Msk /*MPU clock switch*/
#define RCC_MPCKSELR_MPUSRC_0 (0x0U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000000 */
#define RCC_MPCKSELR_MPUSRC_1 (0x1U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000001 */
#define RCC_MPCKSELR_MPUSRC_2 (0x2U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000002 */
#define RCC_MPCKSELR_MPUSRC_3 (0x3U << RCC_MPCKSELR_MPUSRC_Pos) /*!< 0x00000003 */
#define RCC_MPCKSELR_MPUSRCRDY_Pos (31U)
#define RCC_MPCKSELR_MPUSRCRDY_Msk (0x1U << RCC_MPCKSELR_MPUSRCRDY_Pos) /*!< 0x80000000 */
#define RCC_MPCKSELR_MPUSRCRDY RCC_MPCKSELR_MPUSRCRDY_Msk /*MPU clock switch status*/
/******************** Bit definition for RCC_ASSCKSELR register********************/
#define RCC_ASSCKSELR_AXISSRC_Pos (0U)
#define RCC_ASSCKSELR_AXISSRC_Msk (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */
#define RCC_ASSCKSELR_AXISSRC RCC_ASSCKSELR_AXISSRC_Msk /*AXI sub-system clock switch*/
#define RCC_ASSCKSELR_AXISSRC_0 (0x0U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000000 */
#define RCC_ASSCKSELR_AXISSRC_1 (0x1U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000001 */
#define RCC_ASSCKSELR_AXISSRC_2 (0x2U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000002 */
#define RCC_ASSCKSELR_AXISSRC_3 (0x3U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000003 */
#define RCC_ASSCKSELR_AXISSRC_4 (0x4U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000004 */
#define RCC_ASSCKSELR_AXISSRC_5 (0x5U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000005 */
#define RCC_ASSCKSELR_AXISSRC_6 (0x6U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000006 */
#define RCC_ASSCKSELR_AXISSRC_7 (0x7U << RCC_ASSCKSELR_AXISSRC_Pos) /*!< 0x00000007 */
#define RCC_ASSCKSELR_AXISSRCRDY_Pos (31U)
#define RCC_ASSCKSELR_AXISSRCRDY_Msk (0x1U << RCC_ASSCKSELR_AXISSRCRDY_Pos) /*!< 0x80000000 */
#define RCC_ASSCKSELR_AXISSRCRDY RCC_ASSCKSELR_AXISSRCRDY_Msk /*AXI sub-system clock switch status*/
/******************** Bit definition for RCC_MSSCKSELR register********************/
#define RCC_MSSCKSELR_MCUSSRC_Pos (0U)
#define RCC_MSSCKSELR_MCUSSRC_Msk (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */
#define RCC_MSSCKSELR_MCUSSRC RCC_MSSCKSELR_MCUSSRC_Msk /*MCU sub-system clock switch*/
#define RCC_MSSCKSELR_MCUSSRC_0 (0x0U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000000 */
#define RCC_MSSCKSELR_MCUSSRC_1 (0x1U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000001 */
#define RCC_MSSCKSELR_MCUSSRC_2 (0x2U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000002 */
#define RCC_MSSCKSELR_MCUSSRC_3 (0x3U << RCC_MSSCKSELR_MCUSSRC_Pos) /*!< 0x00000003 */
#define RCC_MSSCKSELR_MCUSSRCRDY_Pos (31U)
#define RCC_MSSCKSELR_MCUSSRCRDY_Msk (0x1U << RCC_MSSCKSELR_MCUSSRCRDY_Pos) /*!< 0x80000000 */
#define RCC_MSSCKSELR_MCUSSRCRDY RCC_MSSCKSELR_MCUSSRCRDY_Msk /*MCU sub-system clock switch status*/
/******************** Bit definition for RCC_RCK12SELR register********************/
#define RCC_RCK12SELR_PLL12SRC_Pos (0U)
#define RCC_RCK12SELR_PLL12SRC_Msk (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */
#define RCC_RCK12SELR_PLL12SRC RCC_RCK12SELR_PLL12SRC_Msk /*Reference clock selection for PLL1 and PLL2*/
#define RCC_RCK12SELR_PLL12SRC_0 (0x0U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000000 */
#define RCC_RCK12SELR_PLL12SRC_1 (0x1U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000001 */
#define RCC_RCK12SELR_PLL12SRC_2 (0x2U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000002 */
#define RCC_RCK12SELR_PLL12SRC_3 (0x3U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000003 */
#define RCC_RCK12SELR_PLL12SRC_4 (0x4U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000004 */
#define RCC_RCK12SELR_PLL12SRC_5 (0x5U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000005 */
#define RCC_RCK12SELR_PLL12SRC_6 (0x6U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000006 */
#define RCC_RCK12SELR_PLL12SRC_7 (0x7U << RCC_RCK12SELR_PLL12SRC_Pos) /*!< 0x00000007 */
#define RCC_RCK12SELR_PLL12SRCRDY_Pos (31U)
#define RCC_RCK12SELR_PLL12SRCRDY_Msk (0x1U << RCC_RCK12SELR_PLL12SRCRDY_Pos) /*!< 0x80000000 */
#define RCC_RCK12SELR_PLL12SRCRDY RCC_RCK12SELR_PLL12SRCRDY_Msk /*PLL12 reference clock switch status*/
/******************** Bit definition for RCC_RCK3SELR register********************/
#define RCC_RCK3SELR_PLL3SRC_Pos (0U)
#define RCC_RCK3SELR_PLL3SRC_Msk (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */
#define RCC_RCK3SELR_PLL3SRC RCC_RCK3SELR_PLL3SRC_Msk /*Reference clock selection for PLL3*/
#define RCC_RCK3SELR_PLL3SRC_0 (0x0U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000000 */
#define RCC_RCK3SELR_PLL3SRC_1 (0x1U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000001 */
#define RCC_RCK3SELR_PLL3SRC_2 (0x2U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000002 */
#define RCC_RCK3SELR_PLL3SRC_3 (0x3U << RCC_RCK3SELR_PLL3SRC_Pos) /*!< 0x00000003 */
#define RCC_RCK3SELR_PLL3SRCRDY_Pos (31U)
#define RCC_RCK3SELR_PLL3SRCRDY_Msk (0x1U << RCC_RCK3SELR_PLL3SRCRDY_Pos) /*!< 0x80000000 */
#define RCC_RCK3SELR_PLL3SRCRDY RCC_RCK3SELR_PLL3SRCRDY_Msk /*PLL3 reference clock switch status*/
/******************** Bit definition for RCC_RCK4SELR register********************/
#define RCC_RCK4SELR_PLL4SRC_Pos (0U)
#define RCC_RCK4SELR_PLL4SRC_Msk (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */
#define RCC_RCK4SELR_PLL4SRC RCC_RCK4SELR_PLL4SRC_Msk /*Reference clock selection for PLL4*/
#define RCC_RCK4SELR_PLL4SRC_0 (0x0U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000000 */
#define RCC_RCK4SELR_PLL4SRC_1 (0x1U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000001 */
#define RCC_RCK4SELR_PLL4SRC_2 (0x2U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000002 */
#define RCC_RCK4SELR_PLL4SRC_3 (0x3U << RCC_RCK4SELR_PLL4SRC_Pos) /*!< 0x00000003 */
#define RCC_RCK4SELR_PLL4SRCRDY_Pos (31U)
#define RCC_RCK4SELR_PLL4SRCRDY_Msk (0x1U << RCC_RCK4SELR_PLL4SRCRDY_Pos) /*!< 0x80000000 */
#define RCC_RCK4SELR_PLL4SRCRDY RCC_RCK4SELR_PLL4SRCRDY_Msk /*PLL4 reference clock switch status*/
/******************** Bit definition for RCC_TIMG1PRER register********************/
#define RCC_TIMG1PRER_TIMG1PRE_Pos (0U)
#define RCC_TIMG1PRER_TIMG1PRE_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000001 */
#define RCC_TIMG1PRER_TIMG1PRE RCC_TIMG1PRER_TIMG1PRE_Msk /*Timers clocks prescaler selection*/
#define RCC_TIMG1PRER_TIMG1PRE_0 (0x0U << RCC_TIMG1PRER_TIMG1PRE_Pos) /*!< 0x00000000 */
/*corresponding to a division by 1 or 2, else it is equal to
2 x Fck_pclk1 (default after reset)*/
#define RCC_TIMG1PRER_TIMG1PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB1DIV is
corresponding to division by 1, 2 or 4, else it is equal to
4 x Fck_pclk1 */
#define RCC_TIMG1PRER_TIMG1PRERDY_Pos (31U)
#define RCC_TIMG1PRER_TIMG1PRERDY_Msk (0x1U << RCC_TIMG1PRER_TIMG1PRERDY_Pos) /*!< 0x80000000 */
#define RCC_TIMG1PRER_TIMG1PRERDY RCC_TIMG1PRER_TIMG1PRERDY_Msk /*Timers clocks prescaler status*/
/******************** Bit definition for RCC_TIMG2PRER register********************/
#define RCC_TIMG2PRER_TIMG2PRE_Pos (0U)
#define RCC_TIMG2PRER_TIMG2PRE_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000001 */
#define RCC_TIMG2PRER_TIMG2PRE RCC_TIMG2PRER_TIMG2PRE_Msk /*Timers clocks prescaler selection*/
#define RCC_TIMG2PRER_TIMG2PRE_0 (0x0U << RCC_TIMG2PRER_TIMG2PRE_Pos) /*!< 0x00000000 */
/*corresponding to a division by 1 or 2, else it is equal
to 2 x Fck_pclk2 (default after reset)*/
#define RCC_TIMG2PRER_TIMG2PRE_1 ((uint32_t)0x00000001) /*The Timers kernel clock is equal to ck_hclk if APB2DIV is
corresponding to division by 1, 2 or 4, else it is equal to
4 x Fck_pclk2 */
#define RCC_TIMG2PRER_TIMG2PRERDY_Pos (31U)
#define RCC_TIMG2PRER_TIMG2PRERDY_Msk (0x1U << RCC_TIMG2PRER_TIMG2PRERDY_Pos) /*!< 0x80000000 */
#define RCC_TIMG2PRER_TIMG2PRERDY RCC_TIMG2PRER_TIMG2PRERDY_Msk /*Timers clocks prescaler status*/
/******************** Bit definition for RCC_RTCDIVR register********************/
#define RCC_RTCDIVR_RTCDIV_Pos (0U)
#define RCC_RTCDIVR_RTCDIV_Msk (0x3FU << RCC_RTCDIVR_RTCDIV_Pos) /*!< 0x0000003F */
#define RCC_RTCDIVR_RTCDIV RCC_RTCDIVR_RTCDIV_Msk /*HSE division factor for RTC clock*/
#define RCC_RTCDIVR_RTCDIV_1 (0x0U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_2 (0x1U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_3 (0x2U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_4 (0x3U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_5 (0x4U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_6 (0x5U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_7 (0x6U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_8 (0x7U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_9 (0x8U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_10 (0x9U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_11 (0xAU << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_12 (0xBU << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_13 (0xCU << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_14 (0xDU << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_15 (0xEU << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_16 (0xFU << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_17 (0x10U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_18 (0x11U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_19 (0x12U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_20 (0x13U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_21 (0x14U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_22 (0x15U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_23 (0x16U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_24 (0x17U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_25 (0x18U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_26 (0x19U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_27 (0x1AU << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_28 (0x1BU << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_29 (0x1CU << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_30 (0x1DU << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_31 (0x1EU << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_32 (0x1FU << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_33 (0x20U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_34 (0x21U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_35 (0x22U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_36 (0x23U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_37 (0x24U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_38 (0x25U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_39 (0x26U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_40 (0x27U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_41 (0x28U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_42 (0x29U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_43 (0x2AU << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_44 (0x2BU << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_45 (0x2CU << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_46 (0x2DU << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_47 (0x2EU << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_48 (0x2FU << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_49 (0x30U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_50 (0x31U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_51 (0x32U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_52 (0x33U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_53 (0x34U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_54 (0x35U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_55 (0x36U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_56 (0x37U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_57 (0x38U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_58 (0x39U << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_59 (0x3AU << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_60 (0x3BU << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_61 (0x3CU << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_62 (0x3DU << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_63 (0x3EU << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_64 (0x3FU << RCC_RTCDIVR_RTCDIV_Pos)
#define RCC_RTCDIVR_RTCDIV_(y) ( (uint32_t) (y-1) ) /*00:HSE, 01:HSE/2... 63: HSE/64*/
/******************** Bit definition for RCC_MPCKDIVR register********************/
#define RCC_MPCKDIVR_MPUDIV_Pos (0U)
#define RCC_MPCKDIVR_MPUDIV_Msk (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */
#define RCC_MPCKDIVR_MPUDIV RCC_MPCKDIVR_MPUDIV_Msk /*MPU Core clock divider*/
#define RCC_MPCKDIVR_MPUDIV_0 (0x0U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000000 */
#define RCC_MPCKDIVR_MPUDIV_1 (0x1U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000001 */
#define RCC_MPCKDIVR_MPUDIV_2 (0x2U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000002 */
#define RCC_MPCKDIVR_MPUDIV_3 (0x3U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000003 */
#define RCC_MPCKDIVR_MPUDIV_4 (0x4U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000004 */
#define RCC_MPCKDIVR_MPUDIV_5 (0x5U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000005 */
#define RCC_MPCKDIVR_MPUDIV_6 (0x6U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000006 */
#define RCC_MPCKDIVR_MPUDIV_7 (0x7U << RCC_MPCKDIVR_MPUDIV_Pos) /*!< 0x00000007 */
#define RCC_MPCKDIVR_MPUDIVRDY_Pos (31U)
#define RCC_MPCKDIVR_MPUDIVRDY_Msk (0x1U << RCC_MPCKDIVR_MPUDIVRDY_Pos) /*!< 0x80000000 */
#define RCC_MPCKDIVR_MPUDIVRDY RCC_MPCKDIVR_MPUDIVRDY_Msk /*MPU sub-system clock divider status*/
/******************** Bit definition for RCC_AXIDIVR register********************/
#define RCC_AXIDIVR_AXIDIV_Pos (0U)
#define RCC_AXIDIVR_AXIDIV_Msk (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */
#define RCC_AXIDIVR_AXIDIV RCC_AXIDIVR_AXIDIV_Msk /*AXI, AHB5 and AHB6 clock divider*/
#define RCC_AXIDIVR_AXIDIV_0 (0x0U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000000 */
#define RCC_AXIDIVR_AXIDIV_1 (0x1U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000001 */
#define RCC_AXIDIVR_AXIDIV_2 (0x2U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000002 */
#define RCC_AXIDIVR_AXIDIV_3 (0x3U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000003 */
#define RCC_AXIDIVR_AXIDIV_4 (0x4U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000004 */
#define RCC_AXIDIVR_AXIDIV_5 (0x5U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000005 */
#define RCC_AXIDIVR_AXIDIV_6 (0x6U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000006 */
#define RCC_AXIDIVR_AXIDIV_7 (0x7U << RCC_AXIDIVR_AXIDIV_Pos) /*!< 0x00000007 */
#define RCC_AXIDIVR_AXIDIVRDY_Pos (31U)
#define RCC_AXIDIVR_AXIDIVRDY_Msk (0x1U << RCC_AXIDIVR_AXIDIVRDY_Pos) /*!< 0x80000000 */
#define RCC_AXIDIVR_AXIDIVRDY RCC_AXIDIVR_AXIDIVRDY_Msk /*AXI sub-system clock divider status*/
/******************** Bit definition for RCC_APB4DIVR register********************/
#define RCC_APB4DIVR_APB4DIV_Pos (0U)
#define RCC_APB4DIVR_APB4DIV_Msk (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */
#define RCC_APB4DIVR_APB4DIV RCC_APB4DIVR_APB4DIV_Msk /*APB4 clock divider */
#define RCC_APB4DIVR_APB4DIV_0 (0x0U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000000 */
#define RCC_APB4DIVR_APB4DIV_1 (0x1U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000001 */
#define RCC_APB4DIVR_APB4DIV_2 (0x2U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000002 */
#define RCC_APB4DIVR_APB4DIV_3 (0x3U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000003 */
#define RCC_APB4DIVR_APB4DIV_4 (0x4U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000004 */
#define RCC_APB4DIVR_APB4DIV_5 (0x5U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000005 */
#define RCC_APB4DIVR_APB4DIV_6 (0x6U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000006 */
#define RCC_APB4DIVR_APB4DIV_7 (0x7U << RCC_APB4DIVR_APB4DIV_Pos) /*!< 0x00000007 */
#define RCC_APB4DIVR_APB4DIVRDY_Pos (31U)
#define RCC_APB4DIVR_APB4DIVRDY_Msk (0x1U << RCC_APB4DIVR_APB4DIVRDY_Pos) /*!< 0x80000000 */
#define RCC_APB4DIVR_APB4DIVRDY RCC_APB4DIVR_APB4DIVRDY_Msk /*APB4 clock divider status*/
/******************** Bit definition for RCC_APB5DIVR register********************/
#define RCC_APB5DIVR_APB5DIV_Pos (0U)
#define RCC_APB5DIVR_APB5DIV_Msk (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */
#define RCC_APB5DIVR_APB5DIV RCC_APB5DIVR_APB5DIV_Msk /*APB5 clock divider*/
#define RCC_APB5DIVR_APB5DIV_0 (0x0U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000000 */
#define RCC_APB5DIVR_APB5DIV_1 (0x1U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000001 */
#define RCC_APB5DIVR_APB5DIV_2 (0x2U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000002 */
#define RCC_APB5DIVR_APB5DIV_3 (0x3U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000003 */
#define RCC_APB5DIVR_APB5DIV_4 (0x4U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000004 */
#define RCC_APB5DIVR_APB5DIV_5 (0x5U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000005 */
#define RCC_APB5DIVR_APB5DIV_6 (0x6U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000006 */
#define RCC_APB5DIVR_APB5DIV_7 (0x7U << RCC_APB5DIVR_APB5DIV_Pos) /*!< 0x00000007 */
#define RCC_APB5DIVR_APB5DIVRDY_Pos (31U)
#define RCC_APB5DIVR_APB5DIVRDY_Msk (0x1U << RCC_APB5DIVR_APB5DIVRDY_Pos) /*!< 0x80000000 */
#define RCC_APB5DIVR_APB5DIVRDY RCC_APB5DIVR_APB5DIVRDY_Msk /*APB5 clock divider status*/
/******************** Bit definition for RCC_MCUDIVR register********************/
#define RCC_MCUDIVR_MCUDIV_Pos (0U)
#define RCC_MCUDIVR_MCUDIV_Msk (0xFU << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x0000000F */
#define RCC_MCUDIVR_MCUDIV RCC_MCUDIVR_MCUDIV_Msk /*MCU clock divider*/
#define RCC_MCUDIVR_MCUDIV_0 (0x0U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000000 */
#define RCC_MCUDIVR_MCUDIV_1 (0x1U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000001 */
#define RCC_MCUDIVR_MCUDIV_2 (0x2U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000002 */
#define RCC_MCUDIVR_MCUDIV_3 (0x3U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000003 */
#define RCC_MCUDIVR_MCUDIV_4 (0x4U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000004 */
#define RCC_MCUDIVR_MCUDIV_5 (0x5U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000005 */
#define RCC_MCUDIVR_MCUDIV_6 (0x6U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000006 */
#define RCC_MCUDIVR_MCUDIV_7 (0x7U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000007 */
#define RCC_MCUDIVR_MCUDIV_8 (0x8U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000008 */
#define RCC_MCUDIVR_MCUDIV_9 (0x9U << RCC_MCUDIVR_MCUDIV_Pos) /*!< 0x00000009 */
/* @note others: ck_mcuss divided by 512 */
#define RCC_MCUDIVR_MCUDIVRDY_Pos (31U)
#define RCC_MCUDIVR_MCUDIVRDY_Msk (0x1U << RCC_MCUDIVR_MCUDIVRDY_Pos) /*!< 0x80000000 */
#define RCC_MCUDIVR_MCUDIVRDY RCC_MCUDIVR_MCUDIVRDY_Msk /*MCU clock prescaler status*/
/******************** Bit definition for RCC_APB1DIVR register********************/
#define RCC_APB1DIVR_APB1DIV_Pos (0U)
#define RCC_APB1DIVR_APB1DIV_Msk (0x7U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000007 */
#define RCC_APB1DIVR_APB1DIV RCC_APB1DIVR_APB1DIV_Msk /*APB1 clock prescaler*/
#define RCC_APB1DIVR_APB1DIV_0 (0x0U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000000 */
#define RCC_APB1DIVR_APB1DIV_1 (0x1U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000001 */
#define RCC_APB1DIVR_APB1DIV_2 (0x2U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000002 */
#define RCC_APB1DIVR_APB1DIV_3 (0x3U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000003 */
#define RCC_APB1DIVR_APB1DIV_4 (0x4U << RCC_APB1DIVR_APB1DIV_Pos) /*!< 0x00000004 */
/* @note others: ck_hclk/16 */
#define RCC_APB1DIVR_APB1DIVRDY_Pos (31U)
#define RCC_APB1DIVR_APB1DIVRDY_Msk (0x1U << RCC_APB1DIVR_APB1DIVRDY_Pos) /*!< 0x80000000 */
#define RCC_APB1DIVR_APB1DIVRDY RCC_APB1DIVR_APB1DIVRDY_Msk /*APB1 clock prescaler status*/
/******************** Bit definition for RCC_APB2DIV register********************/
#define RCC_APB2DIVR_APB2DIV_Pos (0U)
#define RCC_APB2DIVR_APB2DIV_Msk (0x7U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000007 */
#define RCC_APB2DIVR_APB2DIV RCC_APB2DIVR_APB2DIV_Msk /*APB2 clock prescaler*/
#define RCC_APB2DIVR_APB2DIV_0 (0x0U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000000 */
#define RCC_APB2DIVR_APB2DIV_1 (0x1U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000001 */
#define RCC_APB2DIVR_APB2DIV_2 (0x2U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000002 */
#define RCC_APB2DIVR_APB2DIV_3 (0x3U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000003 */
#define RCC_APB2DIVR_APB2DIV_4 (0x4U << RCC_APB2DIVR_APB2DIV_Pos) /*!< 0x00000004 */
/* @note others: ck_hclk/16 */
#define RCC_APB2DIVR_APB2DIVRDY_Pos (31U)
#define RCC_APB2DIVR_APB2DIVRDY_Msk (0x1U << RCC_APB2DIVR_APB2DIVRDY_Pos) /*!< 0x80000000 */
#define RCC_APB2DIVR_APB2DIVRDY RCC_APB2DIVR_APB2DIVRDY_Msk /*APB2 clock prescaler status*/
/******************** Bit definition for RCC_APB3DIV register********************/
#define RCC_APB3DIVR_APB3DIV_Pos (0U)
#define RCC_APB3DIVR_APB3DIV_Msk (0x7U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000007 */
#define RCC_APB3DIVR_APB3DIV RCC_APB3DIVR_APB3DIV_Msk /*APB3 clock prescaler*/
#define RCC_APB3DIVR_APB3DIV_0 (0x0U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000000 */
#define RCC_APB3DIVR_APB3DIV_1 (0x1U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000001 */
#define RCC_APB3DIVR_APB3DIV_2 (0x2U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000002 */
#define RCC_APB3DIVR_APB3DIV_3 (0x3U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000003 */
#define RCC_APB3DIVR_APB3DIV_4 (0x4U << RCC_APB3DIVR_APB3DIV_Pos) /*!< 0x00000004 */
/* @note others: ck_hclk/16 */
#define RCC_APB3DIVR_APB3DIVRDY_Pos (31U)
#define RCC_APB3DIVR_APB3DIVRDY_Msk (0x1U << RCC_APB3DIVR_APB3DIVRDY_Pos) /*!< 0x80000000 */
#define RCC_APB3DIVR_APB3DIVRDY RCC_APB3DIVR_APB3DIVRDY_Msk /*APB3 clock prescaler status*/
/******************** Bit definition for RCC_PLL1CR register********************/
#define RCC_PLL1CR_PLLON_Pos (0U)
#define RCC_PLL1CR_PLLON_Msk (0x1U << RCC_PLL1CR_PLLON_Pos) /*!< 0x00000001 */
#define RCC_PLL1CR_PLLON RCC_PLL1CR_PLLON_Msk /*PLL1 enable*/
#define RCC_PLL1CR_PLL1RDY_Pos (1U)
#define RCC_PLL1CR_PLL1RDY_Msk (0x1U << RCC_PLL1CR_PLL1RDY_Pos) /*!< 0x00000002 */
#define RCC_PLL1CR_PLL1RDY RCC_PLL1CR_PLL1RDY_Msk /*PLL1 clock ready flag*/
#define RCC_PLL1CR_SSCG_CTRL_Pos (2U)
#define RCC_PLL1CR_SSCG_CTRL_Msk (0x1U << RCC_PLL1CR_SSCG_CTRL_Pos) /*!< 0x00000004 */
#define RCC_PLL1CR_SSCG_CTRL RCC_PLL1CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL1 enable*/
#define RCC_PLL1CR_DIVPEN_Pos (4U)
#define RCC_PLL1CR_DIVPEN_Msk (0x1U << RCC_PLL1CR_DIVPEN_Pos) /*!< 0x00000010 */
#define RCC_PLL1CR_DIVPEN RCC_PLL1CR_DIVPEN_Msk /*PLL1 DIVP divider output enable*/
#define RCC_PLL1CR_DIVQEN_Pos (5U)
#define RCC_PLL1CR_DIVQEN_Msk (0x1U << RCC_PLL1CR_DIVQEN_Pos) /*!< 0x00000020 */
#define RCC_PLL1CR_DIVQEN RCC_PLL1CR_DIVQEN_Msk /*PLL1 DIVQ divider output enable*/
#define RCC_PLL1CR_DIVREN_Pos (6U)
#define RCC_PLL1CR_DIVREN_Msk (0x1U << RCC_PLL1CR_DIVREN_Pos) /*!< 0x00000040 */
#define RCC_PLL1CR_DIVREN RCC_PLL1CR_DIVREN_Msk /*PLL1 DIVR divider output enable*/
/******************** Bit definition for RCC_PLL1CFGR1 register********************/
#define RCC_PLL1CFGR1_DIVN_Pos (0U)
#define RCC_PLL1CFGR1_DIVN_Msk (0x1FFU << RCC_PLL1CFGR1_DIVN_Pos) /*!< 0x000001FF */
#define RCC_PLL1CFGR1_DIVN RCC_PLL1CFGR1_DIVN_Msk /*Multiplication factor for PLL1 VCO*/
/* @note Valid division rations for DIVN: between 25 and 100 */
#define RCC_PLL1CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */
#define RCC_PLL1CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */
#define RCC_PLL1CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */
#define RCC_PLL1CFGR1_DIVM1_Pos (16U)
#define RCC_PLL1CFGR1_DIVM1_Msk (0x3FU << RCC_PLL1CFGR1_DIVM1_Pos) /*!< 0x003F0000 */
#define RCC_PLL1CFGR1_DIVM1 RCC_PLL1CFGR1_DIVM1_Msk /*Prescaler for PLL1*/
/* @note "y" division factor must be an integer value between 1 and 64 */
#define RCC_PLL1CFGR1_DIVM1_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4))
/******************** Bit definition for RCC_PLL1CFGR2 register********************/
/* @TODO To compleate as needed */
#define RCC_PLL1CFGR2_DIVP_Pos (0U)
#define RCC_PLL1CFGR2_DIVP_Msk (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */
#define RCC_PLL1CFGR2_DIVP RCC_PLL1CFGR2_DIVP_Msk /*PLL1 DIVP division factor*/
#define RCC_PLL1CFGR2_DIVP_0 (0x00U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000000 */
#define RCC_PLL1CFGR2_DIVP_1 (0x01U << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x00000001 */
#define RCC_PLL1CFGR2_DIVP_128 (0x7FU << RCC_PLL1CFGR2_DIVP_Pos) /*!< 0x0000007F */
#define RCC_PLL1CFGR2_DIVQ_Pos (8U)
#define RCC_PLL1CFGR2_DIVQ_Msk (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
#define RCC_PLL1CFGR2_DIVQ RCC_PLL1CFGR2_DIVQ_Msk /*PLL1 DIVQ division factor*/
#define RCC_PLL1CFGR2_DIVQ_0 (0x00U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000000 */
#define RCC_PLL1CFGR2_DIVQ_1 (0x01U << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00000100 */
#define RCC_PLL1CFGR2_DIVQ_128 (0x7FU << RCC_PLL1CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
#define RCC_PLL1CFGR2_DIVR_Pos (16U)
#define RCC_PLL1CFGR2_DIVR_Msk (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */
#define RCC_PLL1CFGR2_DIVR RCC_PLL1CFGR2_DIVR_Msk /*PLL1 DIVR division factor*/
#define RCC_PLL1CFGR2_DIVR_0 (0x00U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00000000 */
#define RCC_PLL1CFGR2_DIVR_1 (0x01U << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x00010000 */
#define RCC_PLL1CFGR2_DIVR_128 (0x7FU << RCC_PLL1CFGR2_DIVR_Pos) /*!< 0x007F0000 */
/******************** Bit definition for RCC_PLL1FRACR register********************/
#define RCC_PLL1FRACR_FRACV_Pos (3U)
#define RCC_PLL1FRACR_FRACV_Msk (0x1FFFU << RCC_PLL1FRACR_FRACV_Pos) /*!< 0x0000FFF8 */
#define RCC_PLL1FRACR_FRACV RCC_PLL1FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL1 VCO*/
/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */
#define RCC_PLL1FRACR_FRACLE_Pos (16U)
#define RCC_PLL1FRACR_FRACLE_Msk (0x1U << RCC_PLL1FRACR_FRACLE_Pos) /*!< 0x00010000 */
#define RCC_PLL1FRACR_FRACLE RCC_PLL1FRACR_FRACLE_Msk /*PLL1 fractional latch enable*/
/******************** Bit definition for RCC_PLL1CSGR register********************/
#define RCC_PLL1CSGR_MOD_PER_Pos (0U)
#define RCC_PLL1CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL1CSGR_MOD_PER_Pos) /*!< 0x00001FFF */
#define RCC_PLL1CSGR_MOD_PER RCC_PLL1CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL1*/
#define RCC_PLL1CSGR_TPDFN_DIS_Pos (13U)
#define RCC_PLL1CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */
#define RCC_PLL1CSGR_TPDFN_DIS RCC_PLL1CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/
#define RCC_PLL1CSGR_RPDFN_DIS_Pos (14U)
#define RCC_PLL1CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL1CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */
#define RCC_PLL1CSGR_RPDFN_DIS RCC_PLL1CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/
#define RCC_PLL1CSGR_SSCG_MODE_Pos (15U)
#define RCC_PLL1CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL1CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */
#define RCC_PLL1CSGR_SSCG_MODE RCC_PLL1CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/
#define RCC_PLL1CSGR_INC_STEP_Pos (16U)
#define RCC_PLL1CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL1CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */
#define RCC_PLL1CSGR_INC_STEP RCC_PLL1CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL1*/
/******************** Bit definition for RCC_PLL2CR register********************/
#define RCC_PLL2CR_PLLON_Pos (0U)
#define RCC_PLL2CR_PLLON_Msk (0x1U << RCC_PLL2CR_PLLON_Pos) /*!< 0x00000001 */
#define RCC_PLL2CR_PLLON RCC_PLL2CR_PLLON_Msk /*PLL2 enable*/
#define RCC_PLL2CR_PLL2RDY_Pos (1U)
#define RCC_PLL2CR_PLL2RDY_Msk (0x1U << RCC_PLL2CR_PLL2RDY_Pos) /*!< 0x00000002 */
#define RCC_PLL2CR_PLL2RDY RCC_PLL2CR_PLL2RDY_Msk /*PLL2 clock ready flag*/
#define RCC_PLL2CR_SSCG_CTRL_Pos (2U)
#define RCC_PLL2CR_SSCG_CTRL_Msk (0x1U << RCC_PLL2CR_SSCG_CTRL_Pos) /*!< 0x00000004 */
#define RCC_PLL2CR_SSCG_CTRL RCC_PLL2CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL2 enable*/
#define RCC_PLL2CR_DIVPEN_Pos (4U)
#define RCC_PLL2CR_DIVPEN_Msk (0x1U << RCC_PLL2CR_DIVPEN_Pos) /*!< 0x00000010 */
#define RCC_PLL2CR_DIVPEN RCC_PLL2CR_DIVPEN_Msk /*PLL2 DIVP divider output enable*/
#define RCC_PLL2CR_DIVQEN_Pos (5U)
#define RCC_PLL2CR_DIVQEN_Msk (0x1U << RCC_PLL2CR_DIVQEN_Pos) /*!< 0x00000020 */
#define RCC_PLL2CR_DIVQEN RCC_PLL2CR_DIVQEN_Msk /*PLL2 DIVQ divider output enable*/
#define RCC_PLL2CR_DIVREN_Pos (6U)
#define RCC_PLL2CR_DIVREN_Msk (0x1U << RCC_PLL2CR_DIVREN_Pos) /*!< 0x00000040 */
#define RCC_PLL2CR_DIVREN RCC_PLL2CR_DIVREN_Msk /*PLL2 DIVR divider output enable*/
/******************** Bit definition for RCC_PLL2CFGR1 register********************/
#define RCC_PLL2CFGR1_DIVN_Pos (0U)
#define RCC_PLL2CFGR1_DIVN_Msk (0x1FFU << RCC_PLL2CFGR1_DIVN_Pos) /*!< 0x000001FF */
#define RCC_PLL2CFGR1_DIVN RCC_PLL2CFGR1_DIVN_Msk /*Multiplication factor for PLL2*/
/* @note Valid division rations for DIVN: between 25 and 100 */
#define RCC_PLL2CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */
#define RCC_PLL2CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */
#define RCC_PLL2CFGR1_DIVN_100 ((uint32_t)0x00000063) /* Division ratio is 100 */
#define RCC_PLL2CFGR1_DIVM2_Pos (16U)
#define RCC_PLL2CFGR1_DIVM2_Pos (16U)
#define RCC_PLL2CFGR1_DIVM2_Msk (0x3FU << RCC_PLL2CFGR1_DIVM2_Pos) /*!< 0x003F0000 */
#define RCC_PLL2CFGR1_DIVM2 RCC_PLL2CFGR1_DIVM2_Msk /*Prescaler for PLL2*/
/* @note "y" division factor must be an integer value between 1 and 64 */
#define RCC_PLL2CFGR1_DIVM2_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4))
/******************** Bit definition for RCC_PLL2CFGR2 register********************/
/* @TODO To compleate as needed */
#define RCC_PLL2CFGR2_DIVP_Pos (0U)
#define RCC_PLL2CFGR2_DIVP_Msk (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */
#define RCC_PLL2CFGR2_DIVP RCC_PLL2CFGR2_DIVP_Msk /*PLL2 DIVP division factor*/
#define RCC_PLL2CFGR2_DIVP_0 (0x00U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000000 */
#define RCC_PLL2CFGR2_DIVP_1 (0x01U << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x00000001 */
#define RCC_PLL2CFGR2_DIVP_128 (0x7FU << RCC_PLL2CFGR2_DIVP_Pos) /*!< 0x0000007F */
#define RCC_PLL2CFGR2_DIVQ_Pos (8U)
#define RCC_PLL2CFGR2_DIVQ_Msk (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
#define RCC_PLL2CFGR2_DIVQ RCC_PLL2CFGR2_DIVQ_Msk /*PLL2 DIVQ division factor*/
#define RCC_PLL2CFGR2_DIVQ_0 (0x00U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000000 */
#define RCC_PLL2CFGR2_DIVQ_1 (0x01U << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00000100 */
#define RCC_PLL2CFGR2_DIVQ_128 (0x7FU << RCC_PLL2CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
#define RCC_PLL2CFGR2_DIVR_Pos (16U)
#define RCC_PLL2CFGR2_DIVR_Msk (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */
#define RCC_PLL2CFGR2_DIVR RCC_PLL2CFGR2_DIVR_Msk /*PLL2 DIVR division factor*/
#define RCC_PLL2CFGR2_DIVR_0 (0x00U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00000000 */
#define RCC_PLL2CFGR2_DIVR_1 (0x01U << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x00010000 */
#define RCC_PLL2CFGR2_DIVR_128 (0x7FU << RCC_PLL2CFGR2_DIVR_Pos) /*!< 0x007F0000 */
/******************** Bit definition for RCC_PLL2FRACR register********************/
#define RCC_PLL2FRACR_FRACV_Pos (3U)
#define RCC_PLL2FRACR_FRACV_Msk (0x1FFFU << RCC_PLL2FRACR_FRACV_Pos) /*!< 0x0000FFF8 */
#define RCC_PLL2FRACR_FRACV RCC_PLL2FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL2 VCO*/
/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */
#define RCC_PLL2FRACR_FRACLE_Pos (16U)
#define RCC_PLL2FRACR_FRACLE_Msk (0x1U << RCC_PLL2FRACR_FRACLE_Pos) /*!< 0x00010000 */
#define RCC_PLL2FRACR_FRACLE RCC_PLL2FRACR_FRACLE_Msk /*PLL2 fractional latch enable*/
/******************** Bit definition for RCC_PLL2CSGR register********************/
#define RCC_PLL2CSGR_MOD_PER_Pos (0U)
#define RCC_PLL2CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL2CSGR_MOD_PER_Pos) /*!< 0x00001FFF */
#define RCC_PLL2CSGR_MOD_PER RCC_PLL2CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL2*/
#define RCC_PLL2CSGR_TPDFN_DIS_Pos (13U)
#define RCC_PLL2CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */
#define RCC_PLL2CSGR_TPDFN_DIS RCC_PLL2CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/
#define RCC_PLL2CSGR_RPDFN_DIS_Pos (14U)
#define RCC_PLL2CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL2CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */
#define RCC_PLL2CSGR_RPDFN_DIS RCC_PLL2CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/
#define RCC_PLL2CSGR_SSCG_MODE_Pos (15U)
#define RCC_PLL2CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL2CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */
#define RCC_PLL2CSGR_SSCG_MODE RCC_PLL2CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/
#define RCC_PLL2CSGR_INC_STEP_Pos (16U)
#define RCC_PLL2CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL2CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */
#define RCC_PLL2CSGR_INC_STEP RCC_PLL2CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL2*/
/******************** Bit definition for RCC_PLL3CR register********************/
#define RCC_PLL3CR_PLLON_Pos (0U)
#define RCC_PLL3CR_PLLON_Msk (0x1U << RCC_PLL3CR_PLLON_Pos) /*!< 0x00000001 */
#define RCC_PLL3CR_PLLON RCC_PLL3CR_PLLON_Msk /*PLL3 enable*/
#define RCC_PLL3CR_PLL3RDY_Pos (1U)
#define RCC_PLL3CR_PLL3RDY_Msk (0x1U << RCC_PLL3CR_PLL3RDY_Pos) /*!< 0x00000002 */
#define RCC_PLL3CR_PLL3RDY RCC_PLL3CR_PLL3RDY_Msk /*PLL3 clock ready flag*/
#define RCC_PLL3CR_SSCG_CTRL_Pos (2U)
#define RCC_PLL3CR_SSCG_CTRL_Msk (0x1U << RCC_PLL3CR_SSCG_CTRL_Pos) /*!< 0x00000004 */
#define RCC_PLL3CR_SSCG_CTRL RCC_PLL3CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL3 enable*/
#define RCC_PLL3CR_DIVPEN_Pos (4U)
#define RCC_PLL3CR_DIVPEN_Msk (0x1U << RCC_PLL3CR_DIVPEN_Pos) /*!< 0x00000010 */
#define RCC_PLL3CR_DIVPEN RCC_PLL3CR_DIVPEN_Msk /*PLL3 DIVP divider output enable*/
#define RCC_PLL3CR_DIVQEN_Pos (5U)
#define RCC_PLL3CR_DIVQEN_Msk (0x1U << RCC_PLL3CR_DIVQEN_Pos) /*!< 0x00000020 */
#define RCC_PLL3CR_DIVQEN RCC_PLL3CR_DIVQEN_Msk /*PLL3 DIVQ divider output enable*/
#define RCC_PLL3CR_DIVREN_Pos (6U)
#define RCC_PLL3CR_DIVREN_Msk (0x1U << RCC_PLL3CR_DIVREN_Pos) /*!< 0x00000040 */
#define RCC_PLL3CR_DIVREN RCC_PLL3CR_DIVREN_Msk /*PLL3 DIVR divider output enable*/
/******************** Bit definition for RCC_PLL3CFGR1 register********************/
#define RCC_PLL3CFGR1_DIVN_Pos (0U)
#define RCC_PLL3CFGR1_DIVN_Msk (0x1FFU << RCC_PLL3CFGR1_DIVN_Pos) /*!< 0x000001FF */
#define RCC_PLL3CFGR1_DIVN RCC_PLL3CFGR1_DIVN_Msk /*Multiplication factor for PLL3*/
/* @note Valid division rations for DIVN: between 25 and 200 */
#define RCC_PLL3CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */
#define RCC_PLL3CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */
#define RCC_PLL3CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */
#define RCC_PLL3CFGR1_DIVM3_Pos (16U)
#define RCC_PLL3CFGR1_DIVM3_Pos (16U)
#define RCC_PLL3CFGR1_DIVM3_Msk (0x3FU << RCC_PLL3CFGR1_DIVM3_Pos) /*!< 0x003F0000 */
#define RCC_PLL3CFGR1_DIVM3 RCC_PLL3CFGR1_DIVM3_Msk /*Prescaler for PLL3*/
/* @note "y" division factor must be an integer value between 1 and 64 */
#define RCC_PLL3CFGR1_DIVM3_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4))
#define RCC_PLL3CFGR1_IFRGE_Pos (24U)
#define RCC_PLL3CFGR1_IFRGE_Msk (0x3U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x03000000 */
#define RCC_PLL3CFGR1_IFRGE RCC_PLL3CFGR1_IFRGE_Msk /*PLL3 input frequency range*/
#define RCC_PLL3CFGR1_IFRGE_0 (0x0U << RCC_PLL3CFGR1_IFRGE_Pos) /*!< 0x00000000 */
/* between 4 and 8 MHz (default after reset) */
#define RCC_PLL3CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL3 input (ck_ref3) clock range frequency is
between 8 and 16 MHz */
/* @note other IFRGE values are reserved */
/******************** Bit definition for RCC_PLL3CFGR2 register********************/
/* @TODO To compleate as needed */
#define RCC_PLL3CFGR2_DIVP_Pos (0U)
#define RCC_PLL3CFGR2_DIVP_Msk (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */
#define RCC_PLL3CFGR2_DIVP RCC_PLL3CFGR2_DIVP_Msk /*PLL3 DIVP division factor*/
#define RCC_PLL3CFGR2_DIVP_0 (0x00U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000000 */
#define RCC_PLL3CFGR2_DIVP_1 (0x01U << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x00000001 */
#define RCC_PLL3CFGR2_DIVP_128 (0x7FU << RCC_PLL3CFGR2_DIVP_Pos) /*!< 0x0000007F */
#define RCC_PLL3CFGR2_DIVQ_Pos (8U)
#define RCC_PLL3CFGR2_DIVQ_Msk (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
#define RCC_PLL3CFGR2_DIVQ RCC_PLL3CFGR2_DIVQ_Msk /*PLL3 DIVQ division factor*/
#define RCC_PLL3CFGR2_DIVQ_0 (0x00U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000000 */
#define RCC_PLL3CFGR2_DIVQ_1 (0x01U << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00000100 */
#define RCC_PLL3CFGR2_DIVQ_128 (0x7FU << RCC_PLL3CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
#define RCC_PLL3CFGR2_DIVR_Pos (16U)
#define RCC_PLL3CFGR2_DIVR_Msk (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */
#define RCC_PLL3CFGR2_DIVR RCC_PLL3CFGR2_DIVR_Msk /*PLL3 DIVR division factor*/
#define RCC_PLL3CFGR2_DIVR_0 (0x00U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00000000 */
#define RCC_PLL3CFGR2_DIVR_1 (0x01U << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x00010000 */
#define RCC_PLL3CFGR2_DIVR_128 (0x7FU << RCC_PLL3CFGR2_DIVR_Pos) /*!< 0x007F0000 */
/******************** Bit definition for RCC_PLL3FRACR register********************/
#define RCC_PLL3FRACR_FRACV_Pos (3U)
#define RCC_PLL3FRACR_FRACV_Msk (0x1FFFU << RCC_PLL3FRACR_FRACV_Pos) /*!< 0x0000FFF8 */
#define RCC_PLL3FRACR_FRACV RCC_PLL3FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL3 VCO*/
/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */
#define RCC_PLL3FRACR_FRACLE_Pos (16U)
#define RCC_PLL3FRACR_FRACLE_Msk (0x1U << RCC_PLL3FRACR_FRACLE_Pos) /*!< 0x00010000 */
#define RCC_PLL3FRACR_FRACLE RCC_PLL3FRACR_FRACLE_Msk /*PLL3 fractional latch enable*/
/******************** Bit definition for RCC_PLL3CSGR register********************/
#define RCC_PLL3CSGR_MOD_PER_Pos (0U)
#define RCC_PLL3CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL3CSGR_MOD_PER_Pos) /*!< 0x00001FFF */
#define RCC_PLL3CSGR_MOD_PER RCC_PLL3CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL3*/
#define RCC_PLL3CSGR_TPDFN_DIS_Pos (13U)
#define RCC_PLL3CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL3CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */
#define RCC_PLL3CSGR_TPDFN_DIS RCC_PLL3CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/
#define RCC_PLL3CSGR_RPDFN_DIS_Pos (14U)
#define RCC_PLL3CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL3CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */
#define RCC_PLL3CSGR_RPDFN_DIS RCC_PLL3CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/
#define RCC_PLL3CSGR_SSCG_MODE_Pos (15U)
#define RCC_PLL3CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL3CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */
#define RCC_PLL3CSGR_SSCG_MODE RCC_PLL3CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/
#define RCC_PLL3CSGR_INC_STEP_Pos (16U)
#define RCC_PLL3CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL3CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */
#define RCC_PLL3CSGR_INC_STEP RCC_PLL3CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL3*/
/******************** Bit definition for RCC_PLL4CR register********************/
#define RCC_PLL4CR_PLLON_Pos (0U)
#define RCC_PLL4CR_PLLON_Msk (0x1U << RCC_PLL4CR_PLLON_Pos) /*!< 0x00000001 */
#define RCC_PLL4CR_PLLON RCC_PLL4CR_PLLON_Msk /*PLL4 enable*/
#define RCC_PLL4CR_PLL4RDY_Pos (1U)
#define RCC_PLL4CR_PLL4RDY_Msk (0x1U << RCC_PLL4CR_PLL4RDY_Pos) /*!< 0x00000002 */
#define RCC_PLL4CR_PLL4RDY RCC_PLL4CR_PLL4RDY_Msk /*PLL4 clock ready flag*/
#define RCC_PLL4CR_SSCG_CTRL_Pos (2U)
#define RCC_PLL4CR_SSCG_CTRL_Msk (0x1U << RCC_PLL4CR_SSCG_CTRL_Pos) /*!< 0x00000004 */
#define RCC_PLL4CR_SSCG_CTRL RCC_PLL4CR_SSCG_CTRL_Msk /*Spread Spectrum Clock Generator of PLL4 enable*/
#define RCC_PLL4CR_DIVPEN_Pos (4U)
#define RCC_PLL4CR_DIVPEN_Msk (0x1U << RCC_PLL4CR_DIVPEN_Pos) /*!< 0x00000010 */
#define RCC_PLL4CR_DIVPEN RCC_PLL4CR_DIVPEN_Msk /*PLL4 DIVP divider output enable*/
#define RCC_PLL4CR_DIVQEN_Pos (5U)
#define RCC_PLL4CR_DIVQEN_Msk (0x1U << RCC_PLL4CR_DIVQEN_Pos) /*!< 0x00000020 */
#define RCC_PLL4CR_DIVQEN RCC_PLL4CR_DIVQEN_Msk /*PLL4 DIVQ divider output enable*/
#define RCC_PLL4CR_DIVREN_Pos (6U)
#define RCC_PLL4CR_DIVREN_Msk (0x1U << RCC_PLL4CR_DIVREN_Pos) /*!< 0x00000040 */
#define RCC_PLL4CR_DIVREN RCC_PLL4CR_DIVREN_Msk /*PLL4 DIVR divider output enable*/
/******************** Bit definition for RCC_PLL4CFGR1 register********************/
#define RCC_PLL4CFGR1_DIVN_Pos (0U)
#define RCC_PLL4CFGR1_DIVN_Msk (0x1FFU << RCC_PLL4CFGR1_DIVN_Pos) /*!< 0x000001FF */
#define RCC_PLL4CFGR1_DIVN RCC_PLL4CFGR1_DIVN_Msk /*Multiplication factor for PLL4*/
/* @note Valid division rations for DIVN: between 25 and 200 */
#define RCC_PLL4CFGR1_DIVN_25 ((uint32_t)0x00000018) /* Division ratio is 25 */
#define RCC_PLL4CFGR1_DIVN_26 ((uint32_t)0x00000019) /* Division ratio is 26 */
#define RCC_PLL4CFGR1_DIVN_200 ((uint32_t)0x000000C7) /* Division ratio is 200 */
#define RCC_PLL4CFGR1_DIVM4_Pos (16U)
#define RCC_PLL4CFGR1_DIVM4_Pos (16U)
#define RCC_PLL4CFGR1_DIVM4_Msk (0x3FU << RCC_PLL4CFGR1_DIVM4_Pos) /*!< 0x003F0000 */
#define RCC_PLL4CFGR1_DIVM4 RCC_PLL4CFGR1_DIVM4_Msk /*Prescaler for PLL4*/
/* @note "y" division factor must be an integer value between 1 and 64 */
#define RCC_PLL4CFGR1_DIVM4_(y) ((uint32_t)(0x003F0000) & ((y-1) << 4))
#define RCC_PLL4CFGR1_IFRGE_Pos (24U)
#define RCC_PLL4CFGR1_IFRGE_Msk (0x3U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x03000000 */
#define RCC_PLL4CFGR1_IFRGE RCC_PLL4CFGR1_IFRGE_Msk /*PLL4 input frequency range*/
#define RCC_PLL4CFGR1_IFRGE_0 (0x0U << RCC_PLL4CFGR1_IFRGE_Pos) /*!< 0x00000000 */
/*between 4 and 8 MHz (default after reset) */
#define RCC_PLL4CFGR1_IFRGE_1 ((uint32_t)0x01000000) /*The PLL4 input (ck_ref4) clock range frequency is
between 8 and 16 MHz */
/* @note other IFRGE values are reserved */
/******************** Bit definition for RCC_PLL4CFGR2 register********************/
/* @TODO To compleate as needed */
#define RCC_PLL4CFGR2_DIVP_Pos (0U)
#define RCC_PLL4CFGR2_DIVP_Msk (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */
#define RCC_PLL4CFGR2_DIVP RCC_PLL4CFGR2_DIVP_Msk /*PLL4 DIVP division factor*/
#define RCC_PLL4CFGR2_DIVP_0 (0x00U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000000 */
#define RCC_PLL4CFGR2_DIVP_1 (0x01U << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x00000001 */
#define RCC_PLL4CFGR2_DIVP_128 (0x7FU << RCC_PLL4CFGR2_DIVP_Pos) /*!< 0x0000007F */
#define RCC_PLL4CFGR2_DIVQ_Pos (8U)
#define RCC_PLL4CFGR2_DIVQ_Msk (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
#define RCC_PLL4CFGR2_DIVQ RCC_PLL4CFGR2_DIVQ_Msk /*PLL4 DIVQ division factor*/
#define RCC_PLL4CFGR2_DIVQ_0 (0x00U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000000 */
#define RCC_PLL4CFGR2_DIVQ_1 (0x01U << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00000100 */
#define RCC_PLL4CFGR2_DIVQ_128 (0x7FU << RCC_PLL4CFGR2_DIVQ_Pos) /*!< 0x00007F00 */
#define RCC_PLL4CFGR2_DIVR_Pos (16U)
#define RCC_PLL4CFGR2_DIVR_Msk (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */
#define RCC_PLL4CFGR2_DIVR RCC_PLL4CFGR2_DIVR_Msk /*PLL4 DIVR division factor*/
#define RCC_PLL4CFGR2_DIVR_0 (0x00U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00000000 */
#define RCC_PLL4CFGR2_DIVR_1 (0x01U << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x00010000 */
#define RCC_PLL4CFGR2_DIVR_128 (0x7FU << RCC_PLL4CFGR2_DIVR_Pos) /*!< 0x007F0000 */
/******************** Bit definition for RCC_PLL4FRACR register********************/
#define RCC_PLL4FRACR_FRACV_Pos (3U)
#define RCC_PLL4FRACR_FRACV_Msk (0x1FFFU << RCC_PLL4FRACR_FRACV_Pos) /*!< 0x0000FFF8 */
#define RCC_PLL4FRACR_FRACV RCC_PLL4FRACR_FRACV_Msk /*Fractional part of the multiplication factor for PLL4 VCO*/
/* @note FRACV can be between 0 and (2^13)-1 : 0-8191 : 0-0x1FFF */
#define RCC_PLL4FRACR_FRACLE_Pos (16U)
#define RCC_PLL4FRACR_FRACLE_Msk (0x1U << RCC_PLL4FRACR_FRACLE_Pos) /*!< 0x00010000 */
#define RCC_PLL4FRACR_FRACLE RCC_PLL4FRACR_FRACLE_Msk /*PLL4 fractional latch enable*/
/******************** Bit definition for RCC_PLL4CSGR register********************/
#define RCC_PLL4CSGR_MOD_PER_Pos (0U)
#define RCC_PLL4CSGR_MOD_PER_Msk (0x1FFFU << RCC_PLL4CSGR_MOD_PER_Pos) /*!< 0x00001FFF */
#define RCC_PLL4CSGR_MOD_PER RCC_PLL4CSGR_MOD_PER_Msk /*Modulation Period Adjustment for PLL4*/
#define RCC_PLL4CSGR_TPDFN_DIS_Pos (13U)
#define RCC_PLL4CSGR_TPDFN_DIS_Msk (0x1U << RCC_PLL4CSGR_TPDFN_DIS_Pos) /*!< 0x00002000 */
#define RCC_PLL4CSGR_TPDFN_DIS RCC_PLL4CSGR_TPDFN_DIS_Msk /*Dithering TPDF noise control*/
#define RCC_PLL4CSGR_RPDFN_DIS_Pos (14U)
#define RCC_PLL4CSGR_RPDFN_DIS_Msk (0x1U << RCC_PLL4CSGR_RPDFN_DIS_Pos) /*!< 0x00004000 */
#define RCC_PLL4CSGR_RPDFN_DIS RCC_PLL4CSGR_RPDFN_DIS_Msk /*Dithering RPDF noise control*/
#define RCC_PLL4CSGR_SSCG_MODE_Pos (15U)
#define RCC_PLL4CSGR_SSCG_MODE_Msk (0x1U << RCC_PLL4CSGR_SSCG_MODE_Pos) /*!< 0x00008000 */
#define RCC_PLL4CSGR_SSCG_MODE RCC_PLL4CSGR_SSCG_MODE_Msk /*Spread spectrum clock generator mode*/
#define RCC_PLL4CSGR_INC_STEP_Pos (16U)
#define RCC_PLL4CSGR_INC_STEP_Msk (0x7FFFU << RCC_PLL4CSGR_INC_STEP_Pos) /*!< 0x7FFF0000 */
#define RCC_PLL4CSGR_INC_STEP RCC_PLL4CSGR_INC_STEP_Msk /*Modulation Depth Adjustment for PLL4*/
/******************** Bit definition for RCC_I2C12CKSELR register********************/
#define RCC_I2C12CKSELR_I2C12SRC_Pos (0U)
#define RCC_I2C12CKSELR_I2C12SRC_Msk (0x7U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000007 */
#define RCC_I2C12CKSELR_I2C12SRC RCC_I2C12CKSELR_I2C12SRC_Msk /*I2C1 and I2C2 kernel clock source selection*/
#define RCC_I2C12CKSELR_I2C12SRC_0 (0x0U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000000 */
#define RCC_I2C12CKSELR_I2C12SRC_1 (0x1U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000001 */
#define RCC_I2C12CKSELR_I2C12SRC_2 (0x2U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000002 */
#define RCC_I2C12CKSELR_I2C12SRC_3 (0x3U << RCC_I2C12CKSELR_I2C12SRC_Pos) /*!< 0x00000003 */
/******************** Bit definition for RCC_I2C35CKSELR register********************/
#define RCC_I2C35CKSELR_I2C35SRC_Pos (0U)
#define RCC_I2C35CKSELR_I2C35SRC_Msk (0x7U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000007 */
#define RCC_I2C35CKSELR_I2C35SRC RCC_I2C35CKSELR_I2C35SRC_Msk /*I2C3 and I2C5 kernel clock source selection*/
#define RCC_I2C35CKSELR_I2C35SRC_0 (0x0U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000000 */
#define RCC_I2C35CKSELR_I2C35SRC_1 (0x1U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000001 */
#define RCC_I2C35CKSELR_I2C35SRC_2 (0x2U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000002 */
#define RCC_I2C35CKSELR_I2C35SRC_3 (0x3U << RCC_I2C35CKSELR_I2C35SRC_Pos) /*!< 0x00000003 */
/******************** Bit definition for RCC_I2C46CKSELR register********************/
#define RCC_I2C46CKSELR_I2C46SRC_Pos (0U)
#define RCC_I2C46CKSELR_I2C46SRC_Msk (0x7U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000007 */
#define RCC_I2C46CKSELR_I2C46SRC RCC_I2C46CKSELR_I2C46SRC_Msk /*I2C4 kernel clock source selection*/
#define RCC_I2C46CKSELR_I2C46SRC_0 (0x0U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000000 */
#define RCC_I2C46CKSELR_I2C46SRC_1 (0x1U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000001 */
#define RCC_I2C46CKSELR_I2C46SRC_2 (0x2U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000002 */
#define RCC_I2C46CKSELR_I2C46SRC_3 (0x3U << RCC_I2C46CKSELR_I2C46SRC_Pos) /*!< 0x00000003 */
/******************** Bit definition for RCC_SAI1CKSELR register********************/
#define RCC_SAI1CKSELR_SAI1SRC_Pos (0U)
#define RCC_SAI1CKSELR_SAI1SRC_Msk (0x7U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000007 */
#define RCC_SAI1CKSELR_SAI1SRC RCC_SAI1CKSELR_SAI1SRC_Msk /*SAI1 kernel clock source selection*/
#define RCC_SAI1CKSELR_SAI1SRC_0 (0x0U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000000 */
#define RCC_SAI1CKSELR_SAI1SRC_1 (0x1U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000001 */
#define RCC_SAI1CKSELR_SAI1SRC_2 (0x2U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000002 */
#define RCC_SAI1CKSELR_SAI1SRC_3 (0x3U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000003 */
#define RCC_SAI1CKSELR_SAI1SRC_4 (0x4U << RCC_SAI1CKSELR_SAI1SRC_Pos) /*!< 0x00000004 */
/******************** Bit definition for RCC_SAI2CKSELR register********************/
#define RCC_SAI2CKSELR_SAI2SRC_Pos (0U)
#define RCC_SAI2CKSELR_SAI2SRC_Msk (0x7U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000007 */
#define RCC_SAI2CKSELR_SAI2SRC RCC_SAI2CKSELR_SAI2SRC_Msk /*SAI2 kernel clock source selection*/
#define RCC_SAI2CKSELR_SAI2SRC_0 (0x0U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000000 */
#define RCC_SAI2CKSELR_SAI2SRC_1 (0x1U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000001 */
#define RCC_SAI2CKSELR_SAI2SRC_2 (0x2U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000002 */
#define RCC_SAI2CKSELR_SAI2SRC_3 (0x3U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000003 */
#define RCC_SAI2CKSELR_SAI2SRC_4 (0x4U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000004 */
#define RCC_SAI2CKSELR_SAI2SRC_5 (0x5U << RCC_SAI2CKSELR_SAI2SRC_Pos) /*!< 0x00000005 */
/******************** Bit definition for RCC_SAI3CKSELR register********************/
#define RCC_SAI3CKSELR_SAI3SRC_Pos (0U)
#define RCC_SAI3CKSELR_SAI3SRC_Msk (0x7U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000007 */
#define RCC_SAI3CKSELR_SAI3SRC RCC_SAI3CKSELR_SAI3SRC_Msk /*SAI3 kernel clock source selection*/
#define RCC_SAI3CKSELR_SAI3SRC_0 (0x0U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000000 */
#define RCC_SAI3CKSELR_SAI3SRC_1 (0x1U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000001 */
#define RCC_SAI3CKSELR_SAI3SRC_2 (0x2U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000002 */
#define RCC_SAI3CKSELR_SAI3SRC_3 (0x3U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000003 */
#define RCC_SAI3CKSELR_SAI3SRC_4 (0x4U << RCC_SAI3CKSELR_SAI3SRC_Pos) /*!< 0x00000004 */
/******************** Bit definition for RCC_SAI4CKSELR register********************/
#define RCC_SAI4CKSELR_SAI4SRC_Pos (0U)
#define RCC_SAI4CKSELR_SAI4SRC_Msk (0x7U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000007 */
#define RCC_SAI4CKSELR_SAI4SRC RCC_SAI4CKSELR_SAI4SRC_Msk /*SAI4 kernel clock source selection*/
#define RCC_SAI4CKSELR_SAI4SRC_0 (0x0U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000000 */
#define RCC_SAI4CKSELR_SAI4SRC_1 (0x1U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000001 */
#define RCC_SAI4CKSELR_SAI4SRC_2 (0x2U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000002 */
#define RCC_SAI4CKSELR_SAI4SRC_3 (0x3U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000003 */
#define RCC_SAI4CKSELR_SAI4SRC_4 (0x4U << RCC_SAI4CKSELR_SAI4SRC_Pos) /*!< 0x00000004 */
/******************** Bit definition for RCC_SPI2S1CKSELR register********************/
#define RCC_SPI2S1CKSELR_SPI1SRC_Pos (0U)
#define RCC_SPI2S1CKSELR_SPI1SRC_Msk (0x7U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000007 */
#define RCC_SPI2S1CKSELR_SPI1SRC RCC_SPI2S1CKSELR_SPI1SRC_Msk /*SPI/I2S1 kernel clock source selection*/
#define RCC_SPI2S1CKSELR_SPI1SRC_0 (0x0U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000000 */
#define RCC_SPI2S1CKSELR_SPI1SRC_1 (0x1U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000001 */
#define RCC_SPI2S1CKSELR_SPI1SRC_2 (0x2U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000002 */
#define RCC_SPI2S1CKSELR_SPI1SRC_3 (0x3U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000003 */
#define RCC_SPI2S1CKSELR_SPI1SRC_4 (0x4U << RCC_SPI2S1CKSELR_SPI1SRC_Pos) /*!< 0x00000004 */
/******************** Bit definition for RCC_SPI2S23CKSELR register********************/
#define RCC_SPI2S23CKSELR_SPI23SRC_Pos (0U)
#define RCC_SPI2S23CKSELR_SPI23SRC_Msk (0x7U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000007 */
#define RCC_SPI2S23CKSELR_SPI23SRC RCC_SPI2S23CKSELR_SPI23SRC_Msk /*SPI/I2S2,3 kernel clock source selection*/
#define RCC_SPI2S23CKSELR_SPI23SRC_0 (0x0U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000000 */
#define RCC_SPI2S23CKSELR_SPI23SRC_1 (0x1U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000001 */
#define RCC_SPI2S23CKSELR_SPI23SRC_2 (0x2U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000002 */
#define RCC_SPI2S23CKSELR_SPI23SRC_3 (0x3U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000003 */
#define RCC_SPI2S23CKSELR_SPI23SRC_4 (0x4U << RCC_SPI2S23CKSELR_SPI23SRC_Pos) /*!< 0x00000004 */
/******************** Bit definition for RCC_SPI45CKSELR register********************/
#define RCC_SPI45CKSELR_SPI45SRC_Pos (0U)
#define RCC_SPI45CKSELR_SPI45SRC_Msk (0x7U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000007 */
#define RCC_SPI45CKSELR_SPI45SRC RCC_SPI45CKSELR_SPI45SRC_Msk /*SPI4,5 kernel clock source selection*/
#define RCC_SPI45CKSELR_SPI45SRC_0 (0x0U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000000 */
#define RCC_SPI45CKSELR_SPI45SRC_1 (0x1U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000001 */
#define RCC_SPI45CKSELR_SPI45SRC_2 (0x2U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000002 */
#define RCC_SPI45CKSELR_SPI45SRC_3 (0x3U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000003 */
#define RCC_SPI45CKSELR_SPI45SRC_4 (0x4U << RCC_SPI45CKSELR_SPI45SRC_Pos) /*!< 0x00000004 */
/******************** Bit definition for RCC_SPI6CKSELR register********************/
#define RCC_SPI6CKSELR_SPI6SRC_Pos (0U)
#define RCC_SPI6CKSELR_SPI6SRC_Msk (0x7U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000007 */
#define RCC_SPI6CKSELR_SPI6SRC RCC_SPI6CKSELR_SPI6SRC_Msk /*SPI6 kernel clock source selection*/
#define RCC_SPI6CKSELR_SPI6SRC_0 (0x0U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000000 */
#define RCC_SPI6CKSELR_SPI6SRC_1 (0x1U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000001 */
#define RCC_SPI6CKSELR_SPI6SRC_2 (0x2U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000002 */
#define RCC_SPI6CKSELR_SPI6SRC_3 (0x3U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000003 */
#define RCC_SPI6CKSELR_SPI6SRC_4 (0x4U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000004 */
#define RCC_SPI6CKSELR_SPI6SRC_5 (0x5U << RCC_SPI6CKSELR_SPI6SRC_Pos) /*!< 0x00000005 */
/******************** Bit definition for RCC_UART6CKSELR register********************/
#define RCC_UART6CKSELR_UART6SRC_Pos (0U)
#define RCC_UART6CKSELR_UART6SRC_Msk (0x7U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000007 */
#define RCC_UART6CKSELR_UART6SRC RCC_UART6CKSELR_UART6SRC_Msk /*UART6 kernel clock source selection*/
#define RCC_UART6CKSELR_UART6SRC_0 (0x0U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000000 */
#define RCC_UART6CKSELR_UART6SRC_1 (0x1U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000001 */
#define RCC_UART6CKSELR_UART6SRC_2 (0x2U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000002 */
#define RCC_UART6CKSELR_UART6SRC_3 (0x3U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000003 */
#define RCC_UART6CKSELR_UART6SRC_4 (0x4U << RCC_UART6CKSELR_UART6SRC_Pos) /*!< 0x00000004 */
/******************** Bit definition for RCC_UART24CKSELR register********************/
#define RCC_UART24CKSELR_UART24SRC_Pos (0U)
#define RCC_UART24CKSELR_UART24SRC_Msk (0x7U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000007 */
#define RCC_UART24CKSELR_UART24SRC RCC_UART24CKSELR_UART24SRC_Msk /*UART2,4 kernel clock source selection*/
#define RCC_UART24CKSELR_UART24SRC_0 (0x0U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000000 */
#define RCC_UART24CKSELR_UART24SRC_1 (0x1U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000001 */
#define RCC_UART24CKSELR_UART24SRC_2 (0x2U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000002 */
#define RCC_UART24CKSELR_UART24SRC_3 (0x3U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000003 */
#define RCC_UART24CKSELR_UART24SRC_4 (0x4U << RCC_UART24CKSELR_UART24SRC_Pos) /*!< 0x00000004 */
/******************** Bit definition for RCC_UART35CKSELR register********************/
#define RCC_UART35CKSELR_UART35SRC_Pos (0U)
#define RCC_UART35CKSELR_UART35SRC_Msk (0x7U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000007 */
#define RCC_UART35CKSELR_UART35SRC RCC_UART35CKSELR_UART35SRC_Msk /*UART3,5 kernel clock source selection*/
#define RCC_UART35CKSELR_UART35SRC_0 (0x0U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000000 */
#define RCC_UART35CKSELR_UART35SRC_1 (0x1U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000001 */
#define RCC_UART35CKSELR_UART35SRC_2 (0x2U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000002 */
#define RCC_UART35CKSELR_UART35SRC_3 (0x3U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000003 */
#define RCC_UART35CKSELR_UART35SRC_4 (0x4U << RCC_UART35CKSELR_UART35SRC_Pos) /*!< 0x00000004 */
/******************** Bit definition for RCC_UART78CKSELR register********************/
#define RCC_UART78CKSELR_UART78SRC_Pos (0U)
#define RCC_UART78CKSELR_UART78SRC_Msk (0x7U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000007 */
#define RCC_UART78CKSELR_UART78SRC RCC_UART78CKSELR_UART78SRC_Msk /*UART7,8 kernel clock source selection*/
#define RCC_UART78CKSELR_UART78SRC_0 (0x0U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000000 */
#define RCC_UART78CKSELR_UART78SRC_1 (0x1U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000001 */
#define RCC_UART78CKSELR_UART78SRC_2 (0x2U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000002 */
#define RCC_UART78CKSELR_UART78SRC_3 (0x3U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000003 */
#define RCC_UART78CKSELR_UART78SRC_4 (0x4U << RCC_UART78CKSELR_UART78SRC_Pos) /*!< 0x00000004 */
/******************** Bit definition for RCC_UART1CKSELR register********************/
#define RCC_UART1CKSELR_UART1SRC_Pos (0U)
#define RCC_UART1CKSELR_UART1SRC_Msk (0x7U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000007 */
#define RCC_UART1CKSELR_UART1SRC RCC_UART1CKSELR_UART1SRC_Msk /*UART1 kernel clock source selection*/
#define RCC_UART1CKSELR_UART1SRC_0 (0x0U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000000 */
#define RCC_UART1CKSELR_UART1SRC_1 (0x1U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000001 */
#define RCC_UART1CKSELR_UART1SRC_2 (0x2U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000002 */
#define RCC_UART1CKSELR_UART1SRC_3 (0x3U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000003 */
#define RCC_UART1CKSELR_UART1SRC_4 (0x4U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000004 */
#define RCC_UART1CKSELR_UART1SRC_5 (0x5U << RCC_UART1CKSELR_UART1SRC_Pos) /*!< 0x00000005 */
/******************** Bit definition for RCC_SDMMC12CKSELR register********************/
#define RCC_SDMMC12CKSELR_SDMMC12SRC_Pos (0U)
#define RCC_SDMMC12CKSELR_SDMMC12SRC_Msk (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */
#define RCC_SDMMC12CKSELR_SDMMC12SRC RCC_SDMMC12CKSELR_SDMMC12SRC_Msk /*SDMMC1 and SDMMC2 kernel clock source selection*/
#define RCC_SDMMC12CKSELR_SDMMC12SRC_0 (0x0U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000000 */
#define RCC_SDMMC12CKSELR_SDMMC12SRC_1 (0x1U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000001 */
#define RCC_SDMMC12CKSELR_SDMMC12SRC_2 (0x2U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000002 */
#define RCC_SDMMC12CKSELR_SDMMC12SRC_3 (0x3U << RCC_SDMMC12CKSELR_SDMMC12SRC_Pos) /*!< 0x00000003 */
/******************** Bit definition for RCC_SDMMC3CKSELR register********************/
#define RCC_SDMMC3CKSELR_SDMMC3SRC_Pos (0U)
#define RCC_SDMMC3CKSELR_SDMMC3SRC_Msk (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */
#define RCC_SDMMC3CKSELR_SDMMC3SRC RCC_SDMMC3CKSELR_SDMMC3SRC_Msk /*SDMMC3 kernel clock source selection*/
#define RCC_SDMMC3CKSELR_SDMMC3SRC_0 (0x0U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000000 */
#define RCC_SDMMC3CKSELR_SDMMC3SRC_1 (0x1U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000001 */
#define RCC_SDMMC3CKSELR_SDMMC3SRC_2 (0x2U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000002 */
#define RCC_SDMMC3CKSELR_SDMMC3SRC_3 (0x3U << RCC_SDMMC3CKSELR_SDMMC3SRC_Pos) /*!< 0x00000003 */
/******************** Bit definition for RCC_ETHCKSELR register********************/
#define RCC_ETHCKSELR_ETHSRC_Pos (0U)
#define RCC_ETHCKSELR_ETHSRC_Msk (0x3U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000003 */
#define RCC_ETHCKSELR_ETHSRC RCC_ETHCKSELR_ETHSRC_Msk /*ETH kernel clock source selection*/
#define RCC_ETHCKSELR_ETHSRC_0 (0x0U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000000 */
#define RCC_ETHCKSELR_ETHSRC_1 (0x1U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000001 */
#define RCC_ETHCKSELR_ETHSRC_2 (0x2U << RCC_ETHCKSELR_ETHSRC_Pos) /*!< 0x00000002 */
#define RCC_ETHCKSELR_ETHPTPDIV_Pos (4U)
#define RCC_ETHCKSELR_ETHPTPDIV_Msk (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */
#define RCC_ETHCKSELR_ETHPTPDIV RCC_ETHCKSELR_ETHPTPDIV_Msk /*Clock divider for Ethernet Precision Time Protocol (PTP)*/
#define RCC_ETHCKSELR_ETHPTPDIV_0 (0x0U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000000 */
#define RCC_ETHCKSELR_ETHPTPDIV_1 (0x1U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000010 */
#define RCC_ETHCKSELR_ETHPTPDIV_2 (0x2U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000020 */
#define RCC_ETHCKSELR_ETHPTPDIV_3 (0x3U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000030 */
#define RCC_ETHCKSELR_ETHPTPDIV_4 (0x4U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000040 */
#define RCC_ETHCKSELR_ETHPTPDIV_5 (0x5U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000050 */
#define RCC_ETHCKSELR_ETHPTPDIV_6 (0x6U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000060 */
#define RCC_ETHCKSELR_ETHPTPDIV_7 (0x7U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000070 */
#define RCC_ETHCKSELR_ETHPTPDIV_8 (0x8U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000080 */
#define RCC_ETHCKSELR_ETHPTPDIV_9 (0x9U << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x00000090 */
#define RCC_ETHCKSELR_ETHPTPDIV_10 (0xAU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000A0 */
#define RCC_ETHCKSELR_ETHPTPDIV_11 (0xBU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000B0 */
#define RCC_ETHCKSELR_ETHPTPDIV_12 (0xCU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000C0 */
#define RCC_ETHCKSELR_ETHPTPDIV_13 (0xDU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000D0 */
#define RCC_ETHCKSELR_ETHPTPDIV_14 (0xEU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000E0 */
#define RCC_ETHCKSELR_ETHPTPDIV_15 (0xFU << RCC_ETHCKSELR_ETHPTPDIV_Pos) /*!< 0x000000F0 */
/******************** Bit definition for RCC_QSPICKSELR register********************/
#define RCC_QSPICKSELR_QSPISRC_Pos (0U)
#define RCC_QSPICKSELR_QSPISRC_Msk (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */
#define RCC_QSPICKSELR_QSPISRC RCC_QSPICKSELR_QSPISRC_Msk /*QUADSPI kernel clock source selection*/
#define RCC_QSPICKSELR_QSPISRC_0 (0x0U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000000 */
#define RCC_QSPICKSELR_QSPISRC_1 (0x1U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000001 */
#define RCC_QSPICKSELR_QSPISRC_2 (0x2U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000002 */
#define RCC_QSPICKSELR_QSPISRC_3 (0x3U << RCC_QSPICKSELR_QSPISRC_Pos) /*!< 0x00000003 */
/******************** Bit definition for RCC_FMCCKSELR register********************/
#define RCC_FMCCKSELR_FMCSRC_Pos (0U)
#define RCC_FMCCKSELR_FMCSRC_Msk (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */
#define RCC_FMCCKSELR_FMCSRC RCC_FMCCKSELR_FMCSRC_Msk /*FMC kernel clock source selection*/
#define RCC_FMCCKSELR_FMCSRC_0 (0x0U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000000 */
#define RCC_FMCCKSELR_FMCSRC_1 (0x1U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000001 */
#define RCC_FMCCKSELR_FMCSRC_2 (0x2U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000002 */
#define RCC_FMCCKSELR_FMCSRC_3 (0x3U << RCC_FMCCKSELR_FMCSRC_Pos) /*!< 0x00000003 */
/******************** Bit definition for RCC_FDCANCKSELR register********************/
#define RCC_FDCANCKSELR_FDCANSRC_Pos (0U)
#define RCC_FDCANCKSELR_FDCANSRC_Msk (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */
#define RCC_FDCANCKSELR_FDCANSRC RCC_FDCANCKSELR_FDCANSRC_Msk /*FDCAN kernel clock source selection*/
#define RCC_FDCANCKSELR_FDCANSRC_0 (0x0U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000000 */
#define RCC_FDCANCKSELR_FDCANSRC_1 (0x1U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000001 */
#define RCC_FDCANCKSELR_FDCANSRC_2 (0x2U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000002 */
#define RCC_FDCANCKSELR_FDCANSRC_3 (0x3U << RCC_FDCANCKSELR_FDCANSRC_Pos) /*!< 0x00000003 */
/******************** Bit definition for RCC_SPDIFCKSELR register********************/
#define RCC_SPDIFCKSELR_SPDIFSRC_Pos (0U)
#define RCC_SPDIFCKSELR_SPDIFSRC_Msk (0x3U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000003 */
#define RCC_SPDIFCKSELR_SPDIFSRC RCC_SPDIFCKSELR_SPDIFSRC_Msk /*SPDIF-RX kernel clock source selection*/
#define RCC_SPDIFCKSELR_SPDIFSRC_0 (0x0U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000000 */
#define RCC_SPDIFCKSELR_SPDIFSRC_1 (0x1U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000001 */
#define RCC_SPDIFCKSELR_SPDIFSRC_2 (0x2U << RCC_SPDIFCKSELR_SPDIFSRC_Pos) /*!< 0x00000002 */
/******************** Bit definition for RCC_CECCKSELR register********************/
#define RCC_CECCKSELR_CECSRC_Pos (0U)
#define RCC_CECCKSELR_CECSRC_Msk (0x3U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000003 */
#define RCC_CECCKSELR_CECSRC RCC_CECCKSELR_CECSRC_Msk /*CEC-HDMI kernel clock source selection*/
#define RCC_CECCKSELR_CECSRC_0 (0x0U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000000 */
#define RCC_CECCKSELR_CECSRC_1 (0x1U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000001 */
#define RCC_CECCKSELR_CECSRC_2 (0x2U << RCC_CECCKSELR_CECSRC_Pos) /*!< 0x00000002 */
/******************** Bit definition for RCC_USBCKSELR register********************/
#define RCC_USBCKSELR_USBPHYSRC_Pos (0U)
#define RCC_USBCKSELR_USBPHYSRC_Msk (0x3U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000003 */
#define RCC_USBCKSELR_USBPHYSRC RCC_USBCKSELR_USBPHYSRC_Msk /*USB PHY kernel clock source selection*/
#define RCC_USBCKSELR_USBPHYSRC_0 (0x0U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000000 */
#define RCC_USBCKSELR_USBPHYSRC_1 (0x1U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000001 */
#define RCC_USBCKSELR_USBPHYSRC_2 (0x2U << RCC_USBCKSELR_USBPHYSRC_Pos) /*!< 0x00000002 */
#define RCC_USBCKSELR_USBOSRC_Pos (4U)
#define RCC_USBCKSELR_USBOSRC_Msk (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */
#define RCC_USBCKSELR_USBOSRC RCC_USBCKSELR_USBOSRC_Msk /*USB OTG kernel clock source selection*/
#define RCC_USBCKSELR_USBOSRC_0 (0x0U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000000 */
#define RCC_USBCKSELR_USBOSRC_1 (0x1U << RCC_USBCKSELR_USBOSRC_Pos) /*!< 0x00000010 */
/******************** Bit definition for RCC_RNG1CKSELR register********************/
#define RCC_RNG1CKSELR_RNG1SRC_Pos (0U)
#define RCC_RNG1CKSELR_RNG1SRC_Msk (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */
#define RCC_RNG1CKSELR_RNG1SRC RCC_RNG1CKSELR_RNG1SRC_Msk /*RNG1 kernel clock source selection*/
#define RCC_RNG1CKSELR_RNG1SRC_0 (0x0U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000000 */
#define RCC_RNG1CKSELR_RNG1SRC_1 (0x1U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000001 */
#define RCC_RNG1CKSELR_RNG1SRC_2 (0x2U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000002 */
#define RCC_RNG1CKSELR_RNG1SRC_3 (0x3U << RCC_RNG1CKSELR_RNG1SRC_Pos) /*!< 0x00000003 */
/******************** Bit definition for RCC_RNG2CKSELR register********************/
#define RCC_RNG2CKSELR_RNG2SRC_Pos (0U)
#define RCC_RNG2CKSELR_RNG2SRC_Msk (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */
#define RCC_RNG2CKSELR_RNG2SRC RCC_RNG2CKSELR_RNG2SRC_Msk /*RNG2 kernel clock source selection*/
#define RCC_RNG2CKSELR_RNG2SRC_0 (0x0U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000000 */
#define RCC_RNG2CKSELR_RNG2SRC_1 (0x1U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000001 */
#define RCC_RNG2CKSELR_RNG2SRC_2 (0x2U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000002 */
#define RCC_RNG2CKSELR_RNG2SRC_3 (0x3U << RCC_RNG2CKSELR_RNG2SRC_Pos) /*!< 0x00000003 */
/******************** Bit definition for RCC_CPERCKSELR register********************/
#define RCC_CPERCKSELR_CKPERSRC_Pos (0U)
#define RCC_CPERCKSELR_CKPERSRC_Msk (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */
#define RCC_CPERCKSELR_CKPERSRC RCC_CPERCKSELR_CKPERSRC_Msk /*Oscillator selection for kernel clock*/
#define RCC_CPERCKSELR_CKPERSRC_0 (0x0U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000000 */
#define RCC_CPERCKSELR_CKPERSRC_1 (0x1U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000001 */
#define RCC_CPERCKSELR_CKPERSRC_2 (0x2U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000002 */
#define RCC_CPERCKSELR_CKPERSRC_3 (0x3U << RCC_CPERCKSELR_CKPERSRC_Pos) /*!< 0x00000003 */
/******************** Bit definition for RCC_CSTGENCKSELR register******************/
#define RCC_STGENCKSELR_STGENSRC_Pos (0U)
#define RCC_STGENCKSELR_STGENSRC_Msk (0x3U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000003 */
#define RCC_STGENCKSELR_STGENSRC RCC_STGENCKSELR_STGENSRC_Msk /*Oscillator selection for kernel clock*/
#define RCC_STGENCKSELR_STGENSRC_0 (0x0U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000000 */
#define RCC_STGENCKSELR_STGENSRC_1 (0x1U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000001 */
#define RCC_STGENCKSELR_STGENSRC_2 (0x2U << RCC_STGENCKSELR_STGENSRC_Pos) /*!< 0x00000002 */
/******************** Bit definition for RCC_DDRITFCR register*********************/
#define RCC_DDRITFCR_DDRC1EN B(0)
#define RCC_DDRITFCR_DDRC1LPEN B(1)
#define RCC_DDRITFCR_DDRC2EN B(2)
#define RCC_DDRITFCR_DDRC2LPEN B(3)
#define RCC_DDRITFCR_DDRPHYCEN B(4)
#define RCC_DDRITFCR_DDRPHYCLPEN B(5)
#define RCC_DDRITFCR_DDRCAPBEN B(6)
#define RCC_DDRITFCR_DDRCAPBLPEN B(7)
#define RCC_DDRITFCR_AXIDCGEN B(8)
#define RCC_DDRITFCR_DDRPHYCAPBEN B(9)
#define RCC_DDRITFCR_DDRPHYCAPBLPEN B(10)
#define RCC_DDRITFCR_KERDCG_DLY_Pos (10U)
#define RCC_DDRITFCR_KERDCG_DLY_Msk (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */
#define RCC_DDRITFCR_KERDCG_DLY RCC_DDRITFCR_KERDCG_DLY_Msk /*AXIDCG delay*/
#define RCC_DDRITFCR_KERDCG_DLY_0 (0x0U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000000 */
#define RCC_DDRITFCR_KERDCG_DLY_1 (0x1U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000400 */
#define RCC_DDRITFCR_KERDCG_DLY_2 (0x2U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000800 */
#define RCC_DDRITFCR_KERDCG_DLY_3 (0x3U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00000C00 */
#define RCC_DDRITFCR_KERDCG_DLY_4 (0x4U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001000 */
#define RCC_DDRITFCR_KERDCG_DLY_5 (0x5U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001400 */
#define RCC_DDRITFCR_KERDCG_DLY_6 (0x6U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001800 */
#define RCC_DDRITFCR_KERDCG_DLY_7 (0x7U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00001C00 */
#define RCC_DDRITFCR_KERDCG_DLY_8 (0x8U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002000 */
#define RCC_DDRITFCR_KERDCG_DLY_9 (0x9U << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002400 */
#define RCC_DDRITFCR_KERDCG_DLY_10 (0xAU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002800 */
#define RCC_DDRITFCR_KERDCG_DLY_11 (0xBU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00002C00 */
#define RCC_DDRITFCR_KERDCG_DLY_12 (0xCU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003000 */
#define RCC_DDRITFCR_KERDCG_DLY_13 (0xDU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003400 */
#define RCC_DDRITFCR_KERDCG_DLY_14 (0xEU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003800 */
#define RCC_DDRITFCR_KERDCG_DLY_15 (0xFU << RCC_DDRITFCR_KERDCG_DLY_Pos) /*!< 0x00003C00 */
#define RCC_DDRITFCR_DDRCAPBRST B(14)
#define RCC_DDRITFCR_DDRCAXIRST B(15)
#define RCC_DDRITFCR_DDRCORERST B(16)
#define RCC_DDRITFCR_DPHYAPBRST B(17)
#define RCC_DDRITFCR_DPHYRST B(18)
#define RCC_DDRITFCR_DPHYCTLRST B(19)
#define RCC_DDRITFCR_DDRCKMOD_Pos (20U)
#define RCC_DDRITFCR_DDRCKMOD_Msk (0x7U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00700000 */
#define RCC_DDRITFCR_DDRCKMOD RCC_DDRITFCR_DDRCKMOD_Msk /*RCC mode for DDR clock control*/
#define RCC_DDRITFCR_DDRCKMOD_0 (0x0U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00000000 */
#define RCC_DDRITFCR_DDRCKMOD_1 (0x1U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00100000 */
#define RCC_DDRITFCR_DDRCKMOD_2 (0x2U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00200000 */
#define RCC_DDRITFCR_DDRCKMOD_5 (0x5U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00500000 */
#define RCC_DDRITFCR_DDRCKMOD_6 (0x6U << RCC_DDRITFCR_DDRCKMOD_Pos) /*!< 0x00600000 */
/******************** Bit definition for RCC_DSICKSELR register********************/
#define RCC_DSICKSELR_DSISRC_Pos (0U)
#define RCC_DSICKSELR_DSISRC_Msk (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */
#define RCC_DSICKSELR_DSISRC RCC_DSICKSELR_DSISRC_Msk /*DSIHOST kernel clock source selection*/
#define RCC_DSICKSELR_DSISRC_0 (0x0U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000000 */
#define RCC_DSICKSELR_DSISRC_1 (0x1U << RCC_DSICKSELR_DSISRC_Pos) /*!< 0x00000001 */
/******************** Bit definition for RCC_ADCCKSELR register********************/
#define RCC_ADCCKSELR_ADCSRC_Pos (0U)
#define RCC_ADCCKSELR_ADCSRC_Msk (0x3U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000003 */
#define RCC_ADCCKSELR_ADCSRC RCC_ADCCKSELR_ADCSRC_Msk /*ADC1&2 kernel clock source selection*/
#define RCC_ADCCKSELR_ADCSRC_0 (0x0U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000000 */
#define RCC_ADCCKSELR_ADCSRC_1 (0x1U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000001 */
#define RCC_ADCCKSELR_ADCSRC_2 (0x2U << RCC_ADCCKSELR_ADCSRC_Pos) /*!< 0x00000002 */
/******************** Bit definition for RCC_LPTIM45CKSELR register********************/
#define RCC_LPTIM45CKSELR_LPTIM45SRC_Pos (0U)
#define RCC_LPTIM45CKSELR_LPTIM45SRC_Msk (0x7U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000007 */
#define RCC_LPTIM45CKSELR_LPTIM45SRC RCC_LPTIM45CKSELR_LPTIM45SRC_Msk /*LPTIM4 and LPTIM5 kernel clock source selection*/
#define RCC_LPTIM45CKSELR_LPTIM45SRC_0 (0x0U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000000 */
#define RCC_LPTIM45CKSELR_LPTIM45SRC_1 (0x1U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000001 */
#define RCC_LPTIM45CKSELR_LPTIM45SRC_2 (0x2U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000002 */
#define RCC_LPTIM45CKSELR_LPTIM45SRC_3 (0x3U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000003 */
#define RCC_LPTIM45CKSELR_LPTIM45SRC_4 (0x4U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000004 */
#define RCC_LPTIM45CKSELR_LPTIM45SRC_5 (0x5U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000005 */
#define RCC_LPTIM45CKSELR_LPTIM45SRC_6 (0x6U << RCC_LPTIM45CKSELR_LPTIM45SRC_Pos) /*!< 0x00000006 */
/******************** Bit definition for RCC_LPTIM23CKSELR register********************/
#define RCC_LPTIM23CKSELR_LPTIM23SRC_Pos (0U)
#define RCC_LPTIM23CKSELR_LPTIM23SRC_Msk (0x7U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000007 */
#define RCC_LPTIM23CKSELR_LPTIM23SRC RCC_LPTIM23CKSELR_LPTIM23SRC_Msk /*LPTIM2 and LPTIM3 kernel clock source selection*/
#define RCC_LPTIM23CKSELR_LPTIM23SRC_0 (0x0U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000000 */
#define RCC_LPTIM23CKSELR_LPTIM23SRC_1 (0x1U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000001 */
#define RCC_LPTIM23CKSELR_LPTIM23SRC_2 (0x2U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000002 */
#define RCC_LPTIM23CKSELR_LPTIM23SRC_3 (0x3U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000003 */
#define RCC_LPTIM23CKSELR_LPTIM23SRC_4 (0x4U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000004 */
#define RCC_LPTIM23CKSELR_LPTIM23SRC_5 (0x5U << RCC_LPTIM23CKSELR_LPTIM23SRC_Pos) /*!< 0x00000005 */
/******************** Bit definition for RCC_LPTIM1CKSELR register********************/
#define RCC_LPTIM1CKSELR_LPTIM1SRC_Pos (0U)
#define RCC_LPTIM1CKSELR_LPTIM1SRC_Msk (0x7U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000007 */
#define RCC_LPTIM1CKSELR_LPTIM1SRC RCC_LPTIM1CKSELR_LPTIM1SRC_Msk /*LPTIM1 kernel clock source selection*/
#define RCC_LPTIM1CKSELR_LPTIM1SRC_0 (0x0U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000000 */
#define RCC_LPTIM1CKSELR_LPTIM1SRC_1 (0x1U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000001 */
#define RCC_LPTIM1CKSELR_LPTIM1SRC_2 (0x2U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000002 */
#define RCC_LPTIM1CKSELR_LPTIM1SRC_3 (0x3U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000003 */
#define RCC_LPTIM1CKSELR_LPTIM1SRC_4 (0x4U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000004 */
#define RCC_LPTIM1CKSELR_LPTIM1SRC_5 (0x5U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000005 */
#define RCC_LPTIM1CKSELR_LPTIM1SRC_6 (0x6U << RCC_LPTIM1CKSELR_LPTIM1SRC_Pos) /*!< 0x00000006 */
/******************** Bit definition for RCC_MP_BOOTCR register*********************/
#define RCC_MP_BOOTCR_MCU_BEN_Pos (0U)
#define RCC_MP_BOOTCR_MCU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MCU_BEN_Pos) /*!< 0x00000001 */
#define RCC_MP_BOOTCR_MCU_BEN RCC_MP_BOOTCR_MCU_BEN_Msk /*MCU Boot Enable after STANDBY*/
#define RCC_MP_BOOTCR_MPU_BEN_Pos (1U)
#define RCC_MP_BOOTCR_MPU_BEN_Msk (0x1U << RCC_MP_BOOTCR_MPU_BEN_Pos) /*!< 0x00000002 */
#define RCC_MP_BOOTCR_MPU_BEN RCC_MP_BOOTCR_MPU_BEN_Msk /*MPU Boot Enable after STANDBY*/
/******************** Bit definition for RCC_MP_SREQSETR register********************/
/* @note The MCU cannot access to this register */
#define RCC_MP_SREQSETR_STPREQ_P0_Pos (0U)
#define RCC_MP_SREQSETR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P0_Pos) /*!< 0x00000001 */
#define RCC_MP_SREQSETR_STPREQ_P0 RCC_MP_SREQSETR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/
#define RCC_MP_SREQSETR_STPREQ_P1_Pos (1U)
#define RCC_MP_SREQSETR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQSETR_STPREQ_P1_Pos) /*!< 0x00000002 */
#define RCC_MP_SREQSETR_STPREQ_P1 RCC_MP_SREQSETR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/
/******************** Bit definition for RCC_MP_SREQCLRR register********************/
/* @note The MCU cannot access to this register */
#define RCC_MP_SREQCLRR_STPREQ_P0_Pos (0U)
#define RCC_MP_SREQCLRR_STPREQ_P0_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P0_Pos) /*!< 0x00000001 */
#define RCC_MP_SREQCLRR_STPREQ_P0 RCC_MP_SREQCLRR_STPREQ_P0_Msk /*Stop Request for MPU processor number 0*/
#define RCC_MP_SREQCLRR_STPREQ_P1_Pos (1U)
#define RCC_MP_SREQCLRR_STPREQ_P1_Msk (0x1U << RCC_MP_SREQCLRR_STPREQ_P1_Pos) /*!< 0x00000002 */
#define RCC_MP_SREQCLRR_STPREQ_P1 RCC_MP_SREQCLRR_STPREQ_P1_Msk /*Stop Request for MPU processor number 1*/
/******************** Bit definition for RCC_MP_GCR register********************/
#define RCC_MP_GCR_BOOT_MCU_Pos (0U)
#define RCC_MP_GCR_BOOT_MCU_Msk (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */
#define RCC_MP_GCR_BOOT_MCU RCC_MP_GCR_BOOT_MCU_Msk /*Allows the MCU to boot*/
#define RCC_MP_GCR_BOOT_MCU_0 (0x0U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000000 */
#define RCC_MP_GCR_BOOT_MCU_1 (0x1U << RCC_MP_GCR_BOOT_MCU_Pos) /*!< 0x00000001 */
/******************** Bit definition for RCC_MP_APRSTCR register ********************/
#define RCC_MP_APRSTCR_RDCTLEN_Pos (0U)
#define RCC_MP_APRSTCR_RDCTLEN_Msk (0x1U << RCC_MP_APRSTCR_RDCTLEN_Pos) /*!< 0x00000001 */
#define RCC_MP_APRSTCR_RDCTLEN RCC_MP_APRSTCR_RDCTLEN_Msk /*Reset Delay Control Enable*/
#define RCC_MP_APRSTCR_RSTTO_Pos (8U)
#define RCC_MP_APRSTCR_RSTTO_Msk (0x7FU << RCC_MP_APRSTCR_RSTTO_Pos) /*!< 0x00007F00 */
#define RCC_MP_APRSTCR_RSTTO RCC_MP_APRSTCR_RSTTO_Msk /*Reset Timeout Delay Adjust*/
/******************** Bit definition for RCC_MP_APRSTSR register ********************/
#define RCC_MP_APRSTSR_RSTTOV_Pos (8U)
#define RCC_MP_APRSTSR_RSTTOV_Msk (0x7FU << RCC_MP_APRSTSR_RSTTOV_Pos) /*!< 0x00007F00 */
#define RCC_MP_APRSTSR_RSTTOV RCC_MP_APRSTSR_RSTTOV_Msk /*Reset Timeout Delay Value*/
/******************* Bit definition for RCC_BDCR register ********************/
#define RCC_BDCR_LSEON_Pos (0U)
#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*LSE oscillator enabled*/
#define RCC_BDCR_LSEBYP_Pos (1U)
#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000002 */
#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*LSE oscillator bypass*/
#define RCC_BDCR_LSERDY_Pos (2U)
#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000004 */
#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*LSE oscillator ready*/
#define RCC_BDCR_DIGBYP_Pos (3U)
#define RCC_BDCR_DIGBYP_Msk (0x1U << RCC_BDCR_DIGBYP_Pos) /*!< 0x00000008 */
#define RCC_BDCR_DIGBYP RCC_BDCR_DIGBYP_Msk /*LSE digital bypass */
#define RCC_BDCR_LSEDRV_Pos (4U)
#define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */
#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*LSE oscillator driving capability*/
#define RCC_BDCR_LSEDRV_0 (0x0U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000000 */
#define RCC_BDCR_LSEDRV_1 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
#define RCC_BDCR_LSEDRV_2 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000020 */
#define RCC_BDCR_LSEDRV_3 (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000030 */
#define RCC_BDCR_LSECSSON_Pos (8U)
#define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000100 */
#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk /*LSE clock security system enable*/
#define RCC_BDCR_LSECSSD_Pos (9U)
#define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000200 */
#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk /*LSE clock security system failure detection*/
#define RCC_BDCR_RTCSRC_Pos (16U)
#define RCC_BDCR_RTCSRC_Msk (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */
#define RCC_BDCR_RTCSRC RCC_BDCR_RTCSRC_Msk /* RTC clock source selection*/
#define RCC_BDCR_RTCSRC_0 (0x0U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00000000 */
#define RCC_BDCR_RTCSRC_1 (0x1U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00010000 */
#define RCC_BDCR_RTCSRC_2 (0x2U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00020000 */
#define RCC_BDCR_RTCSRC_3 (0x3U << RCC_BDCR_RTCSRC_Pos) /*!< 0x00030000 */
#define RCC_BDCR_RTCCKEN_Pos (20U)
#define RCC_BDCR_RTCCKEN_Msk (0x1U << RCC_BDCR_RTCCKEN_Pos) /*!< 0x00100000 */
#define RCC_BDCR_RTCCKEN RCC_BDCR_RTCCKEN_Msk /*RTC clock enable*/
#define RCC_BDCR_VSWRST_Pos (31U)
#define RCC_BDCR_VSWRST_Msk (0x1U << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */
#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*V Switch domain software reset*/
/******************* Bit definition for RCC_RDLSICR register ********************/
#define RCC_RDLSICR_LSION_Pos (0U)
#define RCC_RDLSICR_LSION_Msk (0x1U << RCC_RDLSICR_LSION_Pos) /*!< 0x00000001 */
#define RCC_RDLSICR_LSION RCC_RDLSICR_LSION_Msk /*LSI oscillator enabled*/
#define RCC_RDLSICR_LSIRDY_Pos (1U)
#define RCC_RDLSICR_LSIRDY_Msk (0x1U << RCC_RDLSICR_LSIRDY_Pos) /*!< 0x00000002 */
#define RCC_RDLSICR_LSIRDY RCC_RDLSICR_LSIRDY_Msk /*LSI oscillator ready*/
#define RCC_RDLSICR_MRD_Pos (16U)
#define RCC_RDLSICR_MRD_Msk (0x1FU << RCC_RDLSICR_MRD_Pos) /*!< 0x001F0000 */
#define RCC_RDLSICR_MRD RCC_RDLSICR_MRD_Msk /*Minimum Reset Duration*/
#define RCC_RDLSICR_EADLY_Pos (24U)
#define RCC_RDLSICR_EADLY_Msk (0x7U << RCC_RDLSICR_EADLY_Pos) /*!< 0x07000000 */
#define RCC_RDLSICR_EADLY RCC_RDLSICR_EADLY_Msk /*External access delays*/
#define RCC_RDLSICR_SPARE_Pos (27U)
#define RCC_RDLSICR_SPARE_Msk (0x1FU << RCC_RDLSICR_SPARE_Pos) /*!< 0xF8000000 */
#define RCC_RDLSICR_SPARE RCC_RDLSICR_SPARE_Msk /*Spare bits*/
/******************* Bit definition for RCC_MP_CIER register *******************/
#define RCC_MP_CIER_LSIRDYIE_Pos (0U)
#define RCC_MP_CIER_LSIRDYIE_Msk (0x1U << RCC_MP_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
#define RCC_MP_CIER_LSIRDYIE RCC_MP_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/
#define RCC_MP_CIER_LSERDYIE_Pos (1U)
#define RCC_MP_CIER_LSERDYIE_Msk (0x1U << RCC_MP_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
#define RCC_MP_CIER_LSERDYIE RCC_MP_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/
#define RCC_MP_CIER_HSIRDYIE_Pos (2U)
#define RCC_MP_CIER_HSIRDYIE_Msk (0x1U << RCC_MP_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
#define RCC_MP_CIER_HSIRDYIE RCC_MP_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/
#define RCC_MP_CIER_HSERDYIE_Pos (3U)
#define RCC_MP_CIER_HSERDYIE_Msk (0x1U << RCC_MP_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
#define RCC_MP_CIER_HSERDYIE RCC_MP_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/
#define RCC_MP_CIER_CSIRDYIE_Pos (4U)
#define RCC_MP_CIER_CSIRDYIE_Msk (0x1U << RCC_MP_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */
#define RCC_MP_CIER_CSIRDYIE RCC_MP_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/
#define RCC_MP_CIER_PLL1DYIE_Pos (8U)
#define RCC_MP_CIER_PLL1DYIE_Msk (0x1U << RCC_MP_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */
#define RCC_MP_CIER_PLL1DYIE RCC_MP_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/
#define RCC_MP_CIER_PLL2DYIE_Pos (9U)
#define RCC_MP_CIER_PLL2DYIE_Msk (0x1U << RCC_MP_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */
#define RCC_MP_CIER_PLL2DYIE RCC_MP_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/
#define RCC_MP_CIER_PLL3DYIE_Pos (10U)
#define RCC_MP_CIER_PLL3DYIE_Msk (0x1U << RCC_MP_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */
#define RCC_MP_CIER_PLL3DYIE RCC_MP_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/
#define RCC_MP_CIER_PLL4DYIE_Pos (11U)
#define RCC_MP_CIER_PLL4DYIE_Msk (0x1U << RCC_MP_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */
#define RCC_MP_CIER_PLL4DYIE RCC_MP_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/
#define RCC_MP_CIER_LSECSSIE_Pos (16U)
#define RCC_MP_CIER_LSECSSIE_Msk (0x1U << RCC_MP_CIER_LSECSSIE_Pos) /*!< 0x00010000 */
#define RCC_MP_CIER_LSECSSIE RCC_MP_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/
#define RCC_MP_CIER_WKUPIE_Pos (20U)
#define RCC_MP_CIER_WKUPIE_Msk (0x1U << RCC_MP_CIER_WKUPIE_Pos) /*!< 0x00100000 */
#define RCC_MP_CIER_WKUPIE RCC_MP_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/
/******************* Bit definition for RCC_MP_CIFR register ********************/
#define RCC_MP_CIFR_LSIRDYF_Pos (0U)
#define RCC_MP_CIFR_LSIRDYF_Msk (0x1U << RCC_MP_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
#define RCC_MP_CIFR_LSIRDYF RCC_MP_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/
#define RCC_MP_CIFR_LSERDYF_Pos (1U)
#define RCC_MP_CIFR_LSERDYF_Msk (0x1U << RCC_MP_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
#define RCC_MP_CIFR_LSERDYF RCC_MP_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/
#define RCC_MP_CIFR_HSIRDYF_Pos (2U)
#define RCC_MP_CIFR_HSIRDYF_Msk (0x1U << RCC_MP_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
#define RCC_MP_CIFR_HSIRDYF RCC_MP_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/
#define RCC_MP_CIFR_HSERDYF_Pos (3U)
#define RCC_MP_CIFR_HSERDYF_Msk (0x1U << RCC_MP_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
#define RCC_MP_CIFR_HSERDYF RCC_MP_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/
#define RCC_MP_CIFR_CSIRDYF_Pos (4U)
#define RCC_MP_CIFR_CSIRDYF_Msk (0x1U << RCC_MP_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */
#define RCC_MP_CIFR_CSIRDYF RCC_MP_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/
#define RCC_MP_CIFR_PLL1DYF_Pos (8U)
#define RCC_MP_CIFR_PLL1DYF_Msk (0x1U << RCC_MP_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */
#define RCC_MP_CIFR_PLL1DYF RCC_MP_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/
#define RCC_MP_CIFR_PLL2DYF_Pos (9U)
#define RCC_MP_CIFR_PLL2DYF_Msk (0x1U << RCC_MP_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */
#define RCC_MP_CIFR_PLL2DYF RCC_MP_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/
#define RCC_MP_CIFR_PLL3DYF_Pos (10U)
#define RCC_MP_CIFR_PLL3DYF_Msk (0x1U << RCC_MP_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */
#define RCC_MP_CIFR_PLL3DYF RCC_MP_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/
#define RCC_MP_CIFR_PLL4DYF_Pos (11U)
#define RCC_MP_CIFR_PLL4DYF_Msk (0x1U << RCC_MP_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */
#define RCC_MP_CIFR_PLL4DYF RCC_MP_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/
#define RCC_MP_CIFR_LSECSSF_Pos (16U)
#define RCC_MP_CIFR_LSECSSF_Msk (0x1U << RCC_MP_CIFR_LSECSSF_Pos) /*!< 0x00010000 */
#define RCC_MP_CIFR_LSECSSF RCC_MP_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/
#define RCC_MP_CIFR_WKUPF_Pos (20U)
#define RCC_MP_CIFR_WKUPF_Msk (0x1U << RCC_MP_CIFR_WKUPF_Pos) /*!< 0x00100000 */
#define RCC_MP_CIFR_WKUPF RCC_MP_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/
/******************* Bit definition for RCC_MC_CIER register *******************/
#define RCC_MC_CIER_LSIRDYIE_Pos (0U)
#define RCC_MC_CIER_LSIRDYIE_Msk (0x1U << RCC_MC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
#define RCC_MC_CIER_LSIRDYIE RCC_MC_CIER_LSIRDYIE_Msk /*LSI ready Interrupt Enable*/
#define RCC_MC_CIER_LSERDYIE_Pos (1U)
#define RCC_MC_CIER_LSERDYIE_Msk (0x1U << RCC_MC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
#define RCC_MC_CIER_LSERDYIE RCC_MC_CIER_LSERDYIE_Msk /*LSE ready Interrupt Enable*/
#define RCC_MC_CIER_HSIRDYIE_Pos (2U)
#define RCC_MC_CIER_HSIRDYIE_Msk (0x1U << RCC_MC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
#define RCC_MC_CIER_HSIRDYIE RCC_MC_CIER_HSIRDYIE_Msk /*HSI ready Interrupt Enable*/
#define RCC_MC_CIER_HSERDYIE_Pos (3U)
#define RCC_MC_CIER_HSERDYIE_Msk (0x1U << RCC_MC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
#define RCC_MC_CIER_HSERDYIE RCC_MC_CIER_HSERDYIE_Msk /*HSE ready Interrupt Enable*/
#define RCC_MC_CIER_CSIRDYIE_Pos (4U)
#define RCC_MC_CIER_CSIRDYIE_Msk (0x1U << RCC_MC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */
#define RCC_MC_CIER_CSIRDYIE RCC_MC_CIER_CSIRDYIE_Msk /*CSI ready Interrupt Enable*/
#define RCC_MC_CIER_PLL1DYIE_Pos (8U)
#define RCC_MC_CIER_PLL1DYIE_Msk (0x1U << RCC_MC_CIER_PLL1DYIE_Pos) /*!< 0x00000100 */
#define RCC_MC_CIER_PLL1DYIE RCC_MC_CIER_PLL1DYIE_Msk /*PLL1DYIE ready Interrupt Enable*/
#define RCC_MC_CIER_PLL2DYIE_Pos (9U)
#define RCC_MC_CIER_PLL2DYIE_Msk (0x1U << RCC_MC_CIER_PLL2DYIE_Pos) /*!< 0x00000200 */
#define RCC_MC_CIER_PLL2DYIE RCC_MC_CIER_PLL2DYIE_Msk /*PLL2DYIE ready Interrupt Enable*/
#define RCC_MC_CIER_PLL3DYIE_Pos (10U)
#define RCC_MC_CIER_PLL3DYIE_Msk (0x1U << RCC_MC_CIER_PLL3DYIE_Pos) /*!< 0x00000400 */
#define RCC_MC_CIER_PLL3DYIE RCC_MC_CIER_PLL3DYIE_Msk /*PLL3DYIE ready Interrupt Enable*/
#define RCC_MC_CIER_PLL4DYIE_Pos (11U)
#define RCC_MC_CIER_PLL4DYIE_Msk (0x1U << RCC_MC_CIER_PLL4DYIE_Pos) /*!< 0x00000800 */
#define RCC_MC_CIER_PLL4DYIE RCC_MC_CIER_PLL4DYIE_Msk /*PLL4DYIE ready Interrupt Enable*/
#define RCC_MC_CIER_LSECSSIE_Pos (16U)
#define RCC_MC_CIER_LSECSSIE_Msk (0x1U << RCC_MC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */
#define RCC_MC_CIER_LSECSSIE RCC_MC_CIER_LSECSSIE_Msk /*LSE clock security system Interrupt Enable*/
#define RCC_MC_CIER_WKUPIE_Pos (20U)
#define RCC_MC_CIER_WKUPIE_Msk (0x1U << RCC_MC_CIER_WKUPIE_Pos) /*!< 0x00100000 */
#define RCC_MC_CIER_WKUPIE RCC_MC_CIER_WKUPIE_Msk /*Wake-up from CSTOP Interrupt Enable*/
/******************* Bit definition for RCC_MC_CIFR register ********************/
#define RCC_MC_CIFR_LSIRDYF_Pos (0U)
#define RCC_MC_CIFR_LSIRDYF_Msk (0x1U << RCC_MC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
#define RCC_MC_CIFR_LSIRDYF RCC_MC_CIFR_LSIRDYF_Msk /*LSI ready Interrupt Flag*/
#define RCC_MC_CIFR_LSERDYF_Pos (1U)
#define RCC_MC_CIFR_LSERDYF_Msk (0x1U << RCC_MC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
#define RCC_MC_CIFR_LSERDYF RCC_MC_CIFR_LSERDYF_Msk /*LSE ready Interrupt Flag*/
#define RCC_MC_CIFR_HSIRDYF_Pos (2U)
#define RCC_MC_CIFR_HSIRDYF_Msk (0x1U << RCC_MC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
#define RCC_MC_CIFR_HSIRDYF RCC_MC_CIFR_HSIRDYF_Msk /*HSI ready Interrupt Flag*/
#define RCC_MC_CIFR_HSERDYF_Pos (3U)
#define RCC_MC_CIFR_HSERDYF_Msk (0x1U << RCC_MC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
#define RCC_MC_CIFR_HSERDYF RCC_MC_CIFR_HSERDYF_Msk /*HSE ready Interrupt Flag*/
#define RCC_MC_CIFR_CSIRDYF_Pos (4U)
#define RCC_MC_CIFR_CSIRDYF_Msk (0x1U << RCC_MC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */
#define RCC_MC_CIFR_CSIRDYF RCC_MC_CIFR_CSIRDYF_Msk /*CSI ready Interrupt Flag*/
#define RCC_MC_CIFR_PLL1DYF_Pos (8U)
#define RCC_MC_CIFR_PLL1DYF_Msk (0x1U << RCC_MC_CIFR_PLL1DYF_Pos) /*!< 0x00000100 */
#define RCC_MC_CIFR_PLL1DYF RCC_MC_CIFR_PLL1DYF_Msk /*PLL1 ready Interrupt Flag*/
#define RCC_MC_CIFR_PLL2DYF_Pos (9U)
#define RCC_MC_CIFR_PLL2DYF_Msk (0x1U << RCC_MC_CIFR_PLL2DYF_Pos) /*!< 0x00000200 */
#define RCC_MC_CIFR_PLL2DYF RCC_MC_CIFR_PLL2DYF_Msk /*PLL2 ready Interrupt Flag*/
#define RCC_MC_CIFR_PLL3DYF_Pos (10U)
#define RCC_MC_CIFR_PLL3DYF_Msk (0x1U << RCC_MC_CIFR_PLL3DYF_Pos) /*!< 0x00000400 */
#define RCC_MC_CIFR_PLL3DYF RCC_MC_CIFR_PLL3DYF_Msk /*PLL3 ready Interrupt Flag*/
#define RCC_MC_CIFR_PLL4DYF_Pos (11U)
#define RCC_MC_CIFR_PLL4DYF_Msk (0x1U << RCC_MC_CIFR_PLL4DYF_Pos) /*!< 0x00000800 */
#define RCC_MC_CIFR_PLL4DYF RCC_MC_CIFR_PLL4DYF_Msk /*PLL4 ready Interrupt Flag*/
#define RCC_MC_CIFR_LSECSSF_Pos (16U)
#define RCC_MC_CIFR_LSECSSF_Msk (0x1U << RCC_MC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */
#define RCC_MC_CIFR_LSECSSF RCC_MC_CIFR_LSECSSF_Msk /*LSE clock security system Interrupt Flag*/
#define RCC_MC_CIFR_WKUPF_Pos (20U)
#define RCC_MC_CIFR_WKUPF_Msk (0x1U << RCC_MC_CIFR_WKUPF_Pos) /*!< 0x00100000 */
#define RCC_MC_CIFR_WKUPF RCC_MC_CIFR_WKUPF_Msk /*Wake-up from CSTOP Interrupt Flag*/
/******************* Bit definition for RCC_PWRLPDLYCR register ********************/
#define RCC_PWRLPDLYCR_PWRLP_DLY_Pos (0U)
#define RCC_PWRLPDLYCR_PWRLP_DLY_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x003FFFFF */
#define RCC_PWRLPDLYCR_PWRLP_DLY RCC_PWRLPDLYCR_PWRLP_DLY_Msk /*PWR_LP Delay value*/
#define RCC_PWRLPDLYCR_PWRLP_DLY_0 (0x000000U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000000 */
#define RCC_PWRLPDLYCR_PWRLP_DLY_1 (0x000001U << RCC_PWRLPDLYCR_PWRLP_DLY_Pos) /*!< 0x00000001 */
#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos (0U)
#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk (0x3FFFFFU << RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Pos) /*!< 0x003FFFFF */
#define RCC_PWRLPDLYCR_PWRLP_DLY_LAST RCC_PWRLPDLYCR_PWRLP_DLY_LAST_Msk /*A PWR_LP delay of about 65.5 milliseconds is observed*/
#define RCC_PWRLPDLYCR_MCTMPSKP B(24) /*Skip the PWR_LP Delay for MCU*/
/******************* Bit definition for RCC_MP_RSTSSETR register *********************/
/*!< This register is dedicated to the BOOTROM code in order to update the reset source.
* This register is updated by the BOOTROM code, after a power-on reset (por_rst), a
* system reset (nreset), or an exit from Standby or CStandby.
*@note The application software shall not use this register. In order to identify the
* reset source, the MPU application must use RCC MPU Reset Status Clear Register
* (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status
* Clear Register (RCC_MC_RSTSCLRR).
*@note Writing '0' has no effect, reading will return the effective values of the
* corresponding bits. Writing a '1' sets the corresponding bit to '1'.
*@note The register is located in VDDCORE.
*@note If TZEN = '1', this register can only be modified in secure mode.
*/
#define RCC_MP_RSTSSETR_PORRSTF_Pos (0U)
#define RCC_MP_RSTSSETR_PORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PORRSTF_Pos) /*!< 0x00000001 */
#define RCC_MP_RSTSSETR_PORRSTF RCC_MP_RSTSSETR_PORRSTF_Msk /*POR/PDR reset flag*/
#define RCC_MP_RSTSSETR_BORRSTF_Pos (1U)
#define RCC_MP_RSTSSETR_BORRSTF_Msk (0x1U << RCC_MP_RSTSSETR_BORRSTF_Pos) /*!< 0x00000002 */
#define RCC_MP_RSTSSETR_BORRSTF RCC_MP_RSTSSETR_BORRSTF_Msk /*BOR reset flag*/
#define RCC_MP_RSTSSETR_PADRSTF_Pos (2U)
#define RCC_MP_RSTSSETR_PADRSTF_Msk (0x1U << RCC_MP_RSTSSETR_PADRSTF_Pos) /*!< 0x00000004 */
#define RCC_MP_RSTSSETR_PADRSTF RCC_MP_RSTSSETR_PADRSTF_Msk /*NRST reset flag*/
#define RCC_MP_RSTSSETR_HCSSRSTF_Pos (3U)
#define RCC_MP_RSTSSETR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_HCSSRSTF_Pos) /*!< 0x00000008 */
#define RCC_MP_RSTSSETR_HCSSRSTF RCC_MP_RSTSSETR_HCSSRSTF_Msk /*HSE CSS reset flag*/
#define RCC_MP_RSTSSETR_VCORERSTF_Pos (4U)
#define RCC_MP_RSTSSETR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSSETR_VCORERSTF_Pos) /*!< 0x00000010 */
#define RCC_MP_RSTSSETR_VCORERSTF RCC_MP_RSTSSETR_VCORERSTF_Msk /*VDDCORE reset flag*/
#define RCC_MP_RSTSSETR_MPSYSRSTF_Pos (6U)
#define RCC_MP_RSTSSETR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPSYSRSTF_Pos) /*!< 0x00000040 */
#define RCC_MP_RSTSSETR_MPSYSRSTF RCC_MP_RSTSSETR_MPSYSRSTF_Msk /*MPU System reset flag*/
#define RCC_MP_RSTSSETR_MCSYSRSTF_Pos (7U)
#define RCC_MP_RSTSSETR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSSETR_MCSYSRSTF_Pos) /*!< 0x00000080 */
#define RCC_MP_RSTSSETR_MCSYSRSTF RCC_MP_RSTSSETR_MCSYSRSTF_Msk /*MCU System reset flag*/
#define RCC_MP_RSTSSETR_IWDG1RSTF_Pos (8U)
#define RCC_MP_RSTSSETR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG1RSTF_Pos) /*!< 0x00000100 */
#define RCC_MP_RSTSSETR_IWDG1RSTF RCC_MP_RSTSSETR_IWDG1RSTF_Msk /*IWDG1 reset flag*/
#define RCC_MP_RSTSSETR_IWDG2RSTF_Pos (9U)
#define RCC_MP_RSTSSETR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSSETR_IWDG2RSTF_Pos) /*!< 0x00000200 */
#define RCC_MP_RSTSSETR_IWDG2RSTF RCC_MP_RSTSSETR_IWDG2RSTF_Msk /*IWDG2 reset flag*/
#define RCC_MP_RSTSSETR_STDBYRSTF_Pos (11U)
#define RCC_MP_RSTSSETR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_STDBYRSTF_Pos) /*!< 0x00000800 */
#define RCC_MP_RSTSSETR_STDBYRSTF RCC_MP_RSTSSETR_STDBYRSTF_Msk /*System Standby reset flag*/
#define RCC_MP_RSTSSETR_CSTDBYRSTF_Pos (12U)
#define RCC_MP_RSTSSETR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSSETR_CSTDBYRSTF_Pos) /*!< 0x00001000 */
#define RCC_MP_RSTSSETR_CSTDBYRSTF RCC_MP_RSTSSETR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/
#define RCC_MP_RSTSSETR_MPUP0RSTF_Pos (13U)
#define RCC_MP_RSTSSETR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP0RSTF_Pos) /*!< 0x00002000 */
#define RCC_MP_RSTSSETR_MPUP0RSTF RCC_MP_RSTSSETR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/
#define RCC_MP_RSTSSETR_MPUP1RSTF_Pos (14U)
#define RCC_MP_RSTSSETR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSSETR_MPUP1RSTF_Pos) /*!< 0x00004000 */
#define RCC_MP_RSTSSETR_MPUP1RSTF RCC_MP_RSTSSETR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/
#define RCC_MP_RSTSSETR_SPARE_Pos (15U)
#define RCC_MP_RSTSSETR_SPARE_Msk (0x1U << RCC_MP_RSTSSETR_SPARE_Pos) /*!< 0x00008000 */
#define RCC_MP_RSTSSETR_SPARE RCC_MP_RSTSSETR_SPARE_Msk /*Spare bits*/
/******************* Bit definition for RCC_APB1RSTSETR register ************/
/*!< This register is used to activate the reset of the corresponding peripheral */
#define RCC_APB1RSTSETR_TIM2RST B(0)
#define RCC_APB1RSTSETR_TIM3RST B(1)
#define RCC_APB1RSTSETR_TIM4RST B(2)
#define RCC_APB1RSTSETR_TIM5RST B(3)
#define RCC_APB1RSTSETR_TIM6RST B(4)
#define RCC_APB1RSTSETR_TIM7RST B(5)
#define RCC_APB1RSTSETR_TIM12RST B(6)
#define RCC_APB1RSTSETR_TIM13RST B(7)
#define RCC_APB1RSTSETR_TIM14RST B(8)
#define RCC_APB1RSTSETR_LPTIM1RST B(9)
#define RCC_APB1RSTSETR_SPI2RST B(11)
#define RCC_APB1RSTSETR_SPI3RST B(12)
#define RCC_APB1RSTSETR_USART2RST B(14)
#define RCC_APB1RSTSETR_USART3RST B(15)
#define RCC_APB1RSTSETR_UART4RST B(16)
#define RCC_APB1RSTSETR_UART5RST B(17)
#define RCC_APB1RSTSETR_UART7RST B(18)
#define RCC_APB1RSTSETR_UART8RST B(19)
#define RCC_APB1RSTSETR_I2C1RST B(21)
#define RCC_APB1RSTSETR_I2C2RST B(22)
#define RCC_APB1RSTSETR_I2C3RST B(23)
#define RCC_APB1RSTSETR_I2C5RST B(24)
#define RCC_APB1RSTSETR_SPDIFRST B(26)
#define RCC_APB1RSTSETR_CECRST B(27)
#define RCC_APB1RSTSETR_DAC12RST B(29)
#define RCC_APB1RSTSETR_MDIOSRST B(31)
/******************* Bit definition for RCC_APB1RSTCLRR register ************/
/*!< This register is used to release the reset of the corresponding peripheral */
#define RCC_APB1RSTCLRR_TIM2RST B(0)
#define RCC_APB1RSTCLRR_TIM3RST B(1)
#define RCC_APB1RSTCLRR_TIM4RST B(2)
#define RCC_APB1RSTCLRR_TIM5RST B(3)
#define RCC_APB1RSTCLRR_TIM6RST B(4)
#define RCC_APB1RSTCLRR_TIM7RST B(5)
#define RCC_APB1RSTCLRR_TIM12RST B(6)
#define RCC_APB1RSTCLRR_TIM13RST B(7)
#define RCC_APB1RSTCLRR_TIM14RST B(8)
#define RCC_APB1RSTCLRR_LPTIM1RST B(9)
#define RCC_APB1RSTCLRR_SPI2RST B(11)
#define RCC_APB1RSTCLRR_SPI3RST B(12)
#define RCC_APB1RSTCLRR_USART2RST B(14)
#define RCC_APB1RSTCLRR_USART3RST B(15)
#define RCC_APB1RSTCLRR_UART4RST B(16)
#define RCC_APB1RSTCLRR_UART5RST B(17)
#define RCC_APB1RSTCLRR_UART7RST B(18)
#define RCC_APB1RSTCLRR_UART8RST B(19)
#define RCC_APB1RSTCLRR_I2C1RST B(21)
#define RCC_APB1RSTCLRR_I2C2RST B(22)
#define RCC_APB1RSTCLRR_I2C3RST B(23)
#define RCC_APB1RSTCLRR_I2C5RST B(24)
#define RCC_APB1RSTCLRR_SPDIFRST B(26)
#define RCC_APB1RSTCLRR_CECRST B(27)
#define RCC_APB1RSTCLRR_DAC12RST B(29)
#define RCC_APB1RSTCLRR_MDIOSRST B(31)
/******************* Bit definition for RCC_APB2RSTSETR register ************/
/*!< This register is used to activate the reset of the corresponding peripheral */
#define RCC_APB2RSTSETR_TIM1RST B(0)
#define RCC_APB2RSTSETR_TIM8RST B(1)
#define RCC_APB2RSTSETR_TIM15RST B(2)
#define RCC_APB2RSTSETR_TIM16RST B(3)
#define RCC_APB2RSTSETR_TIM17RST B(4)
#define RCC_APB2RSTSETR_SPI1RST B(8)
#define RCC_APB2RSTSETR_SPI4RST B(9)
#define RCC_APB2RSTSETR_SPI5RST B(10)
#define RCC_APB2RSTSETR_USART6RST B(13)
#define RCC_APB2RSTSETR_SAI1RST B(16)
#define RCC_APB2RSTSETR_SAI2RST B(17)
#define RCC_APB2RSTSETR_SAI3RST B(18)
#define RCC_APB2RSTSETR_DFSDMRST B(20)
#define RCC_APB2RSTSETR_FDCANRST B(24)
/******************* Bit definition for RCC_APB2RSTCLRR register ************/
/*!< This register is used to release the reset of the corresponding peripheral */
#define RCC_APB2RSTCLRR_TIM1RST B(0)
#define RCC_APB2RSTCLRR_TIM8RST B(1)
#define RCC_APB2RSTCLRR_TIM15RST B(2)
#define RCC_APB2RSTCLRR_TIM16RST B(3)
#define RCC_APB2RSTCLRR_TIM17RST B(4)
#define RCC_APB2RSTCLRR_SPI1RST B(8)
#define RCC_APB2RSTCLRR_SPI4RST B(9)
#define RCC_APB2RSTCLRR_SPI5RST B(10)
#define RCC_APB2RSTCLRR_USART6RST B(13)
#define RCC_APB2RSTCLRR_SAI1RST B(16)
#define RCC_APB2RSTCLRR_SAI2RST B(17)
#define RCC_APB2RSTCLRR_SAI3RST B(18)
#define RCC_APB2RSTCLRR_DFSDMRST B(20)
#define RCC_APB2RSTCLRR_FDCANRST B(24)
/******************* Bit definition for RCC_APB3RSTSETR register ************/
/*!< This register is used to activate the reset of the corresponding peripheral */
#define RCC_APB3RSTSETR_LPTIM2RST B(0)
#define RCC_APB3RSTSETR_LPTIM3RST B(1)
#define RCC_APB3RSTSETR_LPTIM4RST B(2)
#define RCC_APB3RSTSETR_LPTIM5RST B(3)
#define RCC_APB3RSTSETR_SAI4RST B(8)
#define RCC_APB3RSTSETR_SYSCFGRST B(11)
#define RCC_APB3RSTSETR_VREFRST B(13)
#define RCC_APB3RSTSETR_DTSRST B(16)
#define RCC_APB3RSTSETR_PMBCTRLRST B(17)
/******************* Bit definition for RCC_APB3RSTCLRR register ************/
/*!< This register is used to release the reset of the corresponding peripheral */
#define RCC_APB3RSTCLRR_LPTIM2RST B(0)
#define RCC_APB3RSTCLRR_LPTIM3RST B(1)
#define RCC_APB3RSTCLRR_LPTIM4RST B(2)
#define RCC_APB3RSTCLRR_LPTIM5RST B(3)
#define RCC_APB3RSTCLRR_SAI4RST B(8)
#define RCC_APB3RSTCLRR_SYSCFGRST B(11)
#define RCC_APB3RSTCLRR_VREFRST B(13)
#define RCC_APB3RSTCLRR_DTSRST B(16)
#define RCC_APB3RSTCLRR_PMBCTRLRST B(17)
/******************* Bit definition for RCC_AHB2RSTSETR register ************/
/*!< This register is used to activate the reset of the corresponding peripheral */
#define RCC_AHB2RSTSETR_DMA1RST B(0)
#define RCC_AHB2RSTSETR_DMA2RST B(1)
#define RCC_AHB2RSTSETR_DMAMUXRST B(2)
#define RCC_AHB2RSTSETR_ADC12RST B(5)
#define RCC_AHB2RSTSETR_USBORST B(8)
#define RCC_AHB2RSTSETR_SDMMC3RST B(16)
/******************* Bit definition for RCC_AHB2RSTCLRR register ************/
/*!< This register is used to release the reset of the corresponding peripheral */
#define RCC_AHB2RSTCLRR_DMA1RST B(0)
#define RCC_AHB2RSTCLRR_DMA2RST B(1)
#define RCC_AHB2RSTCLRR_DMAMUXRST B(2)
#define RCC_AHB2RSTCLRR_ADC12RST B(5)
#define RCC_AHB2RSTCLRR_USBORST B(8)
#define RCC_AHB2RSTCLRR_SDMMC3RST B(16)
/******************* Bit definition for RCC_AHB3RSTSETR register ************/
/*!< This register is used to activate the reset of the corresponding peripheral */
#define RCC_AHB3RSTSETR_DCMIRST B(0)
#define RCC_AHB3RSTSETR_CRYP2RST B(4)
#define RCC_AHB3RSTSETR_HASH2RST B(5)
#define RCC_AHB3RSTSETR_RNG2RST B(6)
#define RCC_AHB3RSTSETR_CRC2RST B(7)
#define RCC_AHB3RSTSETR_HSEMRST B(11)
#define RCC_AHB3RSTSETR_IPCCRST B(12)
/******************* Bit definition for RCC_AHB3RSTCLRR register ************/
/*!< This register is used to release the reset of the corresponding peripheral */
#define RCC_AHB3RSTCLRR_DCMIRST B(0)
#define RCC_AHB3RSTCLRR_CRYP2RST B(4)
#define RCC_AHB3RSTCLRR_HASH2RST B(5)
#define RCC_AHB3RSTCLRR_RNG2RST B(6)
#define RCC_AHB3RSTCLRR_CRC2RST B(7)
#define RCC_AHB3RSTCLRR_HSEMRST B(11)
#define RCC_AHB3RSTCLRR_IPCCRST B(12)
/******************* Bit definition for RCC_AHB4RSTSETR register ************/
/*!< This register is used to activate the reset of the corresponding peripheral */
#define RCC_AHB4RSTSETR_GPIOARST B(0)
#define RCC_AHB4RSTSETR_GPIOBRST B(1)
#define RCC_AHB4RSTSETR_GPIOCRST B(2)
#define RCC_AHB4RSTSETR_GPIODRST B(3)
#define RCC_AHB4RSTSETR_GPIOERST B(4)
#define RCC_AHB4RSTSETR_GPIOFRST B(5)
#define RCC_AHB4RSTSETR_GPIOGRST B(6)
#define RCC_AHB4RSTSETR_GPIOHRST B(7)
#define RCC_AHB4RSTSETR_GPIOIRST B(8)
#define RCC_AHB4RSTSETR_GPIOJRST B(9)
#define RCC_AHB4RSTSETR_GPIOKRST B(10)
/******************* Bit definition for RCC_AHB4RSTCLRR register ************/
/*!< This register is used to release the reset of the corresponding peripheral */
#define RCC_AHB4RSTCLRR_GPIOARST B(0)
#define RCC_AHB4RSTCLRR_GPIOBRST B(1)
#define RCC_AHB4RSTCLRR_GPIOCRST B(2)
#define RCC_AHB4RSTCLRR_GPIODRST B(3)
#define RCC_AHB4RSTCLRR_GPIOERST B(4)
#define RCC_AHB4RSTCLRR_GPIOFRST B(5)
#define RCC_AHB4RSTCLRR_GPIOGRST B(6)
#define RCC_AHB4RSTCLRR_GPIOHRST B(7)
#define RCC_AHB4RSTCLRR_GPIOIRST B(8)
#define RCC_AHB4RSTCLRR_GPIOJRST B(9)
#define RCC_AHB4RSTCLRR_GPIOKRST B(10)
/******************* Bit definition for RCC_APB4RSTSETR register ************/
/*!< This register is used to activate the reset of the corresponding peripheral */
#define RCC_APB4RSTSETR_LTDCRST B(0)
#define RCC_APB4RSTSETR_DSIRST B(4)
#define RCC_APB4RSTSETR_DDRPERFMRST B(8)
#define RCC_APB4RSTSETR_USBPHYRST B(16)
/******************* Bit definition for RCC_APB4RSTCLRR register ************/
/*!< This register is used to release the reset of the corresponding peripheral */
#define RCC_APB4RSTCLRR_LTDCRST B(0)
#define RCC_APB4RSTCLRR_DSIRST B(4)
#define RCC_APB4RSTCLRR_DDRPERFMRST B(8)
#define RCC_APB4RSTCLRR_USBPHYRST B(16)
/******************* Bit definition for RCC_APB5RSTSETR register ************/
/*!< This register is used to activate the reset of the corresponding peripheral */
#define RCC_APB5RSTSETR_SPI6RST B(0)
#define RCC_APB5RSTSETR_I2C4RST B(2)
#define RCC_APB5RSTSETR_I2C6RST B(3)
#define RCC_APB5RSTSETR_USART1RST B(4)
#define RCC_APB5RSTSETR_STGENRST B(20)
/******************* Bit definition for RCC_APB5RSTCLRR register ************/
/*!< This register is used to release the reset of the corresponding peripheral */
#define RCC_APB5RSTCLRR_SPI6RST B(0)
#define RCC_APB5RSTCLRR_I2C4RST B(2)
#define RCC_APB5RSTCLRR_I2C6RST B(3)
#define RCC_APB5RSTCLRR_USART1RST B(4)
#define RCC_APB5RSTCLRR_STGENRST B(20)
/******************* Bit definition for RCC_AHB5RSTSETR register ************/
/*!< This register is used to activate the reset of the corresponding peripheral */
#define RCC_AHB5RSTSETR_GPIOZRST B(0)
#define RCC_AHB5RSTSETR_CRYP1RST B(4)
#define RCC_AHB5RSTSETR_HASH1RST B(5)
#define RCC_AHB5RSTSETR_RNG1RST B(6)
#define RCC_AHB5RSTSETR_AXIMCRST B(16)
/******************* Bit definition for RCC_AHB5RSTCLRR register ************/
/*!< This register is used to release the reset of the corresponding peripheral */
#define RCC_AHB5RSTCLRR_GPIOZRST B(0)
#define RCC_AHB5RSTCLRR_CRYP1RST B(4)
#define RCC_AHB5RSTCLRR_HASH1RST B(5)
#define RCC_AHB5RSTCLRR_RNG1RST B(6)
#define RCC_AHB5RSTCLRR_AXIMCRST B(16)
/******************* Bit definition for RCC_AHB6RSTSETR register ************/
/*!< This register is used to activate the reset of the corresponding peripheral */
#define RCC_AHB6RSTSETR_GPURST B(5)
#define RCC_AHB6RSTSETR_ETHMACRST B(10)
#define RCC_AHB6RSTSETR_FMCRST B(12)
#define RCC_AHB6RSTSETR_QSPIRST B(14)
#define RCC_AHB6RSTSETR_SDMMC1RST B(16)
#define RCC_AHB6RSTSETR_SDMMC2RST B(17)
#define RCC_AHB6RSTSETR_CRC1RST B(20)
#define RCC_AHB6RSTSETR_USBHRST B(24)
/******************* Bit definition for RCC_AHB6RSTCLRR register ************/
/*!< This register is used to release the reset of the corresponding peripheral */
#define RCC_AHB6RSTCLRR_ETHMACRST B(10)
#define RCC_AHB6RSTCLRR_FMCRST B(12)
#define RCC_AHB6RSTCLRR_QSPIRST B(14)
#define RCC_AHB6RSTCLRR_SDMMC1RST B(16)
#define RCC_AHB6RSTCLRR_SDMMC2RST B(17)
#define RCC_AHB6RSTCLRR_CRC1RST B(20)
#define RCC_AHB6RSTCLRR_USBHRST B(24)
/******************* Bit definition for RCC_TZAHB6RSTSETR register ************/
/*!< This register is used to activate the reset of the corresponding peripheral */
#define RCC_TZAHB6RSTSETR_MDMARST B(0)
/******************* Bit definition for RCC_TZAHB6RSTCLRR register ************/
/*!< This register is used to release the reset of the corresponding peripheral */
#define RCC_TZAHB6RSTCLRR_MDMARST B(0)
/******************* Bit definition for RCC_MP_GRSTCSETR register ************/
/*!< This register is used by the MPU in order to generate either a MCU reset
* or a system reset or a reset of one of the two MPU processors. Writing '0' has
* no effect, reading will return the effective values of the corresponding bits.
* Writing a '1' activates the reset */
#define RCC_MP_GRSTCSETR_MPSYSRST_Pos (0U)
#define RCC_MP_GRSTCSETR_MPSYSRST_Msk (0x1U << RCC_MP_GRSTCSETR_MPSYSRST_Pos) /*!< 0x00000001 */
#define RCC_MP_GRSTCSETR_MPSYSRST RCC_MP_GRSTCSETR_MPSYSRST_Msk /*System reset */
#define RCC_MP_GRSTCSETR_MCURST_Pos (1U)
#define RCC_MP_GRSTCSETR_MCURST_Msk (0x1U << RCC_MP_GRSTCSETR_MCURST_Pos) /*!< 0x00000002 */
#define RCC_MP_GRSTCSETR_MCURST RCC_MP_GRSTCSETR_MCURST_Msk /*MCU reset */
#define RCC_MP_GRSTCSETR_MPUP0RST_Pos (4U)
#define RCC_MP_GRSTCSETR_MPUP0RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP0RST_Pos) /*!< 0x00000010 */
#define RCC_MP_GRSTCSETR_MPUP0RST RCC_MP_GRSTCSETR_MPUP0RST_Msk /*MPU processor 0 reset*/
#define RCC_MP_GRSTCSETR_MPUP1RST_Pos (5U)
#define RCC_MP_GRSTCSETR_MPUP1RST_Msk (0x1U << RCC_MP_GRSTCSETR_MPUP1RST_Pos) /*!< 0x00000020 */
#define RCC_MP_GRSTCSETR_MPUP1RST RCC_MP_GRSTCSETR_MPUP1RST_Msk /*MPU processor 1 reset*/
/******************* Bit definition for RCC_MC_APB1ENSETR register ***********/
/*!< This register is used to set the peripheral clock enable bit of the corresponding
* peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
#define RCC_MC_APB1ENSETR_TIM2EN B(0)
#define RCC_MC_APB1ENSETR_TIM3EN B(1)
#define RCC_MC_APB1ENSETR_TIM4EN B(2)
#define RCC_MC_APB1ENSETR_TIM5EN B(3)
#define RCC_MC_APB1ENSETR_TIM6EN B(4)
#define RCC_MC_APB1ENSETR_TIM7EN B(5)
#define RCC_MC_APB1ENSETR_TIM12EN B(6)
#define RCC_MC_APB1ENSETR_TIM13EN B(7)
#define RCC_MC_APB1ENSETR_TIM14EN B(8)
#define RCC_MC_APB1ENSETR_LPTIM1EN B(9)
#define RCC_MC_APB1ENSETR_SPI2EN B(11)
#define RCC_MC_APB1ENSETR_SPI3EN B(12)
#define RCC_MC_APB1ENSETR_USART2EN B(14)
#define RCC_MC_APB1ENSETR_USART3EN B(15)
#define RCC_MC_APB1ENSETR_UART4EN B(16)
#define RCC_MC_APB1ENSETR_UART5EN B(17)
#define RCC_MC_APB1ENSETR_UART7EN B(18)
#define RCC_MC_APB1ENSETR_UART8EN B(19)
#define RCC_MC_APB1ENSETR_I2C1EN B(21)
#define RCC_MC_APB1ENSETR_I2C2EN B(22)
#define RCC_MC_APB1ENSETR_I2C3EN B(23)
#define RCC_MC_APB1ENSETR_I2C5EN B(24)
#define RCC_MC_APB1ENSETR_SPDIFEN B(26)
#define RCC_MC_APB1ENSETR_CECEN B(27)
#define RCC_MC_APB1ENSETR_WWDG1EN B(28)
#define RCC_MC_APB1ENSETR_DAC12EN B(29)
#define RCC_MC_APB1ENSETR_MDIOSEN B(31)
/******************* Bit definition for RCC_MC_APB1ENCLRR register ************/
/*!< This register is used to clear the peripheral clock enable bit of the corresponding
peripheral. It shall be used to deallocate a peripheral from MCU */
#define RCC_MC_APB1ENCLRR_TIM2EN B(0)
#define RCC_MC_APB1ENCLRR_TIM3EN B(1)
#define RCC_MC_APB1ENCLRR_TIM4EN B(2)
#define RCC_MC_APB1ENCLRR_TIM5EN B(3)
#define RCC_MC_APB1ENCLRR_TIM6EN B(4)
#define RCC_MC_APB1ENCLRR_TIM7EN B(5)
#define RCC_MC_APB1ENCLRR_TIM12EN B(6)
#define RCC_MC_APB1ENCLRR_TIM13EN B(7)
#define RCC_MC_APB1ENCLRR_TIM14EN B(8)
#define RCC_MC_APB1ENCLRR_LPTIM1EN B(9)
#define RCC_MC_APB1ENCLRR_SPI2EN B(11)
#define RCC_MC_APB1ENCLRR_SPI3EN B(12)
#define RCC_MC_APB1ENCLRR_USART2EN B(14)
#define RCC_MC_APB1ENCLRR_USART3EN B(15)
#define RCC_MC_APB1ENCLRR_UART4EN B(16)
#define RCC_MC_APB1ENCLRR_UART5EN B(17)
#define RCC_MC_APB1ENCLRR_UART7EN B(18)
#define RCC_MC_APB1ENCLRR_UART8EN B(19)
#define RCC_MC_APB1ENCLRR_I2C1EN B(21)
#define RCC_MC_APB1ENCLRR_I2C2EN B(22)
#define RCC_MC_APB1ENCLRR_I2C3EN B(23)
#define RCC_MC_APB1ENCLRR_I2C5EN B(24)
#define RCC_MC_APB1ENCLRR_SPDIFEN B(26)
#define RCC_MC_APB1ENCLRR_CECEN B(27)
#define RCC_MC_APB1ENCLRR_WWDG1EN B(28)
#define RCC_MC_APB1ENCLRR_DAC12EN B(29)
#define RCC_MC_APB1ENCLRR_MDIOSEN B(31)
/******************* Bit definition for RCC_MC_APB2ENSETR register ***********/
/*!< This register is used to set the peripheral clock enable bit of the corresponding
* peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
#define RCC_MC_APB2ENSETR_TIM1EN B(0)
#define RCC_MC_APB2ENSETR_TIM8EN B(1)
#define RCC_MC_APB2ENSETR_TIM15EN B(2)
#define RCC_MC_APB2ENSETR_TIM16EN B(3)
#define RCC_MC_APB2ENSETR_TIM17EN B(4)
#define RCC_MC_APB2ENSETR_SPI1EN B(8)
#define RCC_MC_APB2ENSETR_SPI4EN B(9)
#define RCC_MC_APB2ENSETR_SPI5EN B(10)
#define RCC_MC_APB2ENSETR_USART6EN B(13)
#define RCC_MC_APB2ENSETR_SAI1EN B(16)
#define RCC_MC_APB2ENSETR_SAI2EN B(17)
#define RCC_MC_APB2ENSETR_SAI3EN B(18)
#define RCC_MC_APB2ENSETR_DFSDMEN B(20)
#define RCC_MC_APB2ENSETR_ADFSDMEN B(21)
#define RCC_MC_APB2ENSETR_FDCANEN B(24)
/******************* Bit definition for RCC_MC_APB2ENCLRR register ************/
/*!< This register is used to clear the peripheral clock enable bit of the corresponding
* peripheral. It shall be used to deallocate a peripheral from MCU */
#define RCC_MC_APB2ENCLRR_TIM1EN B(0)
#define RCC_MC_APB2ENCLRR_TIM8EN B(1)
#define RCC_MC_APB2ENCLRR_TIM15EN B(2)
#define RCC_MC_APB2ENCLRR_TIM16EN B(3)
#define RCC_MC_APB2ENCLRR_TIM17EN B(4)
#define RCC_MC_APB2ENCLRR_SPI1EN B(8)
#define RCC_MC_APB2ENCLRR_SPI4EN B(9)
#define RCC_MC_APB2ENCLRR_SPI5EN B(10)
#define RCC_MC_APB2ENCLRR_USART6EN B(13)
#define RCC_MC_APB2ENCLRR_SAI1EN B(16)
#define RCC_MC_APB2ENCLRR_SAI2EN B(17)
#define RCC_MC_APB2ENCLRR_SAI3EN B(18)
#define RCC_MC_APB2ENCLRR_DFSDMEN B(20)
#define RCC_MC_APB2ENCLRR_ADFSDMEN B(21)
#define RCC_MC_APB2ENCLRR_FDCANEN B(24)
/******************* Bit definition for RCC_MC_APB3ENSETR register ***********/
/*!< This register is used to set the peripheral clock enable bit of the corresponding
* peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
#define RCC_MC_APB3ENSETR_LPTIM2EN B(0)
#define RCC_MC_APB3ENSETR_LPTIM3EN B(1)
#define RCC_MC_APB3ENSETR_LPTIM4EN B(2)
#define RCC_MC_APB3ENSETR_LPTIM5EN B(3)
#define RCC_MC_APB3ENSETR_SAI4EN B(8)
#define RCC_MC_APB3ENSETR_SYSCFGEN B(11)
#define RCC_MC_APB3ENSETR_VREFEN B(13)
#define RCC_MC_APB3ENSETR_DTSEN B(16)
#define RCC_MC_APB3ENSETR_PMBCTRLEN B(17)
#define RCC_MC_APB3ENSETR_HDPEN B(20)
/******************* Bit definition for RCC_MC_APB3ENCLRR register ************/
/*!< This register is used to clear the peripheral clock enable bit of the corresponding
* peripheral. It shall be used to deallocate a peripheral from MCU */
#define RCC_MC_APB3ENCLRR_LPTIM2EN B(0)
#define RCC_MC_APB3ENCLRR_LPTIM3EN B(1)
#define RCC_MC_APB3ENCLRR_LPTIM4EN B(2)
#define RCC_MC_APB3ENCLRR_LPTIM5EN B(3)
#define RCC_MC_APB3ENCLRR_SAI4EN B(8)
#define RCC_MC_APB3ENCLRR_SYSCFGEN B(11)
#define RCC_MC_APB3ENCLRR_VREFEN B(13)
#define RCC_MC_APB3ENCLRR_DTSEN B(16)
#define RCC_MC_APB3ENCLRR_PMBCTRLEN B(17)
#define RCC_MC_APB3ENCLRR_HDPEN B(20)
/******************* Bit definition for RCC_MC_APB4ENSETR register ***********/
/*!< This register is used to set the peripheral clock enable bit of the corresponding
* peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
#define RCC_MC_APB4ENSETR_LTDCEN B(0)
#define RCC_MC_APB4ENSETR_DSIEN B(4)
#define RCC_MC_APB4ENSETR_DDRPERFMEN B(8)
#define RCC_MC_APB4ENSETR_USBPHYEN B(16)
#define RCC_MC_APB4ENSETR_STGENROEN B(20)
/******************* Bit definition for RCC_MP_APB4ENSETR register ***********/
/*!< This register is used to set the peripheral clock enable bit of the corresponding
* peripheral to 1. It shall be used to allocate a peripheral to the MPU. */
#define RCC_MP_APB4ENSETR_LTDCEN B(0)
#define RCC_MP_APB4ENSETR_DSIEN B(4)
#define RCC_MP_APB4ENSETR_IWDG2APBEN B(15)
#define RCC_MP_APB4ENSETR_USBPHYEN B(16)
#define RCC_MP_APB4ENSETR_STGENROEN B(20)
/******************* Bit definition for RCC_MC_APB4ENCLRR register ************/
/*!< This register is used to clear the peripheral clock enable bit of the corresponding
* peripheral. It shall be used to deallocate a peripheral from MCU */
#define RCC_MC_APB4ENCLRR_LTDCEN B(0)
#define RCC_MC_APB4ENCLRR_DSIEN B(4)
#define RCC_MC_APB4ENCLRR_USBPHYEN B(16)
#define RCC_MC_APB4ENCLRR_STGENROEN B(20)
/******************* Bit definition for RCC_MP_APB4ENCLRR register ************/
/*!< This register is used to clear the peripheral clock enable bit of the corresponding
* peripheral. It shall be used to deallocate a peripheral from MCU */
#define RCC_MP_APB4ENCLRR_LTDCEN B(0)
#define RCC_MP_APB4ENCLRR_DSIEN B(4)
#define RCC_MP_APB4ENCLRR_IWDG2APBEN B(15)
#define RCC_MP_APB4ENCLRR_USBPHYEN B(16)
#define RCC_MP_APB4ENCLRR_STGENROEN B(20)
/******************* Bit definition for RCC_MC_APB5ENSETR register ***********/
/*!< This register is used to set the peripheral clock enable bit of the corresponding
* peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
#define RCC_MC_APB5ENSETR_SPI6EN B(0)
#define RCC_MC_APB5ENSETR_I2C4EN B(2)
#define RCC_MC_APB5ENSETR_I2C6EN B(3)
#define RCC_MC_APB5ENSETR_USART1EN B(4)
#define RCC_MC_APB5ENSETR_RTCAPBEN B(8)
#define RCC_MC_APB5ENSETR_TZC1EN B(11)
#define RCC_MC_APB5ENSETR_TZC2EN B(12)
#define RCC_MC_APB5ENSETR_TZPCEN B(13)
#define RCC_MC_APB5ENSETR_BSECEN B(16)
#define RCC_MC_APB5ENSETR_STGENEN B(20)
/******************* Bit definition for RCC_MP_APB5ENSETR register ***********/
/*!< This register is used to set the peripheral clock enable bit of the corresponding
* peripheral to 1. It shall be used to allocate a peripheral to the MPU.
* This bit can also be used to test if IWDG1 peripheral clock is enabled
* If TZEN = 1, this register can only be modified in secure mode. */
#define RCC_MP_APB5ENSETR_IWDG1APBEN B(15)
/******************* Bit definition for RCC_MC_APB5ENCLRR register ************/
/*!< This register is used to clear the peripheral clock enable bit of the corresponding
* peripheral. It shall be used to deallocate a peripheral from MCU */
#define RCC_MC_APB5ENCLRR_SPI6EN B(0)
#define RCC_MC_APB5ENCLRR_I2C4EN B(2)
#define RCC_MC_APB5ENCLRR_I2C6EN B(3)
#define RCC_MC_APB5ENCLRR_USART1EN B(4)
#define RCC_MC_APB5ENCLRR_RTCAPBEN B(8)
#define RCC_MC_APB5ENCLRR_TZC1EN B(11)
#define RCC_MC_APB5ENCLRR_TZC2EN B(12)
#define RCC_MC_APB5ENCLRR_TZPCEN B(13)
#define RCC_MC_APB5ENCLRR_BSECEN B(16)
#define RCC_MC_APB5ENCLRR_STGENEN B(20)
/******************* Bit definition for RCC_MC_AHB5ENSETR register ***********/
/*!< This register is used to set the peripheral clock enable bit of the corresponding
* peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
#define RCC_MC_AHB5ENSETR_GPIOZEN B(0)
#define RCC_MC_AHB5ENSETR_CRYP1EN B(4)
#define RCC_MC_AHB5ENSETR_HASH1EN B(5)
#define RCC_MC_AHB5ENSETR_RNG1EN B(6)
#define RCC_MC_AHB5ENSETR_BKPSRAMEN B(8)
#define RCC_MC_AHB5ENSETR_AXIMC B(16)
/******************* Bit definition for RCC_MC_AHB5ENCLRR register ************/
/*!< This register is used to clear the peripheral clock enable bit of the corresponding
* peripheral. It shall be used to deallocate a peripheral from MCU */
#define RCC_MC_AHB5ENCLRR_GPIOZEN B(0)
#define RCC_MC_AHB5ENCLRR_CRYP1EN B(4)
#define RCC_MC_AHB5ENCLRR_HASH1EN B(5)
#define RCC_MC_AHB5ENCLRR_RNG1EN B(6)
#define RCC_MC_AHB5ENCLRR_BKPSRAMEN B(8)
/******************* Bit definition for RCC_MC_AHB6ENSETR register ***********/
/*!< This register is used to set the peripheral clock enable bit of the corresponding
* peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
#define RCC_MC_AHB6ENSETR_MDMAEN B(0)
#define RCC_MC_AHB6ENSETR_GPUEN B(5)
#define RCC_MC_AHB6ENSETR_ETHCKEN B(7)
#define RCC_MC_AHB6ENSETR_ETHTXEN B(8)
#define RCC_MC_AHB6ENSETR_ETHRXEN B(9)
#define RCC_MC_AHB6ENSETR_ETHMACEN B(10)
#define RCC_MC_AHB6ENSETR_FMCEN B(12)
#define RCC_MC_AHB6ENSETR_QSPIEN B(14)
#define RCC_MC_AHB6ENSETR_SDMMC1EN B(16)
#define RCC_MC_AHB6ENSETR_SDMMC2EN B(17)
#define RCC_MC_AHB6ENSETR_CRC1EN B(20)
#define RCC_MC_AHB6ENSETR_USBHEN B(24)
/******************* Bit definition for RCC_MC_AHB6ENCLRR register ************/
/*!< This register is used to clear the peripheral clock enable bit of the corresponding
* peripheral. It shall be used to deallocate a peripheral from MCU */
#define RCC_MC_AHB6ENCLRR_MDMAEN B(0)
#define RCC_MC_AHB6ENCLRR_GPUEN B(5)
#define RCC_MC_AHB6ENCLRR_ETHCKEN B(7)
#define RCC_MC_AHB6ENCLRR_ETHTXEN B(8)
#define RCC_MC_AHB6ENCLRR_ETHRXEN B(9)
#define RCC_MC_AHB6ENCLRR_ETHMACEN B(10)
#define RCC_MC_AHB6ENCLRR_FMCEN B(12)
#define RCC_MC_AHB6ENCLRR_QSPIEN B(14)
#define RCC_MC_AHB6ENCLRR_SDMMC1EN B(16)
#define RCC_MC_AHB6ENCLRR_SDMMC2EN B(17)
#define RCC_MC_AHB6ENCLRR_CRC1EN B(20)
#define RCC_MC_AHB6ENCLRR_USBHEN B(24)
/******************* Bit definition for RCC_MP_TZAHB6ENSETR register ***********/
/*!< This register is used to set the peripheral clock enable bit of the corresponding
* peripheral to 1. It shall be used to allocate a peripheral to the MPU. */
#define RCC_MP_TZAHB6ENSETR_MDMAEN B(0)
/******************* Bit definition for RCC_MP_TZAHB6ENCLRR register ************/
/*!< This register is used to clear the peripheral clock enable bit of the corresponding
* peripheral. It shall be used to deallocate a peripheral from MPU */
#define RCC_MP_TZAHB6ENCLRR_MDMAEN B(0)
/******************* Bit definition for RCC_MC_AHB2ENSETR register ***********/
/*!< This register is used to set the peripheral clock enable bit of the corresponding
* peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
#define RCC_MC_AHB2ENSETR_DMA1EN B(0)
#define RCC_MC_AHB2ENSETR_DMA2EN B(1)
#define RCC_MC_AHB2ENSETR_DMAMUXEN B(2)
#define RCC_MC_AHB2ENSETR_ADC12EN B(5)
#define RCC_MC_AHB2ENSETR_USBOEN B(8)
#define RCC_MC_AHB2ENSETR_SDMMC3EN B(16)
/******************* Bit definition for RCC_MC_AHB2ENCLRR register ************/
/*!< This register is used to clear the peripheral clock enable bit of the corresponding
* peripheral. It shall be used to deallocate a peripheral from MCU */
#define RCC_MC_AHB2ENCLRR_DMA1EN B(0)
#define RCC_MC_AHB2ENCLRR_DMA2EN B(1)
#define RCC_MC_AHB2ENCLRR_DMAMUXEN B(2)
#define RCC_MC_AHB2ENCLRR_ADC12EN B(5)
#define RCC_MC_AHB2ENCLRR_USBOEN B(8)
#define RCC_MC_AHB2ENCLRR_SDMMC3EN B(16)
/******************* Bit definition for RCC_MC_AHB3ENSETR register ***********/
/*!< This register is used to set the peripheral clock enable bit of the corresponding
* peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
#define RCC_MC_AHB3ENSETR_DCMIEN B(0)
#define RCC_MC_AHB3ENSETR_CRYP2EN B(4)
#define RCC_MC_AHB3ENSETR_HASH2EN B(5)
#define RCC_MC_AHB3ENSETR_RNG2EN B(6)
#define RCC_MC_AHB3ENSETR_CRC2EN B(7)
#define RCC_MC_AHB3ENSETR_HSEMEN B(11)
#define RCC_MC_AHB3ENSETR_IPCCEN B(12)
/******************* Bit definition for RCC_MC_AHB3ENCLRR register ************/
/*!< This register is used to clear the peripheral clock enable bit of the corresponding
* peripheral. It shall be used to deallocate a peripheral from MCU */
#define RCC_MC_AHB3ENCLRR_DCMIEN B(0)
#define RCC_MC_AHB3ENCLRR_CRYP2EN B(4)
#define RCC_MC_AHB3ENCLRR_HASH2EN B(5)
#define RCC_MC_AHB3ENCLRR_RNG2EN B(6)
#define RCC_MC_AHB3ENCLRR_CRC2EN B(7)
#define RCC_MC_AHB3ENCLRR_HSEMEN B(11)
#define RCC_MC_AHB3ENCLRR_IPCCEN B(12)
/******************* Bit definition for RCC_MC_AHB4ENSETR register ***********/
/*!< This register is used to set the peripheral clock enable bit of the corresponding
* peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
#define RCC_MC_AHB4ENSETR_GPIOAEN B(0)
#define RCC_MC_AHB4ENSETR_GPIOBEN B(1)
#define RCC_MC_AHB4ENSETR_GPIOCEN B(2)
#define RCC_MC_AHB4ENSETR_GPIODEN B(3)
#define RCC_MC_AHB4ENSETR_GPIOEEN B(4)
#define RCC_MC_AHB4ENSETR_GPIOFEN B(5)
#define RCC_MC_AHB4ENSETR_GPIOGEN B(6)
#define RCC_MC_AHB4ENSETR_GPIOHEN B(7)
#define RCC_MC_AHB4ENSETR_GPIOIEN B(8)
#define RCC_MC_AHB4ENSETR_GPIOJEN B(9)
#define RCC_MC_AHB4ENSETR_GPIOKEN B(10)
/******************* Bit definition for RCC_MC_AHB4ENCLRR register ************/
/*!< This register is used to clear the peripheral clock enable bit of the corresponding
* peripheral. It shall be used to deallocate a peripheral from MCU */
#define RCC_MC_AHB4ENCLRR_GPIOAEN B(0)
#define RCC_MC_AHB4ENCLRR_GPIOBEN B(1)
#define RCC_MC_AHB4ENCLRR_GPIOCEN B(2)
#define RCC_MC_AHB4ENCLRR_GPIODEN B(3)
#define RCC_MC_AHB4ENCLRR_GPIOEEN B(4)
#define RCC_MC_AHB4ENCLRR_GPIOFEN B(5)
#define RCC_MC_AHB4ENCLRR_GPIOGEN B(6)
#define RCC_MC_AHB4ENCLRR_GPIOHEN B(7)
#define RCC_MC_AHB4ENCLRR_GPIOIEN B(8)
#define RCC_MC_AHB4ENCLRR_GPIOJEN B(9)
#define RCC_MC_AHB4ENCLRR_GPIOKEN B(10)
/******************* Bit definition for RCC_MC_AXIMENSETR register ***********/
/*!< This register is used to set the peripheral clock enable bit of the corresponding
* peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
#define RCC_MC_AXIMENSETR_SYSRAMEN B(0)
/******************* Bit definition for RCC_MC_AXIMENCLRR register ************/
/*!< This register is used to clear the peripheral clock enable bit of the corresponding
* peripheral. It shall be used to deallocate a peripheral from MCU */
#define RCC_MC_AXIMENCLRR_SYSRAMEN B(0)
/******************* Bit definition for RCC_MC_MLAHBENSETR register ***********/
/*!< This register is used to set the peripheral clock enable bit of the corresponding
* peripheral to 1. It shall be used to allocate a peripheral to the MCU. */
#define RCC_MC_MLAHBENSETR_RETRAMEN B(4)
/******************* Bit definition for RCC_MC_MLAHBENCLRR register ************/
/*!< This register is used to clear the peripheral clock enable bit of the corresponding
* peripheral. It shall be used to deallocate a peripheral from MCU */
#define RCC_MC_MLAHBENCLRR_RETRAMEN B(4)
/******************* Bit definition for RCC_MC_APB1LPENSETR register ***********/
/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
* peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
* CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
#define RCC_MC_APB1LPENSETR_TIM2LPEN B(0)
#define RCC_MC_APB1LPENSETR_TIM3LPEN B(1)
#define RCC_MC_APB1LPENSETR_TIM4LPEN B(2)
#define RCC_MC_APB1LPENSETR_TIM5LPEN B(3)
#define RCC_MC_APB1LPENSETR_TIM6LPEN B(4)
#define RCC_MC_APB1LPENSETR_TIM7LPEN B(5)
#define RCC_MC_APB1LPENSETR_TIM12LPEN B(6)
#define RCC_MC_APB1LPENSETR_TIM13LPEN B(7)
#define RCC_MC_APB1LPENSETR_TIM14LPEN B(8)
#define RCC_MC_APB1LPENSETR_LPTIM1LPEN B(9)
#define RCC_MC_APB1LPENSETR_SPI2LPEN B(11)
#define RCC_MC_APB1LPENSETR_SPI3LPEN B(12)
#define RCC_MC_APB1LPENSETR_USART2LPEN B(14)
#define RCC_MC_APB1LPENSETR_USART3LPEN B(15)
#define RCC_MC_APB1LPENSETR_UART4LPEN B(16)
#define RCC_MC_APB1LPENSETR_UART5LPEN B(17)
#define RCC_MC_APB1LPENSETR_UART7LPEN B(18)
#define RCC_MC_APB1LPENSETR_UART8LPEN B(19)
#define RCC_MC_APB1LPENSETR_I2C1LPEN B(21)
#define RCC_MC_APB1LPENSETR_I2C2LPEN B(22)
#define RCC_MC_APB1LPENSETR_I2C3LPEN B(23)
#define RCC_MC_APB1LPENSETR_I2C5LPEN B(24)
#define RCC_MC_APB1LPENSETR_SPDIFLPEN B(26)
#define RCC_MC_APB1LPENSETR_CECLPEN B(27)
#define RCC_MC_APB1LPENSETR_WWDG1LPEN B(28)
#define RCC_MC_APB1LPENSETR_DAC12LPEN B(29)
#define RCC_MC_APB1LPENSETR_MDIOSLPEN B(31)
/******************* Bit definition for RCC_MC_APB1LPENCLRR register ************/
/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
* peripheral. Writing '0' has no effect, reading will return the effective values of the
* corresponding bits. Writing a '1' sets the corresponding bit to '0' */
#define RCC_MC_APB1LPENCLRR_TIM2LPEN B(0)
#define RCC_MC_APB1LPENCLRR_TIM3LPEN B(1)
#define RCC_MC_APB1LPENCLRR_TIM4LPEN B(2)
#define RCC_MC_APB1LPENCLRR_TIM5LPEN B(3)
#define RCC_MC_APB1LPENCLRR_TIM6LPEN B(4)
#define RCC_MC_APB1LPENCLRR_TIM7LPEN B(5)
#define RCC_MC_APB1LPENCLRR_TIM12LPEN B(6)
#define RCC_MC_APB1LPENCLRR_TIM13LPEN B(7)
#define RCC_MC_APB1LPENCLRR_TIM14LPEN B(8)
#define RCC_MC_APB1LPENCLRR_LPTIM1LPEN B(9)
#define RCC_MC_APB1LPENCLRR_SPI2LPEN B(11)
#define RCC_MC_APB1LPENCLRR_SPI3LPEN B(12)
#define RCC_MC_APB1LPENCLRR_USART2LPEN B(14)
#define RCC_MC_APB1LPENCLRR_USART3LPEN B(15)
#define RCC_MC_APB1LPENCLRR_UART4LPEN B(16)
#define RCC_MC_APB1LPENCLRR_UART5LPEN B(17)
#define RCC_MC_APB1LPENCLRR_UART7LPEN B(18)
#define RCC_MC_APB1LPENCLRR_UART8LPEN B(19)
#define RCC_MC_APB1LPENCLRR_I2C1LPEN B(21)
#define RCC_MC_APB1LPENCLRR_I2C2LPEN B(22)
#define RCC_MC_APB1LPENCLRR_I2C3LPEN B(23)
#define RCC_MC_APB1LPENCLRR_I2C5LPEN B(24)
#define RCC_MC_APB1LPENCLRR_SPDIFLPEN B(26)
#define RCC_MC_APB1LPENCLRR_CECLPEN B(27)
#define RCC_MC_APB1LPENCLRR_WWDG1LPEN B(28)
#define RCC_MC_APB1LPENCLRR_DAC12LPEN B(29)
#define RCC_MC_APB1LPENCLRR_MDIOSLPEN B(31)
/******************* Bit definition for RCC_MC_APB2LPENSETR register ***********/
/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
* peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
* CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
#define RCC_MC_APB2LPENSETR_TIM1LPEN B(0)
#define RCC_MC_APB2LPENSETR_TIM8LPEN B(1)
#define RCC_MC_APB2LPENSETR_TIM15LPEN B(2)
#define RCC_MC_APB2LPENSETR_TIM16LPEN B(3)
#define RCC_MC_APB2LPENSETR_TIM17LPEN B(4)
#define RCC_MC_APB2LPENSETR_SPI1LPEN B(8)
#define RCC_MC_APB2LPENSETR_SPI4LPEN B(9)
#define RCC_MC_APB2LPENSETR_SPI5LPEN B(10)
#define RCC_MC_APB2LPENSETR_USART6LPEN B(13)
#define RCC_MC_APB2LPENSETR_SAI1LPEN B(16)
#define RCC_MC_APB2LPENSETR_SAI2LPEN B(17)
#define RCC_MC_APB2LPENSETR_SAI3LPEN B(18)
#define RCC_MC_APB2LPENSETR_DFSDMLPEN B(20)
#define RCC_MC_APB2LPENSETR_ADFSDMLPEN B(21)
#define RCC_MC_APB2LPENSETR_FDCANLPEN B(24)
/******************* Bit definition for RCC_MC_APB2LPENCLRR register ************/
/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
* peripheral. Writing '0' has no effect, reading will return the effective values of the
* corresponding bits. Writing a '1' sets the corresponding bit to '0' */
#define RCC_MC_APB2LPENCLRR_TIM1LPEN B(0)
#define RCC_MC_APB2LPENCLRR_TIM8LPEN B(1)
#define RCC_MC_APB2LPENCLRR_TIM15LPEN B(2)
#define RCC_MC_APB2LPENCLRR_TIM16LPEN B(3)
#define RCC_MC_APB2LPENCLRR_TIM17LPEN B(4)
#define RCC_MC_APB2LPENCLRR_SPI1LPEN B(8)
#define RCC_MC_APB2LPENCLRR_SPI4LPEN B(9)
#define RCC_MC_APB2LPENCLRR_SPI5LPEN B(10)
#define RCC_MC_APB2LPENCLRR_USART6LPEN B(13)
#define RCC_MC_APB2LPENCLRR_SAI1LPEN B(16)
#define RCC_MC_APB2LPENCLRR_SAI2LPEN B(17)
#define RCC_MC_APB2LPENCLRR_SAI3LPEN B(18)
#define RCC_MC_APB2LPENCLRR_DFSDMLPEN B(20)
#define RCC_MC_APB2LPENCLRR_ADFSDMLPEN B(21)
#define RCC_MC_APB2LPENCLRR_FDCANLPEN B(24)
/******************* Bit definition for RCC_MC_APB3LPENSETR register ***********/
/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
* peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
* CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
#define RCC_MC_APB3LPENSETR_LPTIM2LPEN B(0)
#define RCC_MC_APB3LPENSETR_LPTIM3LPEN B(1)
#define RCC_MC_APB3LPENSETR_LPTIM4LPEN B(2)
#define RCC_MC_APB3LPENSETR_LPTIM5LPEN B(3)
#define RCC_MC_APB3LPENSETR_SAI4LPEN B(8)
#define RCC_MC_APB3LPENSETR_SYSCFGLPEN B(11)
#define RCC_MC_APB3LPENSETR_VREFLPEN B(13)
#define RCC_MC_APB3LPENSETR_DTSLPEN B(16)
#define RCC_MC_APB3LPENSETR_PMBCTRLLPEN B(17)
/******************* Bit definition for RCC_MC_APB3LPENCLRR register ************/
/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
* peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
* CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
#define RCC_MC_APB3LPENCLRR_LPTIM2LPEN B(0)
#define RCC_MC_APB3LPENCLRR_LPTIM3LPEN B(1)
#define RCC_MC_APB3LPENCLRR_LPTIM4LPEN B(2)
#define RCC_MC_APB3LPENCLRR_LPTIM5LPEN B(3)
#define RCC_MC_APB3LPENCLRR_SAI4LPEN B(8)
#define RCC_MC_APB3LPENCLRR_SYSCFGLPEN B(11)
#define RCC_MC_APB3LPENCLRR_VREFLPEN B(13)
#define RCC_MC_APB3LPENCLRR_DTSLPEN B(16)
#define RCC_MC_APB3LPENCLRR_PMBCTRLLPEN B(17)
/******************* Bit definition for RCC_MC_APB4LPENSETR register ***********/
/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
* peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
* CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
#define RCC_MC_APB4LPENSETR_LTDCLPEN B(0)
#define RCC_MC_APB4LPENSETR_DSILPEN B(4)
#define RCC_MC_APB4LPENSETR_USBPHYLPEN B(16)
#define RCC_MC_APB4LPENSETR_STGENROLPEN B(20)
#define RCC_MC_APB4LPENSETR_STGENROSTPEN B(21)
/******************* Bit definition for RCC_MP_APB4LPENSETR register ***********/
/*!< This register is used by the MPU in order to set the PERxLPEN bit of the corresponding
* peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
* CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
#define RCC_MP_APB4LPENSETR_LTDCLPEN B(0)
#define RCC_MP_APB4LPENSETR_DSILPEN B(4)
#define RCC_MP_APB4LPENSETR_IWDG2APBLPEN B(15)
#define RCC_MP_APB4LPENSETR_USBPHYLPEN B(16)
#define RCC_MP_APB4LPENSETR_STGENROLPEN B(20)
#define RCC_MP_APB4LPENSETR_STGENROSTPEN B(21)
/******************* Bit definition for RCC_MC_APB4LPENCLRR register ************/
/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
* peripheral. Writing '0' has no effect, reading will return the effective values of the
* corresponding bits. Writing a '1' sets the corresponding bit to '0' */
#define RCC_MC_APB4LPENCLRR_LTDCLPEN B(0)
#define RCC_MC_APB4LPENCLRR_DSILPEN B(4)
#define RCC_MC_APB4LPENCLRR_USBPHYLPEN B(16)
#define RCC_MC_APB4LPENCLRR_STGENROLPEN B(20)
#define RCC_MC_APB4LPENCLRR_STGENROSTPEN B(21)
/******************* Bit definition for RCC_MP_APB4LPENCLRR register ************/
/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
* peripheral. Writing '0' has no effect, reading will return the effective values of the
* corresponding bits. Writing a '1' sets the corresponding bit to '0' */
#define RCC_MP_APB4LPENCLRR_LTDCLPEN B(0)
#define RCC_MP_APB4LPENCLRR_DSILPEN B(4)
#define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN B(15)
#define RCC_MP_APB4LPENCLRR_USBPHYLPEN B(16)
#define RCC_MP_APB4LPENCLRR_STGENROLPEN B(20)
#define RCC_MP_APB4LPENCLRR_STGENROSTPEN B(21)
/******************* Bit definition for RCC_MC_APB5LPENSETR register ***********/
/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
* peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
* CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
#define RCC_MC_APB5LPENSETR_SPI6LPEN B(0)
#define RCC_MC_APB5LPENSETR_I2C4LPEN B(2)
#define RCC_MC_APB5LPENSETR_I2C6LPEN B(3)
#define RCC_MC_APB5LPENSETR_USART1LPEN B(4)
#define RCC_MC_APB5LPENSETR_RTCAPBLPEN B(8)
#define RCC_MC_APB5LPENSETR_TZC1LPEN B(11)
#define RCC_MC_APB5LPENSETR_TZC2LPEN B(12)
#define RCC_MC_APB5LPENSETR_TZPCLPEN B(13)
#define RCC_MC_APB5LPENSETR_BSECLPEN B(16)
#define RCC_MC_APB5LPENSETR_STGENLPEN B(20)
#define RCC_MC_APB5LPENSETR_STGENSTPEN B(21)
/******************* Bit definition for RCC_MC_APB5LPENCLRR register ************/
/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
* peripheral. Writing '0' has no effect, reading will return the effective values of the
* corresponding bits. Writing a '1' sets the corresponding bit to '0' */
#define RCC_MC_APB5LPENCLRR_SPI6LPEN B(0)
#define RCC_MC_APB5LPENCLRR_I2C4LPEN B(2)
#define RCC_MC_APB5LPENCLRR_I2C6LPEN B(3)
#define RCC_MC_APB5LPENCLRR_USART1LPEN B(4)
#define RCC_MC_APB5LPENCLRR_RTCAPBLPEN B(8)
#define RCC_MC_APB5LPENCLRR_TZC1LPEN B(11)
#define RCC_MC_APB5LPENCLRR_TZC2LPEN B(12)
#define RCC_MC_APB5LPENCLRR_TZPCLPEN B(13)
#define RCC_MC_APB5LPENCLRR_BSECLPEN B(16)
#define RCC_MC_APB5LPENCLRR_STGENLPEN B(20)
#define RCC_MC_APB5LPENCLRR_STGENSTPEN B(21)
/******************* Bit definition for RCC_MC_AHB5LPENSETR register ***********/
/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
* peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
* CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
#define RCC_MC_AHB5LPENSETR_GPIOZLPEN B(0)
#define RCC_MC_AHB5LPENSETR_CRYP1LPEN B(4)
#define RCC_MC_AHB5LPENSETR_HASH1LPEN B(5)
#define RCC_MC_AHB5LPENSETR_RNG1LPEN B(6)
#define RCC_MC_AHB5LPENSETR_BKPSRAMLPEN B(8)
/******************* Bit definition for RCC_MC_AHB5LPENCLRR register ************/
/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
* peripheral. Writing '0' has no effect, reading will return the effective values of the
* corresponding bits. Writing a '1' sets the corresponding bit to '0' */
#define RCC_MC_AHB5LPENCLRR_GPIOZLPEN B(0)
#define RCC_MC_AHB5LPENCLRR_CRYP1LPEN B(4)
#define RCC_MC_AHB5LPENCLRR_HASH1LPEN B(5)
#define RCC_MC_AHB5LPENCLRR_RNG1LPEN B(6)
#define RCC_MC_AHB5LPENCLRR_BKPSRAMLPEN B(8)
/******************* Bit definition for RCC_MC_AHB6LPENSETR register ***********/
/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
* peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
* CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
#define RCC_MC_AHB6LPENSETR_MDMALPEN B(0)
#define RCC_MC_AHB6LPENSETR_GPULPEN B(5)
#define RCC_MC_AHB6LPENSETR_ETHCKLPEN B(7)
#define RCC_MC_AHB6LPENSETR_ETHTXLPEN B(8)
#define RCC_MC_AHB6LPENSETR_ETHRXLPEN B(9)
#define RCC_MC_AHB6LPENSETR_ETHMACLPEN B(10)
#define RCC_MC_AHB6LPENSETR_ETHSTPEN B(11)
#define RCC_MC_AHB6LPENSETR_FMCLPEN B(12)
#define RCC_MC_AHB6LPENSETR_QSPILPEN B(14)
#define RCC_MC_AHB6LPENSETR_SDMMC1LPEN B(16)
#define RCC_MC_AHB6LPENSETR_SDMMC2LPEN B(17)
#define RCC_MC_AHB6LPENSETR_CRC1LPEN B(20)
#define RCC_MC_AHB6LPENSETR_USBHLPEN B(24)
/******************* Bit definition for RCC_MC_AHB6LPENCLRR register ************/
/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
* peripheral. Writing '0' has no effect, reading will return the effective values of the
* corresponding bits. Writing a '1' sets the corresponding bit to '0' */
#define RCC_MC_AHB6LPENCLRR_MDMALPEN B(0)
#define RCC_MC_AHB6LPENCLRR_GPULPEN B(5)
#define RCC_MC_AHB6LPENCLRR_ETHCKLPEN B(7)
#define RCC_MC_AHB6LPENCLRR_ETHTXLPEN B(8)
#define RCC_MC_AHB6LPENCLRR_ETHRXLPEN B(9)
#define RCC_MC_AHB6LPENCLRR_ETHMACLPEN B(10)
#define RCC_MC_AHB6LPENCLRR_ETHSTPEN B(11)
#define RCC_MC_AHB6LPENCLRR_FMCLPEN B(12)
#define RCC_MC_AHB6LPENCLRR_QSPILPEN B(14)
#define RCC_MC_AHB6LPENCLRR_SDMMC1LPEN B(16)
#define RCC_MC_AHB6LPENCLRR_SDMMC2LPEN B(17)
#define RCC_MC_AHB6LPENCLRR_CRC1LPEN B(20)
#define RCC_MC_AHB6LPENCLRR_USBHLPEN B(24)
/******************* Bit definition for RCC_MP_TZAHB6LPENSETR register ***********/
/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
* peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
* CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
#define RCC_MP_TZAHB6LPENSETR_MDMALPEN B(0)
/******************* Bit definition for RCC_MP_TZAHB6LPENCLRR register ************/
/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
* peripheral. Writing '0' has no effect, reading will return the effective values of the
* corresponding bits. Writing a '1' sets the corresponding bit to '0' */
#define RCC_MC_TZAHB6LPENCLRR_MDMALPEN B(0)
/******************* Bit definition for RCC_MC_AHB2LPENSETR register ***********/
/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
* peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
* CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
#define RCC_MC_AHB2LPENSETR_DMA1LPEN B(0)
#define RCC_MC_AHB2LPENSETR_DMA2LPEN B(1)
#define RCC_MC_AHB2LPENSETR_DMAMUXLPEN B(2)
#define RCC_MC_AHB2LPENSETR_ADC12LPEN B(5)
#define RCC_MC_AHB2LPENSETR_USBOLPEN B(8)
#define RCC_MC_AHB2LPENSETR_SDMMC3LPEN B(16)
/******************* Bit definition for RCC_MC_AHB2LPENCLRR register ************/
/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
* peripheral. Writing '0' has no effect, reading will return the effective values of the
* corresponding bits. Writing a '1' sets the corresponding bit to '0' */
#define RCC_MC_AHB2LPENCLRR_DMA1LPEN B(0)
#define RCC_MC_AHB2LPENCLRR_DMA2LPEN B(1)
#define RCC_MC_AHB2LPENCLRR_DMAMUXLPEN B(2)
#define RCC_MC_AHB2LPENCLRR_ADC12LPEN B(5)
#define RCC_MC_AHB2LPENCLRR_USBOLPEN B(8)
#define RCC_MC_AHB2LPENCLRR_SDMMC3LPEN B(16)
/******************* Bit definition for RCC_MC_AHB3LPENSETR register ***********/
/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
* peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
* CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
#define RCC_MC_AHB3LPENSETR_DCMILPEN B(0)
#define RCC_MC_AHB3LPENSETR_CRYP2LPEN B(4)
#define RCC_MC_AHB3LPENSETR_HASH2LPEN B(5)
#define RCC_MC_AHB3LPENSETR_RNG2LPEN B(6)
#define RCC_MC_AHB3LPENSETR_CRC2LPEN B(7)
#define RCC_MC_AHB3LPENSETR_HSEMLPEN B(11)
#define RCC_MC_AHB3LPENSETR_IPCCLPEN B(12)
/******************* Bit definition for RCC_MC_AHB3LPENCLRR register ************/
/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
* peripheral. Writing '0' has no effect, reading will return the effective values of the
* corresponding bits. Writing a '1' sets the corresponding bit to '0' */
#define RCC_MC_AHB3LPENCLRR_DCMILPEN B(0)
#define RCC_MC_AHB3LPENCLRR_CRYP2LPEN B(4)
#define RCC_MC_AHB3LPENCLRR_HASH2LPEN B(5)
#define RCC_MC_AHB3LPENCLRR_RNG2LPEN B(6)
#define RCC_MC_AHB3LPENCLRR_CRC2LPEN B(7)
#define RCC_MC_AHB3LPENCLRR_HSEMLPEN B(11)
#define RCC_MC_AHB3LPENCLRR_IPCCLPEN B(12)
/******************* Bit definition for RCC_MC_AHB4LPENSETR register ***********/
/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
* peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
* CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
#define RCC_MC_AHB4LPENSETR_GPIOALPEN B(0)
#define RCC_MC_AHB4LPENSETR_GPIOBLPEN B(1)
#define RCC_MC_AHB4LPENSETR_GPIOCLPEN B(2)
#define RCC_MC_AHB4LPENSETR_GPIODLPEN B(3)
#define RCC_MC_AHB4LPENSETR_GPIOELPEN B(4)
#define RCC_MC_AHB4LPENSETR_GPIOFLPEN B(5)
#define RCC_MC_AHB4LPENSETR_GPIOGLPEN B(6)
#define RCC_MC_AHB4LPENSETR_GPIOHLPEN B(7)
#define RCC_MC_AHB4LPENSETR_GPIOILPEN B(8)
#define RCC_MC_AHB4LPENSETR_GPIOJLPEN B(9)
#define RCC_MC_AHB4LPENSETR_GPIOKLPEN B(10)
/******************* Bit definition for RCC_MC_AHB4LPENCLRR register ************/
/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
* peripheral. Writing '0' has no effect, reading will return the effective values of the
* corresponding bits. Writing a '1' sets the corresponding bit to '0' */
#define RCC_MC_AHB4LPENCLRR_GPIOALPEN B(0)
#define RCC_MC_AHB4LPENCLRR_GPIOBLPEN B(1)
#define RCC_MC_AHB4LPENCLRR_GPIOCLPEN B(2)
#define RCC_MC_AHB4LPENCLRR_GPIODLPEN B(3)
#define RCC_MC_AHB4LPENCLRR_GPIOELPEN B(4)
#define RCC_MC_AHB4LPENCLRR_GPIOFLPEN B(5)
#define RCC_MC_AHB4LPENCLRR_GPIOGLPEN B(6)
#define RCC_MC_AHB4LPENCLRR_GPIOHLPEN B(7)
#define RCC_MC_AHB4LPENCLRR_GPIOILPEN B(8)
#define RCC_MC_AHB4LPENCLRR_GPIOJLPEN B(9)
#define RCC_MC_AHB4LPENCLRR_GPIOKLPEN B(10)
/******************* Bit definition for RCC_MC_AXIMLPENSETR register ***********/
/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
* peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
* CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
#define RCC_MC_AXIMLPENSETR_SYSRAMLPEN B(0)
/******************* Bit definition for RCC_MC_AXIMLPENCLRR register ************/
/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
* peripheral. Writing '0' has no effect, reading will return the effective values of the
* corresponding bits. Writing a '1' sets the corresponding bit to '0' */
#define RCC_MC_AXIMLPENCLRR_SYSRAMLPEN B(0)
/******************* Bit definition for RCC_MC_MLAHBLPENSETR register ***********/
/*!< This register is used by the MCU in order to set the PERxLPEN bit of the corresponding
* peripheral to '1'. Writing '0' has no effect, writing '1' enables the peripheral clocks in
* CSLEEP, reading '1' means that the peripheral clocks are enabled in CSLEEP */
#define RCC_MC_MLAHBLPENSETR_SRAM1LPEN B(0)
#define RCC_MC_MLAHBLPENSETR_SRAM2LPEN B(1)
#define RCC_MC_MLAHBLPENSETR_SRAM3LPEN B(2)
#define RCC_MC_MLAHBLPENSETR_RETRAMLPEN B(4)
/******************* Bit definition for RCC_MC_MLAHBLPENCLRR register ************/
/*!< This register is used by the MCU in order to clear the PERxLPEN bits of the corresponding
* peripheral. Writing '0' has no effect, reading will return the effective values of the
* corresponding bits. Writing a '1' sets the corresponding bit to '0' */
#define RCC_MC_MLAHBLPENCLRR_SRAM1LPEN B(0)
#define RCC_MC_MLAHBLPENCLRR_SRAM2LPEN B(1)
#define RCC_MC_MLAHBLPENCLRR_SRAM3LPEN B(2)
#define RCC_MC_MLAHBLPENCLRR_RETRAMLPEN B(4)
/******************* Bit definition for RCC_BR_RSTSCLRR register ************/
/*!< This register is used by the BOOTROM to check the reset source.
* Writing "0" has no effect, reading will return the effective values of the corresponding
* bits. Writing a '1' clears the corresponding bit to '0'
*
* @note In order to identify the reset source, the MPU application must use
* RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application
* must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR).
* @note This register except MPUP[1:0]RSTF flags is located into VDD domain,
* and is reset by por_rst reset.
* @note If TZEN = '1', this register can only be modified in secure mode.
*/
#define RCC_BR_RSTSCLRR_PORRSTF_Pos (0U)
#define RCC_BR_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */
#define RCC_BR_RSTSCLRR_PORRSTF RCC_BR_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/
#define RCC_BR_RSTSCLRR_BORRSTF_Pos (1U)
#define RCC_BR_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */
#define RCC_BR_RSTSCLRR_BORRSTF RCC_BR_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/
#define RCC_BR_RSTSCLRR_PADRSTF_Pos (2U)
#define RCC_BR_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */
#define RCC_BR_RSTSCLRR_PADRSTF RCC_BR_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/
#define RCC_BR_RSTSCLRR_HCSSRSTF_Pos (3U)
#define RCC_BR_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */
#define RCC_BR_RSTSCLRR_HCSSRSTF RCC_BR_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/
#define RCC_BR_RSTSCLRR_VCORERSTF_Pos (4U)
#define RCC_BR_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_BR_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */
#define RCC_BR_RSTSCLRR_VCORERSTF RCC_BR_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/
#define RCC_BR_RSTSCLRR_MPSYSRSTF_Pos (6U)
#define RCC_BR_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */
#define RCC_BR_RSTSCLRR_MPSYSRSTF RCC_BR_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/
#define RCC_BR_RSTSCLRR_MCSYSRSTF_Pos (7U)
#define RCC_BR_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */
#define RCC_BR_RSTSCLRR_MCSYSRSTF RCC_BR_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/
#define RCC_BR_RSTSCLRR_IWDG1RSTF_Pos (8U)
#define RCC_BR_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */
#define RCC_BR_RSTSCLRR_IWDG1RSTF RCC_BR_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/
#define RCC_BR_RSTSCLRR_IWDG2RSTF_Pos (9U)
#define RCC_BR_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */
#define RCC_BR_RSTSCLRR_IWDG2RSTF RCC_BR_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/
#define RCC_BR_RSTSCLRR_MPUP0RSTF_Pos (13U)
#define RCC_BR_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */
#define RCC_BR_RSTSCLRR_MPUP0RSTF RCC_BR_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/
#define RCC_BR_RSTSCLRR_MPUP1RSTF_Pos (14U)
#define RCC_BR_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_BR_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */
#define RCC_BR_RSTSCLRR_MPUP1RSTF RCC_BR_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/
/******************* Bit definition for RCC_MC_RSTSCLRR register ************/
/*!< This register is used by the MCU to check the reset source.
* Writing "0" has no effect, reading will return the effective values of the corresponding
* bits. Writing a "1" clears the corresponding bit to 0
* @note This register is located into VDD domain, and is reset by rst_por reset.
*/
#define RCC_MC_RSTSCLRR_PORRSTF_Pos (0U)
#define RCC_MC_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */
#define RCC_MC_RSTSCLRR_PORRSTF RCC_MC_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/
#define RCC_MC_RSTSCLRR_BORRSTF_Pos (1U)
#define RCC_MC_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */
#define RCC_MC_RSTSCLRR_BORRSTF RCC_MC_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/
#define RCC_MC_RSTSCLRR_PADRSTF_Pos (2U)
#define RCC_MC_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */
#define RCC_MC_RSTSCLRR_PADRSTF RCC_MC_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/
#define RCC_MC_RSTSCLRR_HCSSRSTF_Pos (3U)
#define RCC_MC_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */
#define RCC_MC_RSTSCLRR_HCSSRSTF RCC_MC_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/
#define RCC_MC_RSTSCLRR_VCORERSTF_Pos (4U)
#define RCC_MC_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MC_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */
#define RCC_MC_RSTSCLRR_VCORERSTF RCC_MC_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/
#define RCC_MC_RSTSCLRR_MCURSTF_Pos (5U)
#define RCC_MC_RSTSCLRR_MCURSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCURSTF_Pos) /*!< 0x00000080 */
#define RCC_MC_RSTSCLRR_MCURSTF RCC_MC_RSTSCLRR_MCURSTF_Msk /*MCU reset flag*/
#define RCC_MC_RSTSCLRR_MPSYSRSTF_Pos (6U)
#define RCC_MC_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */
#define RCC_MC_RSTSCLRR_MPSYSRSTF RCC_MC_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/
#define RCC_MC_RSTSCLRR_MCSYSRSTF_Pos (7U)
#define RCC_MC_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MC_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */
#define RCC_MC_RSTSCLRR_MCSYSRSTF RCC_MC_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/
#define RCC_MC_RSTSCLRR_IWDG1RSTF_Pos (8U)
#define RCC_MC_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */
#define RCC_MC_RSTSCLRR_IWDG1RSTF RCC_MC_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/
#define RCC_MC_RSTSCLRR_IWDG2RSTF_Pos (9U)
#define RCC_MC_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */
#define RCC_MC_RSTSCLRR_IWDG2RSTF RCC_MC_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/
#define RCC_MC_RSTSCLRR_WWDG1RSTF_Pos (10U)
#define RCC_MC_RSTSCLRR_WWDG1RSTF_Msk (0x1U << RCC_MC_RSTSCLRR_WWDG1RSTF_Pos) /*!< 0x00000200 */
#define RCC_MC_RSTSCLRR_WWDG1RSTF RCC_MC_RSTSCLRR_WWDG1RSTF_Msk /*WWDG1 reset flag*/
/******************* Bit definition for RCC_MP_RSTSCLRR register ************/
/*!< This register is used by the MPU to check the reset source. This register is updated
* by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or
* exit from STANDBY or CSTANDBY.
*
* @note Writing '0' has no effect, reading will return the effective values of
* the corresponding bits. Writing a '1' clears the corresponding bit to '0'.
* @note The register is located in VDD_CORE.
* @note If TZEN = '1', this register can only be modified in secure mode.
*/
#define RCC_MP_RSTSCLRR_PORRSTF_Pos (0U)
#define RCC_MP_RSTSCLRR_PORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PORRSTF_Pos) /*!< 0x00000001 */
#define RCC_MP_RSTSCLRR_PORRSTF RCC_MP_RSTSCLRR_PORRSTF_Msk /*POR/PDR reset flag*/
#define RCC_MP_RSTSCLRR_BORRSTF_Pos (1U)
#define RCC_MP_RSTSCLRR_BORRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_BORRSTF_Pos) /*!< 0x00000002 */
#define RCC_MP_RSTSCLRR_BORRSTF RCC_MP_RSTSCLRR_BORRSTF_Msk /*BOR reset flag*/
#define RCC_MP_RSTSCLRR_PADRSTF_Pos (2U)
#define RCC_MP_RSTSCLRR_PADRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_PADRSTF_Pos) /*!< 0x00000004 */
#define RCC_MP_RSTSCLRR_PADRSTF RCC_MP_RSTSCLRR_PADRSTF_Msk /*NRST reset flag*/
#define RCC_MP_RSTSCLRR_HCSSRSTF_Pos (3U)
#define RCC_MP_RSTSCLRR_HCSSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_HCSSRSTF_Pos) /*!< 0x00000008 */
#define RCC_MP_RSTSCLRR_HCSSRSTF RCC_MP_RSTSCLRR_HCSSRSTF_Msk /*HSE CSS reset flag*/
#define RCC_MP_RSTSCLRR_VCORERSTF_Pos (4U)
#define RCC_MP_RSTSCLRR_VCORERSTF_Msk (0x1U << RCC_MP_RSTSCLRR_VCORERSTF_Pos) /*!< 0x00000010 */
#define RCC_MP_RSTSCLRR_VCORERSTF RCC_MP_RSTSCLRR_VCORERSTF_Msk /*VDDCORE reset flag*/
#define RCC_MP_RSTSCLRR_MPSYSRSTF_Pos (6U)
#define RCC_MP_RSTSCLRR_MPSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPSYSRSTF_Pos) /*!< 0x00000040 */
#define RCC_MP_RSTSCLRR_MPSYSRSTF RCC_MP_RSTSCLRR_MPSYSRSTF_Msk /*MPU System reset flag*/
#define RCC_MP_RSTSCLRR_MCSYSRSTF_Pos (7U)
#define RCC_MP_RSTSCLRR_MCSYSRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MCSYSRSTF_Pos) /*!< 0x00000080 */
#define RCC_MP_RSTSCLRR_MCSYSRSTF RCC_MP_RSTSCLRR_MCSYSRSTF_Msk /*MCU System reset flag*/
#define RCC_MP_RSTSCLRR_IWDG1RSTF_Pos (8U)
#define RCC_MP_RSTSCLRR_IWDG1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG1RSTF_Pos) /*!< 0x00000100 */
#define RCC_MP_RSTSCLRR_IWDG1RSTF RCC_MP_RSTSCLRR_IWDG1RSTF_Msk /*IWDG1 reset flag*/
#define RCC_MP_RSTSCLRR_IWDG2RSTF_Pos (9U)
#define RCC_MP_RSTSCLRR_IWDG2RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_IWDG2RSTF_Pos) /*!< 0x00000200 */
#define RCC_MP_RSTSCLRR_IWDG2RSTF RCC_MP_RSTSCLRR_IWDG2RSTF_Msk /*IWDG2 reset flag*/
#define RCC_MP_RSTSCLRR_STDBYRSTF_Pos (11U)
#define RCC_MP_RSTSCLRR_STDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_STDBYRSTF_Pos) /*!< 0x00000800 */
#define RCC_MP_RSTSCLRR_STDBYRSTF RCC_MP_RSTSCLRR_STDBYRSTF_Msk /*System Standby reset flag*/
#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos (12U)
#define RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk (0x1U << RCC_MP_RSTSCLRR_CSTDBYRSTF_Pos) /*!< 0x00001000 */
#define RCC_MP_RSTSCLRR_CSTDBYRSTF RCC_MP_RSTSCLRR_CSTDBYRSTF_Msk /*MPU CStandby reset flag*/
#define RCC_MP_RSTSCLRR_MPUP0RSTF_Pos (13U)
#define RCC_MP_RSTSCLRR_MPUP0RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP0RSTF_Pos) /*!< 0x00002000 */
#define RCC_MP_RSTSCLRR_MPUP0RSTF RCC_MP_RSTSCLRR_MPUP0RSTF_Msk /*MPU processor 0 reset flag*/
#define RCC_MP_RSTSCLRR_MPUP1RSTF_Pos (14U)
#define RCC_MP_RSTSCLRR_MPUP1RSTF_Msk (0x1U << RCC_MP_RSTSCLRR_MPUP1RSTF_Pos) /*!< 0x00004000 */
#define RCC_MP_RSTSCLRR_MPUP1RSTF RCC_MP_RSTSCLRR_MPUP1RSTF_Msk /*MPU processor 1 reset flag*/
#define RCC_MP_RSTSCLRR_SPARE_Pos (15U)
#define RCC_MP_RSTSCLRR_SPARE_Msk (0x1U << RCC_MP_RSTSCLRR_SPARE_Pos) /*!< 0x00008000 */
#define RCC_MP_RSTSCLRR_SPARE RCC_MP_RSTSCLRR_SPARE_Msk /*Spare bits*/
/******************* Bit definition for RCC_MP_IWDGFZSETR register ************/
/*!< This register is used by the MPU in order to freeze the IWDGs clocks.
* After a system reset or STANDBY reset (nreset), or a CSTANDBY reset (rst_cstby)
* the MPU is allowed to write it once.
* Writing "0" has no effect, reading will return the effective values of the corresponding
* bits. Writing a "1" sets the corresponding bit to 1. If TZEN = 1, this register can only be
* modified in secure mode.
*/
#define RCC_MP_IWDGFZSETR_FZ_IWDG1 B(0)
#define RCC_MP_IWDGFZSETR_FZ_IWDG2 B(1)
/******************* Bit definition for RCC_MP_IWDGFZCLRR register ************/
/*!< This register is used by the MPU in order to unfreeze the IWDGs clocks.
* Writing "0" has no effect, reading will return the effective values of the corresponding
* bits. Writing a "1" clears the corresponding bit to 0. If TZEN = 1, this register can only
* be modified in secure mode.
*/
#define RCC_MP_IWDGFZCLRR_FZ_IWDG1 B(0)
#define RCC_MP_IWDGFZCLRR_FZ_IWDG2 B(1)
/******************* Bit definition for RCC_VERR register ************/
/*!< This register gives the IP version. */
#define RCC_VERR_MINREV_Pos (0U)
#define RCC_VERR_MINREV_Msk (0xFU << RCC_VERR_MINREV_Pos) /*!< 0x0000000F */
#define RCC_VERR_MINREV RCC_VERR_MINREV_Msk
#define RCC_VERR_MAJREV_Pos (4U)
#define RCC_VERR_MAJREV_Msk (0xFU << RCC_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define RCC_VERR_MAJREV RCC_VERR_MAJREV_Msk
/******************* Bit definition for RCC_IDR register ************/
/*!< This register gives the unique identifier of the RCC */
#define RCC_VERR_ID_Pos (0U)
#define RCC_VERR_ID_Msk (0xFFFFFFFFU << RCC_VERR_ID_Pos) /*!< 0xFFFFFFFF */
#define RCC_VERR_ID RCC_VERR_ID_Msk
/******************* Bit definition for RCC_IDR register ************/
/*!< This register gives the decoding space, which is for the RCC of 4 kB */
#define RCC_VERR_SIDR_Pos (0U)
#define RCC_VERR_SIDR_Msk (0xFFFFFFFFU << RCC_VERR_SIDR_Pos) /*!< 0xFFFFFFFF */
#define RCC_VERR_SIDR RCC_VERR_SIDR_Msk
/******************************************************************************/
/* */
/* RNG */
/* */
/******************************************************************************/
/******************** Bits definition for RNG_CR register *******************/
#define RNG_CR_RNGEN_Pos (2U)
#define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
#define RNG_CR_IE_Pos (3U)
#define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
#define RNG_CR_IE RNG_CR_IE_Msk
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1U << RNG_CR_CED_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_CED_Msk
/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
#define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
#define RNG_SR_DRDY RNG_SR_DRDY_Msk
#define RNG_SR_CECS_Pos (1U)
#define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
#define RNG_SR_CECS RNG_SR_CECS_Msk
#define RNG_SR_SECS_Pos (2U)
#define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
#define RNG_SR_SECS RNG_SR_SECS_Msk
#define RNG_SR_CEIS_Pos (5U)
#define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
#define RNG_SR_CEIS RNG_SR_CEIS_Msk
#define RNG_SR_SEIS_Pos (6U)
#define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
#define RNG_SR_SEIS RNG_SR_SEIS_Msk
/********************** Bit definition for RNG_VERR register *****************/
#define RNG_VERR_MINREV_Pos (0U)
#define RNG_VERR_MINREV_Msk (0xFU << RNG_VERR_MINREV_Pos) /*!< 0x0000000F */
#define RNG_VERR_MINREV RNG_VERR_MINREV_Msk /*!< Minor Revision number */
#define RNG_VERR_MAJREV_Pos (4U)
#define RNG_VERR_MAJREV_Msk (0xFU << RNG_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define RNG_VERR_MAJREV RNG_VERR_MAJREV_Msk /*!< Major Revision number */
/********************** Bit definition for RNG_IPIDR register ****************/
#define RNG_IPIDR_ID_Pos (0U)
#define RNG_IPIDR_ID_Msk (0xFFFFFFFFU << RNG_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
#define RNG_IPIDR_ID RNG_IPIDR_ID_Msk /*!< IP Identification */
/********************** Bit definition for RNG_SIDR register *****************/
#define RNG_SIDR_SID_Pos (0U)
#define RNG_SIDR_SID_Msk (0xFFFFFFFFU << RNG_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define RNG_SIDR_SID RNG_SIDR_SID_Msk /*!< IP size identification */
/******************************************************************************/
/* */
/* Real-Time Clock (RTC) */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions
*/
/******************** Bits definition for RTC_TR register *******************/
#define RTC_TR_PM_Pos (22U)
#define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
#define RTC_TR_PM RTC_TR_PM_Msk
#define RTC_TR_HT_Pos (20U)
#define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
#define RTC_TR_HT RTC_TR_HT_Msk
#define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
#define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
#define RTC_TR_HU_Pos (16U)
#define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
#define RTC_TR_HU RTC_TR_HU_Msk
#define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
#define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
#define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
#define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
#define RTC_TR_MNT_Pos (12U)
#define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
#define RTC_TR_MNT RTC_TR_MNT_Msk
#define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
#define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
#define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
#define RTC_TR_MNU_Pos (8U)
#define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_TR_MNU RTC_TR_MNU_Msk
#define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
#define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
#define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
#define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
#define RTC_TR_ST_Pos (4U)
#define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
#define RTC_TR_ST RTC_TR_ST_Msk
#define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
#define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
#define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
#define RTC_TR_SU_Pos (0U)
#define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
#define RTC_TR_SU RTC_TR_SU_Msk
#define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
#define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
#define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
#define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_DR register *******************/
#define RTC_DR_YT_Pos (20U)
#define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
#define RTC_DR_YT RTC_DR_YT_Msk
#define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
#define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
#define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
#define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
#define RTC_DR_YU_Pos (16U)
#define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
#define RTC_DR_YU RTC_DR_YU_Msk
#define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
#define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
#define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
#define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
#define RTC_DR_WDU_Pos (13U)
#define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
#define RTC_DR_WDU RTC_DR_WDU_Msk
#define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
#define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
#define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
#define RTC_DR_MT_Pos (12U)
#define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
#define RTC_DR_MT RTC_DR_MT_Msk
#define RTC_DR_MU_Pos (8U)
#define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
#define RTC_DR_MU RTC_DR_MU_Msk
#define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
#define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
#define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
#define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
#define RTC_DR_DT_Pos (4U)
#define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
#define RTC_DR_DT RTC_DR_DT_Msk
#define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
#define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
#define RTC_DR_DU_Pos (0U)
#define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
#define RTC_DR_DU RTC_DR_DU_Msk
#define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
#define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
#define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
#define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_SSR register ******************/
#define RTC_SSR_SS_Pos (0U)
#define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
#define RTC_SSR_SS RTC_SSR_SS_Msk
/**************** Bits definition for RTC_ICSR (RTC_ISR) register *************/
#define RTC_ICSR_RECALPF_Pos (16U)
#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */
#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk
#define RTC_ICSR_INIT_Pos (7U)
#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */
#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk
#define RTC_ICSR_INITF_Pos (6U)
#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */
#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk
#define RTC_ICSR_RSF_Pos (5U)
#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */
#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk
#define RTC_ICSR_INITS_Pos (4U)
#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */
#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk
#define RTC_ICSR_SHPF_Pos (3U)
#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */
#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk
#define RTC_ICSR_WUTWF_Pos (2U)
#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */
#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk
#define RTC_ICSR_ALRBWF_Pos (1U)
#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */
#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk
#define RTC_ICSR_ALRAWF_Pos (0U)
#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */
#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk
/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A_Pos (16U)
#define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
#define RTC_PRER_PREDIV_S_Pos (0U)
#define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
/******************** Bits definition for RTC_WUTR register *****************/
#define RTC_WUTR_WUT_Pos (0U)
#define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
/******************** Bits definition for RTC_CR register *******************/
#define RTC_CR_OUT2EN_Pos (31U)
#define RTC_CR_OUT2EN_Msk (0x1U << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */
#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk
#define RTC_CR_TAMPALRM_TYPE_Pos (30U)
#define RTC_CR_TAMPALRM_TYPE_Msk (0x1U << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */
#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk
#define RTC_CR_TAMPALRM_PU_Pos (29U)
#define RTC_CR_TAMPALRM_PU_Msk (0x1U << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */
#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk
#define RTC_CR_TAMPOE_Pos (26U)
#define RTC_CR_TAMPOE_Msk (0x1U << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */
#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk
#define RTC_CR_TAMPTS_Pos (25U)
#define RTC_CR_TAMPTS_Msk (0x1U << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */
#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk
#define RTC_CR_ITSE_Pos (24U)
#define RTC_CR_ITSE_Msk (0x1U << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
#define RTC_CR_ITSE RTC_CR_ITSE_Msk
#define RTC_CR_COE_Pos (23U)
#define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
#define RTC_CR_COE RTC_CR_COE_Msk
#define RTC_CR_OSEL_Pos (21U)
#define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
#define RTC_CR_OSEL RTC_CR_OSEL_Msk
#define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
#define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
#define RTC_CR_POL_Pos (20U)
#define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
#define RTC_CR_POL RTC_CR_POL_Msk
#define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
#define RTC_CR_ADD1H_Pos (16U)
#define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
#define RTC_CR_TSIE_Pos (15U)
#define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
#define RTC_CR_TSIE RTC_CR_TSIE_Msk
#define RTC_CR_WUTIE_Pos (14U)
#define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
#define RTC_CR_ALRBIE_Pos (13U)
#define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
#define RTC_CR_ALRAIE_Pos (12U)
#define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
#define RTC_CR_TSE_Pos (11U)
#define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
#define RTC_CR_TSE RTC_CR_TSE_Msk
#define RTC_CR_WUTE_Pos (10U)
#define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
#define RTC_CR_WUTE RTC_CR_WUTE_Msk
#define RTC_CR_ALRBE_Pos (9U)
#define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
#define RTC_CR_ALRAE_Pos (8U)
#define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
#define RTC_CR_FMT_Pos (6U)
#define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
#define RTC_CR_FMT RTC_CR_FMT_Msk
#define RTC_CR_BYPSHAD_Pos (5U)
#define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
#define RTC_CR_REFCKON_Pos (4U)
#define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
#define RTC_CR_TSEDGE_Pos (3U)
#define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
#define RTC_CR_WUCKSEL_Pos (0U)
#define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
#define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/******************** Bits definition for RTC_SMCR register *******************/
#define RTC_SMCR_DECPROT_Pos (15U)
#define RTC_SMCR_DECPROT_Msk (0x1U << RTC_SMCR_DECPROT_Pos) /*!< 0x00008000 */
#define RTC_SMCR_DECPROT RTC_SMCR_DECPROT_Msk
#define RTC_SMCR_INITDPROT_Pos (14U)
#define RTC_SMCR_INITDPROT_Msk (0x1U << RTC_SMCR_INITDPROT_Pos) /*!< 0x00004000 */
#define RTC_SMCR_INITDPROT RTC_SMCR_INITDPROT_Msk
#define RTC_SMCR_CALDPROT_Pos (13U)
#define RTC_SMCR_CALDPROT_Msk (0x1U << RTC_SMCR_CALDPROT_Pos) /*!< 0x00002000 */
#define RTC_SMCR_CALDPROT RTC_SMCR_CALDPROT_Msk
#define RTC_SMCR_TSDPROT_Pos (3U)
#define RTC_SMCR_TSDPROT_Msk (0x1U << RTC_SMCR_TSDPROT_Pos) /*!< 0x00000008 */
#define RTC_SMCR_TSDPROT RTC_SMCR_TSDPROT_Msk
#define RTC_SMCR_WUTDPROT_Pos (2U)
#define RTC_SMCR_WUTDPROT_Msk (0x1U << RTC_SMCR_WUTDPROT_Pos) /*!< 0x00000004 */
#define RTC_SMCR_WUTDPROT RTC_SMCR_WUTDPROT_Msk
#define RTC_SMCR_ALRBDPROT_Pos (1U)
#define RTC_SMCR_ALRBDPROT_Msk (0x1U << RTC_SMCR_ALRBDPROT_Pos) /*!< 0x00000002 */
#define RTC_SMCR_ALRBDPROT RTC_SMCR_ALRBDPROT_Msk
#define RTC_SMCR_ALRADPROT_Pos (0U)
#define RTC_SMCR_ALRADPROT_Msk (0x1U << RTC_SMCR_ALRADPROT_Pos) /*!< 0x00000001 */
#define RTC_SMCR_ALRADPROT RTC_SMCR_ALRADPROT_Msk
/******************** Bits definition for RTC_WPR register ******************/
#define RTC_WPR_KEY_Pos (0U)
#define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
#define RTC_WPR_KEY RTC_WPR_KEY_Msk
/******************** Bits definition for RTC_CALR register *****************/
#define RTC_CALR_CALP_Pos (15U)
#define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
#define RTC_CALR_CALP RTC_CALR_CALP_Msk
#define RTC_CALR_CALW8_Pos (14U)
#define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
#define RTC_CALR_CALW16_Pos (13U)
#define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
#define RTC_CALR_CALM_Pos (0U)
#define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
#define RTC_CALR_CALM RTC_CALR_CALM_Msk
#define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
#define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
#define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
#define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
#define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
#define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
#define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
#define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
#define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
/******************** Bits definition for RTC_SHIFTR register ***************/
#define RTC_SHIFTR_SUBFS_Pos (0U)
#define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
#define RTC_SHIFTR_ADD1S_Pos (31U)
#define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
/******************** Bits definition for RTC_TSTR register *****************/
#define RTC_TSTR_PM_Pos (22U)
#define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
#define RTC_TSTR_PM RTC_TSTR_PM_Msk
#define RTC_TSTR_HT_Pos (20U)
#define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
#define RTC_TSTR_HT RTC_TSTR_HT_Msk
#define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
#define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
#define RTC_TSTR_HU_Pos (16U)
#define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
#define RTC_TSTR_HU RTC_TSTR_HU_Msk
#define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
#define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
#define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
#define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
#define RTC_TSTR_MNT_Pos (12U)
#define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
#define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
#define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
#define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
#define RTC_TSTR_MNU_Pos (8U)
#define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
#define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
#define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
#define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
#define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
#define RTC_TSTR_ST_Pos (4U)
#define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
#define RTC_TSTR_ST RTC_TSTR_ST_Msk
#define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
#define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
#define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
#define RTC_TSTR_SU_Pos (0U)
#define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
#define RTC_TSTR_SU RTC_TSTR_SU_Msk
#define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
#define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
#define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
#define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_TSDR register *****************/
#define RTC_TSDR_WDU_Pos (13U)
#define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
#define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
#define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
#define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
#define RTC_TSDR_MT_Pos (12U)
#define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
#define RTC_TSDR_MT RTC_TSDR_MT_Msk
#define RTC_TSDR_MU_Pos (8U)
#define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
#define RTC_TSDR_MU RTC_TSDR_MU_Msk
#define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
#define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
#define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
#define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
#define RTC_TSDR_DT_Pos (4U)
#define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
#define RTC_TSDR_DT RTC_TSDR_DT_Msk
#define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
#define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
#define RTC_TSDR_DU_Pos (0U)
#define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
#define RTC_TSDR_DU RTC_TSDR_DU_Msk
#define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
#define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
#define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
#define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_TSSSR register ******************/
#define RTC_TSSSR_SS_Pos (0U)
#define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
/******************** Bits definition for RTC_ALRMAR register ***************/
#define RTC_ALRMAR_MSK4_Pos (31U)
#define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
#define RTC_ALRMAR_WDSEL_Pos (30U)
#define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
#define RTC_ALRMAR_DT_Pos (28U)
#define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
#define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
#define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
#define RTC_ALRMAR_DU_Pos (24U)
#define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
#define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
#define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
#define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
#define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
#define RTC_ALRMAR_MSK3_Pos (23U)
#define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
#define RTC_ALRMAR_PM_Pos (22U)
#define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
#define RTC_ALRMAR_HT_Pos (20U)
#define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
#define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
#define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
#define RTC_ALRMAR_HU_Pos (16U)
#define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
#define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
#define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
#define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
#define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
#define RTC_ALRMAR_MSK2_Pos (15U)
#define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
#define RTC_ALRMAR_MNT_Pos (12U)
#define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
#define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
#define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
#define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
#define RTC_ALRMAR_MNU_Pos (8U)
#define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
#define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
#define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
#define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
#define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
#define RTC_ALRMAR_MSK1_Pos (7U)
#define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
#define RTC_ALRMAR_ST_Pos (4U)
#define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
#define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
#define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
#define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
#define RTC_ALRMAR_SU_Pos (0U)
#define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
#define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
#define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
#define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
#define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_ALRMASSR register *************/
#define RTC_ALRMASSR_MASKSS_Pos (24U)
#define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
#define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
#define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
#define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
#define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
#define RTC_ALRMASSR_SS_Pos (0U)
#define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
/******************** Bits definition for RTC_ALRMBR register ***************/
#define RTC_ALRMBR_MSK4_Pos (31U)
#define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
#define RTC_ALRMBR_WDSEL_Pos (30U)
#define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
#define RTC_ALRMBR_DT_Pos (28U)
#define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
#define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
#define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
#define RTC_ALRMBR_DU_Pos (24U)
#define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
#define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
#define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
#define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
#define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
#define RTC_ALRMBR_MSK3_Pos (23U)
#define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
#define RTC_ALRMBR_PM_Pos (22U)
#define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
#define RTC_ALRMBR_HT_Pos (20U)
#define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
#define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
#define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
#define RTC_ALRMBR_HU_Pos (16U)
#define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
#define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
#define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
#define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
#define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
#define RTC_ALRMBR_MSK2_Pos (15U)
#define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
#define RTC_ALRMBR_MNT_Pos (12U)
#define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
#define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
#define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
#define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
#define RTC_ALRMBR_MNU_Pos (8U)
#define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
#define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
#define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
#define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
#define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
#define RTC_ALRMBR_MSK1_Pos (7U)
#define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
#define RTC_ALRMBR_ST_Pos (4U)
#define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
#define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
#define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
#define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
#define RTC_ALRMBR_SU_Pos (0U)
#define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
#define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
#define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
#define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
#define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_ALRMBSSR register *************/
#define RTC_ALRMBSSR_MASKSS_Pos (24U)
#define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
#define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
#define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
#define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
#define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
#define RTC_ALRMBSSR_SS_Pos (0U)
#define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
/******************** Bits definition for RTC_SR register *************/
#define RTC_SR_ITSF_Pos (5U)
#define RTC_SR_ITSF_Msk (0x1U << RTC_SR_ITSF_Pos) /*!< 0x00000020 */
#define RTC_SR_ITSF RTC_SR_ITSF_Msk
#define RTC_SR_TSOVF_Pos (4U)
#define RTC_SR_TSOVF_Msk (0x1U << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */
#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk
#define RTC_SR_TSF_Pos (3U)
#define RTC_SR_TSF_Msk (0x1U << RTC_SR_TSF_Pos) /*!< 0x00000008 */
#define RTC_SR_TSF RTC_SR_TSF_Msk
#define RTC_SR_WUTF_Pos (2U)
#define RTC_SR_WUTF_Msk (0x1U << RTC_SR_WUTF_Pos) /*!< 0x00000004 */
#define RTC_SR_WUTF RTC_SR_WUTF_Msk
#define RTC_SR_ALRBF_Pos (1U)
#define RTC_SR_ALRBF_Msk (0x1U << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */
#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk
#define RTC_SR_ALRAF_Pos (0U)
#define RTC_SR_ALRAF_Msk (0x1U << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */
#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk
/******************** Bits definition for RTC_MISR register *************/
#define RTC_MISR_ITSMF_Pos (5U)
#define RTC_MISR_ITSMF_Msk (0x1U << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */
#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk
#define RTC_MISR_TSOVMF_Pos (4U)
#define RTC_MISR_TSOVMF_Msk (0x1U << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */
#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk
#define RTC_MISR_TSMF_Pos (3U)
#define RTC_MISR_TSMF_Msk (0x1U << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */
#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk
#define RTC_MISR_WUTMF_Pos (2U)
#define RTC_MISR_WUTMF_Msk (0x1U << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */
#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk
#define RTC_MISR_ALRBMF_Pos (1U)
#define RTC_MISR_ALRBMF_Msk (0x1U << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */
#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk
#define RTC_MISR_ALRAMF_Pos (0U)
#define RTC_MISR_ALRAMF_Msk (0x1U << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */
#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk
/******************** Bits definition for RTC_SMISR register *************/
#define RTC_SMISR_ITSMF_Pos (5U)
#define RTC_SMISR_ITSMF_Msk (0x1U << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */
#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk
#define RTC_SMISR_TSOVMF_Pos (4U)
#define RTC_SMISR_TSOVMF_Msk (0x1U << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */
#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk
#define RTC_SMISR_TSMF_Pos (3U)
#define RTC_SMISR_TSMF_Msk (0x1U << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */
#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk
#define RTC_SMISR_WUTMF_Pos (2U)
#define RTC_SMISR_WUTMF_Msk (0x1U << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */
#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk
#define RTC_SMISR_ALRBMF_Pos (1U)
#define RTC_SMISR_ALRBMF_Msk (0x1U << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */
#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk
#define RTC_SMISR_ALRAMF_Pos (0U)
#define RTC_SMISR_ALRAMF_Msk (0x1U << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */
#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk
/******************** Bits definition for RTC_SCR register *************/
#define RTC_SCR_CITSF_Pos (5U)
#define RTC_SCR_CITSF_Msk (0x1U << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */
#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk
#define RTC_SCR_CTSOVF_Pos (4U)
#define RTC_SCR_CTSOVF_Msk (0x1U << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */
#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk
#define RTC_SCR_CTSF_Pos (3U)
#define RTC_SCR_CTSF_Msk (0x1U << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */
#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk
#define RTC_SCR_CWUTF_Pos (2U)
#define RTC_SCR_CWUTF_Msk (0x1U << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */
#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk
#define RTC_SCR_CALRBF_Pos (1U)
#define RTC_SCR_CALRBF_Msk (0x1U << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */
#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk
#define RTC_SCR_CALRAF_Pos (0U)
#define RTC_SCR_CALRAF_Msk (0x1U << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
/******************** Bits definition for RTC_OR register ****************/
#define RTC_CFGR_LSCOEN_Pos (1U)
#define RTC_CFGR_LSCOEN_Msk (0x3U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000006 */
#define RTC_CFGR_LSCOEN RTC_CFGR_LSCOEN_Msk
#define RTC_CFGR_LSCOEN_0 (0x1U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000002 */
#define RTC_CFGR_LSCOEN_1 (0x2U << RTC_CFGR_LSCOEN_Pos) /*!< 0x00000004 */
#define RTC_CFGR_OUT2_RMP_Pos (0U)
#define RTC_CFGR_OUT2_RMP_Msk (0x1U << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */
#define RTC_CFGR_OUT2_RMP RTC_OR_OUT2_RMP_Msk
/******************** Bits definition for RTC_HWCFGR register *************/
#define RTC_HWCFGR_TRUST_ZONE_Pos (24U)
#define RTC_HWCFGR_TRUST_ZONE_Msk (0xFU << RTC_HWCFGR_TRUST_ZONE_Pos) /*!< 0x0F000000 */
#define RTC_HWCFGR_TRUST_ZONE RTC_HWCFGR_TRUST_ZONE_Msk
#define RTC_HWCFGR_TRUST_ZONE_0 (0x1U << RTC_HWCFGR_TRUST_ZONE_Pos) /*!< 0x01000000 */
#define RTC_HWCFGR_TRUST_ZONE_1 (0x2U << RTC_HWCFGR_TRUST_ZONE_Pos) /*!< 0x02000000 */
#define RTC_HWCFGR_TRUST_ZONE_2 (0x4U << RTC_HWCFGR_TRUST_ZONE_Pos) /*!< 0x04000000 */
#define RTC_HWCFGR_TRUST_ZONE_3 (0x8U << RTC_HWCFGR_TRUST_ZONE_Pos) /*!< 0x08000000 */
#define RTC_HWCFGR_OPTIONREG_OUT_Pos (16U)
#define RTC_HWCFGR_OPTIONREG_OUT_Msk (0xFFU << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00FF0000 */
#define RTC_HWCFGR_OPTIONREG_OUT RTC_HWCFGR_OPTIONREG_OUT_Msk
#define RTC_HWCFGR_OPTIONREG_OUT_0 (0x01U << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00010000 */
#define RTC_HWCFGR_OPTIONREG_OUT_1 (0x02U << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00020000 */
#define RTC_HWCFGR_OPTIONREG_OUT_2 (0x04U << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00040000 */
#define RTC_HWCFGR_OPTIONREG_OUT_3 (0x08U << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00080000 */
#define RTC_HWCFGR_OPTIONREG_OUT_4 (0x10U << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00100000 */
#define RTC_HWCFGR_OPTIONREG_OUT_5 (0x20U << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00200000 */
#define RTC_HWCFGR_OPTIONREG_OUT_6 (0x40U << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00400000 */
#define RTC_HWCFGR_OPTIONREG_OUT_7 (0x80U << RTC_HWCFGR_OPTIONREG_OUT_Pos) /*!< 0x00800000 */
#define RTC_HWCFGR_TIMESTAMP_Pos (12U)
#define RTC_HWCFGR_TIMESTAMP_Msk (0xFU << RTC_HWCFGR_TIMESTAMP_Pos) /*!< 0x0000F000 */
#define RTC_HWCFGR_TIMESTAMP RTC_HWCFGR_TIMESTAMP_Msk
#define RTC_HWCFGR_TIMESTAMP_0 (0x1U << RTC_HWCFGR_TIMESTAMP_Pos) /*!< 0x00001000 */
#define RTC_HWCFGR_TIMESTAMP_1 (0x2U << RTC_HWCFGR_TIMESTAMP_Pos) /*!< 0x00002000 */
#define RTC_HWCFGR_TIMESTAMP_2 (0x4U << RTC_HWCFGR_TIMESTAMP_Pos) /*!< 0x00004000 */
#define RTC_HWCFGR_TIMESTAMP_3 (0x8U << RTC_HWCFGR_TIMESTAMP_Pos) /*!< 0x00008000 */
#define RTC_HWCFGR_SMOOTH_CALIB_Pos (8U)
#define RTC_HWCFGR_SMOOTH_CALIB_Msk (0xFU << RTC_HWCFGR_SMOOTH_CALIB_Pos) /*!< 0x00000F00 */
#define RTC_HWCFGR_SMOOTH_CALIB RTC_HWCFGR_SMOOTH_CALIB_Msk
#define RTC_HWCFGR_SMOOTH_CALIB_0 (0x1U << RTC_HWCFGR_SMOOTH_CALIB_Pos) /*!< 0x00000100 */
#define RTC_HWCFGR_SMOOTH_CALIB_1 (0x2U << RTC_HWCFGR_SMOOTH_CALIB_Pos) /*!< 0x00000200 */
#define RTC_HWCFGR_SMOOTH_CALIB_2 (0x4U << RTC_HWCFGR_SMOOTH_CALIB_Pos) /*!< 0x00000400 */
#define RTC_HWCFGR_SMOOTH_CALIB_3 (0x8U << RTC_HWCFGR_SMOOTH_CALIB_Pos) /*!< 0x00000800 */
#define RTC_HWCFGR_WAKEUP_Pos (4U)
#define RTC_HWCFGR_WAKEUP_Msk (0xFU << RTC_HWCFGR_WAKEUP_Pos) /*!< 0x000000F0 */
#define RTC_HWCFGR_WAKEUP RTC_HWCFGR_WAKEUP_Msk
#define RTC_HWCFGR_WAKEUP_0 (0x1U << RTC_HWCFGR_WAKEUP_Pos) /*!< 0x00000010 */
#define RTC_HWCFGR_WAKEUP_1 (0x2U << RTC_HWCFGR_WAKEUP_Pos) /*!< 0x00000020 */
#define RTC_HWCFGR_WAKEUP_2 (0x4U << RTC_HWCFGR_WAKEUP_Pos) /*!< 0x00000040 */
#define RTC_HWCFGR_WAKEUP_3 (0x8U << RTC_HWCFGR_WAKEUP_Pos) /*!< 0x00000080 */
#define RTC_HWCFGR_ALARMB_Pos (0U)
#define RTC_HWCFGR_ALARMB_Msk (0xFU << RTC_HWCFGR_ALARMB_Pos) /*!< 0x0000000F */
#define RTC_HWCFGR_ALARMB RTC_HWCFGR_ALARMB_Msk
#define RTC_HWCFGR_ALARMB_0 (0x1U << RTC_HWCFGR_ALARMB_Pos) /*!< 0x00000001 */
#define RTC_HWCFGR_ALARMB_1 (0x2U << RTC_HWCFGR_ALARMB_Pos) /*!< 0x00000002 */
#define RTC_HWCFGR_ALARMB_2 (0x4U << RTC_HWCFGR_ALARMB_Pos) /*!< 0x00000004 */
#define RTC_HWCFGR_ALARMB_3 (0x8U << RTC_HWCFGR_ALARMB_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_VERR register ****************/
#define RTC_VERR_MAJREV_Pos (4U)
#define RTC_VERR_MAJREV_Msk (0xFU << RTC_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define RTC_VERR_MAJREV RTC_VERR_MAJREV_Msk
#define RTC_VERR_MAJREV_0 (0x1U << RTC_VERR_MAJREV_Pos) /*!< 0x00000010 */
#define RTC_VERR_MAJREV_1 (0x2U << RTC_VERR_MAJREV_Pos) /*!< 0x00000020 */
#define RTC_VERR_MAJREV_2 (0x4U << RTC_VERR_MAJREV_Pos) /*!< 0x00000040 */
#define RTC_VERR_MAJREV_3 (0x8U << RTC_VERR_MAJREV_Pos) /*!< 0x00000080 */
#define RTC_VERR_MINREV_Pos (0U)
#define RTC_VERR_MINREV_Msk (0xFU << RTC_VERR_MINREV_Pos) /*!< 0x0000000F */
#define RTC_VERR_MINREV RTC_VERR_MINREV_Msk
#define RTC_VERR_MINREV_0 (0x1U << RTC_VERR_MINREV_Pos) /*!< 0x00000001 */
#define RTC_VERR_MINREV_1 (0x2U << RTC_VERR_MINREV_Pos) /*!< 0x00000002 */
#define RTC_VERR_MINREV_2 (0x4U << RTC_VERR_MINREV_Pos) /*!< 0x00000004 */
#define RTC_VERR_MINREV_3 (0x8U << RTC_VERR_MINREV_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_IPIDR register ****************/
#define RTC_IPIDR_ID_Pos (0U)
#define RTC_IPIDR_ID_Msk (0xFFFFFFFFU << RTC_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
#define RTC_IPIDR_ID RTC_IPIDR_ID_Msk
/******************** Bits definition for RTC_SIDR register ****************/
#define RTC_SIDR_SID_Pos (0U)
#define RTC_SIDR_SID_Msk (0xFFFFFFFFU << RTC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define RTC_SIDR_SID RTC_SIDR_SID_Msk
/******************************************************************************/
/* */
/* Tamper and Backup registers (TAMP) */
/* */
/******************************************************************************/
/******************** Bits definition for TAMP_CR1 register ***************/
#define TAMP_CR1_TAMPE_Pos (0U)
#define TAMP_CR1_TAMPE_Msk (0x7U << TAMP_CR1_TAMPE_Pos) /*!< 0x000000FF */
#define TAMP_CR1_TAMPE TAMP_CR1_TAMPE_Msk
#define TAMP_CR1_TAMP1E_Pos (0U)
#define TAMP_CR1_TAMP1E_Msk (0x1U << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */
#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk
#define TAMP_CR1_TAMP2E_Pos (1U)
#define TAMP_CR1_TAMP2E_Msk (0x1U << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */
#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk
#define TAMP_CR1_TAMP3E_Pos (2U)
#define TAMP_CR1_TAMP3E_Msk (0x1U << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */
#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk
#define TAMP_CR1_ITAMPE_Pos (16U)
#define TAMP_CR1_ITAMPE_Msk (0x9FU << TAMP_CR1_ITAMPE_Pos) /*!< 0xFFFF0000 */
#define TAMP_CR1_ITAMPE TAMP_CR1_ITAMPE_Msk
#define TAMP_CR1_ITAMP1E_Pos (16U)
#define TAMP_CR1_ITAMP1E_Msk (0x1U << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */
#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk
#define TAMP_CR1_ITAMP2E_Pos (17U)
#define TAMP_CR1_ITAMP2E_Msk (0x1U << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00020000 */
#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk
#define TAMP_CR1_ITAMP3E_Pos (18U)
#define TAMP_CR1_ITAMP3E_Msk (0x1U << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */
#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk
#define TAMP_CR1_ITAMP4E_Pos (19U)
#define TAMP_CR1_ITAMP4E_Msk (0x1U << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */
#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk
#define TAMP_CR1_ITAMP5E_Pos (20U)
#define TAMP_CR1_ITAMP5E_Msk (0x1U << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */
#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk
#define TAMP_CR1_ITAMP8E_Pos (23U)
#define TAMP_CR1_ITAMP8E_Msk (0x1U << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */
#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk
/******************** Bits definition for TAMP_CR2 register ***************/
#define TAMP_CR2_TAMPNOERASE_Pos (0U)
#define TAMP_CR2_TAMPNOERase_Msk (0x7U << TAMP_CR2_TAMPNOERASE_Pos) /*!< 0x000000FF */
#define TAMP_CR2_TAMPNOER TAMP_CR2_TAMPNOERase_Msk
#define TAMP_CR2_TAMP1NOERASE_Pos (0U)
#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */
#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk
#define TAMP_CR2_TAMP2NOERASE_Pos (1U)
#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */
#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk
#define TAMP_CR2_TAMP3NOERASE_Pos (2U)
#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */
#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk
#define TAMP_CR2_TAMPMSK_Pos (16U)
#define TAMP_CR2_TAMPMSK_Msk (0x7U << TAMP_CR2_TAMPMSK_Pos) /*!< 0x00FF0000 */
#define TAMP_CR2_TAMPMSK TAMP_CR2_TAMPMSK_Msk
#define TAMP_CR2_TAMP1MSK_Pos (16U)
#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */
#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk
#define TAMP_CR2_TAMP2MSK_Pos (17U)
#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */
#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk
#define TAMP_CR2_TAMP3MSK_Pos (18U)
#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */
#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk
#define TAMP_CR2_TAMPTRG_Pos (24U)
#define TAMP_CR2_TAMPTRG_Msk (0xFFU << TAMP_CR2_TAMPTRG_Pos) /*!< 0xFF000000 */
#define TAMP_CR2_TAMPTRG TAMP_CR2_TAMPTRG_Msk
#define TAMP_CR2_TAMP1TRG_Pos (24U)
#define TAMP_CR2_TAMP1TRG_Msk (0x1U << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */
#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk
#define TAMP_CR2_TAMP2TRG_Pos (25U)
#define TAMP_CR2_TAMP2TRG_Msk (0x1U << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */
#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk
#define TAMP_CR2_TAMP3TRG_Pos (26U)
#define TAMP_CR2_TAMP3TRG_Msk (0x1U << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
/******************** Bits definition for TAMP_FLTCR register ***************/
#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
#define TAMP_FLTCR_TAMPFREQ_Msk (0x7U << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
#define TAMP_FLTCR_TAMPFREQ_0 (0x1U << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */
#define TAMP_FLTCR_TAMPFREQ_1 (0x2U << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */
#define TAMP_FLTCR_TAMPFREQ_2 (0x4U << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */
#define TAMP_FLTCR_TAMPFLT_Pos (3U)
#define TAMP_FLTCR_TAMPFLT_Msk (0x3U << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
#define TAMP_FLTCR_TAMPFLT_0 (0x1U << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */
#define TAMP_FLTCR_TAMPFLT_1 (0x2U << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */
#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
#define TAMP_FLTCR_TAMPPRCH_Msk (0x3U << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
#define TAMP_FLTCR_TAMPPRCH_0 (0x1U << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */
#define TAMP_FLTCR_TAMPPRCH_1 (0x2U << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */
#define TAMP_FLTCR_TAMPPUDIS_Pos (7U)
#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1U << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */
#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk
/******************** Bits definition for TAMP_ATCR1 register ***************/
#define TAMP_ATCR1_TAMPAM_Pos (0U)
#define TAMP_ATCR1_TAMPAM_Msk (0xFFU << TAMP_ATCR1_TAMPAM_Pos) /*!< 0x000000FF */
#define TAMP_ATCR1_TAMPAM TAMP_ATCR1_TAMPAM_Msk
#define TAMP_ATCR1_TAMP1AM_Pos (0U)
#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL <<TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */
#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk
#define TAMP_ATCR1_TAMP2AM_Pos (1U)
#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL <<TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */
#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk
#define TAMP_ATCR1_TAMP3AM_Pos (2U)
#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL <<TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */
#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk
#define TAMP_ATCR1_TAMP4AM_Pos (3U)
#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL <<TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */
#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk
#define TAMP_ATCR1_TAMP5AM_Pos (4U)
#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL <<TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */
#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk
#define TAMP_ATCR1_TAMP6AM_Pos (6U)
#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL <<TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000020 */
#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk
#define TAMP_ATCR1_TAMP7AM_Pos (6U)
#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL <<TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */
#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk
#define TAMP_ATCR1_TAMP8AM_Pos (7U)
#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL <<TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */
#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk
#define TAMP_ATCR1_ATOSEL1_Pos (8U)
#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL <<TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */
#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk
#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */
#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */
#define TAMP_ATCR1_ATOSEL2_Pos (10U)
#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL <<TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */
#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk
#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */
#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */
#define TAMP_ATCR1_ATOSEL3_Pos (12U)
#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL <<TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */
#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk
#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */
#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */
#define TAMP_ATCR1_ATOSEL4_Pos (14U)
#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL <<TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */
#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk
#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */
#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */
#define TAMP_ATCR1_ATCKSEL_Pos (16U)
#define TAMP_ATCR1_ATCKSEL_Msk (0x7UL <<TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00070000 */
#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk
#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */
#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */
#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */
#define TAMP_ATCR1_ATPER_Pos (24U)
#define TAMP_ATCR1_ATPER_Msk (0x7UL <<TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */
#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk
#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */
#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */
#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */
#define TAMP_ATCR1_ATOSHARE_Pos (30U)
#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL <<TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */
#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk
#define TAMP_ATCR1_FLTEN_Pos (31U)
#define TAMP_ATCR1_FLTEN_Msk (0x1UL <<TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */
#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk
/******************** Bits definition for TAMP_ATSEEDR register ***************/
#define TAMP_ATSEEDR_SEED_Pos (0U)
#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFU << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */
#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk
/******************** Bits definition for TAMP_ATOR register ***************/
#define TAMP_ATOR_PRNG_Pos (0U)
#define TAMP_ATOR_PRNG_Msk (0xFFU << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */
#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk
#define TAMP_ATOR_PRNG_0 (0x01U << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */
#define TAMP_ATOR_PRNG_1 (0x02U << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */
#define TAMP_ATOR_PRNG_2 (0x04U << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */
#define TAMP_ATOR_PRNG_3 (0x08U << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */
#define TAMP_ATOR_PRNG_4 (0x10U << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */
#define TAMP_ATOR_PRNG_5 (0x20U << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */
#define TAMP_ATOR_PRNG_6 (0x40U << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */
#define TAMP_ATOR_PRNG_7 (0x80U << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */
#define TAMP_ATOR_SEEDF_Pos (14U)
#define TAMP_ATOR_SEEDF_Msk (0x1U << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */
#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk
#define TAMP_ATOR_INITS_Pos (15U)
#define TAMP_ATOR_INITS_Msk (0x1U << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */
#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk
/******************** Bits definition for TAMP_SMCR register ***************/
#define TAMP_SMCR_BKPRWDPROT_Pos (0U)
#define TAMP_SMCR_BKPRWDPROT_Msk (0xFFU << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x000000FF */
#define TAMP_SMCR_BKPRWDPROT TAMP_SMCR_BKPRWDPROT_Msk
#define TAMP_SMCR_BKPRWDPROT_0 (0x01U << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000001 */
#define TAMP_SMCR_BKPRWDPROT_1 (0x02U << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000002 */
#define TAMP_SMCR_BKPRWDPROT_2 (0x04U << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000004 */
#define TAMP_SMCR_BKPRWDPROT_3 (0x08U << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000008 */
#define TAMP_SMCR_BKPRWDPROT_4 (0x10U << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000010 */
#define TAMP_SMCR_BKPRWDPROT_5 (0x20U << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000020 */
#define TAMP_SMCR_BKPRWDPROT_6 (0x40U << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000040 */
#define TAMP_SMCR_BKPRWDPROT_7 (0x80U << TAMP_SMCR_BKPRWDPROT_Pos) /*!< 0x00000080 */
#define TAMP_SMCR_BKPWDPROT_Pos (16U)
#define TAMP_SMCR_BKPWDPROT_Msk (0xFFU << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00FF0000 */
#define TAMP_SMCR_BKPWDPROT TAMP_SMCR_BKPWDPROT_Msk
#define TAMP_SMCR_BKPWDPROT_0 (0x01U << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00010000 */
#define TAMP_SMCR_BKPWDPROT_1 (0x02U << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00020000 */
#define TAMP_SMCR_BKPWDPROT_2 (0x04U << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00040000 */
#define TAMP_SMCR_BKPWDPROT_3 (0x08U << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00080000 */
#define TAMP_SMCR_BKPWDPROT_4 (0x10U << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00100000 */
#define TAMP_SMCR_BKPWDPROT_5 (0x20U << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00200000 */
#define TAMP_SMCR_BKPWDPROT_6 (0x40U << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00400000 */
#define TAMP_SMCR_BKPWDPROT_7 (0x80U << TAMP_SMCR_BKPWDPROT_Pos) /*!< 0x00800000 */
#define TAMP_SMCR_TAMPDPROT_Pos (31U)
#define TAMP_SMCR_TAMPDPROT_Msk (0x1U << TAMP_SMCR_TAMPDPROT_Pos) /*!< 0x80000000 */
#define TAMP_SMCR_TAMPDPROT TAMP_SMCR_TAMPDPROT_Msk
/******************** Bits definition for TAMP_IER register ***************/
#define TAMP_IER_TAMPIE_Pos (0U)
#define TAMP_IER_TAMPIE_Msk (0x7U << TAMP_IER_TAMPIE_Pos) /*!< 0x000000FF */
#define TAMP_IER_TAMPIE TAMP_IER_TAMPIE_Msk
#define TAMP_IER_TAMP1IE_Pos (0U)
#define TAMP_IER_TAMP1IE_Msk (0x1U << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */
#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk
#define TAMP_IER_TAMP2IE_Pos (1U)
#define TAMP_IER_TAMP2IE_Msk (0x1U << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */
#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk
#define TAMP_IER_TAMP3IE_Pos (2U)
#define TAMP_IER_TAMP3IE_Msk (0x1U << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */
#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk
#define TAMP_IER_ITAMPIE_Pos (16U)
#define TAMP_IER_ITAMPIE_Msk (0x9FU << TAMP_IER_ITAMPIE_Pos) /*!< 0xFFFF0000 */
#define TAMP_IER_ITAMPIE TAMP_IER_ITAMPIE_Msk
#define TAMP_IER_ITAMP1IE_Pos (16U)
#define TAMP_IER_ITAMP1IE_Msk (0x1U << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */
#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk
#define TAMP_IER_ITAMP2IE_Pos (17U)
#define TAMP_IER_ITAMP2IE_Msk (0x1U << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */
#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk
#define TAMP_IER_ITAMP3IE_Pos (18U)
#define TAMP_IER_ITAMP3IE_Msk (0x1U << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */
#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk
#define TAMP_IER_ITAMP4IE_Pos (19U)
#define TAMP_IER_ITAMP4IE_Msk (0x1U << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */
#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk
#define TAMP_IER_ITAMP5IE_Pos (20U)
#define TAMP_IER_ITAMP5IE_Msk (0x1U << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */
#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk
#define TAMP_IER_ITAMP8IE_Pos (23U)
#define TAMP_IER_ITAMP8IE_Msk (0x1U << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */
#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk
/******************** Bits definition for TAMP_SR register ***************/
#define TAMP_SR_TAMPF_Pos (0U)
#define TAMP_SR_TAMPF_Msk (0x7U << TAMP_SR_TAMPF_Pos) /*!< 0x000000FF */
#define TAMP_SR_TAMPF TAMP_SR_TAMPF_Msk
#define TAMP_SR_TAMP1F_Pos (0U)
#define TAMP_SR_TAMP1F_Msk (0x1U << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */
#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk
#define TAMP_SR_TAMP2F_Pos (1U)
#define TAMP_SR_TAMP2F_Msk (0x1U << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */
#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk
#define TAMP_SR_TAMP3F_Pos (2U)
#define TAMP_SR_TAMP3F_Msk (0x1U << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */
#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk
#define TAMP_SR_ITAMPF_Pos (16U)
#define TAMP_SR_ITAMPF_Msk (0x9FU << TAMP_SR_ITAMPF_Pos) /*!< 0xFFFF0000 */
#define TAMP_SR_ITAMPF TAMP_SR_ITAMPF_Msk
#define TAMP_SR_ITAMP1F_Pos (16U)
#define TAMP_SR_ITAMP1F_Msk (0x1U << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */
#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk
#define TAMP_SR_ITAMP2F_Pos (17U)
#define TAMP_SR_ITAMP2F_Msk (0x1U << TAMP_SR_ITAMP2F_Pos) /*!< 0x00020000 */
#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk
#define TAMP_SR_ITAMP3F_Pos (18U)
#define TAMP_SR_ITAMP3F_Msk (0x1U << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */
#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk
#define TAMP_SR_ITAMP4F_Pos (19U)
#define TAMP_SR_ITAMP4F_Msk (0x1U << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */
#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk
#define TAMP_SR_ITAMP5F_Pos (20U)
#define TAMP_SR_ITAMP5F_Msk (0x1U << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */
#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk
#define TAMP_SR_ITAMP8F_Pos (23U)
#define TAMP_SR_ITAMP8F_Msk (0x1U << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */
#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk
/******************** Bits definition for TAMP_MISR register ***************/
#define TAMP_MISR_TAMPMF_Pos (0U)
#define TAMP_MISR_TAMPMF_Msk (0x7U << TAMP_MISR_TAMPMF_Pos) /*!< 0x000000FF */
#define TAMP_MISR_TAMPMF TAMP_MISR_TAMPMF_Msk
#define TAMP_MISR_TAMP1MF_Pos (0U)
#define TAMP_MISR_TAMP1MF_Msk (0x1U << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */
#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk
#define TAMP_MISR_TAMP2MF_Pos (1U)
#define TAMP_MISR_TAMP2MF_Msk (0x1U << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */
#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk
#define TAMP_MISR_TAMP3MF_Pos (2U)
#define TAMP_MISR_TAMP3MF_Msk (0x1U << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */
#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk
#define TAMP_MISR_ITAMPMF_Pos (16U)
#define TAMP_MISR_ITAMPMF_Msk (0x9FU << TAMP_MISR_ITAMPMF_Pos) /*!< 0xFFFF0000 */
#define TAMP_MISR_ITAMPMF TAMP_MISR_ITAMPMF_Msk
#define TAMP_MISR_ITAMP1MF_Pos (16U)
#define TAMP_MISR_ITAMP1MF_Msk (0x1U << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */
#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk
#define TAMP_MISR_ITAMP2MF_Pos (17U)
#define TAMP_MISR_ITAMP2MF_Msk (0x1U << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00020000 */
#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk
#define TAMP_MISR_ITAMP3MF_Pos (18U)
#define TAMP_MISR_ITAMP3MF_Msk (0x1U << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */
#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk
#define TAMP_MISR_ITAMP4MF_Pos (19U)
#define TAMP_MISR_ITAMP4MF_Msk (0x1U << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */
#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk
#define TAMP_MISR_ITAMP5MF_Pos (20U)
#define TAMP_MISR_ITAMP5MF_Msk (0x1U << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */
#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk
#define TAMP_MISR_ITAMP8MF_Pos (23U)
#define TAMP_MISR_ITAMP8MF_Msk (0x1U << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */
#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk
/******************** Bits definition for TAMP_SMISR register ***************/
#define TAMP_SMISR_TAMPMF_Pos (0U)
#define TAMP_SMISR_TAMPMF_Msk (0x7U << TAMP_SMISR_TAMPMF_Pos) /*!< 0x000000FF */
#define TAMP_SMISR_TAMPMF TAMP_SMISR_TAMPMF_Msk
#define TAMP_SMISR_TAMP1MF_Pos (0U)
#define TAMP_SMISR_TAMP1MF_Msk (0x1U << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */
#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk
#define TAMP_SMISR_TAMP2MF_Pos (1U)
#define TAMP_SMISR_TAMP2MF_Msk (0x1U << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */
#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk
#define TAMP_SMISR_TAMP3MF_Pos (2U)
#define TAMP_SMISR_TAMP3MF_Msk (0x1U << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */
#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk
#define TAMP_SMISR_ITAMPMF_Pos (16U)
#define TAMP_SMISR_ITAMPMF_Msk (0x9FU << TAMP_SMISR_ITAMPMF_Pos) /*!< 0xFFFF0000 */
#define TAMP_SMISR_ITAMPMF TAMP_SMISR_ITAMPMF_Msk
#define TAMP_SMISR_ITAMP1MF_Pos (16U)
#define TAMP_SMISR_ITAMP1MF_Msk (0x1U << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */
#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk
#define TAMP_SMISR_ITAMP2MF_Pos (17U)
#define TAMP_SMISR_ITAMP2MF_Msk (0x1U << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00020000 */
#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk
#define TAMP_SMISR_ITAMP3MF_Pos (18U)
#define TAMP_SMISR_ITAMP3MF_Msk (0x1U << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */
#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk
#define TAMP_SMISR_ITAMP4MF_Pos (19U)
#define TAMP_SMISR_ITAMP4MF_Msk (0x1U << TAMP_SMISR_ITAMP4MF_Pos) /*!< 0x00080000 */
#define TAMP_SMISR_ITAMP4MF TAMP_SMISR_ITAMP4MF_Msk
#define TAMP_SMISR_ITAMP5MF_Pos (20U)
#define TAMP_SMISR_ITAMP5MF_Msk (0x1U << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */
#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk
#define TAMP_SMISR_ITAMP8MF_Pos (23U)
#define TAMP_SMISR_ITAMP8MF_Msk (0x1U << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */
#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk
/******************** Bits definition for TAMP_SCR register ***************/
#define TAMP_SCR_CTAMPF_Pos (0U)
#define TAMP_SCR_CTAMPF_Msk (0x7U << TAMP_SCR_CTAMPF_Pos) /*!< 0x000000FF */
#define TAMP_SCR_CTAMPF TAMP_SCR_CTAMPF_Msk
#define TAMP_SCR_CTAMP1F_Pos (0U)
#define TAMP_SCR_CTAMP1F_Msk (0x1U << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */
#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk
#define TAMP_SCR_CTAMP2F_Pos (1U)
#define TAMP_SCR_CTAMP2F_Msk (0x1U << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */
#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk
#define TAMP_SCR_CTAMP3F_Pos (2U)
#define TAMP_SCR_CTAMP3F_Msk (0x1U << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */
#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk
#define TAMP_SCR_CITAMPF_Pos (16U)
#define TAMP_SCR_CITAMPF_Msk (0x9FU << TAMP_SCR_CITAMPF_Pos) /*!< 0xFFFF0000 */
#define TAMP_SCR_CITAMPF TAMP_SCR_CITAMPF_Msk
#define TAMP_SCR_CITAMP1F_Pos (16U)
#define TAMP_SCR_CITAMP1F_Msk (0x1U << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */
#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk
#define TAMP_SCR_CITAMP2F_Pos (17U)
#define TAMP_SCR_CITAMP2F_Msk (0x1U << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00020000 */
#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk
#define TAMP_SCR_CITAMP3F_Pos (18U)
#define TAMP_SCR_CITAMP3F_Msk (0x1U << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */
#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk
#define TAMP_SCR_CITAMP4F_Pos (19U)
#define TAMP_SCR_CITAMP4F_Msk (0x1U << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */
#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk
#define TAMP_SCR_CITAMP5F_Pos (20U)
#define TAMP_SCR_CITAMP5F_Msk (0x1U << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */
#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk
#define TAMP_SCR_CITAMP8F_Pos (23U)
#define TAMP_SCR_CITAMP8F_Msk (0x1U << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */
#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk
/******************** Bits definition for TAMP_OR register (TAMP_CFGR) ****************/
#define TAMP_CFGR_OUT3_RMP_Pos (0U)
#define TAMP_CFGR_OUT3_RMP_Msk (0x1U << TAMP_CFGR_OUT3_RMP_Pos) /*!< 0x00000001 */
#define TAMP_CFGR_OUT3_RMP TAMP_CFGR_OUT3_RMP_Msk
/******************** Bits definition for TAMP_COUNTR register ****************/
#define TAMP_COUNTR_COUNT_Pos (0U)
#define TAMP_COUNTR_COUNT_Msk (0xFFFFFFFFU << TAMP_COUNTR_COUNT_Pos) /*!< 0xFFFFFFFF */
#define TAMP_COUNTR_COUNT TAMP_COUNTR_COUNT_Msk
/******************** Bits definition for TAMP_BKPxR register ****************/
#define TAMP_BKP0R_Pos (0U)
#define TAMP_BKP0R_Msk (0xFFFFFFFFU << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP0R TAMP_BKP0R_Msk
#define TAMP_BKP1R_Pos (0U)
#define TAMP_BKP1R_Msk (0xFFFFFFFFU << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP1R TAMP_BKP1R_Msk
#define TAMP_BKP2R_Pos (0U)
#define TAMP_BKP2R_Msk (0xFFFFFFFFU << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP2R TAMP_BKP2R_Msk
#define TAMP_BKP3R_Pos (0U)
#define TAMP_BKP3R_Msk (0xFFFFFFFFU << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP3R TAMP_BKP3R_Msk
#define TAMP_BKP4R_Pos (0U)
#define TAMP_BKP4R_Msk (0xFFFFFFFFU << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP4R TAMP_BKP4R_Msk
#define TAMP_BKP5R_Pos (0U)
#define TAMP_BKP5R_Msk (0xFFFFFFFFU << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP5R TAMP_BKP5R_Msk
#define TAMP_BKP6R_Pos (0U)
#define TAMP_BKP6R_Msk (0xFFFFFFFFU << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP6R TAMP_BKP6R_Msk
#define TAMP_BKP7R_Pos (0U)
#define TAMP_BKP7R_Msk (0xFFFFFFFFU << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP7R TAMP_BKP7R_Msk
#define TAMP_BKP8R_Pos (0U)
#define TAMP_BKP8R_Msk (0xFFFFFFFFU << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP8R TAMP_BKP8R_Msk
#define TAMP_BKP9R_Pos (0U)
#define TAMP_BKP9R_Msk (0xFFFFFFFFU << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP9R TAMP_BKP9R_Msk
#define TAMP_BKP10R_Pos (0U)
#define TAMP_BKP10R_Msk (0xFFFFFFFFU << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP10R TAMP_BKP10R_Msk
#define TAMP_BKP11R_Pos (0U)
#define TAMP_BKP11R_Msk (0xFFFFFFFFU << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP11R TAMP_BKP11R_Msk
#define TAMP_BKP12R_Pos (0U)
#define TAMP_BKP12R_Msk (0xFFFFFFFFU << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP12R TAMP_BKP12R_Msk
#define TAMP_BKP13R_Pos (0U)
#define TAMP_BKP13R_Msk (0xFFFFFFFFU << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP13R TAMP_BKP13R_Msk
#define TAMP_BKP14R_Pos (0U)
#define TAMP_BKP14R_Msk (0xFFFFFFFFU << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP14R TAMP_BKP14R_Msk
#define TAMP_BKP15R_Pos (0U)
#define TAMP_BKP15R_Msk (0xFFFFFFFFU << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP15R TAMP_BKP15R_Msk
#define TAMP_BKP16R_Pos (0U)
#define TAMP_BKP16R_Msk (0xFFFFFFFFU << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP16R TAMP_BKP16R_Msk
#define TAMP_BKP17R_Pos (0U)
#define TAMP_BKP17R_Msk (0xFFFFFFFFU << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP17R TAMP_BKP17R_Msk
#define TAMP_BKP18R_Pos (0U)
#define TAMP_BKP18R_Msk (0xFFFFFFFFU << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP18R TAMP_BKP18R_Msk
#define TAMP_BKP19R_Pos (0U)
#define TAMP_BKP19R_Msk (0xFFFFFFFFU << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP19R TAMP_BKP19R_Msk
#define TAMP_BKP20R_Pos (0U)
#define TAMP_BKP20R_Msk (0xFFFFFFFFU << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP20R TAMP_BKP20R_Msk
#define TAMP_BKP21R_Pos (0U)
#define TAMP_BKP21R_Msk (0xFFFFFFFFU << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP21R TAMP_BKP21R_Msk
#define TAMP_BKP22R_Pos (0U)
#define TAMP_BKP22R_Msk (0xFFFFFFFFU << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP22R TAMP_BKP22R_Msk
#define TAMP_BKP23R_Pos (0U)
#define TAMP_BKP23R_Msk (0xFFFFFFFFU << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP23R TAMP_BKP23R_Msk
#define TAMP_BKP24R_Pos (0U)
#define TAMP_BKP24R_Msk (0xFFFFFFFFU << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP24R TAMP_BKP24R_Msk
#define TAMP_BKP25R_Pos (0U)
#define TAMP_BKP25R_Msk (0xFFFFFFFFU << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP25R TAMP_BKP25R_Msk
#define TAMP_BKP26R_Pos (0U)
#define TAMP_BKP26R_Msk (0xFFFFFFFFU << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP26R TAMP_BKP26R_Msk
#define TAMP_BKP27R_Pos (0U)
#define TAMP_BKP27R_Msk (0xFFFFFFFFU << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP27R TAMP_BKP27R_Msk
#define TAMP_BKP28R_Pos (0U)
#define TAMP_BKP28R_Msk (0xFFFFFFFFU << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP28R TAMP_BKP28R_Msk
#define TAMP_BKP29R_Pos (0U)
#define TAMP_BKP29R_Msk (0xFFFFFFFFU << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP29R TAMP_BKP29R_Msk
#define TAMP_BKP30R_Pos (0U)
#define TAMP_BKP30R_Msk (0xFFFFFFFFU << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP30R TAMP_BKP30R_Msk
#define TAMP_BKP31R_Pos (0U)
#define TAMP_BKP31R_Msk (0xFFFFFFFFU << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP31R TAMP_BKP31R_Msk
/******************** Bits definition for TAMP_HWCFGR2 register *************/
#define TAMP_HWCFGR2_TRUST_ZONE_Pos (8U)
#define TAMP_HWCFGR2_TRUST_ZONE_Msk (0xFU << TAMP_HWCFGR2_TRUST_ZONE_Pos) /*!< 0x00000F00 */
#define TAMP_HWCFGR2_TRUST_ZONE TAMP_HWCFGR2_TRUST_ZONE_Msk
#define TAMP_HWCFGR2_TRUST_ZONE_0 (0x1U << TAMP_HWCFGR2_TRUST_ZONE_Pos) /*!< 0x00000100 */
#define TAMP_HWCFGR2_TRUST_ZONE_1 (0x2U << TAMP_HWCFGR2_TRUST_ZONE_Pos) /*!< 0x00000200 */
#define TAMP_HWCFGR2_TRUST_ZONE_2 (0x4U << TAMP_HWCFGR2_TRUST_ZONE_Pos) /*!< 0x00000400 */
#define TAMP_HWCFGR2_TRUST_ZONE_3 (0x8U << TAMP_HWCFGR2_TRUST_ZONE_Pos) /*!< 0x00000800 */
#define TAMP_HWCFGR2_OPTIONREG_OUT_Pos (0U)
#define TAMP_HWCFGR2_OPTIONREG_OUT_Msk (0xFFU << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x000000FF */
#define TAMP_HWCFGR2_OPTIONREG_OUT TAMP_HWCFGR2_OPTIONREG_OUT_Msk
#define TAMP_HWCFGR2_OPTIONREG_OUT_0 (0x01U << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x00000001 */
#define TAMP_HWCFGR2_OPTIONREG_OUT_1 (0x02U << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x00000002 */
#define TAMP_HWCFGR2_OPTIONREG_OUT_2 (0x04U << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x00000004 */
#define TAMP_HWCFGR2_OPTIONREG_OUT_3 (0x08U << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x00000008 */
#define TAMP_HWCFGR2_OPTIONREG_OUT_4 (0x10U << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x00000010 */
#define TAMP_HWCFGR2_OPTIONREG_OUT_5 (0x20U << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x00000020 */
#define TAMP_HWCFGR2_OPTIONREG_OUT_6 (0x40U << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x00000040 */
#define TAMP_HWCFGR2_OPTIONREG_OUT_7 (0x80U << TAMP_HWCFGR2_OPTIONREG_OUT_Pos) /*!< 0x00000080 */
/******************** Bits definition for TAMP_HWCFGR1 register *************/
#define TAMP_HWCFGR1_INT_TAMPER_Pos (16U)
#define TAMP_HWCFGR1_INT_TAMPER_Msk (0xFFFFU << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0xFFFF0000 */
#define TAMP_HWCFGR1_INT_TAMPER TAMP_HWCFGR1_INT_TAMPER_Msk
#define TAMP_HWCFGR1_INT_TAMPER_0 (0x0001U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x00010000 */
#define TAMP_HWCFGR1_INT_TAMPER_1 (0x0002U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x00020000 */
#define TAMP_HWCFGR1_INT_TAMPER_2 (0x0004U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x00040000 */
#define TAMP_HWCFGR1_INT_TAMPER_3 (0x0008U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x00080000 */
#define TAMP_HWCFGR1_INT_TAMPER_4 (0x0010U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x00100000 */
#define TAMP_HWCFGR1_INT_TAMPER_5 (0x0020U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x00200000 */
#define TAMP_HWCFGR1_INT_TAMPER_6 (0x0040U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x00400000 */
#define TAMP_HWCFGR1_INT_TAMPER_7 (0x0080U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x00800000 */
#define TAMP_HWCFGR1_INT_TAMPER_8 (0x0100U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x01000000 */
#define TAMP_HWCFGR1_INT_TAMPER_9 (0x0200U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x02000000 */
#define TAMP_HWCFGR1_INT_TAMPER_10 (0x0400U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x04000000 */
#define TAMP_HWCFGR1_INT_TAMPER_11 (0x0800U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x08000000 */
#define TAMP_HWCFGR1_INT_TAMPER_12 (0x1000U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x10000000 */
#define TAMP_HWCFGR1_INT_TAMPER_13 (0x2000U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x20000000 */
#define TAMP_HWCFGR1_INT_TAMPER_14 (0x4000U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x40000000 */
#define TAMP_HWCFGR1_INT_TAMPER_15 (0x8000U << TAMP_HWCFGR1_INT_TAMPER_Pos) /*!< 0x80000000 */
#define TAMP_HWCFGR1_ACTIVE_TAMPER_Pos (12U)
#define TAMP_HWCFGR1_ACTIVE_TAMPER_Msk (0xFU << TAMP_HWCFGR1_ACTIVE_TAMPER_Pos) /*!< 0x0000F000 */
#define TAMP_HWCFGR1_ACTIVE_TAMPER TAMP_HWCFGR1_ACTIVE_TAMPER_Msk
#define TAMP_HWCFGR1_ACTIVE_TAMPER_0 (0x1U << TAMP_HWCFGR1_ACTIVE_TAMPER_Pos) /*!< 0x00001000 */
#define TAMP_HWCFGR1_ACTIVE_TAMPER_1 (0x2U << TAMP_HWCFGR1_ACTIVE_TAMPER_Pos) /*!< 0x00002000 */
#define TAMP_HWCFGR1_ACTIVE_TAMPER_2 (0x4U << TAMP_HWCFGR1_ACTIVE_TAMPER_Pos) /*!< 0x00004000 */
#define TAMP_HWCFGR1_ACTIVE_TAMPER_3 (0x8U << TAMP_HWCFGR1_ACTIVE_TAMPER_Pos) /*!< 0x00008000 */
#define TAMP_HWCFGR1_TAMPER_Pos (8U)
#define TAMP_HWCFGR1_TAMPER_Msk (0xFU << TAMP_HWCFGR1_TAMPER_Pos) /*!< 0x00000F00 */
#define TAMP_HWCFGR1_TAMPER TAMP_HWCFGR1_TAMPER_Msk
#define TAMP_HWCFGR1_TAMPER_0 (0x1U << TAMP_HWCFGR1_TAMPER_Pos) /*!< 0x00000100 */
#define TAMP_HWCFGR1_TAMPER_1 (0x2U << TAMP_HWCFGR1_TAMPER_Pos) /*!< 0x00000200 */
#define TAMP_HWCFGR1_TAMPER_2 (0x4U << TAMP_HWCFGR1_TAMPER_Pos) /*!< 0x00000400 */
#define TAMP_HWCFGR1_TAMPER_3 (0x8U << TAMP_HWCFGR1_TAMPER_Pos) /*!< 0x00000800 */
#define TAMP_HWCFGR1_BACKUP_REGS_Pos (0U)
#define TAMP_HWCFGR1_BACKUP_REGS_Msk (0xFFU << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x000000FF */
#define TAMP_HWCFGR1_BACKUP_REGS TAMP_HWCFGR1_BACKUP_REGS_Msk
#define TAMP_HWCFGR1_BACKUP_REGS_0 (0x01U << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x00000001 */
#define TAMP_HWCFGR1_BACKUP_REGS_1 (0x02U << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x00000002 */
#define TAMP_HWCFGR1_BACKUP_REGS_2 (0x04U << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x00000004 */
#define TAMP_HWCFGR1_BACKUP_REGS_3 (0x08U << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x00000008 */
#define TAMP_HWCFGR1_BACKUP_REGS_4 (0x10U << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x00000010 */
#define TAMP_HWCFGR1_BACKUP_REGS_5 (0x20U << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x00000020 */
#define TAMP_HWCFGR1_BACKUP_REGS_6 (0x40U << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x00000040 */
#define TAMP_HWCFGR1_BACKUP_REGS_7 (0x80U << TAMP_HWCFGR1_BACKUP_REGS_Pos) /*!< 0x00000080 */
/******************** Bits definition for TAMP_VERR register ****************/
#define TAMP_VERR_MAJREV_Pos (4U)
#define TAMP_VERR_MAJREV_Msk (0xFU << TAMP_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define TAMP_VERR_MAJREV TAMP_VERR_MAJREV_Msk
#define TAMP_VERR_MAJREV_0 (0x1U << TAMP_VERR_MAJREV_Pos) /*!< 0x00000010 */
#define TAMP_VERR_MAJREV_1 (0x2U << TAMP_VERR_MAJREV_Pos) /*!< 0x00000020 */
#define TAMP_VERR_MAJREV_2 (0x4U << TAMP_VERR_MAJREV_Pos) /*!< 0x00000040 */
#define TAMP_VERR_MAJREV_3 (0x8U << TAMP_VERR_MAJREV_Pos) /*!< 0x00000080 */
#define TAMP_VERR_MINREV_Pos (0U)
#define TAMP_VERR_MINREV_Msk (0xFU << TAMP_VERR_MINREV_Pos) /*!< 0x0000000F */
#define TAMP_VERR_MINREV TAMP_VERR_MINREV_Msk
#define TAMP_VERR_MINREV_0 (0x1U << TAMP_VERR_MINREV_Pos) /*!< 0x00000001 */
#define TAMP_VERR_MINREV_1 (0x2U << TAMP_VERR_MINREV_Pos) /*!< 0x00000002 */
#define TAMP_VERR_MINREV_2 (0x4U << TAMP_VERR_MINREV_Pos) /*!< 0x00000004 */
#define TAMP_VERR_MINREV_3 (0x8U << TAMP_VERR_MINREV_Pos) /*!< 0x00000008 */
/******************** Bits definition for TAMP_IPIDR register ****************/
#define TAMP_IPIDR_ID_Pos (0U)
#define TAMP_IPIDR_ID_Msk (0xFFFFFFFFU << TAMP_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
#define TAMP_IPIDR_ID TAMP_IPIDR_ID_Msk
/******************** Bits definition for TAMP_SIDR register ****************/
#define TAMP_SIDR_SID_Pos (0U)
#define TAMP_SIDR_SID_Msk (0xFFFFFFFFU << TAMP_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define TAMP_SIDR_SID TAMP_SIDR_SID_Msk
/******************** Number of backup registers ******************************/
#define TAMP_BKP_NUMBER_Pos (5U)
#define TAMP_BKP_NUMBER_Msk (0x1U << TAMP_BKP_NUMBER_Pos) /*!< 0x00000020 */
#define TAMP_BKP_NUMBER TAMP_BKP_NUMBER_Msk
/******************** Number of tamper registers ******************************/
#define TAMP_TAMPER_NUMBER_Pos (0U)
#define TAMP_TAMPER_NUMBER_Msk (0x3U << TAMP_TAMPER_NUMBER_Pos) /*!< 0x00000003 */
#define TAMP_TAMPER_NUMBER TAMP_TAMPER_NUMBER_Msk
/******************************************************************************/
/* */
/* SPDIF-RX Interface */
/* */
/******************************************************************************/
/******************** Bit definition for SPDIF_CR register *******************/
#define SPDIFRX_CR_SPDIFEN_Pos (0U)
#define SPDIFRX_CR_SPDIFEN_Msk (0x3U << SPDIFRX_CR_SPDIFEN_Pos) /*!< 0x00000003 */
#define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk /*!<Peripheral Block Enable */
#define SPDIFRX_CR_RXDMAEN_Pos (2U)
#define SPDIFRX_CR_RXDMAEN_Msk (0x1U << SPDIFRX_CR_RXDMAEN_Pos) /*!< 0x00000004 */
#define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk /*!<Receiver DMA Enable for data flow */
#define SPDIFRX_CR_RXSTEO_Pos (3U)
#define SPDIFRX_CR_RXSTEO_Msk (0x1U << SPDIFRX_CR_RXSTEO_Pos) /*!< 0x00000008 */
#define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk /*!<Stereo Mode */
#define SPDIFRX_CR_DRFMT_Pos (4U)
#define SPDIFRX_CR_DRFMT_Msk (0x3U << SPDIFRX_CR_DRFMT_Pos) /*!< 0x00000030 */
#define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk /*!<RX Data format */
#define SPDIFRX_CR_PMSK_Pos (6U)
#define SPDIFRX_CR_PMSK_Msk (0x1U << SPDIFRX_CR_PMSK_Pos) /*!< 0x00000040 */
#define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk /*!<Mask Parity error bit */
#define SPDIFRX_CR_VMSK_Pos (7U)
#define SPDIFRX_CR_VMSK_Msk (0x1U << SPDIFRX_CR_VMSK_Pos) /*!< 0x00000080 */
#define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk /*!<Mask of Validity bit */
#define SPDIFRX_CR_CUMSK_Pos (8U)
#define SPDIFRX_CR_CUMSK_Msk (0x1U << SPDIFRX_CR_CUMSK_Pos) /*!< 0x00000100 */
#define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk /*!<Mask of channel status and user bits */
#define SPDIFRX_CR_PTMSK_Pos (9U)
#define SPDIFRX_CR_PTMSK_Msk (0x1U << SPDIFRX_CR_PTMSK_Pos) /*!< 0x00000200 */
#define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk /*!<Mask of Preamble Type bits */
#define SPDIFRX_CR_CBDMAEN_Pos (10U)
#define SPDIFRX_CR_CBDMAEN_Msk (0x1U << SPDIFRX_CR_CBDMAEN_Pos) /*!< 0x00000400 */
#define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk /*!<Control Buffer DMA ENable for control flow */
#define SPDIFRX_CR_CHSEL_Pos (11U)
#define SPDIFRX_CR_CHSEL_Msk (0x1U << SPDIFRX_CR_CHSEL_Pos) /*!< 0x00000800 */
#define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk /*!<Channel Selection */
#define SPDIFRX_CR_NBTR_Pos (12U)
#define SPDIFRX_CR_NBTR_Msk (0x3U << SPDIFRX_CR_NBTR_Pos) /*!< 0x00003000 */
#define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchronization phase */
#define SPDIFRX_CR_WFA_Pos (14U)
#define SPDIFRX_CR_WFA_Msk (0x1U << SPDIFRX_CR_WFA_Pos) /*!< 0x00004000 */
#define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk /*!<Wait For Activity */
#define SPDIFRX_CR_INSEL_Pos (16U)
#define SPDIFRX_CR_INSEL_Msk (0x7U << SPDIFRX_CR_INSEL_Pos) /*!< 0x00070000 */
#define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk /*!<SPDIF input selection */
/******************* Bit definition for SPDIFRX_IMR register *******************/
#define SPDIFRX_IMR_RXNEIE_Pos (0U)
#define SPDIFRX_IMR_RXNEIE_Msk (0x1U << SPDIFRX_IMR_RXNEIE_Pos) /*!< 0x00000001 */
#define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk /*!<RXNE interrupt enable */
#define SPDIFRX_IMR_CSRNEIE_Pos (1U)
#define SPDIFRX_IMR_CSRNEIE_Msk (0x1U << SPDIFRX_IMR_CSRNEIE_Pos) /*!< 0x00000002 */
#define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk /*!<Control Buffer Ready Interrupt Enable */
#define SPDIFRX_IMR_PERRIE_Pos (2U)
#define SPDIFRX_IMR_PERRIE_Msk (0x1U << SPDIFRX_IMR_PERRIE_Pos) /*!< 0x00000004 */
#define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk /*!<Parity error interrupt enable */
#define SPDIFRX_IMR_OVRIE_Pos (3U)
#define SPDIFRX_IMR_OVRIE_Msk (0x1U << SPDIFRX_IMR_OVRIE_Pos) /*!< 0x00000008 */
#define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk /*!<Overrun error Interrupt Enable */
#define SPDIFRX_IMR_SBLKIE_Pos (4U)
#define SPDIFRX_IMR_SBLKIE_Msk (0x1U << SPDIFRX_IMR_SBLKIE_Pos) /*!< 0x00000010 */
#define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk /*!<Synchronization Block Detected Interrupt Enable */
#define SPDIFRX_IMR_SYNCDIE_Pos (5U)
#define SPDIFRX_IMR_SYNCDIE_Msk (0x1U << SPDIFRX_IMR_SYNCDIE_Pos) /*!< 0x00000020 */
#define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk /*!<Synchronization Done */
#define SPDIFRX_IMR_IFEIE_Pos (6U)
#define SPDIFRX_IMR_IFEIE_Msk (0x1U << SPDIFRX_IMR_IFEIE_Pos) /*!< 0x00000040 */
#define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk /*!<Serial Interface Error Interrupt Enable */
/******************* Bit definition for SPDIFRX_SR register *******************/
#define SPDIFRX_SR_RXNE_Pos (0U)
#define SPDIFRX_SR_RXNE_Msk (0x1U << SPDIFRX_SR_RXNE_Pos) /*!< 0x00000001 */
#define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk /*!<Read data register not empty */
#define SPDIFRX_SR_CSRNE_Pos (1U)
#define SPDIFRX_SR_CSRNE_Msk (0x1U << SPDIFRX_SR_CSRNE_Pos) /*!< 0x00000002 */
#define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk /*!<The Control Buffer register is not empty */
#define SPDIFRX_SR_PERR_Pos (2U)
#define SPDIFRX_SR_PERR_Msk (0x1U << SPDIFRX_SR_PERR_Pos) /*!< 0x00000004 */
#define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk /*!<Parity error */
#define SPDIFRX_SR_OVR_Pos (3U)
#define SPDIFRX_SR_OVR_Msk (0x1U << SPDIFRX_SR_OVR_Pos) /*!< 0x00000008 */
#define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk /*!<Overrun error */
#define SPDIFRX_SR_SBD_Pos (4U)
#define SPDIFRX_SR_SBD_Msk (0x1U << SPDIFRX_SR_SBD_Pos) /*!< 0x00000010 */
#define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk /*!<Synchronization Block Detected */
#define SPDIFRX_SR_SYNCD_Pos (5U)
#define SPDIFRX_SR_SYNCD_Msk (0x1U << SPDIFRX_SR_SYNCD_Pos) /*!< 0x00000020 */
#define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk /*!<Synchronization Done */
#define SPDIFRX_SR_FERR_Pos (6U)
#define SPDIFRX_SR_FERR_Msk (0x1U << SPDIFRX_SR_FERR_Pos) /*!< 0x00000040 */
#define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk /*!<Framing error */
#define SPDIFRX_SR_SERR_Pos (7U)
#define SPDIFRX_SR_SERR_Msk (0x1U << SPDIFRX_SR_SERR_Pos) /*!< 0x00000080 */
#define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk /*!<Synchronization error */
#define SPDIFRX_SR_TERR_Pos (8U)
#define SPDIFRX_SR_TERR_Msk (0x1U << SPDIFRX_SR_TERR_Pos) /*!< 0x00000100 */
#define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error */
#define SPDIFRX_SR_WIDTH5_Pos (16U)
#define SPDIFRX_SR_WIDTH5_Msk (0x7FFFU << SPDIFRX_SR_WIDTH5_Pos) /*!< 0x7FFF0000 */
#define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk /*!<Duration of 5 symbols counted with spdif_clk */
/******************* Bit definition for SPDIFRX_IFCR register *******************/
#define SPDIFRX_IFCR_PERRCF_Pos (2U)
#define SPDIFRX_IFCR_PERRCF_Msk (0x1U << SPDIFRX_IFCR_PERRCF_Pos) /*!< 0x00000004 */
#define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk /*!<Clears the Parity error flag */
#define SPDIFRX_IFCR_OVRCF_Pos (3U)
#define SPDIFRX_IFCR_OVRCF_Msk (0x1U << SPDIFRX_IFCR_OVRCF_Pos) /*!< 0x00000008 */
#define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk /*!<Clears the Overrun error flag */
#define SPDIFRX_IFCR_SBDCF_Pos (4U)
#define SPDIFRX_IFCR_SBDCF_Msk (0x1U << SPDIFRX_IFCR_SBDCF_Pos) /*!< 0x00000010 */
#define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk /*!<Clears the Synchronization Block Detected flag */
#define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
#define SPDIFRX_IFCR_SYNCDCF_Msk (0x1U << SPDIFRX_IFCR_SYNCDCF_Pos) /*!< 0x00000020 */
#define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk /*!<Clears the Synchronization Done flag */
/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
#define SPDIFRX_DR0_DR_Pos (0U)
#define SPDIFRX_DR0_DR_Msk (0xFFFFFFU << SPDIFRX_DR0_DR_Pos) /*!< 0x00FFFFFF */
#define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk /*!<Data value */
#define SPDIFRX_DR0_PE_Pos (24U)
#define SPDIFRX_DR0_PE_Msk (0x1U << SPDIFRX_DR0_PE_Pos) /*!< 0x01000000 */
#define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk /*!<Parity Error bit */
#define SPDIFRX_DR0_V_Pos (25U)
#define SPDIFRX_DR0_V_Msk (0x1U << SPDIFRX_DR0_V_Pos) /*!< 0x02000000 */
#define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk /*!<Validity bit */
#define SPDIFRX_DR0_U_Pos (26U)
#define SPDIFRX_DR0_U_Msk (0x1U << SPDIFRX_DR0_U_Pos) /*!< 0x04000000 */
#define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk /*!<User bit */
#define SPDIFRX_DR0_C_Pos (27U)
#define SPDIFRX_DR0_C_Msk (0x1U << SPDIFRX_DR0_C_Pos) /*!< 0x08000000 */
#define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk /*!<Channel Status bit */
#define SPDIFRX_DR0_PT_Pos (28U)
#define SPDIFRX_DR0_PT_Msk (0x3U << SPDIFRX_DR0_PT_Pos) /*!< 0x30000000 */
#define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk /*!<Preamble Type */
/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
#define SPDIFRX_DR1_DR_Pos (8U)
#define SPDIFRX_DR1_DR_Msk (0xFFFFFFU << SPDIFRX_DR1_DR_Pos) /*!< 0xFFFFFF00 */
#define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk /*!<Data value */
#define SPDIFRX_DR1_PT_Pos (4U)
#define SPDIFRX_DR1_PT_Msk (0x3U << SPDIFRX_DR1_PT_Pos) /*!< 0x00000030 */
#define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk /*!<Preamble Type */
#define SPDIFRX_DR1_C_Pos (3U)
#define SPDIFRX_DR1_C_Msk (0x1U << SPDIFRX_DR1_C_Pos) /*!< 0x00000008 */
#define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk /*!<Channel Status bit */
#define SPDIFRX_DR1_U_Pos (2U)
#define SPDIFRX_DR1_U_Msk (0x1U << SPDIFRX_DR1_U_Pos) /*!< 0x00000004 */
#define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk /*!<User bit */
#define SPDIFRX_DR1_V_Pos (1U)
#define SPDIFRX_DR1_V_Msk (0x1U << SPDIFRX_DR1_V_Pos) /*!< 0x00000002 */
#define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk /*!<Validity bit */
#define SPDIFRX_DR1_PE_Pos (0U)
#define SPDIFRX_DR1_PE_Msk (0x1U << SPDIFRX_DR1_PE_Pos) /*!< 0x00000001 */
#define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk /*!<Parity Error bit */
/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
#define SPDIFRX_DR1_DRNL1_Pos (16U)
#define SPDIFRX_DR1_DRNL1_Msk (0xFFFFU << SPDIFRX_DR1_DRNL1_Pos) /*!< 0xFFFF0000 */
#define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk /*!<Data value Channel B */
#define SPDIFRX_DR1_DRNL2_Pos (0U)
#define SPDIFRX_DR1_DRNL2_Msk (0xFFFFU << SPDIFRX_DR1_DRNL2_Pos) /*!< 0x0000FFFF */
#define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk /*!<Data value Channel A */
/******************* Bit definition for SPDIFRX_CSR register *******************/
#define SPDIFRX_CSR_USR_Pos (0U)
#define SPDIFRX_CSR_USR_Msk (0xFFFFU << SPDIFRX_CSR_USR_Pos) /*!< 0x0000FFFF */
#define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk /*!<User data information */
#define SPDIFRX_CSR_CS_Pos (16U)
#define SPDIFRX_CSR_CS_Msk (0xFFU << SPDIFRX_CSR_CS_Pos) /*!< 0x00FF0000 */
#define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk /*!<Channel A status information */
#define SPDIFRX_CSR_SOB_Pos (24U)
#define SPDIFRX_CSR_SOB_Msk (0x1U << SPDIFRX_CSR_SOB_Pos) /*!< 0x01000000 */
#define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk /*!<Start Of Block */
/******************* Bit definition for SPDIFRX_DIR register *******************/
#define SPDIFRX_DIR_THI_Pos (0U)
#define SPDIFRX_DIR_THI_Msk (0x1FFFU << SPDIFRX_DIR_THI_Pos) /*!< 0x00001FFF */
#define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk /*!<Threshold LOW */
#define SPDIFRX_DIR_TLO_Pos (16U)
#define SPDIFRX_DIR_TLO_Msk (0x1FFFU << SPDIFRX_DIR_TLO_Pos) /*!< 0x1FFF0000 */
#define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk /*!<Threshold HIGH */
/********************** Bit definition for SPDIFRX_VERR register *****************/
#define SPDIFRX_VERR_MINREV_Pos (0U)
#define SPDIFRX_VERR_MINREV_Msk (0xFU << SPDIFRX_VERR_MINREV_Pos) /*!< 0x0000000F */
#define SPDIFRX_VERR_MINREV SPDIFRX_VERR_MINREV_Msk /*!< Minor Revision number */
#define SPDIFRX_VERR_MAJREV_Pos (4U)
#define SPDIFRX_VERR_MAJREV_Msk (0xFU << SPDIFRX_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define SPDIFRX_VERR_MAJREV SPDIFRX_VERR_MAJREV_Msk /*!< Major Revision number */
/********************** Bit definition for SPDIFRX_IPIDR register ****************/
#define SPDIFRX_IPIDR_IPID_Pos (0U)
#define SPDIFRX_IPIDR_IPID_Msk (0xFFFFFFFFU << SPDIFRX_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
#define SPDIFRX_IPIDR_IPID SPDIFRX_IPIDR_IPID_Msk /*!< IP Identification */
/********************** Bit definition for SPDIFRX_SIDR register *****************/
#define SPDIFRX_SIDR_SID_Pos (0U)
#define SPDIFRX_SIDR_SID_Msk (0xFFFFFFFFU << SPDIFRX_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define SPDIFRX_SIDR_SID SPDIFRX_SIDR_SID_Msk /*!< IP size identification */
/******************************************************************************/
/* */
/* Serial Audio Interface */
/* */
/******************************************************************************/
/******************** Bit definition for SAI_GCR register *******************/
#define SAI_GCR_SYNCIN_Pos (0U)
#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
#define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
#define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
#define SAI_GCR_SYNCOUT_Pos (4U)
#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
#define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
#define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
/******************* Bit definition for SAI_xCR1 register *******************/
#define SAI_xCR1_MODE_Pos (0U)
#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
#define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
#define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
#define SAI_xCR1_PRTCFG_Pos (2U)
#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
#define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
#define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
#define SAI_xCR1_DS_Pos (5U)
#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
#define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
#define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
#define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
#define SAI_xCR1_LSBFIRST_Pos (8U)
#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
#define SAI_xCR1_CKSTR_Pos (9U)
#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
#define SAI_xCR1_SYNCEN_Pos (10U)
#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
#define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
#define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
#define SAI_xCR1_MONO_Pos (12U)
#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
#define SAI_xCR1_OUTDRIV_Pos (13U)
#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
#define SAI_xCR1_SAIEN_Pos (16U)
#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
#define SAI_xCR1_DMAEN_Pos (17U)
#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
#define SAI_xCR1_NODIV_Pos (19U)
#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
#define SAI_xCR1_MCKDIV_Pos (20U)
#define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */
#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[5:0] (Master ClocK Divider) */
#define SAI_xCR1_MCKDIV_0 (0x01U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
#define SAI_xCR1_MCKDIV_1 (0x02U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
#define SAI_xCR1_MCKDIV_2 (0x04U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
#define SAI_xCR1_MCKDIV_3 (0x08U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
#define SAI_xCR1_MCKDIV_4 (0x10U << SAI_xCR1_MCKDIV_Pos) /*!< 0x01000000 */
#define SAI_xCR1_MCKDIV_5 (0x20U << SAI_xCR1_MCKDIV_Pos) /*!< 0x02000000 */
#define SAI_xCR1_MCKEN_Pos (27U)
#define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos) /*!< 0x08000000 */
#define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk /*!<Master ClocK enable */
#define SAI_xCR1_OSR_Pos (26U)
#define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */
#define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<OverSampling Ratio for master clock */
/* Legacy define */
#define SAI_xCR1_NOMCK SAI_xCR1_NODIV
/******************* Bit definition for SAI_xCR2 register *******************/
#define SAI_xCR2_FTH_Pos (0U)
#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
#define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
#define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
#define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
#define SAI_xCR2_FFLUSH_Pos (3U)
#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
#define SAI_xCR2_TRIS_Pos (4U)
#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
#define SAI_xCR2_MUTE_Pos (5U)
#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
#define SAI_xCR2_MUTEVAL_Pos (6U)
#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
#define SAI_xCR2_MUTECNT_Pos (7U)
#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
#define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
#define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
#define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
#define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
#define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
#define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
#define SAI_xCR2_CPL_Pos (13U)
#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
#define SAI_xCR2_COMP_Pos (14U)
#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
#define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
#define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
/****************** Bit definition for SAI_xFRCR register *******************/
#define SAI_xFRCR_FRL_Pos (0U)
#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](FRame Length) */
#define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
#define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
#define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
#define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
#define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
#define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
#define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
#define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
#define SAI_xFRCR_FSALL_Pos (8U)
#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FSALL[6:0] (Frame Synchronization Active Level Length) */
#define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
#define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
#define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
#define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
#define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
#define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
#define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
#define SAI_xFRCR_FSDEF_Pos (16U)
#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!<Frame Synchronization Definition */
#define SAI_xFRCR_FSPOL_Pos (17U)
#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
#define SAI_xFRCR_FSOFF_Pos (18U)
#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
/* Legacy define */
#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
/****************** Bit definition for SAI_xSLOTR register *******************/
#define SAI_xSLOTR_FBOFF_Pos (0U)
#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FBOFF[4:0](First Bit Offset) */
#define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
#define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
#define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
#define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
#define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
#define SAI_xSLOTR_SLOTSZ_Pos (6U)
#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
#define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
#define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
#define SAI_xSLOTR_NBSLOT_Pos (8U)
#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
#define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
#define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
#define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
#define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
#define SAI_xSLOTR_SLOTEN_Pos (16U)
#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
/******************* Bit definition for SAI_xIMR register *******************/
#define SAI_xIMR_OVRUDRIE_Pos (0U)
#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
#define SAI_xIMR_MUTEDETIE_Pos (1U)
#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
#define SAI_xIMR_WCKCFGIE_Pos (2U)
#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
#define SAI_xIMR_FREQIE_Pos (3U)
#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
#define SAI_xIMR_CNRDYIE_Pos (4U)
#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
#define SAI_xIMR_AFSDETIE_Pos (5U)
#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
#define SAI_xIMR_LFSDETIE_Pos (6U)
#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
/******************** Bit definition for SAI_xSR register *******************/
#define SAI_xSR_OVRUDR_Pos (0U)
#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
#define SAI_xSR_MUTEDET_Pos (1U)
#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
#define SAI_xSR_WCKCFG_Pos (2U)
#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
#define SAI_xSR_FREQ_Pos (3U)
#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
#define SAI_xSR_CNRDY_Pos (4U)
#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
#define SAI_xSR_AFSDET_Pos (5U)
#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
#define SAI_xSR_LFSDET_Pos (6U)
#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
#define SAI_xSR_FLVL_Pos (16U)
#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
#define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
#define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
#define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
/****************** Bit definition for SAI_xCLRFR register ******************/
#define SAI_xCLRFR_COVRUDR_Pos (0U)
#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
#define SAI_xCLRFR_CMUTEDET_Pos (1U)
#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
#define SAI_xCLRFR_CWCKCFG_Pos (2U)
#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
#define SAI_xCLRFR_CFREQ_Pos (3U)
#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
#define SAI_xCLRFR_CCNRDY_Pos (4U)
#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
#define SAI_xCLRFR_CAFSDET_Pos (5U)
#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
#define SAI_xCLRFR_CLFSDET_Pos (6U)
#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
/****************** Bit definition for SAI_xDR register *********************/
#define SAI_xDR_DATA_Pos (0U)
#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
#define SAI_xDR_DATA SAI_xDR_DATA_Msk
/******************* Bit definition for SAI_PDMCR register ******************/
#define SAI_PDMCR_PDMEN_Pos (0U)
#define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos) /*!< 0x00000001 */
#define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk /*!<PDM Enable */
#define SAI_PDMCR_MICNBR_Pos (4U)
#define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000030 */
#define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk /*!<Number of microphones */
#define SAI_PDMCR_MICNBR_0 (0x1U << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000010 */
#define SAI_PDMCR_MICNBR_1 (0x2U << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000020 */
#define SAI_PDMCR_CKEN1_Pos (8U)
#define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos) /*!< 0x00000100 */
#define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk /*!<Clock enable of bitstream clock number 1 */
#define SAI_PDMCR_CKEN2_Pos (9U)
#define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos) /*!< 0x00000200 */
#define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk /*!<Clock enable of bitstream clock number 2 */
#define SAI_PDMCR_CKEN3_Pos (10U)
#define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos) /*!< 0x00000400 */
#define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk /*!<Clock enable of bitstream clock number 3 */
#define SAI_PDMCR_CKEN4_Pos (11U)
#define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos) /*!< 0x00000800 */
#define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk /*!<Clock enable of bitstream clock number 4 */
/****************** Bit definition for SAI_PDMDLY register ******************/
#define SAI_PDMDLY_DLYM1L_Pos (0U)
#define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000007 */
#define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
#define SAI_PDMDLY_DLYM1L_0 (0x1U << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000001 */
#define SAI_PDMDLY_DLYM1L_1 (0x2U << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000002 */
#define SAI_PDMDLY_DLYM1L_2 (0x4U << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000004 */
#define SAI_PDMDLY_DLYM1R_Pos (4U)
#define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000070 */
#define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
#define SAI_PDMDLY_DLYM1R_0 (0x1U << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000010 */
#define SAI_PDMDLY_DLYM1R_1 (0x2U << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000020 */
#define SAI_PDMDLY_DLYM1R_2 (0x4U << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000040 */
#define SAI_PDMDLY_DLYM2L_Pos (8U)
#define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000700 */
#define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
#define SAI_PDMDLY_DLYM2L_0 (0x1U << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000100 */
#define SAI_PDMDLY_DLYM2L_1 (0x2U << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000200 */
#define SAI_PDMDLY_DLYM2L_2 (0x4U << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000400 */
#define SAI_PDMDLY_DLYM2R_Pos (12U)
#define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00007000 */
#define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/
#define SAI_PDMDLY_DLYM2R_0 (0x1U << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00001000 */
#define SAI_PDMDLY_DLYM2R_1 (0x2U << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00002000 */
#define SAI_PDMDLY_DLYM2R_2 (0x4U << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00004000 */
#define SAI_PDMDLY_DLYM3L_Pos (16U)
#define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00070000 */
#define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/
#define SAI_PDMDLY_DLYM3L_0 (0x1U << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00010000 */
#define SAI_PDMDLY_DLYM3L_1 (0x2U << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00020000 */
#define SAI_PDMDLY_DLYM3L_2 (0x4U << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00040000 */
#define SAI_PDMDLY_DLYM3R_Pos (20U)
#define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00700000 */
#define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/
#define SAI_PDMDLY_DLYM3R_0 (0x1U << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00100000 */
#define SAI_PDMDLY_DLYM3R_1 (0x2U << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00200000 */
#define SAI_PDMDLY_DLYM3R_2 (0x4U << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00400000 */
#define SAI_PDMDLY_DLYM4L_Pos (24U)
#define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x07000000 */
#define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/
#define SAI_PDMDLY_DLYM4L_0 (0x1U << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x01000000 */
#define SAI_PDMDLY_DLYM4L_1 (0x2U << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x02000000 */
#define SAI_PDMDLY_DLYM4L_2 (0x4U << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x04000000 */
#define SAI_PDMDLY_DLYM4R_Pos (28U)
#define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x70000000 */
#define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/
#define SAI_PDMDLY_DLYM4R_0 (0x1U << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x10000000 */
#define SAI_PDMDLY_DLYM4R_1 (0x2U << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */
#define SAI_PDMDLY_DLYM4R_2 (0x4U << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */
/********************** Bit definition for SAI_HWCFGR register ***************/
#define SAI_HWCFGR_FIFO_SIZE_Pos (0U)
#define SAI_HWCFGR_FIFO_SIZE_Msk (0xFFU << SAI_HWCFGR_FIFO_SIZE_Pos) /*!< 0x000000FF */
#define SAI_HWCFGR_FIFO_SIZE SAI_HWCFGR_FIFO_SIZE_Msk /*!< FIFO size for SAIA and SAIB */
#define SAI_HWCFGR_SPDIF_PDM_Pos (8U)
#define SAI_HWCFGR_SPDIF_PDM_Msk (0xFU << SAI_HWCFGR_SPDIF_PDM_Pos) /*!< 0x00000F00 */
#define SAI_HWCFGR_SPDIF_PDM SAI_HWCFGR_SPDIF_PDM_Msk /*!< Support of SPDIF-OUT and PDM interfaces */
#define SAI_HWCFGR_OPTION_REGOUT_Pos (12U)
#define SAI_HWCFGR_OPTION_REGOUT_Msk (0xFFU << SAI_HWCFGR_OPTION_REGOUT_Pos) /*!< 0x000FF000 */
#define SAI_HWCFGR_OPTION_REGOUT SAI_HWCFGR_OPTION_REGOUT_Msk /*!< Support of SAI_IOR register */
/********************** Bit definition for SAI_VERR register *****************/
#define SAI_VERR_MINREV_Pos (0U)
#define SAI_VERR_MINREV_Msk (0xFU << SAI_VERR_MINREV_Pos) /*!< 0x0000000F */
#define SAI_VERR_MINREV SAI_VERR_MINREV_Msk /*!< Minor Revision number */
#define SAI_VERR_MAJREV_Pos (4U)
#define SAI_VERR_MAJREV_Msk (0xFU << SAI_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define SAI_VERR_MAJREV SAI_VERR_MAJREV_Msk /*!< Major Revision number */
/********************** Bit definition for SAI_IPIDR register ****************/
#define SAI_IPIDR_IPID_Pos (0U)
#define SAI_IPIDR_IPID_Msk (0xFFFFFFFFU << SAI_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
#define SAI_IPIDR_IPID SAI_IPIDR_IPID_Msk /*!< IP Identification */
/********************** Bit definition for SAI_SIDR register *****************/
#define SAI_SIDR_SID_Pos (0U)
#define SAI_SIDR_SID_Msk (0xFFFFFFFFU << SAI_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define SAI_SIDR_SID SAI_SIDR_SID_Msk /*!< IP size identification */
/******************************************************************************/
/* */
/* LCD Controller (LCD) */
/* */
/******************************************************************************/
/******************* Bit definition for LCD_CR register *********************/
#define LCD_CR_LCDEN_Pos (0U)
#define LCD_CR_LCDEN_Msk (0x1U << LCD_CR_LCDEN_Pos) /*!< 0x00000001 */
#define LCD_CR_LCDEN LCD_CR_LCDEN_Msk /*!< LCD Enable Bit */
#define LCD_CR_VSEL_Pos (1U)
#define LCD_CR_VSEL_Msk (0x1U << LCD_CR_VSEL_Pos) /*!< 0x00000002 */
#define LCD_CR_VSEL LCD_CR_VSEL_Msk /*!< Voltage source selector Bit */
#define LCD_CR_DUTY_Pos (2U)
#define LCD_CR_DUTY_Msk (0x7U << LCD_CR_DUTY_Pos) /*!< 0x0000001C */
#define LCD_CR_DUTY LCD_CR_DUTY_Msk /*!< DUTY[2:0] bits (Duty selector) */
#define LCD_CR_DUTY_0 (0x1U << LCD_CR_DUTY_Pos) /*!< 0x00000004 */
#define LCD_CR_DUTY_1 (0x2U << LCD_CR_DUTY_Pos) /*!< 0x00000008 */
#define LCD_CR_DUTY_2 (0x4U << LCD_CR_DUTY_Pos) /*!< 0x00000010 */
#define LCD_CR_BIAS_Pos (5U)
#define LCD_CR_BIAS_Msk (0x3U << LCD_CR_BIAS_Pos) /*!< 0x00000060 */
#define LCD_CR_BIAS LCD_CR_BIAS_Msk /*!< BIAS[1:0] bits (Bias selector) */
#define LCD_CR_BIAS_0 (0x1U << LCD_CR_BIAS_Pos) /*!< 0x00000020 */
#define LCD_CR_BIAS_1 (0x2U << LCD_CR_BIAS_Pos) /*!< 0x00000040 */
#define LCD_CR_MUX_SEG_Pos (7U)
#define LCD_CR_MUX_SEG_Msk (0x1U << LCD_CR_MUX_SEG_Pos) /*!< 0x00000080 */
#define LCD_CR_MUX_SEG LCD_CR_MUX_SEG_Msk /*!< Mux Segment Enable Bit */
#define LCD_CR_BUFEN_Pos (8U)
#define LCD_CR_BUFEN_Msk (0x1U << LCD_CR_BUFEN_Pos) /*!< 0x00000100 */
#define LCD_CR_BUFEN LCD_CR_BUFEN_Msk /*!< Voltage output buffer enable */
/******************* Bit definition for LCD_FCR register ********************/
#define LCD_FCR_HD_Pos (0U)
#define LCD_FCR_HD_Msk (0x1U << LCD_FCR_HD_Pos) /*!< 0x00000001 */
#define LCD_FCR_HD LCD_FCR_HD_Msk /*!< High Drive Enable Bit */
#define LCD_FCR_SOFIE_Pos (1U)
#define LCD_FCR_SOFIE_Msk (0x1U << LCD_FCR_SOFIE_Pos) /*!< 0x00000002 */
#define LCD_FCR_SOFIE LCD_FCR_SOFIE_Msk /*!< Start of Frame Interrupt Enable Bit */
#define LCD_FCR_UDDIE_Pos (3U)
#define LCD_FCR_UDDIE_Msk (0x1U << LCD_FCR_UDDIE_Pos) /*!< 0x00000008 */
#define LCD_FCR_UDDIE LCD_FCR_UDDIE_Msk /*!< Update Display Done Interrupt Enable Bit */
#define LCD_FCR_PON_Pos (4U)
#define LCD_FCR_PON_Msk (0x7U << LCD_FCR_PON_Pos) /*!< 0x00000070 */
#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
#define LCD_FCR_PON_0 (0x1U << LCD_FCR_PON_Pos) /*!< 0x00000010 */
#define LCD_FCR_PON_1 (0x2U << LCD_FCR_PON_Pos) /*!< 0x00000020 */
#define LCD_FCR_PON_2 (0x4U << LCD_FCR_PON_Pos) /*!< 0x00000040 */
#define LCD_FCR_DEAD_Pos (7U)
#define LCD_FCR_DEAD_Msk (0x7U << LCD_FCR_DEAD_Pos) /*!< 0x00000380 */
#define LCD_FCR_DEAD LCD_FCR_DEAD_Msk /*!< DEAD[2:0] bits (DEAD Time) */
#define LCD_FCR_DEAD_0 (0x1U << LCD_FCR_DEAD_Pos) /*!< 0x00000080 */
#define LCD_FCR_DEAD_1 (0x2U << LCD_FCR_DEAD_Pos) /*!< 0x00000100 */
#define LCD_FCR_DEAD_2 (0x4U << LCD_FCR_DEAD_Pos) /*!< 0x00000200 */
#define LCD_FCR_CC_Pos (10U)
#define LCD_FCR_CC_Msk (0x7U << LCD_FCR_CC_Pos) /*!< 0x00001C00 */
#define LCD_FCR_CC LCD_FCR_CC_Msk /*!< CC[2:0] bits (Contrast Control) */
#define LCD_FCR_CC_0 (0x1U << LCD_FCR_CC_Pos) /*!< 0x00000400 */
#define LCD_FCR_CC_1 (0x2U << LCD_FCR_CC_Pos) /*!< 0x00000800 */
#define LCD_FCR_CC_2 (0x4U << LCD_FCR_CC_Pos) /*!< 0x00001000 */
#define LCD_FCR_BLINKF_Pos (13U)
#define LCD_FCR_BLINKF_Msk (0x7U << LCD_FCR_BLINKF_Pos) /*!< 0x0000E000 */
#define LCD_FCR_BLINKF LCD_FCR_BLINKF_Msk /*!< BLINKF[2:0] bits (Blink Frequency) */
#define LCD_FCR_BLINKF_0 (0x1U << LCD_FCR_BLINKF_Pos) /*!< 0x00002000 */
#define LCD_FCR_BLINKF_1 (0x2U << LCD_FCR_BLINKF_Pos) /*!< 0x00004000 */
#define LCD_FCR_BLINKF_2 (0x4U << LCD_FCR_BLINKF_Pos) /*!< 0x00008000 */
#define LCD_FCR_BLINK_Pos (16U)
#define LCD_FCR_BLINK_Msk (0x3U << LCD_FCR_BLINK_Pos) /*!< 0x00030000 */
#define LCD_FCR_BLINK LCD_FCR_BLINK_Msk /*!< BLINK[1:0] bits (Blink Enable) */
#define LCD_FCR_BLINK_0 (0x1U << LCD_FCR_BLINK_Pos) /*!< 0x00010000 */
#define LCD_FCR_BLINK_1 (0x2U << LCD_FCR_BLINK_Pos) /*!< 0x00020000 */
#define LCD_FCR_DIV_Pos (18U)
#define LCD_FCR_DIV_Msk (0xFU << LCD_FCR_DIV_Pos) /*!< 0x003C0000 */
#define LCD_FCR_DIV LCD_FCR_DIV_Msk /*!< DIV[3:0] bits (Divider) */
#define LCD_FCR_PS_Pos (22U)
#define LCD_FCR_PS_Msk (0xFU << LCD_FCR_PS_Pos) /*!< 0x03C00000 */
#define LCD_FCR_PS LCD_FCR_PS_Msk /*!< PS[3:0] bits (Prescaler) */
/******************* Bit definition for LCD_SR register *********************/
#define LCD_SR_ENS_Pos (0U)
#define LCD_SR_ENS_Msk (0x1U << LCD_SR_ENS_Pos) /*!< 0x00000001 */
#define LCD_SR_ENS LCD_SR_ENS_Msk /*!< LCD Enabled Bit */
#define LCD_SR_SOF_Pos (1U)
#define LCD_SR_SOF_Msk (0x1U << LCD_SR_SOF_Pos) /*!< 0x00000002 */
#define LCD_SR_SOF LCD_SR_SOF_Msk /*!< Start Of Frame Flag Bit */
#define LCD_SR_UDR_Pos (2U)
#define LCD_SR_UDR_Msk (0x1U << LCD_SR_UDR_Pos) /*!< 0x00000004 */
#define LCD_SR_UDR LCD_SR_UDR_Msk /*!< Update Display Request Bit */
#define LCD_SR_UDD_Pos (3U)
#define LCD_SR_UDD_Msk (0x1U << LCD_SR_UDD_Pos) /*!< 0x00000008 */
#define LCD_SR_UDD LCD_SR_UDD_Msk /*!< Update Display Done Flag Bit */
#define LCD_SR_RDY_Pos (4U)
#define LCD_SR_RDY_Msk (0x1U << LCD_SR_RDY_Pos) /*!< 0x00000010 */
#define LCD_SR_RDY LCD_SR_RDY_Msk /*!< Ready Flag Bit */
#define LCD_SR_FCRSR_Pos (5U)
#define LCD_SR_FCRSR_Msk (0x1U << LCD_SR_FCRSR_Pos) /*!< 0x00000020 */
#define LCD_SR_FCRSR LCD_SR_FCRSR_Msk /*!< LCD FCR Register Synchronization Flag Bit */
/******************* Bit definition for LCD_CLR register ********************/
#define LCD_CLR_SOFC_Pos (1U)
#define LCD_CLR_SOFC_Msk (0x1U << LCD_CLR_SOFC_Pos) /*!< 0x00000002 */
#define LCD_CLR_SOFC LCD_CLR_SOFC_Msk /*!< Start Of Frame Flag Clear Bit */
#define LCD_CLR_UDDC_Pos (3U)
#define LCD_CLR_UDDC_Msk (0x1U << LCD_CLR_UDDC_Pos) /*!< 0x00000008 */
#define LCD_CLR_UDDC LCD_CLR_UDDC_Msk /*!< Update Display Done Flag Clear Bit */
/******************* Bit definition for LCD_RAM register ********************/
#define LCD_RAM_SEGMENT_DATA_Pos (0U)
#define LCD_RAM_SEGMENT_DATA_Msk (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos) /*!< 0xFFFFFFFF */
#define LCD_RAM_SEGMENT_DATA LCD_RAM_SEGMENT_DATA_Msk /*!< Segment Data Bits */
/******************************************************************************/
/* */
/* SDMMC Interface */
/* */
/******************************************************************************/
/****************** Bit definition for SDMMC_POWER register ******************/
#define SDMMC_POWER_PWRCTRL_Pos (0U)
#define SDMMC_POWER_PWRCTRL_Msk (0x3U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
#define SDMMC_POWER_PWRCTRL_0 (0x1U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000001 */
#define SDMMC_POWER_PWRCTRL_1 (0x2U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000002 */
#define SDMMC_POWER_VSWITCH_Pos (2U)
#define SDMMC_POWER_VSWITCH_Msk (0x1U << SDMMC_POWER_VSWITCH_Pos) /*!< 0x00000004 */
#define SDMMC_POWER_VSWITCH SDMMC_POWER_VSWITCH_Msk /*!<Voltage switch sequence start */
#define SDMMC_POWER_VSWITCHEN_Pos (3U)
#define SDMMC_POWER_VSWITCHEN_Msk (0x1U << SDMMC_POWER_VSWITCHEN_Pos) /*!< 0x00000008 */
#define SDMMC_POWER_VSWITCHEN SDMMC_POWER_VSWITCHEN_Msk /*!<Voltage switch procedure enable */
#define SDMMC_POWER_DIRPOL_Pos (4U)
#define SDMMC_POWER_DIRPOL_Msk (0x1U << SDMMC_POWER_DIRPOL_Pos) /*!< 0x00000010 */
#define SDMMC_POWER_DIRPOL SDMMC_POWER_DIRPOL_Msk /*!<Data and Command direction signals polarity selection */
/****************** Bit definition for SDMMC_CLKCR register ******************/
#define SDMMC_CLKCR_CLKDIV_Pos (0U)
#define SDMMC_CLKCR_CLKDIV_Msk (0x3FFU << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000003FF */
#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
#define SDMMC_CLKCR_PWRSAV_Pos (12U)
#define SDMMC_CLKCR_PWRSAV_Msk (0x1U << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00001000 */
#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
#define SDMMC_CLKCR_WIDBUS_Pos (14U)
#define SDMMC_CLKCR_WIDBUS_Msk (0x3U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x0000C000 */
#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
#define SDMMC_CLKCR_WIDBUS_0 (0x1U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00004000 */
#define SDMMC_CLKCR_WIDBUS_1 (0x2U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00008000 */
#define SDMMC_CLKCR_NEGEDGE_Pos (16U)
#define SDMMC_CLKCR_NEGEDGE_Msk (0x1U << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00010000 */
#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */
#define SDMMC_CLKCR_HWFC_EN_Pos (17U)
#define SDMMC_CLKCR_HWFC_EN_Msk (0x1U << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00020000 */
#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
#define SDMMC_CLKCR_DDR_Pos (18U)
#define SDMMC_CLKCR_DDR_Msk (0x1U << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
#define SDMMC_CLKCR_DDR SDMMC_CLKCR_DDR_Msk /*!<Data rate signaling selection */
#define SDMMC_CLKCR_BUSSPEED_Pos (19U)
#define SDMMC_CLKCR_BUSSPEED_Msk (0x1U << SDMMC_CLKCR_BUSSPEED_Pos) /*!< 0x00080000 */
#define SDMMC_CLKCR_BUSSPEED SDMMC_CLKCR_BUSSPEED_Msk /*!<Bus speed mode selection */
#define SDMMC_CLKCR_SELCLKRX_Pos (20U)
#define SDMMC_CLKCR_SELCLKRX_Msk (0x3U << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00300000 */
#define SDMMC_CLKCR_SELCLKRX SDMMC_CLKCR_SELCLKRX_Msk /*!<SELCLKRX[1:0] bits (Receive clock selection) */
#define SDMMC_CLKCR_SELCLKRX_0 (0x1U << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00100000 */
#define SDMMC_CLKCR_SELCLKRX_1 (0x2U << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00200000 */
/******************* Bit definition for SDMMC_ARG register *******************/
#define SDMMC_ARG_CMDARG_Pos (0U)
#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */
/******************* Bit definition for SDMMC_CMD register *******************/
#define SDMMC_CMD_CMDINDEX_Pos (0U)
#define SDMMC_CMD_CMDINDEX_Msk (0x3FU << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */
#define SDMMC_CMD_CMDTRANS_Pos (6U)
#define SDMMC_CMD_CMDTRANS_Msk (0x1U << SDMMC_CMD_CMDTRANS_Pos) /*!< 0x00000040 */
#define SDMMC_CMD_CMDTRANS SDMMC_CMD_CMDTRANS_Msk /*!<CPSM Treats command as a Data Transfer */
#define SDMMC_CMD_CMDSTOP_Pos (7U)
#define SDMMC_CMD_CMDSTOP_Msk (0x1U << SDMMC_CMD_CMDSTOP_Pos) /*!< 0x00000080 */
#define SDMMC_CMD_CMDSTOP SDMMC_CMD_CMDSTOP_Msk /*!<CPSM Treats command as a Stop */
#define SDMMC_CMD_WAITRESP_Pos (8U)
#define SDMMC_CMD_WAITRESP_Msk (0x3U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000300 */
#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
#define SDMMC_CMD_WAITRESP_0 (0x1U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000100 */
#define SDMMC_CMD_WAITRESP_1 (0x2U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000200 */
#define SDMMC_CMD_WAITINT_Pos (10U)
#define SDMMC_CMD_WAITINT_Msk (0x1U << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000400 */
#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
#define SDMMC_CMD_WAITPEND_Pos (11U)
#define SDMMC_CMD_WAITPEND_Msk (0x1U << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000800 */
#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
#define SDMMC_CMD_CPSMEN_Pos (12U)
#define SDMMC_CMD_CPSMEN_Msk (0x1U << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00001000 */
#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
#define SDMMC_CMD_DTHOLD_Pos (13U)
#define SDMMC_CMD_DTHOLD_Msk (0x1U << SDMMC_CMD_DTHOLD_Pos) /*!< 0x00002000 */
#define SDMMC_CMD_DTHOLD SDMMC_CMD_DTHOLD_Msk /*!<Hold new data block transmission and reception in the DPSM */
#define SDMMC_CMD_BOOTMODE_Pos (14U)
#define SDMMC_CMD_BOOTMODE_Msk (0x1U << SDMMC_CMD_BOOTMODE_Pos) /*!< 0x00004000 */
#define SDMMC_CMD_BOOTMODE SDMMC_CMD_BOOTMODE_Msk /*!<Boot mode */
#define SDMMC_CMD_BOOTEN_Pos (15U)
#define SDMMC_CMD_BOOTEN_Msk (0x1U << SDMMC_CMD_BOOTEN_Pos) /*!< 0x00008000 */
#define SDMMC_CMD_BOOTEN SDMMC_CMD_BOOTEN_Msk /*!<Enable Boot mode procedure */
#define SDMMC_CMD_CMDSUSPEND_Pos (16U)
#define SDMMC_CMD_CMDSUSPEND_Msk (0x1U << SDMMC_CMD_CMDSUSPEND_Pos) /*!< 0x00010000 */
#define SDMMC_CMD_CMDSUSPEND SDMMC_CMD_CMDSUSPEND_Msk /*!<CPSM Treats command as a Suspend or Resume command */
/***************** Bit definition for SDMMC_RESPCMD register *****************/
#define SDMMC_RESPCMD_RESPCMD_Pos (0U)
#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */
/****************** Bit definition for SDMMC_RESP0 register ******************/
#define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
#define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk /*!<Card Status */
/****************** Bit definition for SDMMC_RESP1 register ******************/
#define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */
/****************** Bit definition for SDMMC_RESP2 register ******************/
#define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */
/****************** Bit definition for SDMMC_RESP3 register ******************/
#define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */
/****************** Bit definition for SDMMC_RESP4 register ******************/
#define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */
/****************** Bit definition for SDMMC_DTIMER register *****************/
#define SDMMC_DTIMER_DATATIME_Pos (0U)
#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */
/****************** Bit definition for SDMMC_DLEN register *******************/
#define SDMMC_DLEN_DATALENGTH_Pos (0U)
#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */
/****************** Bit definition for SDMMC_DCTRL register ******************/
#define SDMMC_DCTRL_DTEN_Pos (0U)
#define SDMMC_DCTRL_DTEN_Msk (0x1U << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */
#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
#define SDMMC_DCTRL_DTDIR_Pos (1U)
#define SDMMC_DCTRL_DTDIR_Msk (0x1U << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
#define SDMMC_DCTRL_DTMODE_Pos (2U)
#define SDMMC_DCTRL_DTMODE_Msk (0x3U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x0000000C */
#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<DTMODE[1:0] Data transfer mode selection */
#define SDMMC_DCTRL_DTMODE_0 (0x1U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x0004 */
#define SDMMC_DCTRL_DTMODE_1 (0x2U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x0008 */
#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
#define SDMMC_DCTRL_RWSTART_Pos (8U)
#define SDMMC_DCTRL_RWSTART_Msk (0x1U << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */
#define SDMMC_DCTRL_RWSTOP_Pos (9U)
#define SDMMC_DCTRL_RWSTOP_Msk (0x1U << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */
#define SDMMC_DCTRL_RWMOD_Pos (10U)
#define SDMMC_DCTRL_RWMOD_Msk (0x1U << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */
#define SDMMC_DCTRL_SDIOEN_Pos (11U)
#define SDMMC_DCTRL_SDIOEN_Msk (0x1U << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
#define SDMMC_DCTRL_BOOTACKEN_Pos (12U)
#define SDMMC_DCTRL_BOOTACKEN_Msk (0x1U << SDMMC_DCTRL_BOOTACKEN_Pos) /*!< 0x00001000 */
#define SDMMC_DCTRL_BOOTACKEN SDMMC_DCTRL_BOOTACKEN_Msk /*!<Enable the reception of the Boot Acknowledgment */
#define SDMMC_DCTRL_FIFORST_Pos (13U)
#define SDMMC_DCTRL_FIFORST_Msk (0x1U << SDMMC_DCTRL_FIFORST_Pos) /*!< 0x00002000 */
#define SDMMC_DCTRL_FIFORST SDMMC_DCTRL_FIFORST_Msk /*!<FIFO reset */
/****************** Bit definition for SDMMC_DCOUNT register *****************/
#define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
/****************** Bit definition for SDMMC_STA register ********************/
#define SDMMC_STA_CCRCFAIL_Pos (0U)
#define SDMMC_STA_CCRCFAIL_Msk (0x1U << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
#define SDMMC_STA_DCRCFAIL_Pos (1U)
#define SDMMC_STA_DCRCFAIL_Msk (0x1U << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
#define SDMMC_STA_CTIMEOUT_Pos (2U)
#define SDMMC_STA_CTIMEOUT_Msk (0x1U << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */
#define SDMMC_STA_DTIMEOUT_Pos (3U)
#define SDMMC_STA_DTIMEOUT_Msk (0x1U << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */
#define SDMMC_STA_TXUNDERR_Pos (4U)
#define SDMMC_STA_TXUNDERR_Msk (0x1U << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */
#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
#define SDMMC_STA_RXOVERR_Pos (5U)
#define SDMMC_STA_RXOVERR_Msk (0x1U << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */
#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
#define SDMMC_STA_CMDREND_Pos (6U)
#define SDMMC_STA_CMDREND_Msk (0x1U << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */
#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
#define SDMMC_STA_CMDSENT_Pos (7U)
#define SDMMC_STA_CMDSENT_Msk (0x1U << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */
#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */
#define SDMMC_STA_DATAEND_Pos (8U)
#define SDMMC_STA_DATAEND_Msk (0x1U << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
#define SDMMC_STA_DHOLD_Pos (9U)
#define SDMMC_STA_DHOLD_Msk (0x1U << SDMMC_STA_DHOLD_Pos) /*!< 0x00000200 */
#define SDMMC_STA_DHOLD SDMMC_STA_DHOLD_Msk /*!<Data transfer Hold */
#define SDMMC_STA_DBCKEND_Pos (10U)
#define SDMMC_STA_DBCKEND_Msk (0x1U << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
#define SDMMC_STA_DABORT_Pos (11U)
#define SDMMC_STA_DABORT_Msk (0x1U << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
#define SDMMC_STA_CPSMACT_Pos (12U)
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_DPSMACT_Pos (13U)
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_TXFIFOHE_Pos (14U)
#define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
#define SDMMC_STA_RXFIFOHF_Pos (15U)
#define SDMMC_STA_RXFIFOHF_Msk (0x1U << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
#define SDMMC_STA_TXFIFOF_Pos (16U)
#define SDMMC_STA_TXFIFOF_Msk (0x1U << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */
#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
#define SDMMC_STA_RXFIFOF_Pos (17U)
#define SDMMC_STA_RXFIFOF_Msk (0x1U << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */
#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */
#define SDMMC_STA_TXFIFOE_Pos (18U)
#define SDMMC_STA_TXFIFOE_Msk (0x1U << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */
#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
#define SDMMC_STA_RXFIFOE_Pos (19U)
#define SDMMC_STA_RXFIFOE_Msk (0x1U << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */
#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
#define SDMMC_STA_BUSYD0_Pos (20U)
#define SDMMC_STA_BUSYD0_Msk (0x1U << SDMMC_STA_BUSYD0_Pos) /*!< 0x00100000 */
#define SDMMC_STA_BUSYD0 SDMMC_STA_BUSYD0_Msk /*!<Inverted value of SDMMC_D0 line (Busy) */
#define SDMMC_STA_BUSYD0END_Pos (21U)
#define SDMMC_STA_BUSYD0END_Msk (0x1U << SDMMC_STA_BUSYD0END_Pos) /*!< 0x00200000 */
#define SDMMC_STA_BUSYD0END SDMMC_STA_BUSYD0END_Msk /*!<End of SDMMC_D0 Busy following a CMD response detected */
#define SDMMC_STA_SDIOIT_Pos (22U)
#define SDMMC_STA_SDIOIT_Msk (0x1U << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDIO interrupt received */
#define SDMMC_STA_ACKFAIL_Pos (23U)
#define SDMMC_STA_ACKFAIL_Msk (0x1U << SDMMC_STA_ACKFAIL_Pos) /*!< 0x00800000 */
#define SDMMC_STA_ACKFAIL SDMMC_STA_ACKFAIL_Msk /*!<Boot Acknowledgment received (BootAck check fail) */
#define SDMMC_STA_ACKTIMEOUT_Pos (24U)
#define SDMMC_STA_ACKTIMEOUT_Msk (0x1U << SDMMC_STA_ACKTIMEOUT_Pos) /*!< 0x01000000 */
#define SDMMC_STA_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT_Msk /*!<Boot Acknowledgment timeout */
#define SDMMC_STA_VSWEND_Pos (25U)
#define SDMMC_STA_VSWEND_Msk (0x1U << SDMMC_STA_VSWEND_Pos) /*!< 0x02000000 */
#define SDMMC_STA_VSWEND SDMMC_STA_VSWEND_Msk /*!<Voltage switch critical timing section completion */
#define SDMMC_STA_CKSTOP_Pos (26U)
#define SDMMC_STA_CKSTOP_Msk (0x1U << SDMMC_STA_CKSTOP_Pos) /*!< 0x04000000 */
#define SDMMC_STA_CKSTOP SDMMC_STA_CKSTOP_Msk /*!<SDMMC_CK stopped in Voltage switch procedure */
#define SDMMC_STA_IDMATE_Pos (27U)
#define SDMMC_STA_IDMATE_Msk (0x1U << SDMMC_STA_IDMATE_Pos) /*!< 0x08000000 */
#define SDMMC_STA_IDMATE SDMMC_STA_IDMATE_Msk /*!<IDMA transfer error */
#define SDMMC_STA_IDMABTC_Pos (28U)
#define SDMMC_STA_IDMABTC_Msk (0x1U << SDMMC_STA_IDMABTC_Pos) /*!< 0x10000000 */
#define SDMMC_STA_IDMABTC SDMMC_STA_IDMABTC_Msk /*!<IDMA buffer transfer complete */
/******************* Bit definition for SDMMC_ICR register *******************/
#define SDMMC_ICR_CCRCFAILC_Pos (0U)
#define SDMMC_ICR_CCRCFAILC_Msk (0x1U << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
#define SDMMC_ICR_DCRCFAILC_Pos (1U)
#define SDMMC_ICR_DCRCFAILC_Msk (0x1U << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
#define SDMMC_ICR_CTIMEOUTC_Pos (2U)
#define SDMMC_ICR_CTIMEOUTC_Msk (0x1U << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
#define SDMMC_ICR_DTIMEOUTC_Pos (3U)
#define SDMMC_ICR_DTIMEOUTC_Msk (0x1U << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
#define SDMMC_ICR_TXUNDERRC_Pos (4U)
#define SDMMC_ICR_TXUNDERRC_Msk (0x1U << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
#define SDMMC_ICR_RXOVERRC_Pos (5U)
#define SDMMC_ICR_RXOVERRC_Msk (0x1U << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
#define SDMMC_ICR_CMDRENDC_Pos (6U)
#define SDMMC_ICR_CMDRENDC_Msk (0x1U << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
#define SDMMC_ICR_CMDSENTC_Pos (7U)
#define SDMMC_ICR_CMDSENTC_Msk (0x1U << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
#define SDMMC_ICR_DATAENDC_Pos (8U)
#define SDMMC_ICR_DATAENDC_Msk (0x1U << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */
#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
#define SDMMC_ICR_DHOLDC_Pos (9U)
#define SDMMC_ICR_DHOLDC_Msk (0x1U << SDMMC_ICR_DHOLDC_Pos) /*!< 0x00000200 */
#define SDMMC_ICR_DHOLDC SDMMC_ICR_DHOLDC_Msk /*!<DHOLD flag clear bit */
#define SDMMC_ICR_DBCKENDC_Pos (10U)
#define SDMMC_ICR_DBCKENDC_Msk (0x1U << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
#define SDMMC_ICR_DABORTC_Pos (11U)
#define SDMMC_ICR_DABORTC_Msk (0x1U << SDMMC_ICR_DABORTC_Pos) /*!< 0x00000800 */
#define SDMMC_ICR_DABORTC SDMMC_ICR_DABORTC_Msk /*!<DABORTC flag clear bit */
#define SDMMC_ICR_BUSYD0ENDC_Pos (21U)
#define SDMMC_ICR_BUSYD0ENDC_Msk (0x1U << SDMMC_ICR_BUSYD0ENDC_Pos) /*!< 0x00200000 */
#define SDMMC_ICR_BUSYD0ENDC SDMMC_ICR_BUSYD0ENDC_Msk /*!<BUSYD0ENDC flag clear bit */
#define SDMMC_ICR_SDIOITC_Pos (22U)
#define SDMMC_ICR_SDIOITC_Msk (0x1U << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */
#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
#define SDMMC_ICR_ACKFAILC_Pos (23U)
#define SDMMC_ICR_ACKFAILC_Msk (0x1U << SDMMC_ICR_ACKFAILC_Pos) /*!< 0x00800000 */
#define SDMMC_ICR_ACKFAILC SDMMC_ICR_ACKFAILC_Msk /*!<ACKFAILC flag clear bit */
#define SDMMC_ICR_ACKTIMEOUTC_Pos (24U)
#define SDMMC_ICR_ACKTIMEOUTC_Msk (0x1U << SDMMC_ICR_ACKTIMEOUTC_Pos) /*!< 0x01000000 */
#define SDMMC_ICR_ACKTIMEOUTC SDMMC_ICR_ACKTIMEOUTC_Msk /*!<ACKTIMEOUTC flag clear bit */
#define SDMMC_ICR_VSWENDC_Pos (25U)
#define SDMMC_ICR_VSWENDC_Msk (0x1U << SDMMC_ICR_VSWENDC_Pos) /*!< 0x02000000 */
#define SDMMC_ICR_VSWENDC SDMMC_ICR_VSWENDC_Msk /*!<VSWENDC flag clear bit */
#define SDMMC_ICR_CKSTOPC_Pos (26U)
#define SDMMC_ICR_CKSTOPC_Msk (0x1U << SDMMC_ICR_CKSTOPC_Pos) /*!< 0x04000000 */
#define SDMMC_ICR_CKSTOPC SDMMC_ICR_CKSTOPC_Msk /*!<CKSTOPC flag clear bit */
#define SDMMC_ICR_IDMATEC_Pos (27U)
#define SDMMC_ICR_IDMATEC_Msk (0x1U << SDMMC_ICR_IDMATEC_Pos) /*!< 0x08000000 */
#define SDMMC_ICR_IDMATEC SDMMC_ICR_IDMATEC_Msk /*!<IDMATEC flag clear bit */
#define SDMMC_ICR_IDMABTCC_Pos (28U)
#define SDMMC_ICR_IDMABTCC_Msk (0x1U << SDMMC_ICR_IDMABTCC_Pos) /*!< 0x10000000 */
#define SDMMC_ICR_IDMABTCC SDMMC_ICR_IDMABTCC_Msk /*!<IDMABTCC flag clear bit */
/****************** Bit definition for SDMMC_MASK register *******************/
#define SDMMC_MASK_CCRCFAILIE_Pos (0U)
#define SDMMC_MASK_CCRCFAILIE_Msk (0x1U << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
#define SDMMC_MASK_DCRCFAILIE_Pos (1U)
#define SDMMC_MASK_DCRCFAILIE_Msk (0x1U << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
#define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
#define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
#define SDMMC_MASK_TXUNDERRIE_Pos (4U)
#define SDMMC_MASK_TXUNDERRIE_Msk (0x1U << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
#define SDMMC_MASK_RXOVERRIE_Pos (5U)
#define SDMMC_MASK_RXOVERRIE_Msk (0x1U << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
#define SDMMC_MASK_CMDRENDIE_Pos (6U)
#define SDMMC_MASK_CMDRENDIE_Msk (0x1U << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
#define SDMMC_MASK_CMDSENTIE_Pos (7U)
#define SDMMC_MASK_CMDSENTIE_Msk (0x1U << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
#define SDMMC_MASK_DATAENDIE_Pos (8U)
#define SDMMC_MASK_DATAENDIE_Msk (0x1U << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
#define SDMMC_MASK_DHOLDIE_Pos (9U)
#define SDMMC_MASK_DHOLDIE_Msk (0x1U << SDMMC_MASK_DHOLDIE_Pos) /*!< 0x00000200 */
#define SDMMC_MASK_DHOLDIE SDMMC_MASK_DHOLDIE_Msk /*!<Data Hold Interrupt Enable */
#define SDMMC_MASK_DBCKENDIE_Pos (10U)
#define SDMMC_MASK_DBCKENDIE_Msk (0x1U << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
#define SDMMC_MASK_DABORTIE_Pos (11U)
#define SDMMC_MASK_DABORTIE_Msk (0x1U << SDMMC_MASK_DABORTIE_Pos) /*!< 0x00000800 */
#define SDMMC_MASK_DABORTIE SDMMC_MASK_DABORTIE_Msk /*!<Data transfer aborted interrupt enable */
#define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
#define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
#define SDMMC_MASK_RXFIFOFIE_Pos (17U)
#define SDMMC_MASK_RXFIFOFIE_Msk (0x1U << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
#define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1U << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0ENDIE interrupt Enable */
#define SDMMC_MASK_SDIOITIE_Pos (22U)
#define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDMMC Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE_Pos (23U)
#define SDMMC_MASK_ACKFAILIE_Msk (0x1U << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1U << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE_Pos (25U)
#define SDMMC_MASK_VSWENDIE_Msk (0x1U << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE_Pos (26U)
#define SDMMC_MASK_CKSTOPIE_Msk (0x1U << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x04000000 */
#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE_Pos (28U)
#define SDMMC_MASK_IDMABTCIE_Msk (0x1U << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
/***************** Bit definition for SDMMC_FIFOCNT register *****************/
#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
#define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
#define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
/****************** Bit definition for SDMMC_FIFO register *******************/
#define SDMMC_FIFO_FIFODATA_Pos (0U)
#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
/****************** Bit definition for SDMMC_IDMACTRL register ****************/
#define SDMMC_IDMA_IDMAEN_Pos (0U)
#define SDMMC_IDMA_IDMAEN_Msk (0x1U << SDMMC_IDMA_IDMAEN_Pos) /*!< 0x00000001 */
#define SDMMC_IDMA_IDMAEN SDMMC_IDMA_IDMAEN_Msk /*!< Enable the internal DMA of the SDMMC peripheral */
#define SDMMC_IDMA_IDMABMODE_Pos (1U)
#define SDMMC_IDMA_IDMABMODE_Msk (0x1U << SDMMC_IDMA_IDMABMODE_Pos) /*!< 0x00000002 */
#define SDMMC_IDMA_IDMABMODE SDMMC_IDMA_IDMABMODE_Msk /*!< Enable double buffer mode for IDMA */
#define SDMMC_IDMA_IDMABACT_Pos (2U)
#define SDMMC_IDMA_IDMABACT_Msk (0x1U << SDMMC_IDMA_IDMABACT_Pos) /*!< 0x00000004 */
#define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk /*!< Uses buffer 1 when double buffer mode is selected */
/********************** Bit definition for SDMMC_VERR register *****************/
#define SDMMC_VERR_MINREV_Pos (0U)
#define SDMMC_VERR_MINREV_Msk (0xFU << SDMMC_VERR_MINREV_Pos) /*!< 0x0000000F */
#define SDMMC_VERR_MINREV SDMMC_VERR_MINREV_Msk /*!< Minor Revision number */
#define SDMMC_VERR_MAJREV_Pos (4U)
#define SDMMC_VERR_MAJREV_Msk (0xFU << SDMMC_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define SDMMC_VERR_MAJREV SDMMC_VERR_MAJREV_Msk /*!< Major Revision number */
/********************** Bit definition for SDMMC_IPIDR register ****************/
#define SDMMC_IPIDR_IPID_Pos (0U)
#define SDMMC_IPIDR_IPID_Msk (0xFFFFFFFFU << SDMMC_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_IPIDR_IPID SDMMC_IPIDR_IPID_Msk /*!< IP Identification */
/********************** Bit definition for SDMMC_SIDR register *****************/
#define SDMMC_SIDR_SID_Pos (0U)
#define SDMMC_SIDR_SID_Msk (0xFFFFFFFFU << SDMMC_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_SIDR_SID SDMMC_SIDR_SID_Msk /*!< IP size identification */
/******************************************************************************/
/* */
/* Delay Block Interface (DLYB) */
/* */
/******************************************************************************/
/******************* Bit definition for DLYB_CR register ********************/
#define DLYB_CR_DEN_Pos (0U)
#define DLYB_CR_DEN_Msk (0x1U << DLYB_CR_DEN_Pos) /*!< 0x00000001 */
#define DLYB_CR_DEN DLYB_CR_DEN_Msk /*!<Delay Block enable */
#define DLYB_CR_SEN_Pos (1U)
#define DLYB_CR_SEN_Msk (0x1U << DLYB_CR_SEN_Pos) /*!< 0x00000002 */
#define DLYB_CR_SEN DLYB_CR_SEN_Msk /*!<Sampler length enable */
/******************* Bit definition for DLYB_CFGR register ********************/
#define DLYB_CFGR_SEL_Pos (0U)
#define DLYB_CFGR_SEL_Msk (0xFU << DLYB_CFGR_SEL_Pos) /*!< 0x0000000F */
#define DLYB_CFGR_SEL DLYB_CFGR_SEL_Msk /*!<Select the phase for the Output clock[3:0] */
#define DLYB_CFGR_SEL_0 (0x1U << DLYB_CFGR_SEL_Pos) /*!< 0x00000001 */
#define DLYB_CFGR_SEL_1 (0x2U << DLYB_CFGR_SEL_Pos) /*!< 0x00000002 */
#define DLYB_CFGR_SEL_2 (0x3U << DLYB_CFGR_SEL_Pos) /*!< 0x00000003 */
#define DLYB_CFGR_SEL_3 (0x8U << DLYB_CFGR_SEL_Pos) /*!< 0x00000008 */
#define DLYB_CFGR_UNIT_Pos (8U)
#define DLYB_CFGR_UNIT_Msk (0x7FU << DLYB_CFGR_UNIT_Pos) /*!< 0x00007F00 */
#define DLYB_CFGR_UNIT DLYB_CFGR_UNIT_Msk /*!<Delay Defines the delay of a Unit delay cell[6:0] */
#define DLYB_CFGR_UNIT_0 (0x01U << DLYB_CFGR_UNIT_Pos) /*!< 0x00000100 */
#define DLYB_CFGR_UNIT_1 (0x02U << DLYB_CFGR_UNIT_Pos) /*!< 0x00000200 */
#define DLYB_CFGR_UNIT_2 (0x04U << DLYB_CFGR_UNIT_Pos) /*!< 0x00000400 */
#define DLYB_CFGR_UNIT_3 (0x08U << DLYB_CFGR_UNIT_Pos) /*!< 0x00000800 */
#define DLYB_CFGR_UNIT_4 (0x10U << DLYB_CFGR_UNIT_Pos) /*!< 0x00001000 */
#define DLYB_CFGR_UNIT_5 (0x20U << DLYB_CFGR_UNIT_Pos) /*!< 0x00002000 */
#define DLYB_CFGR_UNIT_6 (0x40U << DLYB_CFGR_UNIT_Pos) /*!< 0x00004000 */
#define DLYB_CFGR_LNG_Pos (16U)
#define DLYB_CFGR_LNG_Msk (0xFFFU << DLYB_CFGR_LNG_Pos) /*!< 0x0FFF0000 */
#define DLYB_CFGR_LNG DLYB_CFGR_LNG_Msk /*!<Delay line length value[11:0] */
#define DLYB_CFGR_LNG_0 (0x001U << DLYB_CFGR_LNG_Pos) /*!< 0x00010000 */
#define DLYB_CFGR_LNG_1 (0x002U << DLYB_CFGR_LNG_Pos) /*!< 0x00020000 */
#define DLYB_CFGR_LNG_2 (0x004U << DLYB_CFGR_LNG_Pos) /*!< 0x00040000 */
#define DLYB_CFGR_LNG_3 (0x008U << DLYB_CFGR_LNG_Pos) /*!< 0x00080000 */
#define DLYB_CFGR_LNG_4 (0x010U << DLYB_CFGR_LNG_Pos) /*!< 0x00100000 */
#define DLYB_CFGR_LNG_5 (0x020U << DLYB_CFGR_LNG_Pos) /*!< 0x00200000 */
#define DLYB_CFGR_LNG_6 (0x040U << DLYB_CFGR_LNG_Pos) /*!< 0x00400000 */
#define DLYB_CFGR_LNG_7 (0x080U << DLYB_CFGR_LNG_Pos) /*!< 0x00800000 */
#define DLYB_CFGR_LNG_8 (0x100U << DLYB_CFGR_LNG_Pos) /*!< 0x01000000 */
#define DLYB_CFGR_LNG_9 (0x200U << DLYB_CFGR_LNG_Pos) /*!< 0x02000000 */
#define DLYB_CFGR_LNG_10 (0x400U << DLYB_CFGR_LNG_Pos) /*!< 0x04000000 */
#define DLYB_CFGR_LNG_11 (0x800U << DLYB_CFGR_LNG_Pos) /*!< 0x08000000 */
#define DLYB_CFGR_LNGF_Pos (31U)
#define DLYB_CFGR_LNGF_Msk (0x1U << DLYB_CFGR_LNGF_Pos) /*!< 0x80000000 */
#define DLYB_CFGR_LNGF DLYB_CFGR_LNGF_Msk /*!<Length valid flag */
/********************** Bit definition for DLYB_VERR register *****************/
#define DLYB_VERR_MINREV_Pos (0U)
#define DLYB_VERR_MINREV_Msk (0xFU << DLYB_VERR_MINREV_Pos) /*!< 0x0000000F */
#define DLYB_VERR_MINREV DLYB_VERR_MINREV_Msk /*!< Minor Revision number */
#define DLYB_VERR_MAJREV_Pos (4U)
#define DLYB_VERR_MAJREV_Msk (0xFU << DLYB_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define DLYB_VERR_MAJREV DLYB_VERR_MAJREV_Msk /*!< Major Revision number */
/********************** Bit definition for DLYB_IPIDR register ****************/
#define DLYB_IPIDR_IPID_Pos (0U)
#define DLYB_IPIDR_IPID_Msk (0xFFFFFFFFU << DLYB_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
#define DLYB_IPIDR_IPID DLYB_IPIDR_IPID_Msk /*!< IP Identification */
/********************** Bit definition for DLYB_SIDR register *****************/
#define DLYB_SIDR_SID_Pos (0U)
#define DLYB_SIDR_SID_Msk (0xFFFFFFFFU << DLYB_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define DLYB_SIDR_SID DLYB_SIDR_SID_Msk /*!< IP size identification */
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
/* */
/******************************************************************************/
/******************* Bit definition for SPI_CR1 register ********************/
#define SPI_CR1_SPE_Pos (0U)
#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000001 */
#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<Serial Peripheral Enable */
#define SPI_CR1_MASRX_Pos (8U)
#define SPI_CR1_MASRX_Msk (0x1U << SPI_CR1_MASRX_Pos) /*!< 0x00000100 */
#define SPI_CR1_MASRX SPI_CR1_MASRX_Msk /*!<Master automatic SUSP in Receive mode */
#define SPI_CR1_CSTART_Pos (9U)
#define SPI_CR1_CSTART_Msk (0x1U << SPI_CR1_CSTART_Pos) /*!< 0x00000200 */
#define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master transfer start */
#define SPI_CR1_CSUSP_Pos (10U)
#define SPI_CR1_CSUSP_Msk (0x1U << SPI_CR1_CSUSP_Pos) /*!< 0x00000400 */
#define SPI_CR1_CSUSP SPI_CR1_CSUSP_Msk /*!<Master SUSPend request */
#define SPI_CR1_HDDIR_Pos (11U)
#define SPI_CR1_HDDIR_Msk (0x1U << SPI_CR1_HDDIR_Pos) /*!< 0x00000800 */
#define SPI_CR1_HDDIR SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode */
#define SPI_CR1_SSI_Pos (12U)
#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00001000 */
#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal SS signal input level */
#define SPI_CR1_CRC33_17_Pos (13U)
#define SPI_CR1_CRC33_17_Msk (0x1U << SPI_CR1_CRC33_17_Pos) /*!< 0x00002000 */
#define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk /*!<32-bit CRC polynomial configuration */
#define SPI_CR1_RCRCINI_Pos (14U)
#define SPI_CR1_RCRCINI_Msk (0x1U << SPI_CR1_RCRCINI_Pos) /*!< 0x00004000 */
#define SPI_CR1_RCRCINI SPI_CR1_RCRCINI_Msk /*!<CRC calculation initialization pattern control for receiver */
#define SPI_CR1_TCRCINI_Pos (15U)
#define SPI_CR1_TCRCINI_Msk (0x1U << SPI_CR1_TCRCINI_Pos) /*!< 0x00008000 */
#define SPI_CR1_TCRCINI SPI_CR1_TCRCINI_Msk /*!<CRC calculation initialization pattern control for transmitter */
#define SPI_CR1_IOLOCK_Pos (16U)
#define SPI_CR1_IOLOCK_Msk (0x1U << SPI_CR1_IOLOCK_Pos) /*!< 0x00010000 */
#define SPI_CR1_IOLOCK SPI_CR1_IOLOCK_Msk /*!<Locking the AF configuration of associated IOs */
/******************* Bit definition for SPI_CR2 register ********************/
#define SPI_CR2_TSER_Pos (16U)
#define SPI_CR2_TSER_Msk (0xFFFFU << SPI_CR2_TSER_Pos) /*!< 0xFFFF0000 */
#define SPI_CR2_TSER SPI_CR2_TSER_Msk /*!<Number of data transfer extension */
#define SPI_CR2_TSIZE_Pos (0U)
#define SPI_CR2_TSIZE_Msk (0xFFFFU << SPI_CR2_TSIZE_Pos) /*!< 0x0000FFFF */
#define SPI_CR2_TSIZE SPI_CR2_TSIZE_Msk /*!<Number of data at current transfer */
/******************* Bit definition for SPI_CFG1 register ********************/
#define SPI_CFG1_DSIZE_Pos (0U)
#define SPI_CFG1_DSIZE_Msk (0x1FU << SPI_CFG1_DSIZE_Pos) /*!< 0x0000001F */
#define SPI_CFG1_DSIZE SPI_CFG1_DSIZE_Msk /*!<DSIZE [4:0]: Number of bits in at single SPI data frame */
#define SPI_CFG1_DSIZE_0 (0x01U << SPI_CFG1_DSIZE_Pos) /*!< 0x00000001 */
#define SPI_CFG1_DSIZE_1 (0x02U << SPI_CFG1_DSIZE_Pos) /*!< 0x00000002 */
#define SPI_CFG1_DSIZE_2 (0x04U << SPI_CFG1_DSIZE_Pos) /*!< 0x00000004 */
#define SPI_CFG1_DSIZE_3 (0x08U << SPI_CFG1_DSIZE_Pos) /*!< 0x00000008 */
#define SPI_CFG1_DSIZE_4 (0x10U << SPI_CFG1_DSIZE_Pos) /*!< 0x00000010 */
#define SPI_CFG1_FTHLV_Pos (5U)
#define SPI_CFG1_FTHLV_Msk (0xFU << SPI_CFG1_FTHLV_Pos) /*!< 0x000001E0 */
#define SPI_CFG1_FTHLV SPI_CFG1_FTHLV_Msk /*!<FTHVL [3:0]: FIFO threshold level*/
#define SPI_CFG1_FTHLV_0 (0x1U << SPI_CFG1_FTHLV_Pos) /*!< 0x00000020 */
#define SPI_CFG1_FTHLV_1 (0x2U << SPI_CFG1_FTHLV_Pos) /*!< 0x00000040 */
#define SPI_CFG1_FTHLV_2 (0x4U << SPI_CFG1_FTHLV_Pos) /*!< 0x00000080 */
#define SPI_CFG1_FTHLV_3 (0x8U << SPI_CFG1_FTHLV_Pos) /*!< 0x00000100 */
#define SPI_CFG1_UDRCFG_Pos (9U)
#define SPI_CFG1_UDRCFG_Msk (0x3U << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000600 */
#define SPI_CFG1_UDRCFG SPI_CFG1_UDRCFG_Msk /*!<UDRCFG [1:0]: Behavior of slave transmitter at underrun condition*/
#define SPI_CFG1_UDRCFG_0 (0x1U << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000200 */
#define SPI_CFG1_UDRCFG_1 (0x2U << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000400 */
#define SPI_CFG1_UDRDET_Pos (11U)
#define SPI_CFG1_UDRDET_Msk (0x3U << SPI_CFG1_UDRDET_Pos) /*!< 0x00001800 */
#define SPI_CFG1_UDRDET SPI_CFG1_UDRDET_Msk /*!<UDRDET [1:0]: Detection of underrun condition at slave transmitter*/
#define SPI_CFG1_UDRDET_0 (0x1U << SPI_CFG1_UDRDET_Pos) /*!< 0x00000800 */
#define SPI_CFG1_UDRDET_1 (0x2U << SPI_CFG1_UDRDET_Pos) /*!< 0x00001000 */
#define SPI_CFG1_RXDMAEN_Pos (14U)
#define SPI_CFG1_RXDMAEN_Msk (0x1U << SPI_CFG1_RXDMAEN_Pos) /*!< 0x00004000 */
#define SPI_CFG1_RXDMAEN SPI_CFG1_RXDMAEN_Msk /*!<Rx DMA stream enable */
#define SPI_CFG1_TXDMAEN_Pos (15U)
#define SPI_CFG1_TXDMAEN_Msk (0x1U << SPI_CFG1_TXDMAEN_Pos) /*!< 0x00008000 */
#define SPI_CFG1_TXDMAEN SPI_CFG1_TXDMAEN_Msk /*!<Tx DMA stream enable */
#define SPI_CFG1_CRCSIZE_Pos (16U)
#define SPI_CFG1_CRCSIZE_Msk (0x1FU << SPI_CFG1_CRCSIZE_Pos) /*!< 0x001F0000 */
#define SPI_CFG1_CRCSIZE SPI_CFG1_CRCSIZE_Msk /*!<CRCSIZE [4:0]: Length of CRC frame*/
#define SPI_CFG1_CRCSIZE_0 (0x01U << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00010000 */
#define SPI_CFG1_CRCSIZE_1 (0x02U << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00020000 */
#define SPI_CFG1_CRCSIZE_2 (0x04U << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00040000 */
#define SPI_CFG1_CRCSIZE_3 (0x08U << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00080000 */
#define SPI_CFG1_CRCSIZE_4 (0x10U << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00100000 */
#define SPI_CFG1_CRCEN_Pos (22U)
#define SPI_CFG1_CRCEN_Msk (0x1U << SPI_CFG1_CRCEN_Pos) /*!< 0x00400000 */
#define SPI_CFG1_CRCEN SPI_CFG1_CRCEN_Msk /*!<Hardware CRC computation enable */
#define SPI_CFG1_MBR_Pos (28U)
#define SPI_CFG1_MBR_Msk (0x7U << SPI_CFG1_MBR_Pos) /*!< 0x70000000 */
#define SPI_CFG1_MBR SPI_CFG1_MBR_Msk /*!<Master baud rate */
#define SPI_CFG1_MBR_0 (0x1U << SPI_CFG1_MBR_Pos) /*!< 0x10000000 */
#define SPI_CFG1_MBR_1 (0x2U << SPI_CFG1_MBR_Pos) /*!< 0x20000000 */
#define SPI_CFG1_MBR_2 (0x4U << SPI_CFG1_MBR_Pos) /*!< 0x40000000 */
/******************* Bit definition for SPI_CFG2 register ********************/
#define SPI_CFG2_MSSI_Pos (0U)
#define SPI_CFG2_MSSI_Msk (0xFU << SPI_CFG2_MSSI_Pos) /*!< 0x0000000F */
#define SPI_CFG2_MSSI SPI_CFG2_MSSI_Msk /*!<Master SS Idleness */
#define SPI_CFG2_MSSI_0 (0x1U << SPI_CFG2_MSSI_Pos) /*!< 0x00000001 */
#define SPI_CFG2_MSSI_1 (0x2U << SPI_CFG2_MSSI_Pos) /*!< 0x00000002 */
#define SPI_CFG2_MSSI_2 (0x4U << SPI_CFG2_MSSI_Pos) /*!< 0x00000004 */
#define SPI_CFG2_MSSI_3 (0x8U << SPI_CFG2_MSSI_Pos) /*!< 0x00000008 */
#define SPI_CFG2_MIDI_Pos (4U)
#define SPI_CFG2_MIDI_Msk (0xFU << SPI_CFG2_MIDI_Pos) /*!< 0x000000F0 */
#define SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Data Idleness */
#define SPI_CFG2_MIDI_0 (0x1U << SPI_CFG2_MIDI_Pos) /*!< 0x00000010 */
#define SPI_CFG2_MIDI_1 (0x2U << SPI_CFG2_MIDI_Pos) /*!< 0x00000020 */
#define SPI_CFG2_MIDI_2 (0x4U << SPI_CFG2_MIDI_Pos) /*!< 0x00000040 */
#define SPI_CFG2_MIDI_3 (0x8U << SPI_CFG2_MIDI_Pos) /*!< 0x00000080 */
#define SPI_CFG2_IOSWP_Pos (15U)
#define SPI_CFG2_IOSWP_Msk (0x1U << SPI_CFG2_IOSWP_Pos) /*!< 0x00008000 */
#define SPI_CFG2_IOSWP SPI_CFG2_IOSWP_Msk /*!<Swap functionality of MISO and MOSI pins */
#define SPI_CFG2_COMM_Pos (17U)
#define SPI_CFG2_COMM_Msk (0x3U << SPI_CFG2_COMM_Pos) /*!< 0x00060000 */
#define SPI_CFG2_COMM SPI_CFG2_COMM_Msk /*!<COMM [1:0]: SPI Communication Mode*/
#define SPI_CFG2_COMM_0 (0x1U << SPI_CFG2_COMM_Pos) /*!< 0x00020000 */
#define SPI_CFG2_COMM_1 (0x2U << SPI_CFG2_COMM_Pos) /*!< 0x00040000 */
#define SPI_CFG2_SP_Pos (19U)
#define SPI_CFG2_SP_Msk (0x7U << SPI_CFG2_SP_Pos) /*!< 0x00380000 */
#define SPI_CFG2_SP SPI_CFG2_SP_Msk /*!<SP[2:0]: Serial Protocol */
#define SPI_CFG2_SP_0 (0x1U << SPI_CFG2_SP_Pos) /*!< 0x00080000 */
#define SPI_CFG2_SP_1 (0x2U << SPI_CFG2_SP_Pos) /*!< 0x00100000 */
#define SPI_CFG2_SP_2 (0x4U << SPI_CFG2_SP_Pos) /*!< 0x00200000 */
#define SPI_CFG2_MASTER_Pos (22U)
#define SPI_CFG2_MASTER_Msk (0x1U << SPI_CFG2_MASTER_Pos) /*!< 0x00400000 */
#define SPI_CFG2_MASTER SPI_CFG2_MASTER_Msk /*!<SPI Master */
#define SPI_CFG2_LSBFRST_Pos (23U)
#define SPI_CFG2_LSBFRST_Msk (0x1U << SPI_CFG2_LSBFRST_Pos) /*!< 0x00800000 */
#define SPI_CFG2_LSBFRST SPI_CFG2_LSBFRST_Msk /*!<Data frame format */
#define SPI_CFG2_CPHA_Pos (24U)
#define SPI_CFG2_CPHA_Msk (0x1U << SPI_CFG2_CPHA_Pos) /*!< 0x01000000 */
#define SPI_CFG2_CPHA SPI_CFG2_CPHA_Msk /*!<Clock Phase */
#define SPI_CFG2_CPOL_Pos (25U)
#define SPI_CFG2_CPOL_Msk (0x1U << SPI_CFG2_CPOL_Pos) /*!< 0x02000000 */
#define SPI_CFG2_CPOL SPI_CFG2_CPOL_Msk /*!<Clock Polarity */
#define SPI_CFG2_SSM_Pos (26U)
#define SPI_CFG2_SSM_Msk (0x1U << SPI_CFG2_SSM_Pos) /*!< 0x04000000 */
#define SPI_CFG2_SSM SPI_CFG2_SSM_Msk /*!<Software slave management */
#define SPI_CFG2_SSIOP_Pos (28U)
#define SPI_CFG2_SSIOP_Msk (0x1U << SPI_CFG2_SSIOP_Pos) /*!< 0x10000000 */
#define SPI_CFG2_SSIOP SPI_CFG2_SSIOP_Msk /*!<SS input/output polarity */
#define SPI_CFG2_SSOE_Pos (29U)
#define SPI_CFG2_SSOE_Msk (0x1U << SPI_CFG2_SSOE_Pos) /*!< 0x20000000 */
#define SPI_CFG2_SSOE SPI_CFG2_SSOE_Msk /*!<SS output enable */
#define SPI_CFG2_SSOM_Pos (30U)
#define SPI_CFG2_SSOM_Msk (0x1U << SPI_CFG2_SSOM_Pos) /*!< 0x40000000 */
#define SPI_CFG2_SSOM SPI_CFG2_SSOM_Msk /*!<SS output management in master mode */
#define SPI_CFG2_AFCNTR_Pos (31U)
#define SPI_CFG2_AFCNTR_Msk (0x1U << SPI_CFG2_AFCNTR_Pos) /*!< 0x80000000 */
#define SPI_CFG2_AFCNTR SPI_CFG2_AFCNTR_Msk /*!<Alternate function GPIOs control */
/******************* Bit definition for SPI_IER register ********************/
#define SPI_IER_RXPIE_Pos (0U)
#define SPI_IER_RXPIE_Msk (0x1U << SPI_IER_RXPIE_Pos) /*!< 0x00000001 */
#define SPI_IER_RXPIE SPI_IER_RXPIE_Msk /*!<RXP Interrupt Enable */
#define SPI_IER_TXPIE_Pos (1U)
#define SPI_IER_TXPIE_Msk (0x1U << SPI_IER_TXPIE_Pos) /*!< 0x00000002 */
#define SPI_IER_TXPIE SPI_IER_TXPIE_Msk /*!<TXP interrupt enable */
#define SPI_IER_DXPIE_Pos (2U)
#define SPI_IER_DXPIE_Msk (0x1U << SPI_IER_DXPIE_Pos) /*!< 0x00000004 */
#define SPI_IER_DXPIE SPI_IER_DXPIE_Msk /*!<DXP interrupt enable */
#define SPI_IER_EOTIE_Pos (3U)
#define SPI_IER_EOTIE_Msk (0x1U << SPI_IER_EOTIE_Pos) /*!< 0x00000008 */
#define SPI_IER_EOTIE SPI_IER_EOTIE_Msk /*!<EOT/SUSP/TXC interrupt enable */
#define SPI_IER_TXTFIE_Pos (4U)
#define SPI_IER_TXTFIE_Msk (0x1U << SPI_IER_TXTFIE_Pos) /*!< 0x00000010 */
#define SPI_IER_TXTFIE SPI_IER_TXTFIE_Msk /*!<TXTF interrupt enable */
#define SPI_IER_UDRIE_Pos (5U)
#define SPI_IER_UDRIE_Msk (0x1U << SPI_IER_UDRIE_Pos) /*!< 0x00000020 */
#define SPI_IER_UDRIE SPI_IER_UDRIE_Msk /*!<UDR interrupt enable */
#define SPI_IER_OVRIE_Pos (6U)
#define SPI_IER_OVRIE_Msk (0x1U << SPI_IER_OVRIE_Pos) /*!< 0x00000040 */
#define SPI_IER_OVRIE SPI_IER_OVRIE_Msk /*!<OVR interrupt enable */
#define SPI_IER_CRCEIE_Pos (7U)
#define SPI_IER_CRCEIE_Msk (0x1U << SPI_IER_CRCEIE_Pos) /*!< 0x00000080 */
#define SPI_IER_CRCEIE SPI_IER_CRCEIE_Msk /*!<CRC interrupt enable */
#define SPI_IER_TIFREIE_Pos (8U)
#define SPI_IER_TIFREIE_Msk (0x1U << SPI_IER_TIFREIE_Pos) /*!< 0x00000100 */
#define SPI_IER_TIFREIE SPI_IER_TIFREIE_Msk /*!<TI Frame Error interrupt enable */
#define SPI_IER_MODFIE_Pos (9U)
#define SPI_IER_MODFIE_Msk (0x1U << SPI_IER_MODFIE_Pos) /*!< 0x00000200 */
#define SPI_IER_MODFIE SPI_IER_MODFIE_Msk /*!<MODF interrupt enable */
#define SPI_IER_TSERFIE_Pos (10U)
#define SPI_IER_TSERFIE_Msk (0x1U << SPI_IER_TSERFIE_Pos) /*!< 0x00000400 */
#define SPI_IER_TSERFIE SPI_IER_TSERFIE_Msk /*!<TSERF interrupt enable */
/******************* Bit definition for SPI_SR register ********************/
#define SPI_SR_RXP_Pos (0U)
#define SPI_SR_RXP_Msk (0x1U << SPI_SR_RXP_Pos) /*!< 0x00000001 */
#define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet available */
#define SPI_SR_TXP_Pos (1U)
#define SPI_SR_TXP_Msk (0x1U << SPI_SR_TXP_Pos) /*!< 0x00000002 */
#define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet space available */
#define SPI_SR_DXP_Pos (2U)
#define SPI_SR_DXP_Msk (0x1U << SPI_SR_DXP_Pos) /*!< 0x00000004 */
#define SPI_SR_DXP SPI_SR_DXP_Msk /*!<Duplex Packet available */
#define SPI_SR_EOT_Pos (3U)
#define SPI_SR_EOT_Msk (0x1U << SPI_SR_EOT_Pos) /*!< 0x00000008 */
#define SPI_SR_EOT SPI_SR_EOT_Msk /*!<Duplex Packet available */
#define SPI_SR_TXTF_Pos (4U)
#define SPI_SR_TXTF_Msk (0x1U << SPI_SR_TXTF_Pos) /*!< 0x00000010 */
#define SPI_SR_TXTF SPI_SR_TXTF_Msk /*!<Transmission Transfer Filled */
#define SPI_SR_UDR_Pos (5U)
#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000020 */
#define SPI_SR_UDR SPI_SR_UDR_Msk /*!<UDR at Slave transmission */
#define SPI_SR_OVR_Pos (6U)
#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
#define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet available */
#define SPI_SR_CRCE_Pos (7U)
#define SPI_SR_CRCE_Msk (0x1U << SPI_SR_CRCE_Pos) /*!< 0x00000080 */
#define SPI_SR_CRCE SPI_SR_CRCE_Msk /*!<CRC Error Detected */
#define SPI_SR_TIFRE_Pos (8U)
#define SPI_SR_TIFRE_Msk (0x1U << SPI_SR_TIFRE_Pos) /*!< 0x00000100 */
#define SPI_SR_TIFRE SPI_SR_TIFRE_Msk /*!<TI frame format error Detected */
#define SPI_SR_MODF_Pos (9U)
#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000200 */
#define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode Fault Detected */
#define SPI_SR_TSERF_Pos (10U)
#define SPI_SR_TSERF_Msk (0x1U << SPI_SR_TSERF_Pos) /*!< 0x00000400 */
#define SPI_SR_TSERF SPI_SR_TSERF_Msk /*!<Additional number of SPI data to be transacted was reload */
#define SPI_SR_SUSP_Pos (11U)
#define SPI_SR_SUSP_Msk (0x1U << SPI_SR_SUSP_Pos) /*!< 0x00000800 */
#define SPI_SR_SUSP SPI_SR_SUSP_Msk /*!<SUSP is set by hardware */
#define SPI_SR_TXC_Pos (12U)
#define SPI_SR_TXC_Msk (0x1U << SPI_SR_TXC_Pos) /*!< 0x00001000 */
#define SPI_SR_TXC SPI_SR_TXC_Msk /*!<TxFIFO transmission complete */
#define SPI_SR_RXPLVL_Pos (13U)
#define SPI_SR_RXPLVL_Msk (0x3U << SPI_SR_RXPLVL_Pos) /*!< 0x00006000 */
#define SPI_SR_RXPLVL SPI_SR_RXPLVL_Msk /*!<RxFIFO Packing Level */
#define SPI_SR_RXPLVL_0 (0x1U << SPI_SR_RXPLVL_Pos) /*!< 0x00002000 */
#define SPI_SR_RXPLVL_1 (0x2U << SPI_SR_RXPLVL_Pos) /*!< 0x00004000 */
#define SPI_SR_RXWNE_Pos (15U)
#define SPI_SR_RXWNE_Msk (0x1U << SPI_SR_RXWNE_Pos) /*!< 0x00008000 */
#define SPI_SR_RXWNE SPI_SR_RXWNE_Msk /*!<Rx FIFO Word Not Empty */
#define SPI_SR_CTSIZE_Pos (16U)
#define SPI_SR_CTSIZE_Msk (0xFFFFU << SPI_SR_CTSIZE_Pos) /*!< 0xFFFF0000 */
#define SPI_SR_CTSIZE SPI_SR_CTSIZE_Msk /*!<Number of data frames remaining in TSIZE */
/******************* Bit definition for SPI_IFCR register ********************/
#define SPI_IFCR_EOTC_Pos (3U)
#define SPI_IFCR_EOTC_Msk (0x1U << SPI_IFCR_EOTC_Pos) /*!< 0x00000008 */
#define SPI_IFCR_EOTC SPI_IFCR_EOTC_Msk /*!<End Of Transfer flag clear */
#define SPI_IFCR_TXTFC_Pos (4U)
#define SPI_IFCR_TXTFC_Msk (0x1U << SPI_IFCR_TXTFC_Pos) /*!< 0x00000010 */
#define SPI_IFCR_TXTFC SPI_IFCR_TXTFC_Msk /*!<Transmission Transfer Filled flag clear */
#define SPI_IFCR_UDRC_Pos (5U)
#define SPI_IFCR_UDRC_Msk (0x1U << SPI_IFCR_UDRC_Pos) /*!< 0x00000020 */
#define SPI_IFCR_UDRC SPI_IFCR_UDRC_Msk /*!<Underrun flag clear */
#define SPI_IFCR_OVRC_Pos (6U)
#define SPI_IFCR_OVRC_Msk (0x1U << SPI_IFCR_OVRC_Pos) /*!< 0x00000040 */
#define SPI_IFCR_OVRC SPI_IFCR_OVRC_Msk /*!<Overrun flag clear */
#define SPI_IFCR_CRCEC_Pos (7U)
#define SPI_IFCR_CRCEC_Msk (0x1U << SPI_IFCR_CRCEC_Pos) /*!< 0x00000080 */
#define SPI_IFCR_CRCEC SPI_IFCR_CRCEC_Msk /*!<CRC Error flag clear */
#define SPI_IFCR_TIFREC_Pos (8U)
#define SPI_IFCR_TIFREC_Msk (0x1U << SPI_IFCR_TIFREC_Pos) /*!< 0x00000100 */
#define SPI_IFCR_TIFREC SPI_IFCR_TIFREC_Msk /*!<TI frame format error flag clear */
#define SPI_IFCR_MODFC_Pos (9U)
#define SPI_IFCR_MODFC_Msk (0x1U << SPI_IFCR_MODFC_Pos) /*!< 0x00000200 */
#define SPI_IFCR_MODFC SPI_IFCR_MODFC_Msk /*!<Mode Fault flag clear */
#define SPI_IFCR_TSERFC_Pos (10U)
#define SPI_IFCR_TSERFC_Msk (0x1U << SPI_IFCR_TSERFC_Pos) /*!< 0x00000400 */
#define SPI_IFCR_TSERFC SPI_IFCR_TSERFC_Msk /*!<TSERFC flag clear */
#define SPI_IFCR_SUSPC_Pos (11U)
#define SPI_IFCR_SUSPC_Msk (0x1U << SPI_IFCR_SUSPC_Pos) /*!< 0x00000800 */
#define SPI_IFCR_SUSPC SPI_IFCR_SUSPC_Msk /*!<SUSPend flag clear */
/******************* Bit definition for SPI_TXDR register ********************/
#define SPI_TXDR_TXDR_Pos (0U)
#define SPI_TXDR_TXDR_Msk (0xFFFFFFFFU << SPI_TXDR_TXDR_Pos) /*!< 0xFFFFFFFF */
#define SPI_TXDR_TXDR SPI_TXDR_TXDR_Msk /* Transmit Data Register */
/******************* Bit definition for SPI_RXDR register ********************/
#define SPI_RXDR_RXDR_Pos (0U)
#define SPI_RXDR_RXDR_Msk (0xFFFFFFFFU << SPI_RXDR_RXDR_Pos) /*!< 0xFFFFFFFF */
#define SPI_RXDR_RXDR SPI_RXDR_RXDR_Msk /* Receive Data Register */
/******************* Bit definition for SPI_CRCPOLY register ********************/
#define SPI_CRCPOLY_CRCPOLY_Pos (0U)
#define SPI_CRCPOLY_CRCPOLY_Msk (0xFFFFFFFFU << SPI_CRCPOLY_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
#define SPI_CRCPOLY_CRCPOLY SPI_CRCPOLY_CRCPOLY_Msk /* CRC Polynomial register */
/******************* Bit definition for SPI_TXCRC register ********************/
#define SPI_TXCRC_TXCRC_Pos (0U)
#define SPI_TXCRC_TXCRC_Msk (0xFFFFFFFFU << SPI_TXCRC_TXCRC_Pos) /*!< 0xFFFFFFFF */
#define SPI_TXCRC_TXCRC SPI_TXCRC_TXCRC_Msk /* CRCRegister for transmitter */
/******************* Bit definition for SPI_RXCRC register ********************/
#define SPI_RXCRC_RXCRC_Pos (0U)
#define SPI_RXCRC_RXCRC_Msk (0xFFFFFFFFU << SPI_RXCRC_RXCRC_Pos) /*!< 0xFFFFFFFF */
#define SPI_RXCRC_RXCRC SPI_RXCRC_RXCRC_Msk /* CRCRegister for receiver */
/******************* Bit definition for SPI_UDRDR register ********************/
#define SPI_UDRDR_UDRDR_Pos (0U)
#define SPI_UDRDR_UDRDR_Msk (0xFFFFFFFFU << SPI_UDRDR_UDRDR_Pos) /*!< 0xFFFFFFFF */
#define SPI_UDRDR_UDRDR SPI_UDRDR_UDRDR_Msk /* Data at slave underrun condition */
/****************** Bit definition for SPI_I2SCFGR register *****************/
#define SPI_I2SCFGR_I2SMOD_Pos (0U)
#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000001 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
#define SPI_I2SCFGR_I2SCFG_Pos (1U)
#define SPI_I2SCFGR_I2SCFG_Msk (0x7U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x0000000E */
#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFGR[1:0] bits (I2S configuration mode) */
#define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000002 */
#define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000004 */
#define SPI_I2SCFGR_I2SCFG_2 (0x4U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000008 */
#define SPI_I2SCFGR_I2SSTD_Pos (4U)
#define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] I2S standard selection */
#define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
#define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
#define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
#define SPI_I2SCFGR_DATLEN_Pos (8U)
#define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000300 */
#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] Data length to be transferred */
#define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000100 */
#define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000200 */
#define SPI_I2SCFGR_CHLEN_Pos (10U)
#define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000400 */
#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
#define SPI_I2SCFGR_CKPOL_Pos (11U)
#define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<Steady state clock polarity */
#define SPI_I2SCFGR_FIXCH_Pos (12U)
#define SPI_I2SCFGR_FIXCH_Msk (0x1U << SPI_I2SCFGR_FIXCH_Pos) /*!< 0x00001000 */
#define SPI_I2SCFGR_FIXCH SPI_I2SCFGR_FIXCH_Msk /*!<Fixed channel length in SLAVE */
#define SPI_I2SCFGR_WSINV_Pos (13U)
#define SPI_I2SCFGR_WSINV_Msk (0x1U << SPI_I2SCFGR_WSINV_Pos) /*!< 0x00002000 */
#define SPI_I2SCFGR_WSINV SPI_I2SCFGR_WSINV_Msk /*!<Word select inversion */
#define SPI_I2SCFGR_DATFMT_Pos (14U)
#define SPI_I2SCFGR_DATFMT_Msk (0x1U << SPI_I2SCFGR_DATFMT_Pos) /*!< 0x00003000 */
#define SPI_I2SCFGR_DATFMT SPI_I2SCFGR_DATFMT_Msk /*!<Data format */
#define SPI_I2SCFGR_I2SDIV_Pos (16U)
#define SPI_I2SCFGR_I2SDIV_Msk (0xFFU << SPI_I2SCFGR_I2SDIV_Pos) /*!< 0x00FF0000 */
#define SPI_I2SCFGR_I2SDIV SPI_I2SCFGR_I2SDIV_Msk /*!<I2S Linear prescaler */
#define SPI_I2SCFGR_ODD_Pos (24U)
#define SPI_I2SCFGR_ODD_Msk (0x1U << SPI_I2SCFGR_ODD_Pos) /*!< 0x01000000 */
#define SPI_I2SCFGR_ODD SPI_I2SCFGR_ODD_Msk /*!<Odd factor for the prescaler */
#define SPI_I2SCFGR_MCKOE_Pos (25U)
#define SPI_I2SCFGR_MCKOE_Msk (0x1U << SPI_I2SCFGR_MCKOE_Pos) /*!< 0x02000000 */
#define SPI_I2SCFGR_MCKOE SPI_I2SCFGR_MCKOE_Msk /*!<Master Clock Output Enable */
/********************** Bit definition for SPI_HWCFGR register ***************/
#define SPI_HWCFGR_TXFCFG_Pos (0U)
#define SPI_HWCFGR_TXFCFG_Msk (0xFU << SPI_HWCFGR_TXFCFG_Pos) /*!< 0x0000000F */
#define SPI_HWCFGR_TXFCFG SPI_HWCFGR_TXFCFG_Msk /*!< TxFIFO size */
#define SPI_HWCFGR_RXFCFG_Pos (4U)
#define SPI_HWCFGR_RXFCFG_Msk (0xFU << SPI_HWCFGR_RXFCFG_Pos) /*!< 0x0000000F */
#define SPI_HWCFGR_RXFCFG SPI_HWCFGR_RXFCFG_Msk /*!< RxFIFO size */
#define SPI_HWCFGR_CRCCFG_Pos (8U)
#define SPI_HWCFGR_CRCCFG_Msk (0xFU << SPI_HWCFGR_CRCCFG_Pos) /*!< 0x0000000F */
#define SPI_HWCFGR_CRCCFG SPI_HWCFGR_CRCCFG_Msk /*!< CRC configuration for SPI */
#define SPI_HWCFGR_I2SCFG_Pos (12U)
#define SPI_HWCFGR_I2SCFG_Msk (0xFU << SPI_HWCFGR_I2SCFG_Pos) /*!< 0x0000000F */
#define SPI_HWCFGR_I2SCFG SPI_HWCFGR_I2SCFG_Msk /*!< I2S configuration */
#define SPI_HWCFGR_DSCFG_Pos (16U)
#define SPI_HWCFGR_DSCFG_Msk (0xFU << SPI_HWCFGR_DSCFG_Pos) /*!< 0x0000000F */
#define SPI_HWCFGR_DSCFG SPI_HWCFGR_DSCFG_Msk /*!< SPI data size configuration */
/********************** Bit definition for SPI_VERR register *****************/
#define SPI_VERR_MINREV_Pos (0U)
#define SPI_VERR_MINREV_Msk (0xFU << SPI_VERR_MINREV_Pos) /*!< 0x0000000F */
#define SPI_VERR_MINREV SPI_VERR_MINREV_Msk /*!< Minor Revision number */
#define SPI_VERR_MAJREV_Pos (4U)
#define SPI_VERR_MAJREV_Msk (0xFU << SPI_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define SPI_VERR_MAJREV SPI_VERR_MAJREV_Msk /*!< Major Revision number */
/********************** Bit definition for SPI_IPIDR register ****************/
#define SPI_IPIDR_IPID_Pos (0U)
#define SPI_IPIDR_IPID_Msk (0xFFFFFFFFU << SPI_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
#define SPI_IPIDR_IPID SPI_IPIDR_IPID_Msk /*!< IP Identification */
/********************** Bit definition for SPI_SIDR register *****************/
#define SPI_SIDR_SID_Pos (0U)
#define SPI_SIDR_SID_Msk (0xFFFFFFFFU << SPI_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define SPI_SIDR_SID SPI_SIDR_SID_Msk /*!< IP size identification */
/******************************************************************************/
/* */
/* QUADSPI */
/* */
/******************************************************************************/
/***************** Bit definition for QUADSPI_CR register *******************/
#define QUADSPI_CR_EN_Pos (0U)
#define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
#define QUADSPI_CR_ABORT_Pos (1U)
#define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
#define QUADSPI_CR_DMAEN_Pos (2U)
#define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
#define QUADSPI_CR_TCEN_Pos (3U)
#define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
#define QUADSPI_CR_SSHIFT_Pos (4U)
#define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< SSHIFT Sample Shift */
#define QUADSPI_CR_DFM_Pos (6U)
#define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
#define QUADSPI_CR_FSEL_Pos (7U)
#define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
#define QUADSPI_CR_FTHRES_Pos (8U)
#define QUADSPI_CR_FTHRES_Msk (0xFU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
#define QUADSPI_CR_FTHRES_0 (0x1U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
#define QUADSPI_CR_FTHRES_1 (0x2U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
#define QUADSPI_CR_FTHRES_2 (0x4U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
#define QUADSPI_CR_FTHRES_3 (0x8U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
#define QUADSPI_CR_TEIE_Pos (16U)
#define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
#define QUADSPI_CR_TCIE_Pos (17U)
#define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
#define QUADSPI_CR_FTIE_Pos (18U)
#define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
#define QUADSPI_CR_SMIE_Pos (19U)
#define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
#define QUADSPI_CR_TOIE_Pos (20U)
#define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
#define QUADSPI_CR_APMS_Pos (22U)
#define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
#define QUADSPI_CR_PMM_Pos (23U)
#define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
#define QUADSPI_CR_PRESCALER_Pos (24U)
#define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
#define QUADSPI_CR_PRESCALER_0 (0x01U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
#define QUADSPI_CR_PRESCALER_1 (0x02U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
#define QUADSPI_CR_PRESCALER_2 (0x04U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
#define QUADSPI_CR_PRESCALER_3 (0x08U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
#define QUADSPI_CR_PRESCALER_4 (0x10U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
#define QUADSPI_CR_PRESCALER_5 (0x20U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
#define QUADSPI_CR_PRESCALER_6 (0x40U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
#define QUADSPI_CR_PRESCALER_7 (0x80U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
/***************** Bit definition for QUADSPI_DCR register ******************/
#define QUADSPI_DCR_CKMODE_Pos (0U)
#define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
#define QUADSPI_DCR_CSHT_Pos (8U)
#define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
#define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
#define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
#define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
#define QUADSPI_DCR_FSIZE_Pos (16U)
#define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
#define QUADSPI_DCR_FSIZE_0 (0x01U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
#define QUADSPI_DCR_FSIZE_1 (0x02U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
#define QUADSPI_DCR_FSIZE_2 (0x04U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
#define QUADSPI_DCR_FSIZE_3 (0x08U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
#define QUADSPI_DCR_FSIZE_4 (0x10U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
/****************** Bit definition for QUADSPI_SR register *******************/
#define QUADSPI_SR_TEF_Pos (0U)
#define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
#define QUADSPI_SR_TCF_Pos (1U)
#define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
#define QUADSPI_SR_FTF_Pos (2U)
#define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
#define QUADSPI_SR_SMF_Pos (3U)
#define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
#define QUADSPI_SR_TOF_Pos (4U)
#define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
#define QUADSPI_SR_BUSY_Pos (5U)
#define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
#define QUADSPI_SR_FLEVEL_Pos (8U)
#define QUADSPI_SR_FLEVEL_Msk (0x1FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */
#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
#define QUADSPI_SR_FLEVEL_0 (0x01U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
#define QUADSPI_SR_FLEVEL_1 (0x02U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
#define QUADSPI_SR_FLEVEL_2 (0x04U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
#define QUADSPI_SR_FLEVEL_3 (0x08U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
#define QUADSPI_SR_FLEVEL_4 (0x10U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
/****************** Bit definition for QUADSPI_FCR register ******************/
#define QUADSPI_FCR_CTEF_Pos (0U)
#define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
#define QUADSPI_FCR_CTCF_Pos (1U)
#define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
#define QUADSPI_FCR_CSMF_Pos (3U)
#define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
#define QUADSPI_FCR_CTOF_Pos (4U)
#define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
/****************** Bit definition for QUADSPI_DLR register ******************/
#define QUADSPI_DLR_DL_Pos (0U)
#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
/****************** Bit definition for QUADSPI_CCR register ******************/
#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
#define QUADSPI_CCR_INSTRUCTION_0 (0x01U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
#define QUADSPI_CCR_INSTRUCTION_1 (0x02U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
#define QUADSPI_CCR_INSTRUCTION_2 (0x04U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
#define QUADSPI_CCR_INSTRUCTION_3 (0x08U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
#define QUADSPI_CCR_INSTRUCTION_4 (0x10U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
#define QUADSPI_CCR_INSTRUCTION_5 (0x20U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
#define QUADSPI_CCR_INSTRUCTION_6 (0x40U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
#define QUADSPI_CCR_INSTRUCTION_7 (0x80U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
#define QUADSPI_CCR_IMODE_Pos (8U)
#define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
#define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
#define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
#define QUADSPI_CCR_ADMODE_Pos (10U)
#define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
#define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
#define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
#define QUADSPI_CCR_ADSIZE_Pos (12U)
#define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
#define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
#define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
#define QUADSPI_CCR_ABMODE_Pos (14U)
#define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
#define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
#define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
#define QUADSPI_CCR_ABSIZE_Pos (16U)
#define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
#define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
#define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
#define QUADSPI_CCR_DCYC_Pos (18U)
#define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
#define QUADSPI_CCR_DCYC_0 (0x01U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
#define QUADSPI_CCR_DCYC_1 (0x02U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
#define QUADSPI_CCR_DCYC_2 (0x04U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
#define QUADSPI_CCR_DCYC_3 (0x08U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
#define QUADSPI_CCR_DCYC_4 (0x10U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
#define QUADSPI_CCR_DMODE_Pos (24U)
#define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
#define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
#define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
#define QUADSPI_CCR_FMODE_Pos (26U)
#define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
#define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
#define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
#define QUADSPI_CCR_SIOO_Pos (28U)
#define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
#define QUADSPI_CCR_DHHC_Pos (30U)
#define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold half cycle */
#define QUADSPI_CCR_DDRM_Pos (31U)
#define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
/****************** Bit definition for QUADSPI_AR register *******************/
#define QUADSPI_AR_ADDRESS_Pos (0U)
#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
/****************** Bit definition for QUADSPI_ABR register ******************/
#define QUADSPI_ABR_ALTERNATE_Pos (0U)
#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
/****************** Bit definition for QUADSPI_DR register *******************/
#define QUADSPI_DR_DATA_Pos (0U)
#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
/****************** Bit definition for QUADSPI_PSMKR register ****************/
#define QUADSPI_PSMKR_MASK_Pos (0U)
#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
/****************** Bit definition for QUADSPI_PSMAR register ****************/
#define QUADSPI_PSMAR_MATCH_Pos (0U)
#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
/****************** Bit definition for QUADSPI_PIR register *****************/
#define QUADSPI_PIR_INTERVAL_Pos (0U)
#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
/****************** Bit definition for QUADSPI_LPTR register *****************/
#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
/********************** Bit definition for QUADSPI_HWCFGR register ***************/
#define QUADSPI_HWCFGR_FIFOSIZE_Pos (0U)
#define QUADSPI_HWCFGR_FIFOSIZE_Msk (0xFU << QUADSPI_HWCFGR_FIFOSIZE_Pos) /*!< 0x0000000F */
#define QUADSPI_HWCFGR_FIFOSIZE QUADSPI_HWCFGR_FIFOSIZE_Msk /*!< size of FIFO in words */
#define QUADSPI_HWCFGR_IDLENGTH_Pos (4U)
#define QUADSPI_HWCFGR_IDLENGTH_Msk (0xFU << QUADSPI_HWCFGR_IDLENGTH_Pos) /*!< 0x0000000F */
#define QUADSPI_HWCFGR_IDLENGTH QUADSPI_HWCFGR_IDLENGTH_Msk /*!< size in bit of the FIFO pointer */
#define QUADSPI_HWCFGR_PRESCVAL_Pos (8U)
#define QUADSPI_HWCFGR_PRESCVAL_Msk (0xFU << QUADSPI_HWCFGR_PRESCVAL_Pos) /*!< 0x0000000F */
#define QUADSPI_HWCFGR_PRESCVAL QUADSPI_HWCFGR_PRESCVAL_Msk /*!< reset value of the prescaler */
#define QUADSPI_HWCFGR_IDLENGTH_Pos (4U)
#define QUADSPI_HWCFGR_IDLENGTH_Msk (0xFU << QUADSPI_HWCFGR_IDLENGTH_Pos) /*!< 0x0000000F */
#define QUADSPI_HWCFGR_IDLENGTH QUADSPI_HWCFGR_IDLENGTH_Msk /*!< length of the AXI IDs. */
/********************** Bit definition for QUADSPI_VERR register *****************/
#define QUADSPI_VERR_MINREV_Pos (0U)
#define QUADSPI_VERR_MINREV_Msk (0xFU << QUADSPI_VERR_MINREV_Pos) /*!< 0x0000000F */
#define QUADSPI_VERR_MINREV QUADSPI_VERR_MINREV_Msk /*!< Minor Revision number */
#define QUADSPI_VERR_MAJREV_Pos (4U)
#define QUADSPI_VERR_MAJREV_Msk (0xFU << QUADSPI_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define QUADSPI_VERR_MAJREV QUADSPI_VERR_MAJREV_Msk /*!< Major Revision number */
/********************** Bit definition for QUADSPI_IPIDR register ****************/
#define QUADSPI_IPIDR_ID_Pos (0U)
#define QUADSPI_IPIDR_ID_Msk (0xFFFFFFFFU << QUADSPI_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
#define QUADSPI_IPIDR_ID QUADSPI_IPIDR_ID_Msk /*!< IP Identification */
/********************** Bit definition for QUADSPI_SIDR register *****************/
#define QUADSPI_SIDR_SID_Pos (0U)
#define QUADSPI_SIDR_SID_Msk (0xFFFFFFFFU << QUADSPI_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define QUADSPI_SIDR_SID QUADSPI_SIDR_SID_Msk /*!< IP size identification */
/******************************************************************************/
/* */
/* SYSCFG */
/* */
/******************************************************************************/
/****************** Bit definition for SYSCFG_BOOTR register *****************/
#define SYSCFG_BOOTR_BOOT0_Pos (0U)
#define SYSCFG_BOOTR_BOOT0_Msk (0x1U << SYSCFG_BOOTR_BOOT0_Pos) /*!< 0x00000001 */
#define SYSCFG_BOOTR_BOOT0 SYSCFG_BOOTR_BOOT0_Msk /*!< BOOT0 pin value */
#define SYSCFG_BOOTR_BOOT1_Pos (1U)
#define SYSCFG_BOOTR_BOOT1_Msk (0x1U << SYSCFG_BOOTR_BOOT1_Pos) /*!< 0x00000002 */
#define SYSCFG_BOOTR_BOOT1 SYSCFG_BOOTR_BOOT1_Msk /*!< BOOT1 pin value */
#define SYSCFG_BOOTR_BOOT2_Pos (2U)
#define SYSCFG_BOOTR_BOOT2_Msk (0x1U << SYSCFG_BOOTR_BOOT2_Pos) /*!< 0x00000004 */
#define SYSCFG_BOOTR_BOOT2 SYSCFG_BOOTR_BOOT2_Msk /*!< BOOT2 pin value */
#define SYSCFG_BOOTR_BOOT0_PD_Pos (4U)
#define SYSCFG_BOOTR_BOOT0_PD_Msk (0x1U << SYSCFG_BOOTR_BOOT0_PD_Pos) /*!< 0x00000010 */
#define SYSCFG_BOOTR_BOOT0_PD SYSCFG_BOOTR_BOOT0_PD_Msk /*!< BOOT0 pin pull-down disable */
#define SYSCFG_BOOTR_BOOT1_PD_Pos (5U)
#define SYSCFG_BOOTR_BOOT1_PD_Msk (0x1U << SYSCFG_BOOTR_BOOT1_PD_Pos) /*!< 0x00000020 */
#define SYSCFG_BOOTR_BOOT1_PD SYSCFG_BOOTR_BOOT1_PD_Msk /*!< BOOT1 pin pull-down disable */
#define SYSCFG_BOOTR_BOOT2_PD_Pos (6U)
#define SYSCFG_BOOTR_BOOT2_PD_Msk (0x1U << SYSCFG_BOOTR_BOOT2_PD_Pos) /*!< 0x00000040 */
#define SYSCFG_BOOTR_BOOT2_PD SYSCFG_BOOTR_BOOT2_PD_Msk /*!< BOOT2 pin pull-down disable */
/****************** Bit definition for SYSCFG_PMCSETR register ******************/
#define SYSCFG_PMCSETR_I2C1_FMP_Pos (0U)
#define SYSCFG_PMCSETR_I2C1_FMP_Msk (0x1U << SYSCFG_PMCSETR_I2C1_FMP_Pos) /*!< 0x00000001 */
#define SYSCFG_PMCSETR_I2C1_FMP SYSCFG_PMCSETR_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
#define SYSCFG_PMCSETR_I2C2_FMP_Pos (1U)
#define SYSCFG_PMCSETR_I2C2_FMP_Msk (0x1U << SYSCFG_PMCSETR_I2C2_FMP_Pos) /*!< 0x00000002 */
#define SYSCFG_PMCSETR_I2C2_FMP SYSCFG_PMCSETR_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
#define SYSCFG_PMCSETR_I2C3_FMP_Pos (2U)
#define SYSCFG_PMCSETR_I2C3_FMP_Msk (0x1U << SYSCFG_PMCSETR_I2C3_FMP_Pos) /*!< 0x00000004 */
#define SYSCFG_PMCSETR_I2C3_FMP SYSCFG_PMCSETR_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
#define SYSCFG_PMCSETR_I2C4_FMP_Pos (3U)
#define SYSCFG_PMCSETR_I2C4_FMP_Msk (0x1U << SYSCFG_PMCSETR_I2C4_FMP_Pos) /*!< 0x00000008 */
#define SYSCFG_PMCSETR_I2C4_FMP SYSCFG_PMCSETR_I2C4_FMP_Msk /*!< I2C4 Fast mode plus */
#define SYSCFG_PMCSETR_I2C5_FMP_Pos (4U)
#define SYSCFG_PMCSETR_I2C5_FMP_Msk (0x1U << SYSCFG_PMCSETR_I2C5_FMP_Pos) /*!< 0x00000010 */
#define SYSCFG_PMCSETR_I2C5_FMP SYSCFG_PMCSETR_I2C5_FMP_Msk /*!< I2C5 Fast mode plus */
#define SYSCFG_PMCSETR_I2C6_FMP_Pos (5U)
#define SYSCFG_PMCSETR_I2C6_FMP_Msk (0x1U << SYSCFG_PMCSETR_I2C6_FMP_Pos) /*!< 0x00000020 */
#define SYSCFG_PMCSETR_I2C6_FMP SYSCFG_PMCSETR_I2C6_FMP_Msk /*!< I2C6 Fast mode plus */
#define SYSCFG_PMCSETR_EN_BOOSTER_Pos (8U)
#define SYSCFG_PMCSETR_EN_BOOSTER_Msk (0x1U << SYSCFG_PMCSETR_EN_BOOSTER_Pos) /*!< 0x00000100 */
#define SYSCFG_PMCSETR_EN_BOOSTER SYSCFG_PMCSETR_EN_BOOSTER_Msk /*!< I/O analog switch voltage booster enable */
#define SYSCFG_PMCSETR_ANASWVDD_Pos (9U)
#define SYSCFG_PMCSETR_ANASWVDD_Msk (0x1U << SYSCFG_PMCSETR_ANASWVDD_Pos) /*!< 0x00000200 */
#define SYSCFG_PMCSETR_ANASWVDD SYSCFG_PMCSETR_ANASWVDD_Msk /*!< GPIO analog switches control voltage selection */
#define SYSCFG_PMCSETR_ETH_CLK_SEL_Pos (16U)
#define SYSCFG_PMCSETR_ETH_CLK_SEL_Msk (0x1U << SYSCFG_PMCSETR_ETH_CLK_SEL_Pos) /*!< 0x00010000 */
#define SYSCFG_PMCSETR_ETH_CLK_SEL SYSCFG_PMCSETR_ETH_CLK_SEL_Msk /*!< Internal clock ETH_CLK1 from RCC is used regardless AFMux */
#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL_Pos (17U)
#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL_Msk (0x1U << SYSCFG_PMCSETR_ETH_REF_CLK_SEL_Pos) /*!< 0x00020000 */
#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL SYSCFG_PMCSETR_ETH_REF_CLK_SEL_Msk /*!< Ethernet 50MHz RMII clock selection */
#define SYSCFG_PMCSETR_ETH_SELMII_Pos (20U)
#define SYSCFG_PMCSETR_ETH_SELMII_Msk (0x1U << SYSCFG_PMCSETR_ETH_SELMII_Pos) /*!< 0x00100000 */
#define SYSCFG_PMCSETR_ETH_SELMII_SEL SYSCFG_PMCSETR_ETH_SELMII_Msk /*!< controls MII or GMII when ETH_SEL[2:0] = 0b000 */
#define SYSCFG_PMCSETR_ETH_SEL_Pos (21U)
#define SYSCFG_PMCSETR_ETH_SEL_Msk (0x7U << SYSCFG_PMCSETR_ETH_SEL_Pos) /*!< 0x00E00000 */
#define SYSCFG_PMCSETR_ETH_SEL SYSCFG_PMCSETR_ETH_SEL_Msk /*!< Ethernet PHY Interface Selection */
#define SYSCFG_PMCSETR_ETH_SEL_0 (0x1U << SYSCFG_PMCSETR_ETH_SEL_Pos) /*!< 0x00200000 */
#define SYSCFG_PMCSETR_ETH_SEL_1 (0x2U << SYSCFG_PMCSETR_ETH_SEL_Pos) /*!< 0x00400000 */
#define SYSCFG_PMCSETR_ETH_SEL_2 (0x4U << SYSCFG_PMCSETR_ETH_SEL_Pos) /*!< 0x00800000 */
#define SYSCFG_PMCSETR_ETH_SEL_CONF_Pos (20U)
#define SYSCFG_PMCSETR_ETH_SEL_CONF_Msk (0xFU << SYSCFG_PMCSETR_ETH_SEL_CONF_Pos) /*!< 0x00F00000 */
#define SYSCFG_PMCSETR_ETH_SEL_CONF SYSCFG_PMCSETR_ETH_SEL_CONF_Msk /*!< Ethernet PHY Interface Configuration */
#define SYSCFG_PMCSETR_ANA0_SEL_Pos (24U)
#define SYSCFG_PMCSETR_ANA0_SEL_Msk (0x1U << SYSCFG_PMCSETR_ANA0_SEL_Pos) /*!< 0x01000000 */
#define SYSCFG_PMCSETR_ANA0_SEL_SEL SYSCFG_PMCSETR_ANA0_SEL_Msk /*!< controls analog connection between ANA0 and PA0 pin */
#define SYSCFG_PMCSETR_ANA1_SEL_Pos (25U)
#define SYSCFG_PMCSETR_ANA1_SEL_Msk (0x1U << SYSCFG_PMCSETR_ANA1_SEL_Pos) /*!< 0x02000000 */
#define SYSCFG_PMCSETR_ANA1_SEL_SEL SYSCFG_PMCSETR_ANA1_SEL_Msk /*!< controls analog connection between ANA1 and PA1 pin */
/****************** Bit definition for SYSCFG_PMCCLRR register ******************/
#define SYSCFG_PMCCLRR_I2C1_FMP_Pos (0U)
#define SYSCFG_PMCCLRR_I2C1_FMP_Msk (0x1U << SYSCFG_PMCCLRR_I2C1_FMP_Pos) /*!< 0x00000001 */
#define SYSCFG_PMCCLRR_I2C1_FMP SYSCFG_PMCCLRR_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
#define SYSCFG_PMCCLRR_I2C2_FMP_Pos (1U)
#define SYSCFG_PMCCLRR_I2C2_FMP_Msk (0x1U << SYSCFG_PMCCLRR_I2C2_FMP_Pos) /*!< 0x00000002 */
#define SYSCFG_PMCCLRR_I2C2_FMP SYSCFG_PMCCLRR_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
#define SYSCFG_PMCCLRR_I2C3_FMP_Pos (2U)
#define SYSCFG_PMCCLRR_I2C3_FMP_Msk (0x1U << SYSCFG_PMCCLRR_I2C3_FMP_Pos) /*!< 0x00000004 */
#define SYSCFG_PMCCLRR_I2C3_FMP SYSCFG_PMCCLRR_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
#define SYSCFG_PMCCLRR_I2C4_FMP_Pos (3U)
#define SYSCFG_PMCCLRR_I2C4_FMP_Msk (0x1U << SYSCFG_PMCCLRR_I2C4_FMP_Pos) /*!< 0x00000008 */
#define SYSCFG_PMCCLRR_I2C4_FMP SYSCFG_PMCCLRR_I2C4_FMP_Msk /*!< I2C4 Fast mode plus */
#define SYSCFG_PMCCLRR_I2C5_FMP_Pos (4U)
#define SYSCFG_PMCCLRR_I2C5_FMP_Msk (0x1U << SYSCFG_PMCCLRR_I2C5_FMP_Pos) /*!< 0x00000010 */
#define SYSCFG_PMCCLRR_I2C5_FMP SYSCFG_PMCCLRR_I2C5_FMP_Msk /*!< I2C5 Fast mode plus */
#define SYSCFG_PMCCLRR_I2C6_FMP_Pos (5U)
#define SYSCFG_PMCCLRR_I2C6_FMP_Msk (0x1U << SYSCFG_PMCCLRR_I2C6_FMP_Pos) /*!< 0x00000020 */
#define SYSCFG_PMCCLRR_I2C6_FMP SYSCFG_PMCCLRR_I2C6_FMP_Msk /*!< I2C6 Fast mode plus */
#define SYSCFG_PMCCLRR_EN_BOOSTER_Pos (8U)
#define SYSCFG_PMCCLRR_EN_BOOSTER_Msk (0x1U << SYSCFG_PMCCLRR_EN_BOOSTER_Pos) /*!< 0x00000100 */
#define SYSCFG_PMCCLRR_EN_BOOSTER SYSCFG_PMCCLRR_EN_BOOSTER_Msk /*!< I/O analog switch voltage booster enable */
#define SYSCFG_PMCCLRR_ANASWVDD_Pos (9U)
#define SYSCFG_PMCCLRR_ANASWVDD_Msk (0x1U << SYSCFG_PMCCLRR_ANASWVDD_Pos) /*!< 0x00000200 */
#define SYSCFG_PMCCLRR_ANASWVDD SYSCFG_PMCCLRR_ANASWVDD_Msk /*!< GPIO analog switches control voltage selection */
#define SYSCFG_PMCCLRR_ETH_CLK_SEL_Pos (16U)
#define SYSCFG_PMCCLRR_ETH_CLK_SEL_Msk (0x1U << SYSCFG_PMCCLRR_ETH_CLK_SEL_Pos) /*!< 0x00010000 */
#define SYSCFG_PMCCLRR_ETH_CLK_SEL SYSCFG_PMCCLRR_ETH_CLK_SEL_Msk /*!< Internal clock ETH_CLK1 from RCC is used regardless AFMux */
#define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos (17U)
#define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk (0x1U << SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Pos) /*!< 0x00020000 */
#define SYSCFG_PMCCLRR_ETH_REF_CLK_SEL SYSCFG_PMCCLRR_ETH_REF_CLK_SEL_Msk /*!< Ethernet 50MHz RMII clock selection */
#define SYSCFG_PMCCLRR_ETH_SELMII_Pos (20U)
#define SYSCFG_PMCCLRR_ETH_SELMII_Msk (0x1U << SYSCFG_PMCCLRR_ETH_SELMII_Pos) /*!< 0x00100000 */
#define SYSCFG_PMCCLRR_ETH_SELMII_SEL SYSCFG_PMCCLRR_ETH_SELMII_Msk /*!< controls MII or GMII when ETH_SEL[2:0] = 0b000 */
#define SYSCFG_PMCCLRR_ETH_SEL_Pos (21U)
#define SYSCFG_PMCCLRR_ETH_SEL_Msk (0x7U << SYSCFG_PMCCLRR_ETH_SEL_Pos) /*!< 0x00E00000 */
#define SYSCFG_PMCCLRR_ETH_SEL SYSCFG_PMCCLRR_ETH_SEL_Msk /*!< Ethernet PHY Interface Selection */
#define SYSCFG_PMCCLRR_ETH_SEL_0 (0x1U << SYSCFG_PMCCLRR_ETH_SEL_Pos) /*!< 0x00200000 */
#define SYSCFG_PMCCLRR_ETH_SEL_1 (0x2U << SYSCFG_PMCCLRR_ETH_SEL_Pos) /*!< 0x00400000 */
#define SYSCFG_PMCCLRR_ETH_SEL_2 (0x4U << SYSCFG_PMCCLRR_ETH_SEL_Pos) /*!< 0x00800000 */
#define SYSCFG_PMCCLRR_ETH_SEL_CONF_Pos (20U)
#define SYSCFG_PMCCLRR_ETH_SEL_CONF_Msk (0xFU << SYSCFG_PMCCLRR_ETH_SEL_CONF_Pos) /*!< 0x00F00000 */
#define SYSCFG_PMCCLRR_ETH_SEL_CONF SYSCFG_PMCCLRR_ETH_SEL_CONF_Msk /*!< Ethernet PHY Interface Configuration */
#define SYSCFG_PMCCLRR_ANA0_SEL_Pos (24U)
#define SYSCFG_PMCCLRR_ANA0_SEL_Msk (0x1U << SYSCFG_PMCCLRR_ANA0_SEL_Pos) /*!< 0x01000000 */
#define SYSCFG_PMCCLRR_ANA0_SEL_SEL SYSCFG_PMCCLRR_ANA0_SEL_Msk /*!< controls analog connection between ANA0 and PA0 pin */
#define SYSCFG_PMCCLRR_ANA1_SEL_Pos (25U)
#define SYSCFG_PMCCLRR_ANA1_SEL_Msk (0x1U << SYSCFG_PMCCLRR_ANA1_SEL_Pos) /*!< 0x02000000 */
#define SYSCFG_PMCCLRR_ANA1_SEL_SEL SYSCFG_PMCCLRR_ANA1_SEL_Msk /*!< controls analog connection between ANA1 and PA1 pin */
/****************** Bit definition for SYSCFG_IOCTRLSETR register *****************/
#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE_Pos (0U)
#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE_Msk (0x1U << SYSCFG_IOCTRLSETR_HSLVEN_TRACE_Pos) /*!< 0x00000001 */
#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE SYSCFG_IOCTRLSETR_HSLVEN_TRACE_Msk /*!< High Speed Low Voltage Pad mode Enable */
#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI_Pos (1U)
#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI_Msk (0x1U << SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI_Pos) /*!< 0x00000002 */
#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI_Msk /*!< High Speed Low Voltage Pad mode Enable */
#define SYSCFG_IOCTRLSETR_HSLVEN_ETH_Pos (2U)
#define SYSCFG_IOCTRLSETR_HSLVEN_ETH_Msk (0x1U << SYSCFG_IOCTRLSETR_HSLVEN_ETH_Pos) /*!< 0x00000004 */
#define SYSCFG_IOCTRLSETR_HSLVEN_ETH SYSCFG_IOCTRLSETR_HSLVEN_ETH_Msk /*!< High Speed Low Voltage Pad mode Enable */
#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC_Pos (3U)
#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC_Msk (0x1U << SYSCFG_IOCTRLSETR_HSLVEN_SDMMC_Pos) /*!< 0x00000008 */
#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC SYSCFG_IOCTRLSETR_HSLVEN_SDMMC_Msk /*!< High Speed Low Voltage Pad mode Enable */
#define SYSCFG_IOCTRLSETR_HSLVEN_SPI_Pos (4U)
#define SYSCFG_IOCTRLSETR_HSLVEN_SPI_Msk (0x1U << SYSCFG_IOCTRLSETR_HSLVEN_SPI_Pos) /*!< 0x00000010 */
#define SYSCFG_IOCTRLSETR_HSLVEN_SPI SYSCFG_IOCTRLSETR_HSLVEN_SPI_Msk /*!< High Speed Low Voltage Pad mode Enable */
/****************** Bit definition for SYSCFG_IOCTRLCLRR register *****************/
#define SYSCFG_IOCTRLCLRR_HSLVEN_TRACE_Pos (0U)
#define SYSCFG_IOCTRLCLRR_HSLVEN_TRACE_Msk (0x1U << SYSCFG_IOCTRLCLRR_HSLVEN_TRACE_Pos) /*!< 0x00000001 */
#define SYSCFG_IOCTRLCLRR_HSLVEN_TRACE SYSCFG_IOCTRLCLRR_HSLVEN_TRACE_Msk /*!< High Speed Low Voltage Pad mode Enable */
#define SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI_Pos (1U)
#define SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI_Msk (0x1U << SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI_Pos) /*!< 0x00000002 */
#define SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI SYSCFG_IOCTRLCLRR_HSLVEN_QUADSPI_Msk /*!< High Speed Low Voltage Pad mode Enable */
#define SYSCFG_IOCTRLCLRR_HSLVEN_ETH_Pos (2U)
#define SYSCFG_IOCTRLCLRR_HSLVEN_ETH_Msk (0x1U << SYSCFG_IOCTRLCLRR_HSLVEN_ETH_Pos) /*!< 0x00000004 */
#define SYSCFG_IOCTRLCLRR_HSLVEN_ETH SYSCFG_IOCTRLCLRR_HSLVEN_ETH_Msk /*!< High Speed Low Voltage Pad mode Enable */
#define SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC_Pos (3U)
#define SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC_Msk (0x1U << SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC_Pos) /*!< 0x00000008 */
#define SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC SYSCFG_IOCTRLCLRR_HSLVEN_SDMMC_Msk /*!< High Speed Low Voltage Pad mode Enable */
#define SYSCFG_IOCTRLCLRR_HSLVEN_SPI_Pos (4U)
#define SYSCFG_IOCTRLCLRR_HSLVEN_SPI_Msk (0x1U << SYSCFG_IOCTRLCLRR_HSLVEN_SPI_Pos) /*!< 0x00000010 */
#define SYSCFG_IOCTRLCLRR_HSLVEN_SPI SYSCFG_IOCTRLCLRR_HSLVEN_SPI_Msk /*!< High Speed Low Voltage Pad mode Enable */
/****************** Bit definition for SYSCFG_ICNR register ********************/
#define SYSCFG_ICNR_AXI_M0_Pos (0U)
#define SYSCFG_ICNR_AXI_M0_Msk (0x1U << SYSCFG_ICNR_AXI_M0_Pos) /*!< 0x00000001 */
#define SYSCFG_ICNR_AXI_M0 SYSCFG_ICNR_AXI_M0_Msk /*!< controls which slave port is used by the master to access the DDR */
#define SYSCFG_ICNR_AXI_M1_Pos (1U)
#define SYSCFG_ICNR_AXI_M1_Msk (0x1U << SYSCFG_ICNR_AXI_M1_Pos) /*!< 0x00000002 */
#define SYSCFG_ICNR_AXI_M1 SYSCFG_ICNR_AXI_M1_Msk /*!< controls which slave port is used by the master to access the DDR */
#define SYSCFG_ICNR_AXI_M2_Pos (2U)
#define SYSCFG_ICNR_AXI_M2_Msk (0x1U << SYSCFG_ICNR_AXI_M2_Pos) /*!< 0x00000004 */
#define SYSCFG_ICNR_AXI_M2 SYSCFG_ICNR_AXI_M2_Msk /*!< controls which slave port is used by the master to access the DDR */
#define SYSCFG_ICNR_AXI_M3_Pos (3U)
#define SYSCFG_ICNR_AXI_M3_Msk (0x1U << SYSCFG_ICNR_AXI_M3_Pos) /*!< 0x00000008 */
#define SYSCFG_ICNR_AXI_M3 SYSCFG_ICNR_AXI_M3_Msk /*!< controls which slave port is used by the master to access the DDR */
#define SYSCFG_ICNR_AXI_M5_Pos (5U)
#define SYSCFG_ICNR_AXI_M5_Msk (0x1U << SYSCFG_ICNR_AXI_M5_Pos) /*!< 0x00000020 */
#define SYSCFG_ICNR_AXI_M5 SYSCFG_ICNR_AXI_M5_Msk /*!< controls which slave port is used by the master to access the DDR */
#define SYSCFG_ICNR_AXI_M6_Pos (6U)
#define SYSCFG_ICNR_AXI_M6_Msk (0x1U << SYSCFG_ICNR_AXI_M6_Pos) /*!< 0x00000040 */
#define SYSCFG_ICNR_AXI_M6 SYSCFG_ICNR_AXI_M6_Msk /*!< controls which slave port is used by the master to access the DDR */
#define SYSCFG_ICNR_AXI_M7_Pos (7U)
#define SYSCFG_ICNR_AXI_M7_Msk (0x1U << SYSCFG_ICNR_AXI_M7_Pos) /*!< 0x00000080 */
#define SYSCFG_ICNR_AXI_M7 SYSCFG_ICNR_AXI_M7_Msk /*!< controls which slave port is used by the master to access the DDR */
#define SYSCFG_ICNR_AXI_M8_Pos (8U)
#define SYSCFG_ICNR_AXI_M8_Msk (0x1U << SYSCFG_ICNR_AXI_M8_Pos) /*!< 0x00000100 */
#define SYSCFG_ICNR_AXI_M8 SYSCFG_ICNR_AXI_M8_Msk /*!< controls which slave port is used by the master to access the DDR */
#define SYSCFG_ICNR_AXI_M9_Pos (9U)
#define SYSCFG_ICNR_AXI_M9_Msk (0x1U << SYSCFG_ICNR_AXI_M9_Pos) /*!< 0x00000200 */
#define SYSCFG_ICNR_AXI_M9 SYSCFG_ICNR_AXI_M9_Msk /*!< controls which slave port is used by the master to access the DDR */
#define SYSCFG_ICNR_AXI_M10_Pos (10U)
#define SYSCFG_ICNR_AXI_M10_Msk (0x1U << SYSCFG_ICNR_AXI_M10_Pos) /*!< 0x00000400 */
#define SYSCFG_ICNR_AXI_M10 SYSCFG_ICNR_AXI_M10_Msk /*!< controls which slave port is used by the master to access the DDR */
/****************** Bit definition for SYSCFG_CMPCR register ********************/
#define SYSCFG_CMPCR_SW_CTRL_Pos (1U)
#define SYSCFG_CMPCR_SW_CTRL_Msk (0x1U << SYSCFG_CMPCR_SW_CTRL_Pos) /*!< 0x00000002 */
#define SYSCFG_CMPCR_SW_CTRL SYSCFG_CMPCR_SW_CTRL_Msk /*!< Compensation Software Control */
#define SYSCFG_CMPCR_READY_Pos (8U)
#define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!< Compensation cell ready flag */
#define SYSCFG_CMPCR_RANSRC_Pos (16U)
#define SYSCFG_CMPCR_RANSRC_Msk (0xFU << SYSCFG_CMPCR_RANSRC_Pos) /*!< 0x000F0000 */
#define SYSCFG_CMPCR_RANSRC SYSCFG_CMPCR_RANSRC_Msk /*!< NMOS I/O Compensation value sent to IOs when SW_CTRL = 1 */
#define SYSCFG_CMPCR_RANSRC_0 (0x1U << SYSCFG_CMPCR_RANSRC_Pos) /*!< 0x00010000 */
#define SYSCFG_CMPCR_RANSRC_1 (0x2U << SYSCFG_CMPCR_RANSRC_Pos) /*!< 0x00020000 */
#define SYSCFG_CMPCR_RANSRC_2 (0x4U << SYSCFG_CMPCR_RANSRC_Pos) /*!< 0x00040000 */
#define SYSCFG_CMPCR_RANSRC_3 (0x8U << SYSCFG_CMPCR_RANSRC_Pos) /*!< 0x00080000 */
#define SYSCFG_CMPCR_RAPSRC_Pos (20U)
#define SYSCFG_CMPCR_RAPSRC_Msk (0xFU << SYSCFG_CMPCR_RAPSRC_Pos) /*!< 0x00F00000 */
#define SYSCFG_CMPCR_RAPSRC SYSCFG_CMPCR_RAPSRC_Msk /*!< PMOS I/O Compensation value sent to IOs when SW_CTRL = 1 */
#define SYSCFG_CMPCR_RAPSRC_0 (0x1U << SYSCFG_CMPCR_RAPSRC_Pos) /*!< 0x00100000 */
#define SYSCFG_CMPCR_RAPSRC_1 (0x2U << SYSCFG_CMPCR_RAPSRC_Pos) /*!< 0x00200000 */
#define SYSCFG_CMPCR_RAPSRC_2 (0x4U << SYSCFG_CMPCR_RAPSRC_Pos) /*!< 0x00400000 */
#define SYSCFG_CMPCR_RAPSRC_3 (0x8U << SYSCFG_CMPCR_RAPSRC_Pos) /*!< 0x00800000 */
#define SYSCFG_CMPCR_ANSRC_Pos (24U)
#define SYSCFG_CMPCR_ANSRC_Msk (0xFU << SYSCFG_CMPCR_ANSRC_Pos) /*!< 0x0F000000 */
#define SYSCFG_CMPCR_ANSRC SYSCFG_CMPCR_ANSRC_Msk /*!< NMOS I/O Compensation value provided by compensation cell */
#define SYSCFG_CMPCR_ANSRC_0 (0x1U << SYSCFG_CMPCR_ANSRC_Pos) /*!< 0x01000000 */
#define SYSCFG_CMPCR_ANSRC_1 (0x2U << SYSCFG_CMPCR_ANSRC_Pos) /*!< 0x02000000 */
#define SYSCFG_CMPCR_ANSRC_2 (0x4U << SYSCFG_CMPCR_ANSRC_Pos) /*!< 0x04000000 */
#define SYSCFG_CMPCR_ANSRC_3 (0x8U << SYSCFG_CMPCR_ANSRC_Pos) /*!< 0x08000000 */
#define SYSCFG_CMPCR_APSRC_Pos (28U)
#define SYSCFG_CMPCR_APSRC_Msk (0xFU << SYSCFG_CMPCR_APSRC_Pos) /*!< 0xF0000000 */
#define SYSCFG_CMPCR_APSRC SYSCFG_CMPCR_APSRC_Msk /*!< PMOS I/O Compensation value provided by compensation cell */
#define SYSCFG_CMPCR_APSRC_0 (0x1U << SYSCFG_CMPCR_APSRC_Pos) /*!< 0x10000000 */
#define SYSCFG_CMPCR_APSRC_1 (0x2U << SYSCFG_CMPCR_APSRC_Pos) /*!< 0x20000000 */
#define SYSCFG_CMPCR_APSRC_2 (0x4U << SYSCFG_CMPCR_APSRC_Pos) /*!< 0x40000000 */
#define SYSCFG_CMPCR_APSRC_3 (0x8U << SYSCFG_CMPCR_APSRC_Pos) /*!< 0x80000000 */
/****************** Bit definition for SYSCFG_CMPENSETR register ********************/
#define SYSCFG_CMPENSETR_MPU_EN_Pos (0U)
#define SYSCFG_CMPENSETR_MPU_EN_Msk (0x1U << SYSCFG_CMPENSETR_MPU_EN_Pos) /*!< 0x00000001 */
#define SYSCFG_CMPENSETR_MPU_EN SYSCFG_CMPENSETR_MPU_EN_Msk /*!< Compensation cell enable */
#define SYSCFG_CMPENSETR_MCU_EN_Pos (1U)
#define SYSCFG_CMPENSETR_MCU_EN_Msk (0x1U << SYSCFG_CMPENSETR_MCU_EN_Pos) /*!< 0x00000001 */
#define SYSCFG_CMPENSETR_MCU_EN SYSCFG_CMPENSETR_MCU_EN_Msk /*!< Compensation cell enable */
/****************** Bit definition for SYSCFG_CMPENCLRR register ********************/
#define SYSCFG_CMPENCLRR_MPU_EN_Pos (0U)
#define SYSCFG_CMPENCLRR_MPU_EN_Msk (0x1U << SYSCFG_CMPENCLRR_MPU_EN_Pos) /*!< 0x00000001 */
#define SYSCFG_CMPENCLRR_MPU_EN SYSCFG_CMPENCLRR_MPU_EN_Msk /*!< Compensation cell disable */
#define SYSCFG_CMPENCLRR_MCU_EN_Pos (0U)
#define SYSCFG_CMPENCLRR_MCU_EN_Msk (0x1U << SYSCFG_CMPENCLRR_MCU_EN_Pos) /*!< 0x00000001 */
#define SYSCFG_CMPENCLRR_MCU_EN SYSCFG_CMPENCLRR_MCU_EN_Msk /*!< Compensation cell disable */
/****************** Bit definition for SYSCFG_CBR register ******************/
#define SYSCFG_CBR_CLL_Pos (0U)
#define SYSCFG_CBR_CLL_Msk (0x1U << SYSCFG_CBR_CLL_Pos) /*!< 0x00000001 */
#define SYSCFG_CBR_CLL SYSCFG_CBR_CLL_Msk /*!< Cortex-M4 LOCKUP (Hardfault) output enable bit */
#define SYSCFG_CBR_PVDL_Pos (2U)
#define SYSCFG_CBR_PVDL_Msk (0x1U << SYSCFG_CBR_PVDL_Pos) /*!< 0x00000004 */
#define SYSCFG_CBR_PVDL SYSCFG_CBR_PVDL_Msk /*!< PVD lock enable bit */
/********************** Bit definition for SYSCFG_VERR register *****************/
#define SYSCFG_VERR_MINREV_Pos (0U)
#define SYSCFG_VERR_MINREV_Msk (0xFU << SYSCFG_VERR_MINREV_Pos) /*!< 0x0000000F */
#define SYSCFG_VERR_MINREV SYSCFG_VERR_MINREV_Msk /*!< Minor Revision number */
#define SYSCFG_VERR_MAJREV_Pos (4U)
#define SYSCFG_VERR_MAJREV_Msk (0xFU << SYSCFG_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define SYSCFG_VERR_MAJREV SYSCFG_VERR_MAJREV_Msk /*!< Major Revision number */
/********************** Bit definition for SYSCFG_IPIDR register ****************/
#define SYSCFG_IPIDR_IPID_Pos (0U)
#define SYSCFG_IPIDR_IPID_Msk (0xFFFFFFFFU << SYSCFG_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
#define SYSCFG_IPIDR_IPID SYSCFG_IPIDR_IPID_Msk /*!< IP Identification */
/********************** Bit definition for SYSCFG_SIDR register *****************/
#define SYSCFG_SIDR_SID_Pos (0U)
#define SYSCFG_SIDR_SID_Msk (0xFFFFFFFFU << SYSCFG_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define SYSCFG_SIDR_SID SYSCFG_SIDR_SID_Msk /*!< IP size identification */
/******************************************************************************/
/* */
/* Temperature Sensor (DTS) */
/* */
/******************************************************************************/
/****************** Bit definition for DTS_CFGR1 register ******************/
#define DTS_CFGR1_TS1_EN_Pos (0U)
#define DTS_CFGR1_TS1_EN_Msk (0x1U << DTS_CFGR1_TS1_EN_Pos) /*!< 0x00000001 */
#define DTS_CFGR1_TS1_EN DTS_CFGR1_TS1_EN_Msk /*!< DTS1 Enable */
#define DTS_CFGR1_TS1_START_Pos (4U)
#define DTS_CFGR1_TS1_START_Msk (0x1U << DTS_CFGR1_TS1_START_Pos) /*!< 0x00000010 */
#define DTS_CFGR1_TS1_START DTS_CFGR1_TS1_START_Msk /*!< Proceed to a frequency measurement on DTS1 */
#define DTS_CFGR1_TS1_INTRIG_SEL_Pos (8U)
#define DTS_CFGR1_TS1_INTRIG_SEL_Msk (0xFU << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000F00 */
#define DTS_CFGR1_TS1_INTRIG_SEL DTS_CFGR1_TS1_INTRIG_SEL_Msk /*!< Input triggers selection bits [3:0] for DTS1 */
#define DTS_CFGR1_TS1_INTRIG_SEL_0 (0x1U << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000100 */
#define DTS_CFGR1_TS1_INTRIG_SEL_1 (0x2U << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000200 */
#define DTS_CFGR1_TS1_INTRIG_SEL_2 (0x4U << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000400 */
#define DTS_CFGR1_TS1_INTRIG_SEL_3 (0x8U << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000800 */
#define DTS_CFGR1_TS1_SMP_TIME_Pos (16U)
#define DTS_CFGR1_TS1_SMP_TIME_Msk (0xFU << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x000F0000 */
#define DTS_CFGR1_TS1_SMP_TIME DTS_CFGR1_TS1_SMP_TIME_Msk /*!< Sample time [3:0] for DTS1 */
#define DTS_CFGR1_TS1_SMP_TIME_0 (0x1U << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00010000 */
#define DTS_CFGR1_TS1_SMP_TIME_1 (0x2U << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00020000 */
#define DTS_CFGR1_TS1_SMP_TIME_2 (0x4U << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00040000 */
#define DTS_CFGR1_TS1_SMP_TIME_3 (0x8U << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00080000 */
#define DTS_CFGR1_REFCLK_SEL_Pos (20U)
#define DTS_CFGR1_REFCLK_SEL_Msk (0x1U << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */
#define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selection */
#define DTS_CFGR1_Q_MEAS_OPT_Pos (21U)
#define DTS_CFGR1_Q_MEAS_OPT_Msk (0x1U << DTS_CFGR1_Q_MEAS_OPT_Pos) /*!< 0x00200000 */
#define DTS_CFGR1_Q_MEAS_OPT DTS_CFGR1_Q_MEAS_OPT_Msk /*!< Quick measure option bit */
#define DTS_CFGR1_HSREF_CLK_DIV_Pos (24U)
#define DTS_CFGR1_HSREF_CLK_DIV_Msk (0x7FU << DTS_CFGR1_HSREF_CLK_DIV_Pos) /*!< 0x7F000000 */
#define DTS_CFGR1_HSREF_CLK_DIV DTS_CFGR1_HSREF_CLK_DIV_Msk /*!< High Speed Clock Divider Ratio [6:0]*/
/****************** Bit definition for DTS_T0VALR1 register ******************/
#define DTS_T0VALR1_TS1_FMT0_Pos (0U)
#define DTS_T0VALR1_TS1_FMT0_Msk (0xFFFFU << DTS_T0VALR1_TS1_FMT0_Pos) /*!< 0x0000FFFF */
#define DTS_T0VALR1_TS1_FMT0 DTS_T0VALR1_TS1_FMT0_Msk /*!< Engineering value of the measured frequency at T0 for DTS1 */
#define DTS_T0VALR1_TS1_T0_Pos (16U)
#define DTS_T0VALR1_TS1_T0_Msk (0x3U << DTS_T0VALR1_TS1_T0_Pos) /*!< 0x00030000 */
#define DTS_T0VALR1_TS1_T0 DTS_T0VALR1_TS1_T0_Msk /*!< Engineering value of the DTSerature T0 for DTS1 */
/****************** Bit definition for DTS_RAMPVALR register ******************/
#define DTS_RAMPVALR_TS1_RAMP_COEFF_Pos (0U)
#define DTS_RAMPVALR_TS1_RAMP_COEFF_Msk (0xFFFFU << DTS_RAMPVALR_TS1_RAMP_COEFF_Pos) /*!< 0x0000FFFF */
#define DTS_RAMPVALR_TS1_RAMP_COEFF DTS_RAMPVALR_TS1_RAMP_COEFF_Msk /*!< Engineering value of the ramp coefficient for DTS1 */
/****************** Bit definition for DTS_ITR1 register ******************/
#define DTS_ITR1_TS1_LITTHD_Pos (0U)
#define DTS_ITR1_TS1_LITTHD_Msk (0xFFFFU << DTS_ITR1_TS1_LITTHD_Pos) /*!< 0x0000FFFF */
#define DTS_ITR1_TS1_LITTHD DTS_ITR1_TS1_LITTHD_Msk /*!< Low interrupt threshold[15:0] for DTS1 */
#define DTS_ITR1_TS1_HITTHD_Pos (16U)
#define DTS_ITR1_TS1_HITTHD_Msk (0xFFFFU << DTS_ITR1_TS1_HITTHD_Pos) /*!< 0xFFFF0000 */
#define DTS_ITR1_TS1_HITTHD DTS_ITR1_TS1_HITTHD_Msk /*!< High interrupt threshold[15:0] for DTS1 */
/****************** Bit definition for DTS_DR register ******************/
#define DTS_DR_TS1_MFREQ_Pos (0U)
#define DTS_DR_TS1_MFREQ_Msk (0xFFFFU << DTS_DR_TS1_MFREQ_Pos) /*!< 0x0000FFFF */
#define DTS_DR_TS1_MFREQ DTS_DR_TS1_MFREQ_Msk /*!< Measured Frequency[15:0] for DTS1 */
/****************** Bit definition for DTS_SR register ******************/
#define DTS_SR_TS1_ITEF_Pos (0U)
#define DTS_SR_TS1_ITEF_Msk (0x1U << DTS_SR_TS1_ITEF_Pos) /*!< 0x00000001 */
#define DTS_SR_TS1_ITEF DTS_SR_TS1_ITEF_Msk /*!< Interrupt flag for end of measure for DTS1 */
#define DTS_SR_TS1_ITLF_Pos (1U)
#define DTS_SR_TS1_ITLF_Msk (0x1U << DTS_SR_TS1_ITLF_Pos) /*!< 0x00000002 */
#define DTS_SR_TS1_ITLF DTS_SR_TS1_ITLF_Msk /*!< Interrupt flag for low threshold for DTS1 */
#define DTS_SR_TS1_ITHF_Pos (2U)
#define DTS_SR_TS1_ITHF_Msk (0x1U << DTS_SR_TS1_ITHF_Pos) /*!< 0x00000004 */
#define DTS_SR_TS1_ITHF DTS_SR_TS1_ITHF_Msk /*!< Interrupt flag for high threshold for DTS1 */
#define DTS_SR_TS1_AITEF_Pos (4U)
#define DTS_SR_TS1_AITEF_Msk (0x1U << DTS_SR_TS1_AITEF_Pos) /*!< 0x00000010 */
#define DTS_SR_TS1_AITEF DTS_SR_TS1_AITEF_Msk /*!< Asynchronous interrupt flag for end of measure for DTS1 */
#define DTS_SR_TS1_AITLF_Pos (5U)
#define DTS_SR_TS1_AITLF_Msk (0x1U << DTS_SR_TS1_AITLF_Pos) /*!< 0x00000020 */
#define DTS_SR_TS1_AITLF DTS_SR_TS1_AITLF_Msk /*!< Asynchronous interrupt flag for low threshold for DTS1 */
#define DTS_SR_TS1_AITHF_Pos (6U)
#define DTS_SR_TS1_AITHF_Msk (0x1U << DTS_SR_TS1_AITHF_Pos) /*!< 0x00000040 */
#define DTS_SR_TS1_AITHF DTS_SR_TS1_AITHF_Msk /*!< Asynchronous interrupt flag for high threshold for DTS1 */
#define DTS_SR_TS1_RDY_Pos (15U)
#define DTS_SR_TS1_RDY_Msk (0x1U << DTS_SR_TS1_RDY_Pos) /*!< 0x00008000 */
#define DTS_SR_TS1_RDY DTS_SR_TS1_RDY_Msk /*!< DTS1 ready flag */
/****************** Bit definition for DTS_ITENR register ******************/
#define DTS_ITENR_TS1_ITEEN_Pos (0U)
#define DTS_ITENR_TS1_ITEEN_Msk (0x1U << DTS_ITENR_TS1_ITEEN_Pos) /*!< 0x00000001 */
#define DTS_ITENR_TS1_ITEEN DTS_ITENR_TS1_ITEEN_Msk /*!< Enable interrupt flag for end of measure for DTS1 */
#define DTS_ITENR_TS1_ITLEN_Pos (1U)
#define DTS_ITENR_TS1_ITLEN_Msk (0x1U << DTS_ITENR_TS1_ITLEN_Pos) /*!< 0x00000002 */
#define DTS_ITENR_TS1_ITLEN DTS_ITENR_TS1_ITLEN_Msk /*!< Enable interrupt flag for low threshold for DTS1 */
#define DTS_ITENR_TS1_ITHEN_Pos (2U)
#define DTS_ITENR_TS1_ITHEN_Msk (0x1U << DTS_ITENR_TS1_ITHEN_Pos) /*!< 0x00000004 */
#define DTS_ITENR_TS1_ITHEN DTS_ITENR_TS1_ITHEN_Msk /*!< Enable interrupt flag for high threshold for DTS1 */
#define DTS_ITENR_TS1_AITEEN_Pos (4U)
#define DTS_ITENR_TS1_AITEEN_Msk (0x1U << DTS_ITENR_TS1_AITEEN_Pos) /*!< 0x00000010 */
#define DTS_ITENR_TS1_AITEEN DTS_ITENR_TS1_AITEEN_Msk /*!< Enable asynchronous interrupt flag for end of measure for DTS1 */
#define DTS_ITENR_TS1_AITLEN_Pos (5U)
#define DTS_ITENR_TS1_AITLEN_Msk (0x1U << DTS_ITENR_TS1_AITLEN_Pos) /*!< 0x00000020 */
#define DTS_ITENR_TS1_AITLEN DTS_ITENR_TS1_AITLEN_Msk /*!< Enable Asynchronous interrupt flag for low threshold for DTS1 */
#define DTS_ITENR_TS1_AITHEN_Pos (6U)
#define DTS_ITENR_TS1_AITHEN_Msk (0x1U << DTS_ITENR_TS1_AITHEN_Pos) /*!< 0x00000040 */
#define DTS_ITENR_TS1_AITHEN DTS_ITENR_TS1_AITHEN_Msk /*!< Enable asynchronous interrupt flag for high threshold for DTS1 */
/****************** Bit definition for DTS_ICIFR register ******************/
#define DTS_ICIFR_TS1_CITEF_Pos (0U)
#define DTS_ICIFR_TS1_CITEF_Msk (0x1U << DTS_ICIFR_TS1_CITEF_Pos) /*!< 0x00000001 */
#define DTS_ICIFR_TS1_CITEF DTS_ICIFR_TS1_CITEF_Msk /*!< Clear the IT flag for End Of Measure for DTS1 */
#define DTS_ICIFR_TS1_CITLF_Pos (1U)
#define DTS_ICIFR_TS1_CITLF_Msk (0x1U << DTS_ICIFR_TS1_CITLF_Pos) /*!< 0x00000002 */
#define DTS_ICIFR_TS1_CITLF DTS_ICIFR_TS1_CITLF_Msk /*!< Clear the IT flag for low threshold for DTS1 */
#define DTS_ICIFR_TS1_CITHF_Pos (2U)
#define DTS_ICIFR_TS1_CITHF_Msk (0x1U << DTS_ICIFR_TS1_CITHF_Pos) /*!< 0x00000004 */
#define DTS_ICIFR_TS1_CITHF DTS_ICIFR_TS1_CITHF_Msk /*!< Clear the IT flag for high threshold on DTS1 */
#define DTS_ICIFR_TS1_CAITEF_Pos (4U)
#define DTS_ICIFR_TS1_CAITEF_Msk (0x1U << DTS_ICIFR_TS1_CAITEF_Pos) /*!< 0x00000010 */
#define DTS_ICIFR_TS1_CAITEF DTS_ICIFR_TS1_CAITEF_Msk /*!< Clear the asynchronous IT flag for End Of Measure for DTS1 */
#define DTS_ICIFR_TS1_CAITLF_Pos (5U)
#define DTS_ICIFR_TS1_CAITLF_Msk (0x1U << DTS_ICIFR_TS1_CAITLF_Pos) /*!< 0x00000020 */
#define DTS_ICIFR_TS1_CAITLF DTS_ICIFR_TS1_CAITLF_Msk /*!< Clear the asynchronous IT flag for low threshold for DTS1 */
#define DTS_ICIFR_TS1_CAITHF_Pos (6U)
#define DTS_ICIFR_TS1_CAITHF_Msk (0x1U << DTS_ICIFR_TS1_CAITHF_Pos) /*!< 0x00000040 */
#define DTS_ICIFR_TS1_CAITHF DTS_ICIFR_TS1_CAITHF_Msk /*!< Clear the asynchronous IT flag for high threshold on DTS1 */
/******************************************************************************/
/* */
/* TIM */
/* */
/******************************************************************************/
/******************* Bit definition for TIM_CR1 register ********************/
#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
#define TIM_CR1_UIFREMAP ((uint16_t)0x0800) /*!<Update interrupt flag remap */
/******************* Bit definition for TIM_CR2 register ********************/
#define TIM_CR2_CCPC_Pos (0U)
#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
#define TIM_CR2_CCUS_Pos (2U)
#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
#define TIM_CR2_CCDS_Pos (3U)
#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
#define TIM_CR2_MMS_Pos (4U)
#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
#define TIM_CR2_TI1S_Pos (7U)
#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
#define TIM_CR2_OIS1_Pos (8U)
#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
#define TIM_CR2_OIS1N_Pos (9U)
#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
#define TIM_CR2_OIS2_Pos (10U)
#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
#define TIM_CR2_OIS2N_Pos (11U)
#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
#define TIM_CR2_OIS3_Pos (12U)
#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
#define TIM_CR2_OIS3N_Pos (13U)
#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
#define TIM_CR2_OIS4_Pos (14U)
#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
#define TIM_CR2_OIS5_Pos (16U)
#define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
#define TIM_CR2_OIS6_Pos (18U)
#define TIM_CR2_OIS6_Msk (0x1U << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
#define TIM_CR2_MMS2_Pos (20U)
#define TIM_CR2_MMS2_Msk (0xFU << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
#define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
#define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
#define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
/******************* Bit definition for TIM_SMCR register *******************/
#define TIM_SMCR_SMS_Pos (0U)
#define TIM_SMCR_SMS_Msk (0x10007U << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
#define TIM_SMCR_SMS_0 (0x00001U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
#define TIM_SMCR_SMS_1 (0x00002U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2 (0x00004U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
#define TIM_SMCR_SMS_3 (0x10000U << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
#define TIM_SMCR_TS_Pos (4U)
#define TIM_SMCR_TS_Msk (0x30007U << TIM_SMCR_TS_Pos) /*!< 0x00300070 */
#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[4:0] bits (Trigger selection) */
#define TIM_SMCR_TS_0 (0x00001U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
#define TIM_SMCR_TS_1 (0x00002U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
#define TIM_SMCR_TS_2 (0x00004U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
#define TIM_SMCR_TS_3 (0x10000U << TIM_SMCR_TS_Pos) /*!< 0x00100000 */
#define TIM_SMCR_TS_4 (0x20000U << TIM_SMCR_TS_Pos) /*!< 0x00200000 */
#define TIM_SMCR_MSM_Pos (7U)
#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
#define TIM_SMCR_ETF_Pos (8U)
#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
#define TIM_SMCR_ETPS_Pos (12U)
#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
#define TIM_SMCR_ECE_Pos (14U)
#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
#define TIM_SMCR_ETP_Pos (15U)
#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
/******************* Bit definition for TIM_DIER register *******************/
#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
/******************** Bit definition for TIM_SR register ********************/
#define TIM_SR_UIF_Pos (0U)
#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
#define TIM_SR_CC1IF_Pos (1U)
#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
#define TIM_SR_CC2IF_Pos (2U)
#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
#define TIM_SR_CC3IF_Pos (3U)
#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
#define TIM_SR_CC4IF_Pos (4U)
#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
#define TIM_SR_COMIF_Pos (5U)
#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
#define TIM_SR_TIF_Pos (6U)
#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
#define TIM_SR_BIF_Pos (7U)
#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
#define TIM_SR_B2IF_Pos (8U)
#define TIM_SR_B2IF_Msk (0x1U << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break2 interrupt Flag */
#define TIM_SR_CC1OF_Pos (9U)
#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
#define TIM_SR_CC2OF_Pos (10U)
#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
#define TIM_SR_CC3OF_Pos (11U)
#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
#define TIM_SR_CC4OF_Pos (12U)
#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
#define TIM_SR_CC5IF_Pos (16U)
#define TIM_SR_CC5IF_Msk (0x1U << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
#define TIM_SR_CC6IF_Pos (17U)
#define TIM_SR_CC6IF_Msk (0x1U << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
#define TIM_SR_SBIF_Pos (13U)
#define TIM_SR_SBIF_Msk (0x1U << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!< System Break Flag */
/******************* Bit definition for TIM_EGR register ********************/
#define TIM_EGR_UG ((uint16_t)0x0001) /*!<Update Generation */
#define TIM_EGR_CC1G ((uint16_t)0x0002) /*!<Capture/Compare 1 Generation */
#define TIM_EGR_CC2G ((uint16_t)0x0004) /*!<Capture/Compare 2 Generation */
#define TIM_EGR_CC3G ((uint16_t)0x0008) /*!<Capture/Compare 3 Generation */
#define TIM_EGR_CC4G ((uint16_t)0x0010) /*!<Capture/Compare 4 Generation */
#define TIM_EGR_COMG ((uint16_t)0x0020) /*!<Capture/Compare Control Update Generation */
#define TIM_EGR_TG ((uint16_t)0x0040) /*!<Trigger Generation */
#define TIM_EGR_BG ((uint16_t)0x0080) /*!<Break Generation */
#define TIM_EGR_B2G ((uint16_t)0x0100) /*!<Break Generation */
/****************** Bit definition for TIM_CCMR1 register *******************/
#define TIM_CCMR1_CC1S_Pos (0U)
#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
#define TIM_CCMR1_OC1FE_Pos (2U)
#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
#define TIM_CCMR1_OC1PE_Pos (3U)
#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
#define TIM_CCMR1_OC1M_Pos (4U)
#define TIM_CCMR1_OC1M_Msk (0x1007U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
#define TIM_CCMR1_OC1M_0 (0x0001U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
#define TIM_CCMR1_OC1M_1 (0x0002U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
#define TIM_CCMR1_OC1M_2 (0x0004U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
#define TIM_CCMR1_OC1M_3 (0x1000U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
#define TIM_CCMR1_OC1CE_Pos (7U)
#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
#define TIM_CCMR1_CC2S_Pos (8U)
#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
#define TIM_CCMR1_OC2FE_Pos (10U)
#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
#define TIM_CCMR1_OC2PE_Pos (11U)
#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
#define TIM_CCMR1_OC2M_Pos (12U)
#define TIM_CCMR1_OC2M_Msk (0x1007U << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
#define TIM_CCMR1_OC2M_0 (0x0001U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
#define TIM_CCMR1_OC2M_1 (0x0002U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
#define TIM_CCMR1_OC2M_2 (0x0004U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
#define TIM_CCMR1_OC2M_3 (0x1000U << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
#define TIM_CCMR1_OC2CE_Pos (15U)
#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
/*----------------------------------------------------------------------------*/
#define TIM_CCMR1_IC1PSC_Pos (2U)
#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
#define TIM_CCMR1_IC1F_Pos (4U)
#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
#define TIM_CCMR1_IC2PSC_Pos (10U)
#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
#define TIM_CCMR1_IC2F_Pos (12U)
#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
/****************** Bit definition for TIM_CCMR2 register *******************/
#define TIM_CCMR2_CC3S_Pos (0U)
#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
#define TIM_CCMR2_OC3FE_Pos (2U)
#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
#define TIM_CCMR2_OC3PE_Pos (3U)
#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
#define TIM_CCMR2_OC3M_Pos (4U)
#define TIM_CCMR2_OC3M_Msk (0x1007U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
#define TIM_CCMR2_OC3M_0 (0x0001U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
#define TIM_CCMR2_OC3M_1 (0x0002U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
#define TIM_CCMR2_OC3M_2 (0x0004U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
#define TIM_CCMR2_OC3M_3 (0x1000U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
#define TIM_CCMR2_OC3CE_Pos (7U)
#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
#define TIM_CCMR2_CC4S_Pos (8U)
#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
#define TIM_CCMR2_OC4FE_Pos (10U)
#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
#define TIM_CCMR2_OC4PE_Pos (11U)
#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
#define TIM_CCMR2_OC4M_Pos (12U)
#define TIM_CCMR2_OC4M_Msk (0x1007U << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
#define TIM_CCMR2_OC4M_0 (0x0001U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
#define TIM_CCMR2_OC4M_1 (0x0002U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
#define TIM_CCMR2_OC4M_2 (0x0004U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
#define TIM_CCMR2_OC4M_3 (0x1000U << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
#define TIM_CCMR2_OC4CE_Pos (15U)
#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
/*----------------------------------------------------------------------------*/
#define TIM_CCMR2_IC3PSC ((uint16_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x00000004) /*!<Bit 0 */
#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x00000008) /*!<Bit 1 */
#define TIM_CCMR2_IC3F ((uint16_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
#define TIM_CCMR2_IC3F_0 ((uint16_t)0x00000010) /*!<Bit 0 */
#define TIM_CCMR2_IC3F_1 ((uint16_t)0x00000020) /*!<Bit 1 */
#define TIM_CCMR2_IC3F_2 ((uint16_t)0x00000040) /*!<Bit 2 */
#define TIM_CCMR2_IC3F_3 ((uint16_t)0x00000080) /*!<Bit 3 */
#define TIM_CCMR2_IC4PSC ((uint16_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x00000400) /*!<Bit 0 */
#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x00000800) /*!<Bit 1 */
#define TIM_CCMR2_IC4F ((uint16_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
#define TIM_CCMR2_IC4F_0 ((uint16_t)0x00001000) /*!<Bit 0 */
#define TIM_CCMR2_IC4F_1 ((uint16_t)0x00002000) /*!<Bit 1 */
#define TIM_CCMR2_IC4F_2 ((uint16_t)0x00004000) /*!<Bit 2 */
#define TIM_CCMR2_IC4F_3 ((uint16_t)0x00008000) /*!<Bit 3 */
/******************* Bit definition for TIM_CCER register *******************/
#define TIM_CCER_CC1E_Pos (0U)
#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
#define TIM_CCER_CC1P_Pos (1U)
#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
#define TIM_CCER_CC1NE_Pos (2U)
#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
#define TIM_CCER_CC1NP_Pos (3U)
#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
#define TIM_CCER_CC2E_Pos (4U)
#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
#define TIM_CCER_CC2P_Pos (5U)
#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
#define TIM_CCER_CC2NE_Pos (6U)
#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
#define TIM_CCER_CC2NP_Pos (7U)
#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
#define TIM_CCER_CC3E_Pos (8U)
#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
#define TIM_CCER_CC3P_Pos (9U)
#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
#define TIM_CCER_CC3NE_Pos (10U)
#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
#define TIM_CCER_CC3NP_Pos (11U)
#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
#define TIM_CCER_CC4E_Pos (12U)
#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
#define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
#define TIM_CCER_CC4NP_Pos (15U)
#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
#define TIM_CCER_CC5E_Pos (16U)
#define TIM_CCER_CC5E_Msk (0x1U << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
#define TIM_CCER_CC5P_Pos (17U)
#define TIM_CCER_CC5P_Msk (0x1U << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
#define TIM_CCER_CC6E_Pos (20U)
#define TIM_CCER_CC6E_Msk (0x1U << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
#define TIM_CCER_CC6P_Pos (21U)
#define TIM_CCER_CC6P_Msk (0x1U << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
/******************* Bit definition for TIM_CNT register ********************/
#define TIM_CNT_CNT_Pos (0U)
#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
#define TIM_CNT_UIFCPY_Pos (31U)
#define TIM_CNT_UIFCPY_Msk (0x1U << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy */
/******************* Bit definition for TIM_PSC register ********************/
#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
/******************* Bit definition for TIM_ARR register ********************/
#define TIM_ARR_ARR_Pos (0U)
#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
/******************* Bit definition for TIM_RCR register ********************/
#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
/******************* Bit definition for TIM_CCR2 register *******************/
#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
/******************* Bit definition for TIM_CCR3 register *******************/
#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
/******************* Bit definition for TIM_CCR4 register *******************/
#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1U << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
#define TIM_CCR5_GC5C2_Pos (30U)
#define TIM_CCR5_GC5C2_Msk (0x1U << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
#define TIM_CCR5_GC5C3_Pos (31U)
#define TIM_CCR5_GC5C3_Msk (0x1U << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
/******************* Bit definition for TIM_CCR6 register *******************/
#define TIM_CCR6_CCR6 ((uint16_t)0xFFFF) /*!<Capture/Compare 6 Value */
/******************* Bit definition for TIM_BDTR register *******************/
#define TIM_BDTR_DTG_Pos (0U)
#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
#define TIM_BDTR_LOCK_Pos (8U)
#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
#define TIM_BDTR_OSSI_Pos (10U)
#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
#define TIM_BDTR_OSSR_Pos (11U)
#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
#define TIM_BDTR_BKE_Pos (12U)
#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break1 */
#define TIM_BDTR_BKP_Pos (13U)
#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break1 */
#define TIM_BDTR_AOE_Pos (14U)
#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
#define TIM_BDTR_MOE_Pos (15U)
#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
#define TIM_BDTR_BKF_Pos (16U)
#define TIM_BDTR_BKF_Msk (0xFU << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break1 */
#define TIM_BDTR_BK2F_Pos (20U)
#define TIM_BDTR_BK2F_Msk (0xFU << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break2 */
#define TIM_BDTR_BK2E_Pos (24U)
#define TIM_BDTR_BK2E_Msk (0x1U << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break2 */
#define TIM_BDTR_BK2P_Pos (25U)
#define TIM_BDTR_BK2P_Msk (0x1U << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
#define TIM_BDTR_BKDSRM_Pos (26U)
#define TIM_BDTR_BKDSRM_Msk (0x1U << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break Disarmed for Break1 */
#define TIM_BDTR_BK2DSRM_Pos (27U)
#define TIM_BDTR_BK2DSRM_Msk (0x1U << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break Disarmed for Break2 */
#define TIM_BDTR_BKBID_Pos (28U)
#define TIM_BDTR_BKBID_Msk (0x1U << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break Bidirectionnal for Break1 */
#define TIM_BDTR_BK2BID_Pos (29U)
#define TIM_BDTR_BK2BID_Msk (0x1U << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break Bidirectionnal for Break2 */
/******************* Bit definition for TIM_DCR register ********************/
#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
/******************* Bit definition for TIM_DMAR register *******************/
#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
/******************* Bit definition for TIM16_OR register *********************/
#define TIM16_OR_TI1_RMP ((uint16_t)0x00C0) /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
#define TIM16_OR_TI1_RMP_0 ((uint16_t)0x0040) /*!<Bit 0 */
#define TIM16_OR_TI1_RMP_1 ((uint16_t)0x0080) /*!<Bit 1 */
/******************* Bit definition for TIM1_OR register *********************/
#define TIM1_OR_ETR_RMP ((uint16_t)0x000F) /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
#define TIM1_OR_ETR_RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */
#define TIM1_OR_ETR_RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */
#define TIM1_OR_ETR_RMP_2 ((uint16_t)0x0004) /*!<Bit 2 */
#define TIM1_OR_ETR_RMP_3 ((uint16_t)0x0008) /*!<Bit 3 */
/******************* Bit definition for TIM8_OR register *********************/
#define TIM8_OR_ETR_RMP ((uint16_t)0x000F) /*!<ETR_RMP[3:0] bits (TIM8 ETR remap) */
#define TIM8_OR_ETR_RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */
#define TIM8_OR_ETR_RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */
#define TIM8_OR_ETR_RMP_2 ((uint16_t)0x0004) /*!<Bit 2 */
#define TIM8_OR_ETR_RMP_3 ((uint16_t)0x0008) /*!<Bit 3 */
/****************** Bit definition for TIM_CCMR3 register *******************/
#define TIM_CCMR3_OC5FE_Pos (2U)
#define TIM_CCMR3_OC5FE_Msk (0x1U << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
#define TIM_CCMR3_OC5PE_Pos (3U)
#define TIM_CCMR3_OC5PE_Msk (0x1U << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
#define TIM_CCMR3_OC5M_Pos (4U)
#define TIM_CCMR3_OC5M_Msk (0x1007U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
#define TIM_CCMR3_OC5M_0 (0x0001U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
#define TIM_CCMR3_OC5M_1 (0x0002U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
#define TIM_CCMR3_OC5M_2 (0x0004U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
#define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
#define TIM_CCMR3_OC5CE_Pos (7U)
#define TIM_CCMR3_OC5CE_Msk (0x1U << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
#define TIM_CCMR3_OC6FE_Pos (10U)
#define TIM_CCMR3_OC6FE_Msk (0x1U << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 4 Fast enable */
#define TIM_CCMR3_OC6PE_Pos (11U)
#define TIM_CCMR3_OC6PE_Msk (0x1U << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
#define TIM_CCMR3_OC6M_Pos (12U)
#define TIM_CCMR3_OC6M_Msk (0x1007U << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
#define TIM_CCMR3_OC6M_0 (0x0001U << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
#define TIM_CCMR3_OC6M_1 (0x0002U << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
#define TIM_CCMR3_OC6M_2 (0x0004U << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
#define TIM_CCMR3_OC6M_3 (0x1000U << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
#define TIM_CCMR3_OC6CE_Pos (15U)
#define TIM_CCMR3_OC6CE_Msk (0x1U << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 4 Clear Enable */
/******************* Bit definition for TIM1_AF1 register *********************/
#define TIM1_AF1_BKINE_Pos (0U)
#define TIM1_AF1_BKINE_Msk (0x1U << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
#define TIM1_AF1_BKDF1BK0E_Pos (8U)
#define TIM1_AF1_BKDF1BK0E_Msk (0x1U << TIM1_AF1_BKDF1BK0E_Pos) /*!< 0x00000100 */
#define TIM1_AF1_BKDF1BK0E TIM1_AF1_BKDF1BK0E_Msk /*!<BKDF1BK0E Break input DFSDM Break 0 */
#define TIM1_AF1_BKINP_Pos (9U)
#define TIM1_AF1_BKINP_Msk (0x1U << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
#define TIM1_AF1_ETRSEL_Pos (14U)
#define TIM1_AF1_ETRSEL_Msk (0xFU << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
#define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETR SEL) */
#define TIM1_AF1_ETRSEL_0 (0x1U << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */
#define TIM1_AF1_ETRSEL_1 (0x2U << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */
#define TIM1_AF1_ETRSEL_2 (0x4U << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */
#define TIM1_AF1_ETRSEL_3 (0x8U << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */
/******************* Bit definition for TIM1_AF2 register *********************/
#define TIM1_AF2_BK2INE_Pos (0U)
#define TIM1_AF2_BK2INE_Msk (0x1U << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BK2INE Break input 2 enable bit */
#define TIM1_AF2_BK2DF1BK1E_Pos (8U)
#define TIM1_AF2_BK2DF1BK1E_Msk (0x1U << TIM1_AF2_BK2DF1BK1E_Pos) /*!< 0x00000100 */
#define TIM1_AF2_BK2DF1BK1E TIM1_AF2_BK2DF1BK1E_Msk /*!<BK2DF1BK1E Break input2 DFSDM Break 1 */
#define TIM1_AF2_BK2INP_Pos (9U)
#define TIM1_AF2_BK2INP_Msk (0x1U << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRKINP Break2 input polarity */
/******************* Bit definition for TIM1_TISEL register *********************/
#define TIM1_TISEL_TI1SEL_Pos (0U)
#define TIM1_TISEL_TI1SEL_Msk (0xFU << TIM1_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM1_TISEL_TI1SEL TIM1_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
#define TIM1_TISEL_TI1SEL_0 (0x1U << TIM1_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM1_TISEL_TI1SEL_1 (0x2U << TIM1_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM1_TISEL_TI1SEL_2 (0x4U << TIM1_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM1_TISEL_TI1SEL_3 (0x8U << TIM1_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
#define TIM1_TISEL_TI2SEL_Pos (8U)
#define TIM1_TISEL_TI2SEL_Msk (0xFU << TIM1_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
#define TIM1_TISEL_TI2SEL TIM1_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
#define TIM1_TISEL_TI2SEL_0 (0x1U << TIM1_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
#define TIM1_TISEL_TI2SEL_1 (0x2U << TIM1_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
#define TIM1_TISEL_TI2SEL_2 (0x4U << TIM1_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
#define TIM1_TISEL_TI2SEL_3 (0x8U << TIM1_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
#define TIM1_TISEL_TI3SEL_Pos (16U)
#define TIM1_TISEL_TI3SEL_Msk (0xFU << TIM1_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
#define TIM1_TISEL_TI3SEL TIM1_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
#define TIM1_TISEL_TI3SEL_0 (0x1U << TIM1_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
#define TIM1_TISEL_TI3SEL_1 (0x2U << TIM1_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
#define TIM1_TISEL_TI3SEL_2 (0x4U << TIM1_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
#define TIM1_TISEL_TI3SEL_3 (0x8U << TIM1_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
#define TIM1_TISEL_TI4SEL_Pos (24U)
#define TIM1_TISEL_TI4SEL_Msk (0xFU << TIM1_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
#define TIM1_TISEL_TI4SEL TIM1_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
#define TIM1_TISEL_TI4SEL_0 (0x1U << TIM1_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
#define TIM1_TISEL_TI4SEL_1 (0x2U << TIM1_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
#define TIM1_TISEL_TI4SEL_2 (0x4U << TIM1_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
#define TIM1_TISEL_TI4SEL_3 (0x8U << TIM1_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
/******************* Bit definition for TIM8_AF1 register *********************/
#define TIM8_AF1_BKINE_Pos (0U)
#define TIM8_AF1_BKINE_Msk (0x1U << TIM8_AF1_BKINE_Pos) /*!< 0x00000001 */
#define TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
#define TIM8_AF1_BKDFBK2E_Pos (8U)
#define TIM8_AF1_BKDFBK2E_Msk (0x1U << TIM8_AF1_BKDFBK2E_Pos) /*!< 0x00000100 */
#define TIM8_AF1_BKDFBK2E TIM8_AF1_BKDFBK2E_Msk /*!<BKDFBK2E Break input DFSDM Break 2 */
#define TIM8_AF1_BKINP_Pos (9U)
#define TIM8_AF1_BKINP_Msk (0x1U << TIM8_AF1_BKINP_Pos) /*!< 0x00000200 */
#define TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
#define TIM8_AF1_ETRSEL_Pos (14U)
#define TIM8_AF1_ETRSEL_Msk (0xFU << TIM8_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
#define TIM8_AF1_ETRSEL TIM8_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM8 ETR SEL) */
#define TIM8_AF1_ETRSEL_0 (0x1U << TIM8_AF1_ETRSEL_Pos) /*!< 0x00004000 */
#define TIM8_AF1_ETRSEL_1 (0x2U << TIM8_AF1_ETRSEL_Pos) /*!< 0x00008000 */
#define TIM8_AF1_ETRSEL_2 (0x4U << TIM8_AF1_ETRSEL_Pos) /*!< 0x00010000 */
#define TIM8_AF1_ETRSEL_3 (0x8U << TIM8_AF1_ETRSEL_Pos) /*!< 0x00020000 */
/******************* Bit definition for TIM8_AF2 register *********************/
#define TIM8_AF2_BK2INE_Pos (0U)
#define TIM8_AF2_BK2INE_Msk (0x1U << TIM8_AF2_BK2INE_Pos) /*!< 0x00000001 */
#define TIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk /*!<BK2INE Break input 2 enable bit */
#define TIM8_AF2_BK2DFBK3E_Pos (8U)
#define TIM8_AF2_BK2DFBK3E_Msk (0x1U << TIM8_AF2_BK2DFBK3E_Pos) /*!< 0x00000100 */
#define TIM8_AF2_BK2DFBK3E TIM8_AF2_BK2DFBK3E_Msk /*!<BK2DFBK1E Break input2 DFSDM Break 3 */
#define TIM8_AF2_BK2INP_Pos (9U)
#define TIM8_AF2_BK2INP_Msk (0x1U << TIM8_AF2_BK2INP_Pos) /*!< 0x00000200 */
#define TIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk /*!<BRKINP Break2 input polarity */
/******************* Bit definition for TIM8_TISEL register *********************/
#define TIM8_TISEL_TI1SEL_Pos (0U)
#define TIM8_TISEL_TI1SEL_Msk (0xFU << TIM8_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM8_TISEL_TI1SEL TIM8_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM8 TI1 SEL)*/
#define TIM8_TISEL_TI1SEL_0 (0x1U << TIM8_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM8_TISEL_TI1SEL_1 (0x2U << TIM8_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM8_TISEL_TI1SEL_2 (0x4U << TIM8_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM8_TISEL_TI1SEL_3 (0x8U << TIM8_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
#define TIM8_TISEL_TI2SEL_Pos (8U)
#define TIM8_TISEL_TI2SEL_Msk (0xFU << TIM8_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
#define TIM8_TISEL_TI2SEL TIM8_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM8 TI2 SEL)*/
#define TIM8_TISEL_TI2SEL_0 (0x1U << TIM8_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
#define TIM8_TISEL_TI2SEL_1 (0x2U << TIM8_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
#define TIM8_TISEL_TI2SEL_2 (0x4U << TIM8_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
#define TIM8_TISEL_TI2SEL_3 (0x8U << TIM8_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
#define TIM8_TISEL_TI3SEL_Pos (16U)
#define TIM8_TISEL_TI3SEL_Msk (0xFU << TIM8_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
#define TIM8_TISEL_TI3SEL TIM8_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM8 TI3 SEL)*/
#define TIM8_TISEL_TI3SEL_0 (0x1U << TIM8_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
#define TIM8_TISEL_TI3SEL_1 (0x2U << TIM8_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
#define TIM8_TISEL_TI3SEL_2 (0x4U << TIM8_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
#define TIM8_TISEL_TI3SEL_3 (0x8U << TIM8_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
#define TIM8_TISEL_TI4SEL_Pos (24U)
#define TIM8_TISEL_TI4SEL_Msk (0xFU << TIM8_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
#define TIM8_TISEL_TI4SEL TIM8_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM8 TI4 SEL)*/
#define TIM8_TISEL_TI4SEL_0 (0x1U << TIM8_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
#define TIM8_TISEL_TI4SEL_1 (0x2U << TIM8_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
#define TIM8_TISEL_TI4SEL_2 (0x4U << TIM8_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
#define TIM8_TISEL_TI4SEL_3 (0x8U << TIM8_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
/******************* Bit definition for TIM2_AF1 register *********************/
#define TIM2_AF1_ETRSEL_Pos (14U)
#define TIM2_AF1_ETRSEL_Msk (0xFU << TIM2_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
#define TIM2_AF1_ETRSEL TIM2_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM2 ETR SEL) */
#define TIM2_AF1_ETRSEL_0 (0x1U << TIM2_AF1_ETRSEL_Pos) /*!< 0x00004000 */
#define TIM2_AF1_ETRSEL_1 (0x2U << TIM2_AF1_ETRSEL_Pos) /*!< 0x00008000 */
#define TIM2_AF1_ETRSEL_2 (0x4U << TIM2_AF1_ETRSEL_Pos) /*!< 0x00010000 */
#define TIM2_AF1_ETRSEL_3 (0x8U << TIM2_AF1_ETRSEL_Pos) /*!< 0x00020000 */
/******************* Bit definition for TIM2_TISEL register *********************/
#define TIM2_TISEL_TI1SEL_Pos (0U)
#define TIM2_TISEL_TI1SEL_Msk (0xFU << TIM2_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM2_TISEL_TI1SEL TIM2_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
#define TIM2_TISEL_TI1SEL_0 (0x1U << TIM2_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM2_TISEL_TI1SEL_1 (0x2U << TIM2_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM2_TISEL_TI1SEL_2 (0x4U << TIM2_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM2_TISEL_TI1SEL_3 (0x8U << TIM2_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
#define TIM2_TISEL_TI2SEL_Pos (8U)
#define TIM2_TISEL_TI2SEL_Msk (0xFU << TIM2_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
#define TIM2_TISEL_TI2SEL TIM2_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM2 TI2 SEL)*/
#define TIM2_TISEL_TI2SEL_0 (0x1U << TIM2_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
#define TIM2_TISEL_TI2SEL_1 (0x2U << TIM2_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
#define TIM2_TISEL_TI2SEL_2 (0x4U << TIM2_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
#define TIM2_TISEL_TI2SEL_3 (0x8U << TIM2_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
#define TIM2_TISEL_TI3SEL_Pos (16U)
#define TIM2_TISEL_TI3SEL_Msk (0xFU << TIM2_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
#define TIM2_TISEL_TI3SEL TIM2_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM2 TI3 SEL)*/
#define TIM2_TISEL_TI3SEL_0 (0x1U << TIM2_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
#define TIM2_TISEL_TI3SEL_1 (0x2U << TIM2_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
#define TIM2_TISEL_TI3SEL_2 (0x4U << TIM2_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
#define TIM2_TISEL_TI3SEL_3 (0x8U << TIM2_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
#define TIM2_TISEL_TI4SEL_Pos (24U)
#define TIM2_TISEL_TI4SEL_Msk (0xFU << TIM2_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
#define TIM2_TISEL_TI4SEL TIM2_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM2 TI4 SEL)*/
#define TIM2_TISEL_TI4SEL_0 (0x1U << TIM2_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
#define TIM2_TISEL_TI4SEL_1 (0x2U << TIM2_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
#define TIM2_TISEL_TI4SEL_2 (0x4U << TIM2_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
#define TIM2_TISEL_TI4SEL_3 (0x8U << TIM2_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
/******************* Bit definition for TIM3_AF1 register *********************/
#define TIM3_AF1_ETRSEL_Pos (14U)
#define TIM3_AF1_ETRSEL_Msk (0xFU << TIM3_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
#define TIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM3 ETR SEL) */
#define TIM3_AF1_ETRSEL_0 (0x1U << TIM3_AF1_ETRSEL_Pos) /*!< 0x00004000 */
#define TIM3_AF1_ETRSEL_1 (0x2U << TIM3_AF1_ETRSEL_Pos) /*!< 0x00008000 */
#define TIM3_AF1_ETRSEL_2 (0x4U << TIM3_AF1_ETRSEL_Pos) /*!< 0x00010000 */
#define TIM3_AF1_ETRSEL_3 (0x8U << TIM3_AF1_ETRSEL_Pos) /*!< 0x00020000 */
/******************* Bit definition for TIM3_TISEL register *********************/
#define TIM3_TISEL_TI1SEL_Pos (0U)
#define TIM3_TISEL_TI1SEL_Msk (0xFU << TIM3_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM3_TISEL_TI1SEL TIM3_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM3 TI1 SEL)*/
#define TIM3_TISEL_TI1SEL_0 (0x1U << TIM3_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM3_TISEL_TI1SEL_1 (0x2U << TIM3_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM3_TISEL_TI1SEL_2 (0x4U << TIM3_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM3_TISEL_TI1SEL_3 (0x8U << TIM3_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
#define TIM3_TISEL_TI2SEL_Pos (8U)
#define TIM3_TISEL_TI2SEL_Msk (0xFU << TIM3_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
#define TIM3_TISEL_TI2SEL TIM3_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM3 TI2 SEL)*/
#define TIM3_TISEL_TI2SEL_0 (0x1U << TIM3_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
#define TIM3_TISEL_TI2SEL_1 (0x2U << TIM3_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
#define TIM3_TISEL_TI2SEL_2 (0x4U << TIM3_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
#define TIM3_TISEL_TI2SEL_3 (0x8U << TIM3_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
#define TIM3_TISEL_TI3SEL_Pos (16U)
#define TIM3_TISEL_TI3SEL_Msk (0xFU << TIM3_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
#define TIM3_TISEL_TI3SEL TIM3_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM3 TI3 SEL)*/
#define TIM3_TISEL_TI3SEL_0 (0x1U << TIM3_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
#define TIM3_TISEL_TI3SEL_1 (0x2U << TIM3_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
#define TIM3_TISEL_TI3SEL_2 (0x4U << TIM3_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
#define TIM3_TISEL_TI3SEL_3 (0x8U << TIM3_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
#define TIM3_TISEL_TI4SEL_Pos (24U)
#define TIM3_TISEL_TI4SEL_Msk (0xFU << TIM3_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
#define TIM3_TISEL_TI4SEL TIM3_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM3 TI4 SEL)*/
#define TIM3_TISEL_TI4SEL_0 (0x1U << TIM3_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
#define TIM3_TISEL_TI4SEL_1 (0x2U << TIM3_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
#define TIM3_TISEL_TI4SEL_2 (0x4U << TIM3_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
#define TIM3_TISEL_TI4SEL_3 (0x8U << TIM3_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
/******************* Bit definition for TIM4_AF1 register *********************/
#define TIM4_AF1_ETRSEL_Pos (14U)
#define TIM4_AF1_ETRSEL_Msk (0xFU << TIM4_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
#define TIM4_AF1_ETRSEL TIM4_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM4 ETR SEL) */
#define TIM4_AF1_ETRSEL_0 (0x1U << TIM4_AF1_ETRSEL_Pos) /*!< 0x00004000 */
#define TIM4_AF1_ETRSEL_1 (0x2U << TIM4_AF1_ETRSEL_Pos) /*!< 0x00008000 */
#define TIM4_AF1_ETRSEL_2 (0x4U << TIM4_AF1_ETRSEL_Pos) /*!< 0x00010000 */
#define TIM4_AF1_ETRSEL_3 (0x8U << TIM4_AF1_ETRSEL_Pos) /*!< 0x00020000 */
/******************* Bit definition for TIM4_TISEL register *********************/
#define TIM4_TISEL_TI1SEL_Pos (0U)
#define TIM4_TISEL_TI1SEL_Msk (0xFU << TIM4_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM4_TISEL_TI1SEL TIM4_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM4 TI1 SEL)*/
#define TIM4_TISEL_TI1SEL_0 (0x1U << TIM4_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM4_TISEL_TI1SEL_1 (0x2U << TIM4_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM4_TISEL_TI1SEL_2 (0x4U << TIM4_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM4_TISEL_TI1SEL_3 (0x8U << TIM4_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
#define TIM4_TISEL_TI2SEL_Pos (8U)
#define TIM4_TISEL_TI2SEL_Msk (0xFU << TIM4_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
#define TIM4_TISEL_TI2SEL TIM4_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM4 TI2 SEL)*/
#define TIM4_TISEL_TI2SEL_0 (0x1U << TIM4_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
#define TIM4_TISEL_TI2SEL_1 (0x2U << TIM4_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
#define TIM4_TISEL_TI2SEL_2 (0x4U << TIM4_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
#define TIM4_TISEL_TI2SEL_3 (0x8U << TIM4_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
#define TIM4_TISEL_TI3SEL_Pos (16U)
#define TIM4_TISEL_TI3SEL_Msk (0xFU << TIM4_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
#define TIM4_TISEL_TI3SEL TIM4_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM4 TI3 SEL)*/
#define TIM4_TISEL_TI3SEL_0 (0x1U << TIM4_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
#define TIM4_TISEL_TI3SEL_1 (0x2U << TIM4_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
#define TIM4_TISEL_TI3SEL_2 (0x4U << TIM4_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
#define TIM4_TISEL_TI3SEL_3 (0x8U << TIM4_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
#define TIM4_TISEL_TI4SEL_Pos (24U)
#define TIM4_TISEL_TI4SEL_Msk (0xFU << TIM4_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
#define TIM4_TISEL_TI4SEL TIM4_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM4 TI4 SEL)*/
#define TIM4_TISEL_TI4SEL_0 (0x1U << TIM4_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
#define TIM4_TISEL_TI4SEL_1 (0x2U << TIM4_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
#define TIM4_TISEL_TI4SEL_2 (0x4U << TIM4_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
#define TIM4_TISEL_TI4SEL_3 (0x8U << TIM4_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
/******************* Bit definition for TIM5_AF1 register *********************/
#define TIM5_AF1_ETRSEL_Pos (14U)
#define TIM5_AF1_ETRSEL_Msk (0xFU << TIM5_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
#define TIM5_AF1_ETRSEL TIM5_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM5 ETR SEL) */
#define TIM5_AF1_ETRSEL_0 (0x1U << TIM5_AF1_ETRSEL_Pos) /*!< 0x00004000 */
#define TIM5_AF1_ETRSEL_1 (0x2U << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */
#define TIM5_AF1_ETRSEL_2 (0x4U << TIM5_AF1_ETRSEL_Pos) /*!< 0x00010000 */
#define TIM5_AF1_ETRSEL_3 (0x8U << TIM5_AF1_ETRSEL_Pos) /*!< 0x00020000 */
/******************* Bit definition for TIM5_TISEL register *********************/
#define TIM5_TISEL_TI1SEL_Pos (0U)
#define TIM5_TISEL_TI1SEL_Msk (0xFU << TIM5_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM5_TISEL_TI1SEL TIM5_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM3 TI1 SEL)*/
#define TIM5_TISEL_TI1SEL_0 (0x1U << TIM5_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM5_TISEL_TI1SEL_1 (0x2U << TIM5_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM5_TISEL_TI1SEL_2 (0x4U << TIM5_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM5_TISEL_TI1SEL_3 (0x8U << TIM5_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
#define TIM5_TISEL_TI2SEL_Pos (8U)
#define TIM5_TISEL_TI2SEL_Msk (0xFU << TIM5_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
#define TIM5_TISEL_TI2SEL TIM5_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM3 TI2 SEL)*/
#define TIM5_TISEL_TI2SEL_0 (0x1U << TIM5_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
#define TIM5_TISEL_TI2SEL_1 (0x2U << TIM5_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
#define TIM5_TISEL_TI2SEL_2 (0x4U << TIM5_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
#define TIM5_TISEL_TI2SEL_3 (0x8U << TIM5_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
#define TIM5_TISEL_TI3SEL_Pos (16U)
#define TIM5_TISEL_TI3SEL_Msk (0xFU << TIM5_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
#define TIM5_TISEL_TI3SEL TIM5_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM3 TI3 SEL)*/
#define TIM5_TISEL_TI3SEL_0 (0x1U << TIM5_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
#define TIM5_TISEL_TI3SEL_1 (0x2U << TIM5_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
#define TIM5_TISEL_TI3SEL_2 (0x4U << TIM5_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
#define TIM5_TISEL_TI3SEL_3 (0x8U << TIM5_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
#define TIM5_TISEL_TI4SEL_Pos (24U)
#define TIM5_TISEL_TI4SEL_Msk (0xFU << TIM5_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
#define TIM5_TISEL_TI4SEL TIM5_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM3 TI4 SEL)*/
#define TIM5_TISEL_TI4SEL_0 (0x1U << TIM5_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
#define TIM5_TISEL_TI4SEL_1 (0x2U << TIM5_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
#define TIM5_TISEL_TI4SEL_2 (0x4U << TIM5_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
#define TIM5_TISEL_TI4SEL_3 (0x8U << TIM5_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
/******************* Bit definition for TIM15_AF1 register *********************/
#define TIM15_AF1_BKINE_Pos (0U)
#define TIM15_AF1_BKINE_Msk (0x1U << TIM15_AF1_BKINE_Pos) /*!< 0x00000001 */
#define TIM15_AF1_BKINE TIM15_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
#define TIM15_AF1_BKCMP1E_Pos (1U)
#define TIM15_AF1_BKCMP1E_Msk (0x1U << TIM15_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
#define TIM15_AF1_BKCMP1E TIM15_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
#define TIM15_AF1_BKCMP2E_Pos (2U)
#define TIM15_AF1_BKCMP2E_Msk (0x1U << TIM15_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
#define TIM15_AF1_BKCMP2E TIM15_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
#define TIM15_AF1_BKDF1BK2E_Pos (8U)
#define TIM15_AF1_BKDF1BK2E_Msk (0x1U << TIM15_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
#define TIM15_AF1_BKDF1BK2E TIM15_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[0] enable */
#define TIM15_AF1_BKINP_Pos (9U)
#define TIM15_AF1_BKINP_Msk (0x1U << TIM15_AF1_BKINP_Pos) /*!< 0x00000200 */
#define TIM15_AF1_BKINP TIM15_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
#define TIM15_AF1_BKCMP1P_Pos (10U)
#define TIM15_AF1_BKCMP1P_Msk (0x1U << TIM15_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
#define TIM15_AF1_BKCMP1P TIM15_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
#define TIM15_AF1_BKCMP2P_Pos (11U)
#define TIM15_AF1_BKCMP2P_Msk (0x1U << TIM15_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
#define TIM15_AF1_BKCMP2P TIM15_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
/******************* Bit definition for TIM15_TISEL register *********************/
#define TIM15_TISEL_TI1SEL_Pos (0U)
#define TIM15_TISEL_TI1SEL_Msk (0xFU << TIM15_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM15_TISEL_TI1SEL TIM15_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM15 TI1 SEL)*/
#define TIM15_TISEL_TI1SEL_0 (0x1U << TIM15_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM15_TISEL_TI1SEL_1 (0x2U << TIM15_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM15_TISEL_TI1SEL_2 (0x4U << TIM15_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM15_TISEL_TI1SEL_3 (0x8U << TIM15_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
#define TIM15_TISEL_TI2SEL_Pos (8U)
#define TIM15_TISEL_TI2SEL_Msk (0xFU << TIM15_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
#define TIM15_TISEL_TI2SEL TIM15_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM15 TI2 SEL)*/
#define TIM15_TISEL_TI2SEL_0 (0x1U << TIM15_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
#define TIM15_TISEL_TI2SEL_1 (0x2U << TIM15_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
#define TIM15_TISEL_TI2SEL_2 (0x4U << TIM15_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
#define TIM15_TISEL_TI2SEL_3 (0x8U << TIM15_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
/******************* Bit definition for TIM12_TISEL register *********************/
#define TIM12_TISEL_TI1SEL_Pos (0U)
#define TIM12_TISEL_TI1SEL_Msk (0xFU << TIM12_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM12_TISEL_TI1SEL TIM12_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM12 TI1 SEL)*/
#define TIM12_TISEL_TI1SEL_0 (0x1U << TIM12_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM12_TISEL_TI1SEL_1 (0x2U << TIM12_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM12_TISEL_TI1SEL_2 (0x4U << TIM12_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM12_TISEL_TI1SEL_3 (0x8U << TIM12_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
#define TIM12_TISEL_TI2SEL_Pos (8U)
#define TIM12_TISEL_TI2SEL_Msk (0xFU << TIM12_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
#define TIM12_TISEL_TI2SEL TIM12_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM15 TI2 SEL)*/
#define TIM12_TISEL_TI2SEL_0 (0x1U << TIM12_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
#define TIM12_TISEL_TI2SEL_1 (0x2U << TIM12_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
#define TIM12_TISEL_TI2SEL_2 (0x4U << TIM12_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
#define TIM12_TISEL_TI2SEL_3 (0x8U << TIM12_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
/******************* Bit definition for TIM16_ register *********************/
#define TIM16_AF1_BKINE_Pos (0U)
#define TIM16_AF1_BKINE_Msk (0x1U << TIM16_AF1_BKINE_Pos) /*!< 0x00000001 */
#define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
#define TIM16_AF1_BKDF1BK2E_Pos (8U)
#define TIM16_AF1_BKDF1BK2E_Msk (0x1U << TIM16_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
#define TIM16_AF1_BKDF1BK2E TIM16_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[1] enable */
#define TIM16_AF1_BKINP_Pos (9U)
#define TIM16_AF1_BKINP_Msk (0x1U << TIM16_AF1_BKINP_Pos) /*!< 0x00000200 */
#define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
/******************* Bit definition for TIM16_TISEL register *********************/
#define TIM16_TISEL_TI1SEL_Pos (0U)
#define TIM16_TISEL_TI1SEL_Msk (0xFU << TIM16_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM16_TISEL_TI1SEL TIM16_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM16 TI1 SEL) */
#define TIM16_TISEL_TI1SEL_0 (0x1U << TIM16_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM16_TISEL_TI1SEL_1 (0x2U << TIM16_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM16_TISEL_TI1SEL_2 (0x4U << TIM16_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM16_TISEL_TI1SEL_3 (0x8U << TIM16_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
/******************* Bit definition for TIM17_AF1 register *********************/
#define TIM17_AF1_BKINE_Pos (0U)
#define TIM17_AF1_BKINE_Msk (0x1U << TIM17_AF1_BKINE_Pos) /*!< 0x00000001 */
#define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
#define TIM17_AF1_BKDF1BK2E_Pos (8U)
#define TIM17_AF1_BKDF1BK2E_Msk (0x1U << TIM17_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
#define TIM17_AF1_BKDF1BK2E TIM17_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[2] enable */
#define TIM17_AF1_BKINP_Pos (9U)
#define TIM17_AF1_BKINP_Msk (0x1U << TIM17_AF1_BKINP_Pos) /*!< 0x00000200 */
#define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
/******************* Bit definition for TIM17_TISEL register *********************/
#define TIM17_TISEL_TI1SEL_Pos (0U)
#define TIM17_TISEL_TI1SEL_Msk (0xFU << TIM17_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM17_TISEL_TI1SEL TIM17_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM17 TI1 SEL) */
#define TIM17_TISEL_TI1SEL_0 (0x1U << TIM17_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM17_TISEL_TI1SEL_1 (0x2U << TIM17_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM17_TISEL_TI1SEL_2 (0x4U << TIM17_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM17_TISEL_TI1SEL_3 (0x8U << TIM17_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
/******************* Bit definition for TIM_TISEL register *********************/
#define TIM_TISEL_TI1SEL_Pos (0U)
#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
#define TIM_TISEL_TI2SEL_Pos (8U)
#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
#define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
#define TIM_TISEL_TI3SEL_Pos (16U)
#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
#define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
#define TIM_TISEL_TI4SEL_Pos (24U)
#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
#define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
/******************************************************************************/
/* */
/* Low Power Timer (LPTTIM) */
/* */
/******************************************************************************/
/****************** Bit definition for LPTIM_ISR register *******************/
#define LPTIM_ISR_CMPM_Pos (0U)
#define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
#define LPTIM_ISR_ARRM_Pos (1U)
#define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
#define LPTIM_ISR_EXTTRIG_Pos (2U)
#define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
#define LPTIM_ISR_CMPOK_Pos (3U)
#define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
#define LPTIM_ISR_ARROK_Pos (4U)
#define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
#define LPTIM_ISR_UP_Pos (5U)
#define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
#define LPTIM_ISR_DOWN_Pos (6U)
#define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
/****************** Bit definition for LPTIM_ICR register *******************/
#define LPTIM_ICR_CMPMCF_Pos (0U)
#define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
#define LPTIM_ICR_ARRMCF_Pos (1U)
#define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
#define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
#define LPTIM_ICR_CMPOKCF_Pos (3U)
#define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
#define LPTIM_ICR_ARROKCF_Pos (4U)
#define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
#define LPTIM_ICR_UPCF_Pos (5U)
#define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
#define LPTIM_ICR_DOWNCF_Pos (6U)
#define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
/****************** Bit definition for LPTIM_IER register ********************/
#define LPTIM_IER_CMPMIE_Pos (0U)
#define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
#define LPTIM_IER_ARRMIE_Pos (1U)
#define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
#define LPTIM_IER_EXTTRIGIE_Pos (2U)
#define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
#define LPTIM_IER_CMPOKIE_Pos (3U)
#define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
#define LPTIM_IER_ARROKIE_Pos (4U)
#define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
#define LPTIM_IER_UPIE_Pos (5U)
#define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
#define LPTIM_IER_DOWNIE_Pos (6U)
#define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
/****************** Bit definition for LPTIM_CFGR register *******************/
#define LPTIM_CFGR_CKSEL_Pos (0U)
#define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
#define LPTIM_CFGR_CKPOL_Pos (1U)
#define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
#define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
#define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
#define LPTIM_CFGR_CKFLT_Pos (3U)
#define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
#define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
#define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
#define LPTIM_CFGR_TRGFLT_Pos (6U)
#define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
#define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
#define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
#define LPTIM_CFGR_PRESC_Pos (9U)
#define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
#define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
#define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
#define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
#define LPTIM_CFGR_TRIGSEL_Pos (13U)
#define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
#define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
#define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
#define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
#define LPTIM_CFGR_TRIGEN_Pos (17U)
#define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
#define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
#define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
#define LPTIM_CFGR_TIMOUT_Pos (19U)
#define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
#define LPTIM_CFGR_WAVE_Pos (20U)
#define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
#define LPTIM_CFGR_WAVPOL_Pos (21U)
#define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
#define LPTIM_CFGR_PRELOAD_Pos (22U)
#define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
#define LPTIM_CFGR_COUNTMODE_Pos (23U)
#define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
#define LPTIM_CFGR_ENC_Pos (24U)
#define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
/****************** Bit definition for LPTIM_CR register ********************/
#define LPTIM_CR_ENABLE_Pos (0U)
#define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
#define LPTIM_CR_SNGSTRT_Pos (1U)
#define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
#define LPTIM_CR_CNTSTRT_Pos (2U)
#define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
#define LPTIM_CR_COUNTRST_Pos (3U)
#define LPTIM_CR_COUNTRST_Msk (0x1U << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Timer Counter reset in synchronous mode*/
#define LPTIM_CR_RSTARE_Pos (4U)
#define LPTIM_CR_RSTARE_Msk (0x1U << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Timer Counter reset after read enable (asynchronously)*/
/****************** Bit definition for LPTIM_CMP register *******************/
#define LPTIM_CMP_CMP_Pos (0U)
#define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
/****************** Bit definition for LPTIM_ARR register *******************/
#define LPTIM_ARR_ARR_Pos (0U)
#define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
/****************** Bit definition for LPTIM_CNT register *******************/
#define LPTIM_CNT_CNT_Pos (0U)
#define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
/****************** Bit definition for LPTIM_CFGR2 register *******************/
#define LPTIM_CFGR2_IN1SEL_Pos (0U)
#define LPTIM_CFGR2_IN1SEL_Msk (0xFUL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x0000000F */
#define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< CFGR2[3:0] bits (INPUT1 selection) */
#define LPTIM_CFGR2_IN1SEL_0_Pos (LPTIM_CFGR2_IN1SEL_Pos)
#define LPTIM_CFGR2_IN1SEL_0_Msk (0x1U << LPTIM_CFGR2_IN1SEL_0_Pos) /*!< 0x00000001 */
#define LPTIM_CFGR2_IN1SEL_0 LPTIM_CFGR2_IN1SEL_0_Msk /*!< Bit 0 */
#define LPTIM_CFGR2_IN1SEL_1_Pos (1U)
#define LPTIM_CFGR2_IN1SEL_1_Msk (0x1U << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */
#define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */
#define LPTIM_CFGR2_IN1SEL_2_Pos (2U)
#define LPTIM_CFGR2_IN1SEL_2_Msk (0x1U << LPTIM_CFGR2_IN1SEL_2_Pos) /*!< 0x00000004 */
#define LPTIM_CFGR2_IN1SEL_2 LPTIM_CFGR2_IN1SEL_2_Msk /*!< Bit 2 */
#define LPTIM_CFGR2_IN1SEL_3_Pos (3U)
#define LPTIM_CFGR2_IN1SEL_3_Msk (0x1U << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */
#define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */
#define LPTIM_CFGR2_IN2SEL_Pos (4U)
#define LPTIM_CFGR2_IN2SEL_Msk (0xFUL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x000000F0 */
#define LPTIM_CFGR2_IN2SEL LPTIM_CFGR2_IN2SEL_Msk /*!< CFGR2[7:4] bits (INPUT2 selection) */
#define LPTIM_CFGR2_IN2SEL_0_Pos (LPTIM_CFGR2_IN2SEL_Pos)
#define LPTIM_CFGR2_IN2SEL_0_Msk (0x1U << LPTIM_CFGR2_IN2SEL_0_Pos) /*!< 0x00000010 */
#define LPTIM_CFGR2_IN2SEL_0 LPTIM_CFGR2_IN2SEL_0_Msk /*!< Bit 4 */
#define LPTIM_CFGR2_IN2SEL_1_Pos (5U)
#define LPTIM_CFGR2_IN2SEL_1_Msk (0x1U << LPTIM_CFGR2_IN2SEL_1_Pos) /*!< 0x00000020 */
#define LPTIM_CFGR2_IN2SEL_1 LPTIM_CFGR2_IN2SEL_1_Msk /*!< Bit 5 */
#define LPTIM_CFGR2_IN2SEL_2_Pos (6U)
#define LPTIM_CFGR2_IN2SEL_2_Msk (0x1U << LPTIM_CFGR2_IN2SEL_2_Pos) /*!< 0x00000040 */
#define LPTIM_CFGR2_IN2SEL_2 LPTIM_CFGR2_IN2SEL_2_Msk /*!< Bit 6 */
#define LPTIM_CFGR2_IN2SEL_3_Pos (7U)
#define LPTIM_CFGR2_IN2SEL_3_Msk (0x1U << LPTIM_CFGR2_IN2SEL_3_Pos) /*!< 0x00000080 */
#define LPTIM_CFGR2_IN2SEL_3 LPTIM_CFGR2_IN2SEL_3_Msk /*!< Bit 7 */
/********************** Bit definition for LPTIM_HWCFGR register ***************/
#define LPTIM_HWCFGR_CFG1_Pos (0U)
#define LPTIM_HWCFGR_CFG1_Msk (0xFFU << LPTIM_HWCFGR_CFG1_Pos) /*!< 0x000000FF */
#define LPTIM_HWCFGR_CFG1 LPTIM_HWCFGR_CFG1_Msk /*!< HW CFG1 */
#define LPTIM_HWCFGR_CFG2_Pos (8U)
#define LPTIM_HWCFGR_CFG2_Msk (0xFFU << LPTIM_HWCFGR_CFG2_Pos) /*!< 0x0000FF00 */
#define LPTIM_HWCFGR_CFG2 LPTIM_HWCFGR_CFG2_Msk /*!< HW CFG2 */
#define LPTIM_HWCFGR_CFG3_Pos (16U)
#define LPTIM_HWCFGR_CFG3_Msk (0xFU << LPTIM_HWCFGR_CFG3_Pos) /*!< 0x000F0000 */
#define LPTIM_HWCFGR_CFG3 LPTIM_HWCFGR_CFG3_Msk /*!< HW CFG3 */
#define LPTIM_HWCFGR_CFG4_Pos (24U)
#define LPTIM_HWCFGR_CFG4_Msk (0xFFU << LPTIM_HWCFGR_CFG4_Pos) /*!< 0xFF000000 */
#define LPTIM_HWCFGR_CFG4 LPTIM_HWCFGR_CFG4_Msk /*!< HW CFG4 */
/********************** Bit definition for LPTIM_VERR register *****************/
#define LPTIM_VERR_MINREV_Pos (0U)
#define LPTIM_VERR_MINREV_Msk (0xFU << LPTIM_VERR_MINREV_Pos) /*!< 0x0000000F */
#define LPTIM_VERR_MINREV LPTIM_VERR_MINREV_Msk /*!< Minor Revision number */
#define LPTIM_VERR_MAJREV_Pos (4U)
#define LPTIM_VERR_MAJREV_Msk (0xFU << LPTIM_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define LPTIM_VERR_MAJREV LPTIM_VERR_MAJREV_Msk /*!< Major Revision number */
/********************** Bit definition for LPTIM_PIDR register ****************/
#define LPTIM_PIDR_IPID_Pos (0U)
#define LPTIM_PIDR_IPID_Msk (0xFFFFFFFFU << LPTIM_PIDR_IPID_Pos) /*!< 0xFFFFFFFF */
#define LPTIM_PIDR_IPID LPTIM_PIDR_IPID_Msk /*!< IP Identification */
/********************** Bit definition for LPTIM_SIDR register *****************/
#define LPTIM_SIDR_SID_Pos (0U)
#define LPTIM_SIDR_SID_Msk (0xFFFFFFFFU << LPTIM_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define LPTIM_SIDR_SID LPTIM_SIDR_SID_Msk /*!< IP size identification */
/******************************************************************************/
/* */
/* Analog Comparators (COMP) */
/* */
/******************************************************************************/
/******************* Bit definition for COMP_SR register ********************/
#define COMP_SR_C1VAL_Pos (0U)
#define COMP_SR_C1VAL_Msk (0x1U << COMP_SR_C1VAL_Pos) /*!< 0x00000001 */
#define COMP_SR_C1VAL COMP_SR_C1VAL_Msk
#define COMP_SR_C2VAL_Pos (1U)
#define COMP_SR_C2VAL_Msk (0x1U << COMP_SR_C2VAL_Pos) /*!< 0x00000002 */
#define COMP_SR_C2VAL COMP_SR_C2VAL_Msk
#define COMP_SR_C1IF_Pos (16U)
#define COMP_SR_C1IF_Msk (0x1U << COMP_SR_C1IF_Pos) /*!< 0x00010000 */
#define COMP_SR_C1IF COMP_SR_C1IF_Msk
#define COMP_SR_C2IF_Pos (17U)
#define COMP_SR_C2IF_Msk (0x1U << COMP_SR_C2IF_Pos) /*!< 0x00020000 */
#define COMP_SR_C2IF COMP_SR_C2IF_Msk
/******************* Bit definition for COMP_ICFR register ********************/
#define COMP_ICFR_C1IF_Pos (16U)
#define COMP_ICFR_C1IF_Msk (0x1U << COMP_ICFR_C1IF_Pos) /*!< 0x00010000 */
#define COMP_ICFR_C1IF COMP_ICFR_C1IF_Msk
#define COMP_ICFR_C2IF_Pos (17U)
#define COMP_ICFR_C2IF_Msk (0x1U << COMP_ICFR_C2IF_Pos) /*!< 0x00020000 */
#define COMP_ICFR_C2IF COMP_ICFR_C2IF_Msk
/******************* Bit definition for COMP_OR register ********************/
#define COMP_OR_AFOPA6_Pos (0U)
#define COMP_OR_AFOPA6_Msk (0x1U << COMP_OR_AFOPA6_Pos) /*!< 0x00000001 */
#define COMP_OR_AFOPA6 COMP_OR_AFOPA6_Msk
#define COMP_OR_AFOPA8_Pos (1U)
#define COMP_OR_AFOPA8_Msk (0x1U << COMP_OR_AFOPA8_Pos) /*!< 0x00000002 */
#define COMP_OR_AFOPA8 COMP_OR_AFOPA8_Msk
#define COMP_OR_AFOPB12_Pos (2U)
#define COMP_OR_AFOPB12_Msk (0x1U << COMP_OR_AFOPB12_Pos) /*!< 0x00000004 */
#define COMP_OR_AFOPB12 COMP_OR_AFOPB12_Msk
#define COMP_OR_AFOPE6_Pos (3U)
#define COMP_OR_AFOPE6_Msk (0x1U << COMP_OR_AFOPE6_Pos) /*!< 0x00000008 */
#define COMP_OR_AFOPE6 COMP_OR_AFOPE6_Msk
#define COMP_OR_AFOPE15_Pos (4U)
#define COMP_OR_AFOPE15_Msk (0x1U << COMP_OR_AFOPE15_Pos) /*!< 0x00000010 */
#define COMP_OR_AFOPE15 COMP_OR_AFOPE15_Msk
#define COMP_OR_AFOPG2_Pos (5U)
#define COMP_OR_AFOPG2_Msk (0x1U << COMP_OR_AFOPG2_Pos) /*!< 0x00000020 */
#define COMP_OR_AFOPG2 COMP_OR_AFOPG2_Msk
#define COMP_OR_AFOPG3_Pos (6U)
#define COMP_OR_AFOPG3_Msk (0x1U << COMP_OR_AFOPG3_Pos) /*!< 0x00000040 */
#define COMP_OR_AFOPG3 COMP_OR_AFOPG3_Msk
#define COMP_OR_AFOPG4_Pos (7U)
#define COMP_OR_AFOPG4_Msk (0x1U << COMP_OR_AFOPG4_Pos) /*!< 0x00000080 */
#define COMP_OR_AFOPG4 COMP_OR_AFOPG4_Msk
#define COMP_OR_AFOPI1_Pos (8U)
#define COMP_OR_AFOPI1_Msk (0x1U << COMP_OR_AFOPI1_Pos) /*!< 0x00000100 */
#define COMP_OR_AFOPI1 COMP_OR_AFOPI1_Msk
#define COMP_OR_AFOPI4_Pos (9U)
#define COMP_OR_AFOPI4_Msk (0x1U << COMP_OR_AFOPI4_Pos) /*!< 0x00000200 */
#define COMP_OR_AFOPI4 COMP_OR_AFOPI4_Msk
#define COMP_OR_AFOPK2_Pos (10U)
#define COMP_OR_AFOPK2_Msk (0x1U << COMP_OR_AFOPK2_Pos) /*!< 0x00000400 */
#define COMP_OR_AFOPK2 COMP_OR_AFOPK2_Msk
/*!< ****************** Bit definition for COMP_CFGRx register ********************/
#define COMP_CFGRx_EN_Pos (0U)
#define COMP_CFGRx_EN_Msk (0x1U << COMP_CFGRx_EN_Pos) /*!< 0x00000001 */
#define COMP_CFGRx_EN COMP_CFGRx_EN_Msk /*!< COMPx enable bit */
#define COMP_CFGRx_BRGEN_Pos (1U)
#define COMP_CFGRx_BRGEN_Msk (0x1U << COMP_CFGRx_BRGEN_Pos) /*!< 0x00000002 */
#define COMP_CFGRx_BRGEN COMP_CFGRx_BRGEN_Msk /*!< COMPx Scaler bridge enable */
#define COMP_CFGRx_SCALEN_Pos (2U)
#define COMP_CFGRx_SCALEN_Msk (0x1U << COMP_CFGRx_SCALEN_Pos) /*!< 0x00000004 */
#define COMP_CFGRx_SCALEN COMP_CFGRx_SCALEN_Msk /*!< COMPx Voltage scaler enable bit */
#define COMP_CFGRx_POLARITY_Pos (3U)
#define COMP_CFGRx_POLARITY_Msk (0x1U << COMP_CFGRx_POLARITY_Pos) /*!< 0x00000008 */
#define COMP_CFGRx_POLARITY COMP_CFGRx_POLARITY_Msk /*!< COMPx polarity selection bit */
#define COMP_CFGRx_WINMODE_Pos (4U)
#define COMP_CFGRx_WINMODE_Msk (0x1U << COMP_CFGRx_WINMODE_Pos) /*!< 0x00000010 */
#define COMP_CFGRx_WINMODE COMP_CFGRx_WINMODE_Msk /*!< COMPx Windows mode selection bit */
#define COMP_CFGRx_ITEN_Pos (6U)
#define COMP_CFGRx_ITEN_Msk (0x1U << COMP_CFGRx_ITEN_Pos) /*!< 0x00000040 */
#define COMP_CFGRx_ITEN COMP_CFGRx_ITEN_Msk /*!< COMPx interrupt enable */
#define COMP_CFGRx_HYST_Pos (8U)
#define COMP_CFGRx_HYST_Msk (0x3U << COMP_CFGRx_HYST_Pos) /*!< 0x00000300 */
#define COMP_CFGRx_HYST COMP_CFGRx_HYST_Msk /*!< COMPx hysteresis selection bits */
#define COMP_CFGRx_HYST_0 (0x1U << COMP_CFGRx_HYST_Pos) /*!< 0x00000100 */
#define COMP_CFGRx_HYST_1 (0x2U << COMP_CFGRx_HYST_Pos) /*!< 0x00000200 */
#define COMP_CFGRx_PWRMODE_Pos (12U)
#define COMP_CFGRx_PWRMODE_Msk (0x3U << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00003000 */
#define COMP_CFGRx_PWRMODE COMP_CFGRx_PWRMODE_Msk /*!< COMPx Power Mode of the comparator */
#define COMP_CFGRx_PWRMODE_0 (0x1U << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00001000 */
#define COMP_CFGRx_PWRMODE_1 (0x2U << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00002000 */
#define COMP_CFGRx_INMSEL_Pos (16U)
#define COMP_CFGRx_INMSEL_Msk (0x7U << COMP_CFGRx_INMSEL_Pos) /*!< 0x00070000 */
#define COMP_CFGRx_INMSEL COMP_CFGRx_INMSEL_Msk /*!< COMPx input minus selection bit */
#define COMP_CFGRx_INMSEL_0 (0x1U << COMP_CFGRx_INMSEL_Pos) /*!< 0x00010000 */
#define COMP_CFGRx_INMSEL_1 (0x2U << COMP_CFGRx_INMSEL_Pos) /*!< 0x00020000 */
#define COMP_CFGRx_INMSEL_2 (0x4U << COMP_CFGRx_INMSEL_Pos) /*!< 0x00040000 */
#define COMP_CFGRx_INPSEL_Pos (20U)
#define COMP_CFGRx_INPSEL_Msk (0x1U << COMP_CFGRx_INPSEL_Pos) /*!< 0x00100000 */
#define COMP_CFGRx_INPSEL COMP_CFGRx_INPSEL_Msk /*!< COMPx input plus selection bit */
#define COMP_CFGRx_BLANKING_Pos (24U)
#define COMP_CFGRx_BLANKING_Msk (0xFU << COMP_CFGRx_BLANKING_Pos) /*!< 0x0F000000 */
#define COMP_CFGRx_BLANKING COMP_CFGRx_BLANKING_Msk /*!< COMPx blanking source selection bits */
#define COMP_CFGRx_BLANKING_0 (0x1U << COMP_CFGRx_BLANKING_Pos) /*!< 0x01000000 */
#define COMP_CFGRx_BLANKING_1 (0x2U << COMP_CFGRx_BLANKING_Pos) /*!< 0x02000000 */
#define COMP_CFGRx_BLANKING_2 (0x4U << COMP_CFGRx_BLANKING_Pos) /*!< 0x04000000 */
#define COMP_CFGRx_LOCK_Pos (31U)
#define COMP_CFGRx_LOCK_Msk (0x1U << COMP_CFGRx_LOCK_Pos) /*!< 0x80000000 */
#define COMP_CFGRx_LOCK COMP_CFGRx_LOCK_Msk /*!< COMPx Lock Bit */
/******************************************************************************/
/* */
/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
/* */
/******************************************************************************/
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_UE_Pos (0U)
#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
#define USART_CR1_UESM_Pos (1U)
#define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
#define USART_CR1_RE_Pos (2U)
#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
#define USART_CR1_TE_Pos (3U)
#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
#define USART_CR1_IDLEIE_Pos (4U)
#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
#define USART_CR1_RXNEIE_Pos (5U)
#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
#define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos
#define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk /*!< 0x00000020 */
#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_Msk /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
#define USART_CR1_TCIE_Pos (6U)
#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE_Pos (7U)
#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
#define USART_CR1_TXEIE_TXFNFIE_Pos USART_CR1_TXEIE_Pos
#define USART_CR1_TXEIE_TXFNFIE_Msk USART_CR1_TXEIE_Msk /*!< 0x00000080 */
#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_Msk /*!< TXE and TX FIFO Not Full Interrupt Enable */
#define USART_CR1_PEIE_Pos (8U)
#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
#define USART_CR1_PS_Pos (9U)
#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
#define USART_CR1_PCE_Pos (10U)
#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
#define USART_CR1_WAKE_Pos (11U)
#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
#define USART_CR1_M_Pos (12U)
#define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */
#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
#define USART_CR1_M0_Pos (12U)
#define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */
#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
#define USART_CR1_MME_Pos (13U)
#define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
#define USART_CR1_CMIE_Pos (14U)
#define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
#define USART_CR1_OVER8_Pos (15U)
#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
#define USART_CR1_DEDT_Pos (16U)
#define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
#define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
#define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
#define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
#define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
#define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
#define USART_CR1_DEAT_Pos (21U)
#define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
#define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
#define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
#define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
#define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
#define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
#define USART_CR1_RTOIE_Pos (26U)
#define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
#define USART_CR1_EOBIE_Pos (27U)
#define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
#define USART_CR1_M1_Pos (28U)
#define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */
#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
#define USART_CR1_FIFOEN_Pos (29U)
#define USART_CR1_FIFOEN_Msk (0x1U << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
#define USART_CR1_TXFEIE_Pos (30U)
#define USART_CR1_TXFEIE_Msk (0x1U << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */
#define USART_CR1_RXFFIE_Pos (31U)
#define USART_CR1_RXFFIE_Msk (0x1U << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */
/****************** Bit definition for USART_CR2 register *******************/
#define USART_CR2_SLVEN_Pos (0U)
#define USART_CR2_SLVEN_Msk (0x1U << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */
#define USART_CR2_DIS_NSS_Pos (3U)
#define USART_CR2_DIS_NSS_Msk (0x1U << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Slave Select (NSS) pin management */
#define USART_CR2_ADDM7_Pos (4U)
#define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
#define USART_CR2_LBDL_Pos (5U)
#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
#define USART_CR2_LBDIE_Pos (6U)
#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL_Pos (8U)
#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
#define USART_CR2_CPHA_Pos (9U)
#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
#define USART_CR2_CPOL_Pos (10U)
#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
#define USART_CR2_CLKEN_Pos (11U)
#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
#define USART_CR2_STOP_Pos (12U)
#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
#define USART_CR2_LINEN_Pos (14U)
#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
#define USART_CR2_SWAP_Pos (15U)
#define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
#define USART_CR2_RXINV_Pos (16U)
#define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
#define USART_CR2_TXINV_Pos (17U)
#define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
#define USART_CR2_DATAINV_Pos (18U)
#define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
#define USART_CR2_MSBFIRST_Pos (19U)
#define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
#define USART_CR2_ABREN_Pos (20U)
#define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
#define USART_CR2_ABRMODE_Pos (21U)
#define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
#define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
#define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
#define USART_CR2_RTOEN_Pos (23U)
#define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
#define USART_CR2_ADD_Pos (24U)
#define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
/****************** Bit definition for USART_CR3 register *******************/
#define USART_CR3_EIE_Pos (0U)
#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
#define USART_CR3_IREN_Pos (1U)
#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
#define USART_CR3_IRLP_Pos (2U)
#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
#define USART_CR3_HDSEL_Pos (3U)
#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
#define USART_CR3_NACK_Pos (4U)
#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
#define USART_CR3_SCEN_Pos (5U)
#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
#define USART_CR3_DMAR_Pos (6U)
#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
#define USART_CR3_DMAT_Pos (7U)
#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
#define USART_CR3_RTSE_Pos (8U)
#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
#define USART_CR3_CTSE_Pos (9U)
#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
#define USART_CR3_CTSIE_Pos (10U)
#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
#define USART_CR3_ONEBIT_Pos (11U)
#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
#define USART_CR3_OVRDIS_Pos (12U)
#define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
#define USART_CR3_DDRE_Pos (13U)
#define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
#define USART_CR3_DEM_Pos (14U)
#define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
#define USART_CR3_DEP_Pos (15U)
#define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
#define USART_CR3_SCARCNT_Pos (17U)
#define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
#define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
#define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
#define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
#define USART_CR3_WUS_Pos (20U)
#define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
#define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
#define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
#define USART_CR3_WUFIE_Pos (22U)
#define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
#define USART_CR3_TXFTIE_Pos (23U)
#define USART_CR3_TXFTIE_Msk (0x1U << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */
#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */
#define USART_CR3_TCBGTIE_Pos (24U)
#define USART_CR3_TCBGTIE_Msk (0x1U << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
#define USART_CR3_RXFTCFG_Pos (25U)
#define USART_CR3_RXFTCFG_Msk (0x7U << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFIFO FIFO threshold configuration */
#define USART_CR3_RXFTCFG_0 (0x1U << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
#define USART_CR3_RXFTCFG_1 (0x2U << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
#define USART_CR3_RXFTCFG_2 (0x4U << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
#define USART_CR3_RXFTIE_Pos (28U)
#define USART_CR3_RXFTIE_Msk (0x1U << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */
#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */
#define USART_CR3_TXFTCFG_Pos (29U)
#define USART_CR3_TXFTCFG_Msk (0x7U << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO threshold configuration */
#define USART_CR3_TXFTCFG_0 (0x1U << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
#define USART_CR3_TXFTCFG_1 (0x2U << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
#define USART_CR3_TXFTCFG_2 (0x4U << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
/****************** Bit definition for USART_BRR register *******************/
#define USART_BRR_LPUART_Pos (0U)
#define USART_BRR_LPUART_Msk (0xFFFFFU << USART_BRR_LPUART_Pos) /*!< 0x000FFFFF */
#define USART_BRR_LPUART USART_BRR_LPUART_Msk /*!< LPUART Baud rate register [19:0] */
#define USART_BRR_BRR_Pos (0U)
#define USART_BRR_BRR_Msk (0xFFFFU << USART_BRR_BRR_Pos) /*!< 0x0000FFFF */
#define USART_BRR_BRR USART_BRR_BRR_Msk /*!< USART Baud rate register [15:0] */
/****************** Bit definition for USART_GTPR register ******************/
#define USART_GTPR_PSC_Pos (0U)
#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
#define USART_GTPR_GT_Pos (8U)
#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
/******************* Bit definition for USART_RTOR register *****************/
#define USART_RTOR_RTO_Pos (0U)
#define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
#define USART_RTOR_BLEN_Pos (24U)
#define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
/******************* Bit definition for USART_RQR register ******************/
#define USART_RQR_ABRRQ_Pos (0U)
#define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
#define USART_RQR_SBKRQ_Pos (1U)
#define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
#define USART_RQR_MMRQ_Pos (2U)
#define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
#define USART_RQR_RXFRQ_Pos (3U)
#define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
#define USART_RQR_TXFRQ_Pos (4U)
#define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
/******************* Bit definition for USART_ISR register ******************/
#define USART_ISR_PE_Pos (0U)
#define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
#define USART_ISR_FE_Pos (1U)
#define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
#define USART_ISR_NE_Pos (2U)
#define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
#define USART_ISR_ORE_Pos (3U)
#define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
#define USART_ISR_IDLE_Pos (4U)
#define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
#define USART_ISR_RXNE_Pos (5U)
#define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
#define USART_ISR_RXNE_RXFNE_Pos USART_ISR_RXNE_Pos
#define USART_ISR_RXNE_RXFNE_Msk USART_ISR_RXNE_Msk /*!< 0x00000020 */
#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_Msk /*!< Read Data Register or RX FIFO Not Empty */
#define USART_ISR_TC_Pos (6U)
#define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
#define USART_ISR_TXE_Pos (7U)
#define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
#define USART_ISR_TXE_TXFNF_Pos USART_ISR_TXE_Pos
#define USART_ISR_TXE_TXFNF_Msk USART_ISR_TXE_Msk /*!< 0x00000080 */
#define USART_ISR_TXE_TXFNF USART_ISR_TXE_Msk /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
#define USART_ISR_LBDF_Pos (8U)
#define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
#define USART_ISR_CTSIF_Pos (9U)
#define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
#define USART_ISR_CTS_Pos (10U)
#define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
#define USART_ISR_RTOF_Pos (11U)
#define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
#define USART_ISR_EOBF_Pos (12U)
#define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
#define USART_ISR_UDR_Pos (13U)
#define USART_ISR_UDR_Msk (0x1U << USART_ISR_UDR_Pos) /*!< 0x00002000 */
#define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI slave underrun error flag */
#define USART_ISR_ABRE_Pos (14U)
#define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
#define USART_ISR_ABRF_Pos (15U)
#define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
#define USART_ISR_BUSY_Pos (16U)
#define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
#define USART_ISR_CMF_Pos (17U)
#define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
#define USART_ISR_SBKF_Pos (18U)
#define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
#define USART_ISR_RWU_Pos (19U)
#define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
#define USART_ISR_WUF_Pos (20U)
#define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
#define USART_ISR_TEACK_Pos (21U)
#define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
#define USART_ISR_REACK_Pos (22U)
#define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
#define USART_ISR_TXFE_Pos (23U)
#define USART_ISR_TXFE_Msk (0x1U << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
#define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty */
#define USART_ISR_RXFF_Pos (24U)
#define USART_ISR_RXFF_Msk (0x1U << USART_ISR_RXFF_Pos) /*!< 0x01000000 */
#define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full */
#define USART_ISR_TCBGT_Pos (25U)
#define USART_ISR_TCBGT_Msk (0x1U << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time completion */
#define USART_ISR_RXFT_Pos (26U)
#define USART_ISR_RXFT_Msk (0x1U << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
#define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO threshold flag */
#define USART_ISR_TXFT_Pos (27U)
#define USART_ISR_TXFT_Msk (0x1U << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
#define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO threshold flag */
/******************* Bit definition for USART_ICR register ******************/
#define USART_ICR_PECF_Pos (0U)
#define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
#define USART_ICR_FECF_Pos (1U)
#define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
#define USART_ICR_NECF_Pos (2U)
#define USART_ICR_NECF_Msk (0x1U << USART_ICR_NECF_Pos) /*!< 0x00000004 */
#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise detected Clear Flag */
#define USART_ICR_ORECF_Pos (3U)
#define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
#define USART_ICR_IDLECF_Pos (4U)
#define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
#define USART_ICR_TXFECF_Pos (5U)
#define USART_ICR_TXFECF_Msk (0x1U << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO empty Clear flag */
#define USART_ICR_TCCF_Pos (6U)
#define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
#define USART_ICR_TCBGTCF_Pos (7U)
#define USART_ICR_TCBGTCF_Msk (0x1U << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
#define USART_ICR_LBDCF_Pos (8U)
#define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
#define USART_ICR_CTSCF_Pos (9U)
#define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
#define USART_ICR_RTOCF_Pos (11U)
#define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
#define USART_ICR_EOBCF_Pos (12U)
#define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
#define USART_ICR_UDRCF_Pos (13U)
#define USART_ICR_UDRCF_Msk (0x1U << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */
#define USART_ICR_CMCF_Pos (17U)
#define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
#define USART_ICR_WUCF_Pos (20U)
#define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
/******************* Bit definition for USART_RDR register ******************/
#define USART_RDR_RDR_Pos (0U)
#define USART_RDR_RDR_Msk (0x1FF << USART_RDR_RDR_Pos) /*!< 0x000001FF */
#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
/******************* Bit definition for USART_TDR register ******************/
#define USART_TDR_TDR_Pos (0U)
#define USART_TDR_TDR_Msk (0x1FF << USART_TDR_TDR_Pos) /*!< 0x000001FF */
#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
/******************* Bit definition for USART_PRESC register ****************/
#define USART_PRESC_PRESCALER_Pos (0U)
#define USART_PRESC_PRESCALER_Msk (0xFU << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
#define USART_PRESC_PRESCALER_0 (0x1U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
#define USART_PRESC_PRESCALER_1 (0x2U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
#define USART_PRESC_PRESCALER_2 (0x4U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3 (0x8U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/********************** Bit definition for USART_HWCFGR2 register ***************/
#define USART_HWCFGR2_CFG1_Pos (0U)
#define USART_HWCFGR2_CFG1_Msk (0xFU << USART_HWCFGR2_CFG1_Pos) /*!< 0x0000000F */
#define USART_HWCFGR2_CFG1 USART_HWCFGR2_CFG1_Msk /*!< HW CFG1 */
#define USART_HWCFGR2_CFG2_Pos (4U)
#define USART_HWCFGR2_CFG2_Msk (0xFU << USART_HWCFGR2_CFG2_Pos) /*!< 0x000000F0 */
#define USART_HWCFGR2_CFG2 USART_HWCFGR2_CFG2_Msk /*!< HW CFG2 */
/********************** Bit definition for USART_HWCFGR1 register ***************/
#define USART_HWCFGR1_CFG1_Pos (0U)
#define USART_HWCFGR1_CFG1_Msk (0xFU << USART_HWCFGR1_CFG1_Pos) /*!< 0x0000000F */
#define USART_HWCFGR1_CFG1 USART_HWCFGR1_CFG1_Msk /*!< HW CFG1 */
#define USART_HWCFGR1_CFG2_Pos (4U)
#define USART_HWCFGR1_CFG2_Msk (0xFU << USART_HWCFGR1_CFG2_Pos) /*!< 0x000000F0 */
#define USART_HWCFGR1_CFG2 USART_HWCFGR1_CFG2_Msk /*!< HW CFG2 */
#define USART_HWCFGR1_CFG3_Pos (8U)
#define USART_HWCFGR1_CFG3_Msk (0xFU << USART_HWCFGR1_CFG3_Pos) /*!< 0x00000F00 */
#define USART_HWCFGR1_CFG3 USART_HWCFGR1_CFG3_Msk /*!< HW CFG3 */
#define USART_HWCFGR1_CFG4_Pos (12U)
#define USART_HWCFGR1_CFG4_Msk (0xFU << USART_HWCFGR1_CFG4_Pos) /*!< 0x0000F000 */
#define USART_HWCFGR1_CFG4 USART_HWCFGR1_CFG4_Msk /*!< HW CFG4 */
#define USART_HWCFGR1_CFG5_Pos (16U)
#define USART_HWCFGR1_CFG5_Msk (0xFU << USART_HWCFGR1_CFG5_Pos) /*!< 0x000F0000 */
#define USART_HWCFGR1_CFG5 USART_HWCFGR1_CFG5_Msk /*!< HW CFG5 */
#define USART_HWCFGR1_CFG6_Pos (20U)
#define USART_HWCFGR1_CFG6_Msk (0xFU << USART_HWCFGR1_CFG6_Pos) /*!< 0x00F00000 */
#define USART_HWCFGR1_CFG6 USART_HWCFGR1_CFG6_Msk /*!< HW CFG6 */
#define USART_HWCFGR1_CFG7_Pos (24U)
#define USART_HWCFGR1_CFG7_Msk (0xFU << USART_HWCFGR1_CFG7_Pos) /*!< 0x0F000000 */
#define USART_HWCFGR1_CFG7 USART_HWCFGR1_CFG7_Msk /*!< HW CFG7 */
#define USART_HWCFGR1_CFG8_Pos (28U)
#define USART_HWCFGR1_CFG8_Msk (0xFU << USART_HWCFGR1_CFG8_Pos) /*!< 0xF0000000 */
#define USART_HWCFGR1_CFG8 USART_HWCFGR1_CFG8_Msk /*!< HW CFG8 */
/********************** Bit definition for USART_VERR register *****************/
#define USART_VERR_MINREV_Pos (0U)
#define USART_VERR_MINREV_Msk (0xFU << USART_VERR_MINREV_Pos) /*!< 0x0000000F */
#define USART_VERR_MINREV USART_VERR_MINREV_Msk /*!< Minor Revision number */
#define USART_VERR_MAJREV_Pos (4U)
#define USART_VERR_MAJREV_Msk (0xFU << USART_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define USART_VERR_MAJREV USART_VERR_MAJREV_Msk /*!< Major Revision number */
/********************** Bit definition for USART_IPIDR register ****************/
#define USART_IPIDR_IPID_Pos (0U)
#define USART_IPIDR_IPID_Msk (0xFFFFFFFFU << USART_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
#define USART_IPIDR_IPID USART_IPIDR_IPID_Msk /*!< IP Identification */
/********************** Bit definition for USART_SIDR register *****************/
#define USART_SIDR_SID_Pos (0U)
#define USART_SIDR_SID_Msk (0xFFFFFFFFU << USART_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define USART_SIDR_SID USART_SIDR_SID_Msk /*!< IP size identification */
/******************************************************************************/
/* */
/* Single Wire Protocol Master Interface (SWPMI) */
/* */
/******************************************************************************/
/******************* Bit definition for SWPMI_CR register ********************/
#define SWPMI_CR_RXDMA ((uint16_t)0x0001) /*!<Reception DMA enable */
#define SWPMI_CR_TXDMA ((uint16_t)0x0002) /*!<Transmission DMA enable */
#define SWPMI_CR_RXMODE ((uint16_t)0x0004) /*!<Reception buffering mode */
#define SWPMI_CR_TXMODE ((uint16_t)0x0008) /*!<Transmission buffering mode */
#define SWPMI_CR_LPBK ((uint16_t)0x0010) /*!<Loopback mode enable */
#define SWPMI_CR_SWPACT ((uint16_t)0x0020) /*!<Single wire protocol master interface activate */
#define SWPMI_CR_DEACT ((uint16_t)0x0400) /*!<Single wire protocol master interface deactivate */
#define SWPMI_CR_SWPEN ((uint16_t)0x0800) /*!<Single wire protocol master transceiver enable */
/******************* Bit definition for SWPMI_BRR register ********************/
#define SWPMI_BRR_BR ((uint16_t)0x003F) /*!<BR[5:0] bits (Bitrate prescaler) */
/******************* Bit definition for SWPMI_ISR register ********************/
#define SWPMI_ISR_RXBFF ((uint16_t)0x0001) /*!<Receive buffer full flag */
#define SWPMI_ISR_TXBEF ((uint16_t)0x0002) /*!<Transmit buffer empty flag */
#define SWPMI_ISR_RXBERF ((uint16_t)0x0004) /*!<Receive CRC error flag */
#define SWPMI_ISR_RXOVRF ((uint16_t)0x0008) /*!<Receive overrun error flag */
#define SWPMI_ISR_TXUNRF ((uint16_t)0x0010) /*!<Transmit underrun error flag */
#define SWPMI_ISR_RXNE ((uint16_t)0x0020) /*!<Receive data register not empty */
#define SWPMI_ISR_TXE ((uint16_t)0x0040) /*!<Transmit data register empty */
#define SWPMI_ISR_TCF ((uint16_t)0x0080) /*!<Transfer complete flag */
#define SWPMI_ISR_SRF ((uint16_t)0x0100) /*!<Slave resume flag */
#define SWPMI_ISR_SUSP ((uint16_t)0x0200) /*!<SUSPEND flag */
#define SWPMI_ISR_DEACTF ((uint16_t)0x0400) /*!<DEACTIVATED flag */
#define SWPMI_ISR_RDYF ((uint16_t)0x0800) /*!<Transceiver ready flag */
/******************* Bit definition for SWPMI_ICR register ********************/
#define SWPMI_ICR_CRXBFF ((uint16_t)0x0001) /*!<Clear receive buffer full flag */
#define SWPMI_ICR_CTXBEF ((uint16_t)0x0002) /*!<Clear transmit buffer empty flag */
#define SWPMI_ICR_CRXBERF ((uint16_t)0x0004) /*!<Clear receive CRC error flag */
#define SWPMI_ICR_CRXOVRF ((uint16_t)0x0008) /*!<Clear receive overrun error flag */
#define SWPMI_ICR_CTXUNRF ((uint16_t)0x0010) /*!<Clear transmit underrun error flag */
#define SWPMI_ICR_CTCF ((uint16_t)0x0080) /*!<Clear transfer complete flag */
#define SWPMI_ICR_CSRF ((uint16_t)0x0100) /*!<Clear slave resume flag */
#define SWPMI_ICR_CRDYF ((uint16_t)0x0800) /*!<Clear transceiver ready flag */
/******************* Bit definition for SWPMI_IER register ********************/
#define SWPMI_IER_RXBFIE ((uint16_t)0x0001) /*!<Receive buffer full interrupt enable */
#define SWPMI_IER_TXBEIE ((uint16_t)0x0002) /*!<Transmit buffer empty interrupt enable */
#define SWPMI_IER_RXBERIE ((uint16_t)0x0004) /*!<Receive CRC error interrupt enable */
#define SWPMI_IER_RXOVRIE ((uint16_t)0x0008) /*!<Receive overrun error interrupt enable */
#define SWPMI_IER_TXUNRIE ((uint16_t)0x0010) /*!<Transmit underrun error interrupt enable */
#define SWPMI_IER_RIE ((uint16_t)0x0020) /*!<Receive interrupt enable */
#define SWPMI_IER_TIE ((uint16_t)0x0040) /*!<Transmit interrupt enable */
#define SWPMI_IER_TCIE ((uint16_t)0x0080) /*!<Transmit complete interrupt enable */
#define SWPMI_IER_SRIE ((uint16_t)0x0100) /*!<Slave resume interrupt enable */
#define SWPMI_IER_RDYIE ((uint16_t)0x0800) /*!<Transceiver ready interrupt enable */
/******************* Bit definition for SWPMI_RFL register ********************/
#define SWPMI_RFL_RFL ((uint16_t)0x001F) /*!<RFL[4:0] bits (Receive Frame length) */
#define SWPMI_RFL_RFL_0_1 ((uint16_t)0x0003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
/******************* Bit definition for SWPMI_TDR register ********************/
#define SWPMI_TDR_TD_Pos (0U)
#define SWPMI_TDR_TD_Msk (0xFFFFFFFFU << SWPMI_TDR_TD_Pos) /*!< 0xFFFFFFFF */
#define SWPMI_TDR_TD SWPMI_TDR_TD_Msk /*!<Transmit Data Register */
/******************* Bit definition for SWPMI_RDR register ********************/
#define SWPMI_RDR_RD_Pos (0U)
#define SWPMI_RDR_RD_Msk (0xFFFFFFFFU << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
/******************* Bit definition for SWPMI_OR register ********************/
#define SWPMI_OR_TBYP ((uint16_t)0x0001) /*!<SWP Transceiver Bypass */
#define SWPMI_OR_CLASS ((uint16_t)0x0002) /*!<SWP CLASS selection */
/******************************************************************************/
/* */
/* Window WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for WWDG_CR register ********************/
#define WWDG_CR_T_Pos (0U)
#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
#define WWDG_CR_WDGA_Pos (7U)
#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
/******************* Bit definition for WWDG_CFR register *******************/
#define WWDG_CFR_W_Pos (0U)
#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
#define WWDG_CFR_WDGTB_Pos (11U)
#define WWDG_CFR_WDGTB_Msk (0x7U << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */
#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */
#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */
#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */
#define WWDG_CFR_WDGTB_2 (0x4U << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */
#define WWDG_CFR_EWI_Pos (9U)
#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
/******************* Bit definition for WWDG_SR register ********************/
#define WWDG_SR_EWIF_Pos (0U)
#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
/******************* Bit definition for WWDG_HWCFGR register ***************/
#define WWDG_HWCFGR_PREDIV_Pos (0U)
#define WWDG_HWCFGR_PREDIV_Msk (0xFFFFU << WWDG_HWCFGR_PREDIV_Pos) /*!< 0x0000FFFF */
#define WWDG_HWCFGR_PREDIV WWDG_HWCFGR_PREDIV_Msk /*!< Watchdog clock prescaler */
/******************* Bit definition for WWDG_VERR register *****************/
#define WWDG_VERR_MINREV_Pos (0U)
#define WWDG_VERR_MINREV_Msk (0xFU << WWDG_VERR_MINREV_Pos) /*!< 0x0000000F */
#define WWDG_VERR_MINREV WWDG_VERR_MINREV_Msk /*!< Minor Revision number */
#define WWDG_VERR_MAJREV_Pos (4U)
#define WWDG_VERR_MAJREV_Msk (0xFU << WWDG_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define WWDG_VERR_MAJREV WWDG_VERR_MAJREV_Msk /*!< Major Revision number */
/******************* Bit definition for WWDG_IPIDR register ****************/
#define WWDG_IPIDR_ID_Pos (0U)
#define WWDG_IPIDR_ID_Msk (0xFFFFFFFFU << WWDG_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
#define WWDG_IPIDR_ID WWDG_IPIDR_ID_Msk /*!< IP Identification */
/********************** Bit definition for WWDG_SIDR register *****************/
#define WWDG_SIDR_SID_Pos (0U)
#define WWDG_SIDR_SID_Msk (0xFFFFFFFFU << WWDG_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define WWDG_SIDR_SID WWDG_SIDR_SID_Msk /*!< IP size identification */
/******************************************************************************/
/* */
/* MDIOS */
/* */
/******************************************************************************/
/******************** Bit definition for MDIOS_CR register *******************/
#define MDIOS_CR_EN_Pos (0U)
#define MDIOS_CR_EN_Msk (0x1U << MDIOS_CR_EN_Pos) /*!< 0x00000001 */
#define MDIOS_CR_EN MDIOS_CR_EN_Msk /*!< MDIOS slave peripheral enable */
#define MDIOS_CR_WRIE_Pos (1U)
#define MDIOS_CR_WRIE_Msk (0x1U << MDIOS_CR_WRIE_Pos) /*!< 0x00000002 */
#define MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk /*!< MDIOS slave register write interrupt enable. */
#define MDIOS_CR_RDIE_Pos (2U)
#define MDIOS_CR_RDIE_Msk (0x1U << MDIOS_CR_RDIE_Pos) /*!< 0x00000004 */
#define MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk /*!< MDIOS slave register read interrupt enable. */
#define MDIOS_CR_EIE_Pos (3U)
#define MDIOS_CR_EIE_Msk (0x1U << MDIOS_CR_EIE_Pos) /*!< 0x00000008 */
#define MDIOS_CR_EIE MDIOS_CR_EIE_Msk /*!< MDIOS slave register error interrupt enable. */
#define MDIOS_CR_DPC_Pos (7U)
#define MDIOS_CR_DPC_Msk (0x1U << MDIOS_CR_DPC_Pos) /*!< 0x00000080 */
#define MDIOS_CR_DPC MDIOS_CR_DPC_Msk /*!< MDIOS slave disable preamble check. */
#define MDIOS_CR_PORT_ADDRESS_Pos (8U)
#define MDIOS_CR_PORT_ADDRESS_Msk (0x1FU << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001F00 */
#define MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk /*!< MDIOS slave port address mask. */
#define MDIOS_CR_PORT_ADDRESS_0 (0x01U << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000100 */
#define MDIOS_CR_PORT_ADDRESS_1 (0x02U << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000200 */
#define MDIOS_CR_PORT_ADDRESS_2 (0x04U << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000400 */
#define MDIOS_CR_PORT_ADDRESS_3 (0x08U << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000800 */
#define MDIOS_CR_PORT_ADDRESS_4 (0x10U << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001000 */
/******************** Bit definition for MDIOS_SR register *******************/
#define MDIOS_SR_PERF_Pos (0U)
#define MDIOS_SR_PERF_Msk (0x1U << MDIOS_SR_PERF_Pos) /*!< 0x00000001 */
#define MDIOS_SR_PERF MDIOS_SR_PERF_Msk /*!< MDIOS slave turnaround error flag*/
#define MDIOS_SR_SERF_Pos (1U)
#define MDIOS_SR_SERF_Msk (0x1U << MDIOS_SR_SERF_Pos) /*!< 0x00000002 */
#define MDIOS_SR_SERF MDIOS_SR_SERF_Msk /*!< MDIOS slave start error flag */
#define MDIOS_SR_TERF_Pos (2U)
#define MDIOS_SR_TERF_Msk (0x1U << MDIOS_SR_TERF_Pos) /*!< 0x00000004 */
#define MDIOS_SR_TERF MDIOS_SR_TERF_Msk /*!< MDIOS slave preamble error flag */
/******************** Bit definition for MDIOS_CLRFR register *******************/
#define MDIOS_SR_CPERF_Pos (0U)
#define MDIOS_SR_CPERF_Msk (0x1U << MDIOS_SR_CPERF_Pos) /*!< 0x00000001 */
#define MDIOS_SR_CPERF MDIOS_SR_CPERF_Msk /*!< MDIOS slave Clear the turnaround error flag */
#define MDIOS_SR_CSERF_Pos (1U)
#define MDIOS_SR_CSERF_Msk (0x1U << MDIOS_SR_CSERF_Pos) /*!< 0x00000002 */
#define MDIOS_SR_CSERF MDIOS_SR_CSERF_Msk /*!< MDIOS slave Clear the start error flag */
#define MDIOS_SR_CTERF_Pos (2U)
#define MDIOS_SR_CTERF_Msk (0x1U << MDIOS_SR_CTERF_Pos) /*!< 0x00000004 */
#define MDIOS_SR_CTERF MDIOS_SR_CTERF_Msk /*!< MDIOS slave Clear the preamble error flag */
/********************** Bit definition for MDIOS_HWCFGR register ***************/
#define MDIOS_HWCFGR_NBREG_Pos (0U)
#define MDIOS_HWCFGR_NBREG_Msk (0xFFU << MDIOS_HWCFGR_NBREG_Pos) /*!< 0x000000FF */
#define MDIOS_HWCFGR_NBREG MDIOS_HWCFGR_NBREG_Msk /*!< IP configuration number of registers */
/********************** Bit definition for MDIOS_VERR register *****************/
#define MDIOS_VERR_MINREV_Pos (0U)
#define MDIOS_VERR_MINREV_Msk (0xFU << MDIOS_VERR_MINREV_Pos) /*!< 0x0000000F */
#define MDIOS_VERR_MINREV MDIOS_VERR_MINREV_Msk /*!< Minor Revision number */
#define MDIOS_VERR_MAJREV_Pos (4U)
#define MDIOS_VERR_MAJREV_Msk (0xFU << MDIOS_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define MDIOS_VERR_MAJREV MDIOS_VERR_MAJREV_Msk /*!< Major Revision number */
/********************** Bit definition for MDIOS_IPIDR register ****************/
#define MDIOS_IPIDR_IPID_Pos (0U)
#define MDIOS_IPIDR_IPID_Msk (0xFFFFFFFFU << MDIOS_IPIDR_IPID_Pos) /*!< 0xFFFFFFFF */
#define MDIOS_IPIDR_IPID MDIOS_IPIDR_IPID_Msk /*!< IP Identification */
/********************** Bit definition for MDIOS_SIDR register *****************/
#define MDIOS_SIDR_SID_Pos (0U)
#define MDIOS_SIDR_SID_Msk (0xFFFFFFFFU << MDIOS_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define MDIOS_SIDR_SID MDIOS_SIDR_SID_Msk /*!< IP size identification */
/******************************************************************************/
/* */
/* USB_OTG */
/* */
/******************************************************************************/
/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
#define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
/******************** Bit definition forUSB_OTG_HCFG register ********************/
#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
#define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
#define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
#define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
#define USB_OTG_HCFG_FSLSS_Pos (2U)
#define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
/******************** Bit definition forUSB_OTG_DCFG register ********************/
#define USB_OTG_DCFG_DSPD_Pos (0U)
#define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
#define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
#define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
#define USB_OTG_DCFG_DAD_Pos (4U)
#define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
#define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
#define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
#define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
#define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
#define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
#define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
#define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
#define USB_OTG_DCFG_PFIVL_Pos (11U)
#define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
#define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
#define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
/******************** Bit definition forUSB_OTG_PCGCR register ********************/
#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
#define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
#define USB_OTG_GOTGINT_SEDET_Pos (2U)
#define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
#define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
/******************** Bit definition forUSB_OTG_DCTL register ********************/
#define USB_OTG_DCTL_RWUSIG_Pos (0U)
#define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
#define USB_OTG_DCTL_SDIS_Pos (1U)
#define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
#define USB_OTG_DCTL_GINSTS_Pos (2U)
#define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
#define USB_OTG_DCTL_GONSTS_Pos (3U)
#define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
#define USB_OTG_DCTL_TCTL_Pos (4U)
#define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
#define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
#define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
#define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
#define USB_OTG_DCTL_SGINAK_Pos (7U)
#define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
#define USB_OTG_DCTL_CGINAK_Pos (8U)
#define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
#define USB_OTG_DCTL_SGONAK_Pos (9U)
#define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
#define USB_OTG_DCTL_CGONAK_Pos (10U)
#define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
/******************** Bit definition forUSB_OTG_HFIR register ********************/
#define USB_OTG_HFIR_FRIVL_Pos (0U)
#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
/******************** Bit definition forUSB_OTG_HFNUM register ********************/
#define USB_OTG_HFNUM_FRNUM_Pos (0U)
#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
#define USB_OTG_HFNUM_FTREM_Pos (16U)
#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
/******************** Bit definition forUSB_OTG_DSTS register ********************/
#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
#define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
#define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
#define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
#define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
#define USB_OTG_DSTS_EERR_Pos (3U)
#define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
#define USB_OTG_DSTS_FNSOF_Pos (8U)
#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
#define USB_OTG_GAHBCFG_GINT_Pos (0U)
#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
#define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
#define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
#define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
#define USB_OTG_GUSBCFG_PHYIF_Pos (3U)
#define USB_OTG_GUSBCFG_PHYIF_Msk (0x1U << USB_OTG_GUSBCFG_PHYIF_Pos) /*!< 0x00000008 */
#define USB_OTG_GUSBCFG_PHYIF USB_OTG_GUSBCFG_PHYIF_Msk /*!< PHY Interface (PHYIf) */
#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Pos (4U)
#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Msk (0x1U << USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Pos) /*!< 0x00000010 */
#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Msk /*!< ULPI or UTMI+ Select (ULPI_UTMI_Sel) */
#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
#define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
#define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
#define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
#define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
#define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
#define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
#define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
#define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
#define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
#define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
#define USB_OTG_DIEPMSK_TOM_Pos (3U)
#define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
#define USB_OTG_DIEPMSK_BIM_Pos (9U)
#define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
/******************** Bit definition forUSB_OTG_HAINT register ********************/
#define USB_OTG_HAINT_HAINT_Pos (0U)
#define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
#define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
#define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
#define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
#define USB_OTG_GINTSTS_CMOD_Pos (0U)
#define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
#define USB_OTG_GINTSTS_MMIS_Pos (1U)
#define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
#define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
#define USB_OTG_GINTSTS_SOF_Pos (3U)
#define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
#define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
#define USB_OTG_GINTSTS_USBRST_Pos (12U)
#define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
#define USB_OTG_GINTSTS_EOPF_Pos (15U)
#define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
#define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
#define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
#define USB_OTG_GINTSTS_HCINT_Pos (25U)
#define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
#define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
#define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
#define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
#define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
#define USB_OTG_GINTMSK_MMISM_Pos (1U)
#define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
#define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
#define USB_OTG_GINTMSK_SOFM_Pos (3U)
#define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
#define USB_OTG_GINTMSK_USBRST_Pos (12U)
#define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
#define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
#define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
#define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
#define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
#define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1U << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */
#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
#define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
#define USB_OTG_GINTMSK_HCIM_Pos (25U)
#define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
#define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
#define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
#define USB_OTG_GINTMSK_WUIM_Pos (31U)
#define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
/******************** Bit definition forUSB_OTG_DAINT register ********************/
#define USB_OTG_DAINT_IEPINT_Pos (0U)
#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
#define USB_OTG_DAINT_OEPINT_Pos (16U)
#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
#define USB_OTG_GRXSTSP_DPID_Pos (15U)
#define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
/******************** Bit definition for OTG register ********************/
#define USB_OTG_CHNUM_Pos (0U)
#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_BCNT_Pos (4U)
#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
#define USB_OTG_DPID_Pos (15U)
#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
#define USB_OTG_PKTSTS_Pos (17U)
#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
#define USB_OTG_EPNUM_Pos (0U)
#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_FRMNUM_Pos (21U)
#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition for OTG register ********************/
#define USB_OTG_CHNUM_Pos (0U)
#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_BCNT_Pos (4U)
#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
#define USB_OTG_DPID_Pos (15U)
#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
#define USB_OTG_PKTSTS_Pos (17U)
#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
#define USB_OTG_EPNUM_Pos (0U)
#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_FRMNUM_Pos (21U)
#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
/******************** Bit definition for OTG register ********************/
#define USB_OTG_NPTXFSA_Pos (0U)
#define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
#define USB_OTG_NPTXFD_Pos (16U)
#define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
#define USB_OTG_TX0FSA_Pos (0U)
#define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
#define USB_OTG_TX0FD_Pos (16U)
#define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
/******************** Bit definition forUSB_OTG_GCCFG register ********************/
#define USB_OTG_GCCFG_DCDET_Pos (0U)
#define USB_OTG_GCCFG_DCDET_Msk (0x1U << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
#define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */
#define USB_OTG_GCCFG_PDET_Pos (1U)
#define USB_OTG_GCCFG_PDET_Msk (0x1U << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
#define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */
#define USB_OTG_GCCFG_SDET_Pos (2U)
#define USB_OTG_GCCFG_SDET_Msk (0x1U << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */
#define USB_OTG_GCCFG_PS2DET_Pos (3U)
#define USB_OTG_GCCFG_PS2DET_Msk (0x1U << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
#define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
#define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
#define USB_OTG_GCCFG_BCDEN_Pos (17U)
#define USB_OTG_GCCFG_BCDEN_Msk (0x1U << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
#define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */
#define USB_OTG_GCCFG_DCDEN_Pos (18U)
#define USB_OTG_GCCFG_DCDEN_Msk (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/
#define USB_OTG_GCCFG_PDEN_Pos (19U)
#define USB_OTG_GCCFG_PDEN_Msk (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/
#define USB_OTG_GCCFG_SDEN_Pos (20U)
#define USB_OTG_GCCFG_SDEN_Msk (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
#define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */
#define USB_OTG_GCCFG_VBDEN_Pos (21U)
#define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Secondary detection (SD) mode enable */
#define USB_OTG_GCCFG_OTGIDEN_Pos (22U)
#define USB_OTG_GCCFG_OTGIDEN_Msk (0x1U << USB_OTG_GCCFG_OTGIDEN_Pos) /*!< 0x00400000 */
#define USB_OTG_GCCFG_OTGIDEN USB_OTG_GCCFG_OTGIDEN_Msk /*!< OTG Id enable */
#define USB_OTG_GCCFG_PHYHSEN_Pos (23U)
#define USB_OTG_GCCFG_PHYHSEN_Msk (0x1U << USB_OTG_GCCFG_PHYHSEN_Pos) /*!< 0x00800000 */
#define USB_OTG_GCCFG_PHYHSEN USB_OTG_GCCFG_PHYHSEN_Msk /*!< HS PHY enable */
/******************** Bit definition forUSB_OTG_GPWRDN) register ********************/
#define USB_OTG_GPWRDN_ADPMEN_Pos (0U)
#define USB_OTG_GPWRDN_ADPMEN_Msk (0x1U << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
#define USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk /*!< ADP module enable */
#define USB_OTG_GPWRDN_ADPIF_Pos (23U)
#define USB_OTG_GPWRDN_ADPIF_Msk (0x1U << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
#define USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk /*!< ADP Interrupt flag */
/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
/******************** Bit definition forUSB_OTG_CID register ********************/
#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
#define USB_OTG_GLPMCFG_BESL_Pos (2U)
#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
/******************** Bit definition forUSB_OTG_HPRT register ********************/
#define USB_OTG_HPRT_PCSTS_Pos (0U)
#define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
#define USB_OTG_HPRT_PCDET_Pos (1U)
#define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
#define USB_OTG_HPRT_PENA_Pos (2U)
#define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
#define USB_OTG_HPRT_PENCHNG_Pos (3U)
#define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
#define USB_OTG_HPRT_POCA_Pos (4U)
#define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
#define USB_OTG_HPRT_POCCHNG_Pos (5U)
#define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
#define USB_OTG_HPRT_PRES_Pos (6U)
#define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
#define USB_OTG_HPRT_PSUSP_Pos (7U)
#define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
#define USB_OTG_HPRT_PRST_Pos (8U)
#define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
#define USB_OTG_HPRT_PLSTS_Pos (10U)
#define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
#define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
#define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
#define USB_OTG_HPRT_PPWR_Pos (12U)
#define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
#define USB_OTG_HPRT_PTCTL_Pos (13U)
#define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
#define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
#define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
#define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
#define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
#define USB_OTG_HPRT_PSPD_Pos (17U)
#define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
#define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
#define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
#define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
#define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
#define USB_OTG_DIEPCTL_STALL_Pos (21U)
#define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
#define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
#define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
#define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
#define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
#define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
#define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
#define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
#define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
#define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
#define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
#define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
#define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
#define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
#define USB_OTG_HCCHAR_MC_Pos (20U)
#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
#define USB_OTG_HCCHAR_DAD_Pos (22U)
#define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
#define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
#define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
#define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
#define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
#define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
#define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
#define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
#define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
#define USB_OTG_HCCHAR_CHENA_Pos (31U)
#define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
#define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
#define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
#define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
#define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
#define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
#define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
#define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
#define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
#define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
#define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
#define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
#define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
#define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
#define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
#define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
#define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
/******************** Bit definition forUSB_OTG_HCINT register ********************/
#define USB_OTG_HCINT_XFRC_Pos (0U)
#define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
#define USB_OTG_HCINT_CHH_Pos (1U)
#define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
#define USB_OTG_HCINT_AHBERR_Pos (2U)
#define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
#define USB_OTG_HCINT_STALL_Pos (3U)
#define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
#define USB_OTG_HCINT_NAK_Pos (4U)
#define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
#define USB_OTG_HCINT_ACK_Pos (5U)
#define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
#define USB_OTG_HCINT_NYET_Pos (6U)
#define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
#define USB_OTG_HCINT_TXERR_Pos (7U)
#define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
#define USB_OTG_HCINT_BBERR_Pos (8U)
#define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
#define USB_OTG_HCINT_FRMOR_Pos (9U)
#define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
#define USB_OTG_HCINT_DTERR_Pos (10U)
#define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
#define USB_OTG_DIEPINT_XFRC_Pos (0U)
#define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
#define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
#define USB_OTG_DIEPINT_TOC_Pos (3U)
#define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
#define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
#define USB_OTG_DIEPINT_TXFE_Pos (7U)
#define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
#define USB_OTG_DIEPINT_BNA_Pos (9U)
#define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
#define USB_OTG_DIEPINT_BERR_Pos (12U)
#define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
#define USB_OTG_DIEPINT_NAK_Pos (13U)
#define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
#define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
#define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
#define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
#define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
#define USB_OTG_HCINTMSK_NYET_Pos (6U)
#define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
#define USB_OTG_HCTSIZ_DPID_Pos (29U)
#define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
#define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
#define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
/******************** Bit definition forUSB_OTG_HCDMA register ********************/
#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
#define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
#define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
#define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
#define USB_OTG_DOEPCTL_STALL_Pos (21U)
#define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
#define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
#define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
#define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
#define USB_OTG_DOEPINT_XFRC_Pos (0U)
#define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
#define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
#define USB_OTG_DOEPINT_STUP_Pos (3U)
#define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
#define USB_OTG_DOEPINT_NYET_Pos (14U)
#define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
/******************** Bit definition for PCGCCTL register ********************/
#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
/**
* @}
*/
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
/******************************* ADC Instances ********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
((INSTANCE) == ADC2))
#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
/******************************** DTS Instances ******************************/
#define IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS1)
/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC1) || \
((INSTANCE) == CRC2))
/******************************* DAC Instances ********************************/
#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
/******************************* DCMI Instances *******************************/
#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
/****************************** DFSDM Instances *******************************/
#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
((INSTANCE) == DFSDM1_Filter1) || \
((INSTANCE) == DFSDM1_Filter2) || \
((INSTANCE) == DFSDM1_Filter3) || \
((INSTANCE) == DFSDM1_Filter4) || \
((INSTANCE) == DFSDM1_Filter5))
#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
((INSTANCE) == DFSDM1_Channel1) || \
((INSTANCE) == DFSDM1_Channel2) || \
((INSTANCE) == DFSDM1_Channel3) || \
((INSTANCE) == DFSDM1_Channel4) || \
((INSTANCE) == DFSDM1_Channel5) || \
((INSTANCE) == DFSDM1_Channel6) || \
((INSTANCE) == DFSDM1_Channel7))
/******************************** DMA Instances *******************************/
#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
((INSTANCE) == DMA1_Stream1) || \
((INSTANCE) == DMA1_Stream2) || \
((INSTANCE) == DMA1_Stream3) || \
((INSTANCE) == DMA1_Stream4) || \
((INSTANCE) == DMA1_Stream5) || \
((INSTANCE) == DMA1_Stream6) || \
((INSTANCE) == DMA1_Stream7) || \
((INSTANCE) == DMA2_Stream0) || \
((INSTANCE) == DMA2_Stream1) || \
((INSTANCE) == DMA2_Stream2) || \
((INSTANCE) == DMA2_Stream3) || \
((INSTANCE) == DMA2_Stream4) || \
((INSTANCE) == DMA2_Stream5) || \
((INSTANCE) == DMA2_Stream6) || \
((INSTANCE) == DMA2_Stream7))
/******************************** DMA Request Generator Instances **************/
#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
((INSTANCE) == DMAMUX1_RequestGenerator1) || \
((INSTANCE) == DMAMUX1_RequestGenerator2) || \
((INSTANCE) == DMAMUX1_RequestGenerator3))
/******************************** MDMA Request Generator Instances **************/
#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0) || \
((INSTANCE) == MDMA_Channel1) || \
((INSTANCE) == MDMA_Channel2) || \
((INSTANCE) == MDMA_Channel3) || \
((INSTANCE) == MDMA_Channel4) || \
((INSTANCE) == MDMA_Channel5) || \
((INSTANCE) == MDMA_Channel6) || \
((INSTANCE) == MDMA_Channel7) || \
((INSTANCE) == MDMA_Channel8) || \
((INSTANCE) == MDMA_Channel9) || \
((INSTANCE) == MDMA_Channel10) || \
((INSTANCE) == MDMA_Channel11) || \
((INSTANCE) == MDMA_Channel12) || \
((INSTANCE) == MDMA_Channel13) || \
((INSTANCE) == MDMA_Channel14) || \
((INSTANCE) == MDMA_Channel15) || \
((INSTANCE) == MDMA_Channel16))
/******************************* QUADSPI Instances *******************************/
#define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
/******************************* FDCAN Instances ******************************/
#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1) || \
((INSTANCE) == FDCAN2))
#define IS_FDCAN_TT_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN1)
/******************************* GPIO Instances *******************************/
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
((INSTANCE) == GPIOB) || \
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOE) || \
((INSTANCE) == GPIOF) || \
((INSTANCE) == GPIOG) || \
((INSTANCE) == GPIOH) || \
((INSTANCE) == GPIOI) || \
((INSTANCE) == GPIOJ) || \
((INSTANCE) == GPIOK) || \
((INSTANCE) == GPIOZ))
/**************************** GPIO Lock Instances *****************************/
/* On L4, all GPIO Bank support the Lock mechanism */
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/******************************** HSEM Instances *******************************/
#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
/******************** Bit definition for HSEM_CR register *****************/
#define HSEM_CPU1_COREID (0x00000001U) /* Semaphore Core CA7 ID */
#define HSEM_CPU2_COREID (0x00000002U) /* Semaphore Core CM4 ID */
#define HSEM_CR_COREID_CURRENT (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos)
#define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/
#define HSEM_SEMID_MAX (31U) /* HSEM ID Max */
#define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */
#define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */
#define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */
#define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */
/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2) || \
((INSTANCE) == I2C3) || \
((INSTANCE) == I2C4) || \
((INSTANCE) == I2C5) || \
((INSTANCE) == I2C6) )
/************** I2C Instances : wakeup capability from stop modes *************/
#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
/****************************** SMBUS Instances *******************************/
#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2) || \
((INSTANCE) == I2C3) || \
((INSTANCE) == I2C4) || \
((INSTANCE) == I2C5) || \
((INSTANCE) == I2C6) )
/******************************* IPCC Instances ********************************/
#define IS_IPCC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IPCC)
/******************************** I2S Instances *******************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3))
/****************************** LTDC Instances ********************************/
#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG1) || \
((INSTANCE) == RNG2))
/******************************* HASH Instances ********************************/
#define IS_HASH_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HASH1) || \
((INSTANCE) == HASH2))
/******************************* HASH Instances ********************************/
#define IS_HASH_DIGEST_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HASH1_DIGEST) || \
((INSTANCE) == HASH2_DIGEST))
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
/******************************** SDMMC Instances *****************************/
#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1) || \
((INSTANCE) == SDMMC2) || \
((INSTANCE) == SDMMC3))
/******************************** SMBUS Instances *****************************/
#define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3) || \
((INSTANCE) == SPI4) || \
((INSTANCE) == SPI5) || \
((INSTANCE) == SPI6))
#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3))
/****************** LPTIM Instances : All supported instances *****************/
#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
((INSTANCE) == LPTIM2) || \
((INSTANCE) == LPTIM3) ||\
((INSTANCE) == LPTIM4) ||\
((INSTANCE) == LPTIM5))
/****************** LPTIM Instances : supporting encoder interface **************/
#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
((INSTANCE) == LPTIM2))
/****************** TIM Instances : All supported instances *******************/
#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM12) || \
((INSTANCE) == TIM13) || \
((INSTANCE) == TIM14) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM12) || \
((INSTANCE) == TIM13) || \
((INSTANCE) == TIM14) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/************ TIM Instances : at least 2 capture/compare channels *************/
#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM12) || \
((INSTANCE) == TIM15))
/************ TIM Instances : at least 3 capture/compare channels *************/
#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/************ TIM Instances : at least 4 capture/compare channels *************/
#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/************ TIM Instances : at least 5 capture/compare channels *************/
#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/************ TIM Instances : at least 6 capture/compare channels *************/
#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/******************** TIM Instances : Advanced-control timers *****************/
/******************* TIM Instances : Timer input XOR function *****************/
#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : DMA requests generation (UDE) *************/
#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/************ TIM Instances : DMA requests generation (CCxDE) *****************/
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/************ TIM Instances : DMA requests generation (COMDE) *****************/
#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15))
/******************** TIM Instances : DMA burst feature ***********************/
#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/***************** TIM Instances : external trigger reamp input availabe *******/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/***************** TIM Instances : external trigger reamp input availabe *******/
#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM12) || \
((INSTANCE) == TIM15))
/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM12) || \
((INSTANCE) == TIM15))
/****************** TIM Instances : remapping capability **********************/
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting commutation event *************/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/
#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/******************* TIM Instances : output(s) available **********************/
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM1) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM2) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM3) && \
(((CHANNEL) == TIM_CHANNEL_1)|| \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM4) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM5) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM8) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM12) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM13) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM14) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM15) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2))) \
|| \
(((INSTANCE) == TIM16) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM17) && \
(((CHANNEL) == TIM_CHANNEL_1))))
/****************** TIM Instances : supporting the break function *************/
#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/************** TIM Instances : supporting Break source selection *************/
#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting complementary output(s) ********/
#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM1) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3))) \
|| \
(((INSTANCE) == TIM8) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3))) \
|| \
(((INSTANCE) == TIM15) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM16) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM17) && \
((CHANNEL) == TIM_CHANNEL_1)))
/****************** TIM Instances : supporting counting mode selection ********/
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting repetition counter *************/
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting external clock mode 1 for ETRF input */
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting external clock mode 2 **********/
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15))
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15))
/****************** TIM Instances : supporting OCxREF clear *******************/
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
/****************** TIM Instances : TIM_32B_COUNTER ***************************/
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM5))
/****************** TIM Instances : TIM_BKIN2 ***************************/
#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/************ TIM Instances : Advanced timers ********************************/
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting encoder interface **************/
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting Hall sensor interface **********/
#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
((__INSTANCE__) == TIM2) || \
((__INSTANCE__) == TIM3) || \
((__INSTANCE__) == TIM4) || \
((__INSTANCE__) == TIM5) || \
((__INSTANCE__) == TIM8))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == USART6))
/******************** USART Instances : SPI slave mode ************************/
#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == USART6))
/******************** UART Instances : Asynchronous mode **********************/
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == USART6) || \
((INSTANCE) == UART7) || \
((INSTANCE) == UART8))
/******************** UART Instances : FIFO mode.******************************/
#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == USART6) || \
((INSTANCE) == UART7) || \
((INSTANCE) == UART8))
/****************** UART Instances : Auto Baud Rate detection *****************/
#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == USART6) || \
((INSTANCE) == UART7) || \
((INSTANCE) == UART8))
/*********************** UART Instances : Driver Enable ***********************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == USART6) || \
((INSTANCE) == UART7) || \
((INSTANCE) == UART8))
/********************* UART Instances : Half-Duplex mode **********************/
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == USART6) || \
((INSTANCE) == UART7) || \
((INSTANCE) == UART8))
/******************* UART Instances : Hardware Flow control *******************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == USART6) || \
((INSTANCE) == UART7) || \
((INSTANCE) == UART8))
/************************* UART Instances : LIN mode **************************/
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == USART6) || \
((INSTANCE) == UART7) || \
((INSTANCE) == UART8))
/****************** UART Instances : Wake-up from Stop mode *******************/
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == USART6) || \
((INSTANCE) == UART7) || \
((INSTANCE) == UART8))
/************************* UART Instances : IRDA mode *************************/
#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == USART6) || \
((INSTANCE) == UART7) || \
((INSTANCE) == UART8))
/********************* USART Instances : Smard card mode **********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == USART6))
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2))
/****************************** USB Instances ********************************/
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1)
/****************************** MDIOS Instances ********************************/
#define IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS)
/****************************** CEC Instances *********************************/
#define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
/****************************** SAI Instances ********************************/
#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
((INSTANCE) == SAI1_Block_B) || \
((INSTANCE) == SAI2_Block_A) || \
((INSTANCE) == SAI2_Block_B) || \
((INSTANCE) == SAI3_Block_A) || \
((INSTANCE) == SAI3_Block_B) || \
((INSTANCE) == SAI4_Block_A) || \
((INSTANCE) == SAI4_Block_B))
/****************************** SPDIFRX Instances ********************************/
#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
/******************************* BSEC VERSION ********************************/
#define BSEC_VERSION(INSTANCE) ((INSTANCE)->VER)
/******************************* TZPC VERSION ********************************/
#define TZPC_VERSION(INSTANCE) ((INSTANCE)->IP_VER)
/******************************* FMC VERSION ********************************/
#define FMC_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* SYSCFG VERSION ********************************/
#define SYSCFG_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* ETHERNET VERSION ********************************/
#define ETH_VERSION(INSTANCE) ((INSTANCE)->MACVR)
/******************************* SYSCFG VERSION ********************************/
#define EXTI_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* PWR VERSION ********************************/
#define PWR_VERSION(INSTANCE) ((INSTANCE)->VER)
/******************************* RCC VERSION ********************************/
#define RCC_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* HDP VERSION ********************************/
#define HDP_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* IPCC VERSION ********************************/
#define IPCC_VERSION(INSTANCE) ((INSTANCE)->VER)
/******************************* HSEM VERSION ********************************/
#define HSEM_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* GPIO VERSION ********************************/
#define GPIO_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* DMA VERSION ********************************/
#define DMA_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* DMAMUX VERSION ********************************/
#define DMAMUX_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* MDMA VERSION ********************************/
#define MDMA_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* TAMP VERSION ********************************/
#define TAMP_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* RTC VERSION ********************************/
#define RTC_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* SDMMC VERSION ********************************/
#define SDMMC_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* QUADSPI VERSION ********************************/
#define QUADSPI_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* CRC VERSION ********************************/
#define CRC_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* RNG VERSION ********************************/
#define RNG_VERSION(INSTANCE) ((INSTANCE)->VER)
/******************************* HASH VERSION ********************************/
#define HASH_VERSION(INSTANCE) ((INSTANCE)->VER)
/******************************* CRYP VERSION ********************************/
#define CRYP_VERSION(INSTANCE) ((INSTANCE)->VER)
/******************************* DCMI VERSION ********************************/
#define DCMI_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* CEC VERSION ********************************/
#define CEC_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* LPTIM VERSION ********************************/
#define LPTIM_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* TIM VERSION ********************************/
#define TIM_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* IWDG VERSION ********************************/
#define IWDG_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* WWDG VERSION ********************************/
#define WWDG_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* DFSDM VERSION ********************************/
#define DFSDM_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* SAI VERSION ********************************/
#define SAI_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* MDIOS VERSION ********************************/
#define MDIOS_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* I2C VERSION ********************************/
#define I2C_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* USART VERSION ********************************/
#define USART_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* SPDIFRX VERSION ********************************/
#define SPDIFRX_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* SPI VERSION ********************************/
#define SPI_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* ADC VERSION ********************************/
#define ADC_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* DLYB VERSION ********************************/
#define DLYB_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* DAC VERSION ********************************/
#define DAC_VERSION(INSTANCE) ((INSTANCE)->IP_VER)
/******************************* DSI VERSION ********************************/
#define DSI_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* USBPHYC VERSION ********************************/
#define USBPHYC_VERSION(INSTANCE) ((INSTANCE)->VERR)
/******************************* DEVICE VERSION ********************************/
#define DEVICE_REVISION() (((DBGMCU->IDCODE) & (DBGMCU_IDCODE_REV_ID_Msk)) >> DBGMCU_IDCODE_REV_ID_Pos)
#define IS_DEVICE_REV_B() (DEVICE_REVISION() == 0x2000)
/******************************* DEVICE ID ************************************/
#define DEVICE_ID() ((DBGMCU->IDCODE) & (DBGMCU_IDCODE_DEV_ID_Msk))
/**
* @brief Check whether platform is engineering boot mode
* @param None
* @retval TRUE or FALSE
*/
#define IS_ENGINEERING_BOOT_MODE() (((SYSCFG->BOOTR) & (SYSCFG_BOOTR_BOOT2|SYSCFG_BOOTR_BOOT1|SYSCFG_BOOTR_BOOT0)) == (SYSCFG_BOOTR_BOOT2))
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32MP157Cxx_CM4_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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