mirror of
https://github.com/RIOT-OS/RIOT.git
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392 lines
14 KiB
C
392 lines
14 KiB
C
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/*
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* Copyright (C) 2019 Otto-von-Guericke-Universität Magdeburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup drivers_nrf24l01p_ng
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* @{
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*
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* @file
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* @brief Functions to debug the NRF24L01+ (NG) transceiver
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*
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* @author Fabian Hüßler <fabian.huessler@ovgu.de>
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* @}
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*/
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#include <stdio.h>
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#include <string.h>
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#include "nrf24l01p_ng_registers.h"
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#include "nrf24l01p_ng_communication.h"
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#include "nrf24l01p_ng_diagnostics.h"
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#if NRF24L01P_NG_ADDR_WIDTH == 3
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#define ADDR_FMT "%02x%02x%02x"
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#define ADDR_P0(dev) \
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NRF24L01P_NG_ADDR_P0(dev)[0], \
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NRF24L01P_NG_ADDR_P0(dev)[1], \
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NRF24L01P_NG_ADDR_P0(dev)[2]
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#define ADDR_P1(dev) \
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NRF24L01P_NG_ADDR_P1(dev)[0], \
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NRF24L01P_NG_ADDR_P1(dev)[1], \
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NRF24L01P_NG_ADDR_P1(dev)[2]
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#elif NRF24L01P_NG_ADDR_WIDTH == 4
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#define ADDR_FMT "%02x%02x%02x%02x"
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#define ADDR_P0(dev) \
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NRF24L01P_NG_ADDR_P0(dev)[0], \
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NRF24L01P_NG_ADDR_P0(dev)[1], \
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NRF24L01P_NG_ADDR_P0(dev)[2], \
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NRF24L01P_NG_ADDR_P0(dev)[3]
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#define ADDR_P1(dev) \
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NRF24L01P_NG_ADDR_P1(dev)[0], \
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NRF24L01P_NG_ADDR_P1(dev)[1], \
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NRF24L01P_NG_ADDR_P1(dev)[2], \
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NRF24L01P_NG_ADDR_P1(dev)[3]
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#else
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#define ADDR_FMT "%02x%02x%02x%02x%02x"
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#define ADDR_P0(dev) \
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NRF24L01P_NG_ADDR_P0(dev)[0], \
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NRF24L01P_NG_ADDR_P0(dev)[1], \
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NRF24L01P_NG_ADDR_P0(dev)[2], \
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NRF24L01P_NG_ADDR_P0(dev)[3], \
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NRF24L01P_NG_ADDR_P0(dev)[4]
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#define ADDR_P1(dev) \
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NRF24L01P_NG_ADDR_P1(dev)[0], \
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NRF24L01P_NG_ADDR_P1(dev)[1], \
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NRF24L01P_NG_ADDR_P1(dev)[2], \
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NRF24L01P_NG_ADDR_P1(dev)[3], \
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NRF24L01P_NG_ADDR_P1(dev)[4]
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#endif
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const char *
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nrf24l01p_ng_diagnostics_state_to_string(nrf24l01p_ng_state_t state)
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{
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if (state == NRF24L01P_NG_STATE_POWER_DOWN) {
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return "POWER_DOWN";
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}
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if (state == NRF24L01P_NG_STATE_STANDBY_1) {
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return "STANDBY_1";
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}
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if (state == NRF24L01P_NG_STATE_STANDBY_2) {
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return "STANDBY_2";
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}
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if (state == NRF24L01P_NG_STATE_TX_MODE) {
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return "TX_MODE";
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}
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if (state == NRF24L01P_NG_STATE_RX_MODE) {
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return "RX_MODE";
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}
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return "UNDEFINED";
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}
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nrf24l01p_ng_state_t
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nrf24l01p_ng_diagnostics_string_to_state(const char *sstate)
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{
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if (!strcmp(sstate, "POWER_DOWN")) {
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return NRF24L01P_NG_STATE_POWER_DOWN;
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}
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if (!strcmp(sstate, "STANDBY_1")) {
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return NRF24L01P_NG_STATE_STANDBY_1;
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}
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if (!strcmp(sstate, "STANDBY_2")) {
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return NRF24L01P_NG_STATE_STANDBY_2;
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}
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if (!strcmp(sstate, "TX_MODE")) {
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return NRF24L01P_NG_STATE_TX_MODE;
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}
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if (!strcmp(sstate, "RX_MODE")) {
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return NRF24L01P_NG_STATE_RX_MODE;
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}
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return NRF24L01P_NG_STATE_UNDEFINED;
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}
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void nrf24l01p_ng_diagnostics_print_all_regs(const nrf24l01p_ng_t *dev)
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{
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uint8_t config;
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nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_CONFIG, &config, 1);
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puts("");
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printf(
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"CONFIG [MASK_RX_DR %u "
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"MASK_TX_DS %u "
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"MASK_MAX_RT %u "
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"EN_CRC %u "
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"CRCO %u "
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"PWR_UP %u "
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"PRIM_RX %u]\n",
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(unsigned)NRF24L01P_NG_VAL_MASK_RX_DR(config),
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(unsigned)NRF24L01P_NG_VAL_MASK_TX_DS(config),
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(unsigned)NRF24L01P_NG_VAL_MAX_RT(config),
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(unsigned)NRF24L01P_NG_VAL_EN_CRC(config),
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(unsigned)NRF24L01P_NG_VAL_CRCO(config),
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(unsigned)NRF24L01P_NG_VAL_PWR_UP(config),
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(unsigned)NRF24L01P_NG_VAL_PRIM_RX(config)
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);
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uint8_t en_aa;
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nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_EN_AA, &en_aa, 1);
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printf(
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"EN_AA [ENAA_P5 %u "
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"ENAA_P4 %u "
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"ENAA_P3 %u "
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"ENAA_P2 %u "
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"ENAA_P1 %u "
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"ENAA_P0 %u]\n",
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(unsigned)NRF24L01P_NG_VAL_ENAA_P5(en_aa),
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(unsigned)NRF24L01P_NG_VAL_ENAA_P4(en_aa),
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(unsigned)NRF24L01P_NG_VAL_ENAA_P3(en_aa),
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(unsigned)NRF24L01P_NG_VAL_ENAA_P2(en_aa),
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(unsigned)NRF24L01P_NG_VAL_ENAA_P1(en_aa),
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(unsigned)NRF24L01P_NG_VAL_ENAA_P0(en_aa)
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);
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uint8_t en_rxaddr;
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nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_EN_RXADDR, &en_rxaddr, 1);
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printf(
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"EN_RXADDR [ERX_P5 %u "
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"ERX_P4 %u "
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"ERX_P3 %u "
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"ERX_P2 %u "
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"ERX_P1 %u "
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"ERX_P0 %u]\n",
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(unsigned)NRF24L01P_NG_VAL_ERX_P5(en_rxaddr),
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(unsigned)NRF24L01P_NG_VAL_ERX_P4(en_rxaddr),
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(unsigned)NRF24L01P_NG_VAL_ERX_P3(en_rxaddr),
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(unsigned)NRF24L01P_NG_VAL_ERX_P2(en_rxaddr),
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(unsigned)NRF24L01P_NG_VAL_ERX_P1(en_rxaddr),
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(unsigned)NRF24L01P_NG_VAL_ERX_P0(en_rxaddr)
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);
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uint8_t setup_aw;
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nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_SETUP_AW, &setup_aw, 1);
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printf(
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"SETUP_AW [AW %u]\n",
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(unsigned)NRF24L01P_NG_VAL_AW(setup_aw)
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);
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uint8_t setup_retr;
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nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_SETUP_RETR, &setup_retr, 1);
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printf(
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"SETUP_RETR [ARD %u ARC %u]\n",
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(unsigned)NRF24L01P_NG_VAL_ARD(setup_retr),
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(unsigned)NRF24L01P_NG_VAL_ARC(setup_retr)
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);
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uint8_t rf_ch;
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nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_RF_CH, &rf_ch, 1);
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printf(
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"RF_CH [RF_CH %u]\n",
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(unsigned)NRF24L01P_NG_VAL_RF_CH(rf_ch)
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);
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uint8_t rf_setup;
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nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_RF_SETUP, &rf_setup, 1);
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printf(
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"RF_SETUP [CONT_WAVE %u "
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"RF_DR_LOW %u "
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"PLL_LOCK %u "
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"RF_DR_HIGH %u "
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"RF_PWR %u]\n",
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(unsigned)NRF24L01P_NG_VAL_CONT_WAVE(rf_setup),
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(unsigned)NRF24L01P_NG_VAL_RF_DR_LOW(rf_setup),
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(unsigned)NRF24L01P_NG_VAL_PLL_LOCK(rf_setup),
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(unsigned)NRF24L01P_NG_VAL_RF_DR_HIGH(rf_setup),
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(unsigned)NRF24L01P_NG_VAL_RF_PWR(rf_setup)
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);
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uint8_t status;
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nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_STATUS, &status, 1);
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printf(
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"STATUS [RX_DR %u "
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"TX_DS %u "
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"MAX_RT %u "
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"RX_P_NO %u "
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"TX_FULL %u]\n",
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(unsigned)NRF24L01P_NG_VAL_RX_DR(status),
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(unsigned)NRF24L01P_NG_VAL_TX_DS(status),
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(unsigned)NRF24L01P_NG_VAL_MAX_RT(status),
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(unsigned)NRF24L01P_NG_VAL_RX_P_NO(status),
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(unsigned)NRF24L01P_NG_VAL_TX_FULL(status)
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);
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uint8_t observe_tx;
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nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_OBSERVE_TX, &observe_tx, 1);
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printf(
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"OBSERVE_TX [PLOS_CNT %u ARC_CNT %u]\n",
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(unsigned)NRF24L01P_NG_VAL_PLOS_CNT(observe_tx),
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(unsigned)NRF24L01P_NG_VAL_ARC_CNT(observe_tx)
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);
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uint8_t rpd;
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nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_RPD, &rpd, 1);
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printf(
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"RPD [RPD %u]\n",
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(unsigned)NRF24L01P_NG_VAL_RPD(rpd)
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);
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uint8_t rx_addr_px_40[2][NRF24L01P_NG_MAX_ADDR_WIDTH]; /* Pipe 0/1 */
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nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_RX_ADDR_P0, rx_addr_px_40[0],
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NRF24L01P_NG_MAX_ADDR_WIDTH);
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printf(
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"RX_ADDR_P0 [RX_ADDR_P0 %02x:%02x:%02x:%02x:%02x]\n",
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rx_addr_px_40[0][0],
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rx_addr_px_40[0][1],
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rx_addr_px_40[0][2],
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rx_addr_px_40[0][3],
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rx_addr_px_40[0][4]
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);
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nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_RX_ADDR_P1, rx_addr_px_40[1],
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NRF24L01P_NG_MAX_ADDR_WIDTH);
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printf(
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"RX_ADDR_P1 [RX_ADDR_P1 %02x:%02x:%02x:%02x:%02x]\n",
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rx_addr_px_40[1][0],
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rx_addr_px_40[1][1],
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rx_addr_px_40[1][2],
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rx_addr_px_40[1][3],
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rx_addr_px_40[1][4]
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);
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uint8_t rx_addr_px_8[4]; /* Pipe 2/3/4/5 */
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nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_RX_ADDR_P2,
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&rx_addr_px_8[0], 1);
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printf(
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"RX_ADDR_P2 [RX_ADDR_P2 %02x]\n",
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rx_addr_px_8[0]
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);
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nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_RX_ADDR_P3,
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&rx_addr_px_8[1], 1);
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printf(
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"RX_ADDR_P3 [RX_ADDR_P3 %02x]\n",
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rx_addr_px_8[1]
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);
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nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_RX_ADDR_P4,
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&rx_addr_px_8[2], 1);
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printf(
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"RX_ADDR_P4 [RX_ADDR_P4 %02x]\n",
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rx_addr_px_8[2]
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);
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nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_RX_ADDR_P5,
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&rx_addr_px_8[3], 1);
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printf(
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"RX_ADDR_P5 [RX_ADDR_P5 %02x]\n",
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rx_addr_px_8[3]
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);
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uint8_t tx_addr[NRF24L01P_NG_MAX_ADDR_WIDTH];
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nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_TX_ADDR, tx_addr,
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NRF24L01P_NG_MAX_ADDR_WIDTH);
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printf(
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"TX_ADDR [TX_ADDR %02x:%02x:%02x:%02x:%02x]\n",
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tx_addr[0],
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tx_addr[1],
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tx_addr[2],
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tx_addr[3],
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tx_addr[4]
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);
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uint8_t rx_pw_px[6];
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nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_RX_PW_P0, &rx_pw_px[0], 1);
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printf(
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"RX_PW_P0 [RX_PW_P0 %u]\n",
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(unsigned)NRF24L01P_NG_VAL_RX_PW_PX(rx_pw_px[0])
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);
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nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_RX_PW_P1, &rx_pw_px[1], 1);
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printf(
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"RX_PW_P1 [RX_PW_P1 %u]\n",
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(unsigned)NRF24L01P_NG_VAL_RX_PW_PX(rx_pw_px[1])
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);
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nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_RX_PW_P2, &rx_pw_px[2], 1);
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printf(
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"RX_PW_P2 [RX_PW_P2 %u]\n",
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(unsigned)NRF24L01P_NG_VAL_RX_PW_PX(rx_pw_px[2])
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);
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nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_RX_PW_P3, &rx_pw_px[3], 1);
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printf(
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"RX_PW_P3 [RX_PW_P3 %u]\n",
|
||
|
|
(unsigned)NRF24L01P_NG_VAL_RX_PW_PX(rx_pw_px[3])
|
||
|
|
);
|
||
|
|
nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_RX_PW_P4, &rx_pw_px[4], 1);
|
||
|
|
printf(
|
||
|
|
"RX_PW_P4 [RX_PW_P4 %u]\n",
|
||
|
|
(unsigned)NRF24L01P_NG_VAL_RX_PW_PX(rx_pw_px[4])
|
||
|
|
);
|
||
|
|
nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_RX_PW_P5, &rx_pw_px[5], 1);
|
||
|
|
printf(
|
||
|
|
"RX_PW_P5 [RX_PW_P5 %u]\n",
|
||
|
|
(unsigned)NRF24L01P_NG_VAL_RX_PW_PX(rx_pw_px[5])
|
||
|
|
);
|
||
|
|
uint8_t fifo_status;
|
||
|
|
nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_FIFO_STATUS, &fifo_status, 1);
|
||
|
|
printf(
|
||
|
|
"FIFO_STATUS [TX_REUSE %u "
|
||
|
|
"TX_FULL %u "
|
||
|
|
"TX_EMPTY %u "
|
||
|
|
"RX_FULL %u "
|
||
|
|
"RX_EMPTY %u]\n",
|
||
|
|
(unsigned)NRF24L01P_NG_VAL_TX_REUSE(fifo_status),
|
||
|
|
(unsigned)NRF24L01P_NG_VAL_TX_FULL_(fifo_status),
|
||
|
|
(unsigned)NRF24L01P_NG_VAL_TX_EMPTY(fifo_status),
|
||
|
|
(unsigned)NRF24L01P_NG_VAL_RX_FULL(fifo_status),
|
||
|
|
NRF24L01P_NG_VAL_RX_EMPTY(fifo_status)
|
||
|
|
);
|
||
|
|
uint8_t dynpd;
|
||
|
|
nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_DYNPD, &dynpd, 1);
|
||
|
|
printf(
|
||
|
|
"DYNDP [DPL_P5 %u "
|
||
|
|
"DPL_P4 %u "
|
||
|
|
"DPL_P3 %u "
|
||
|
|
"DPL_P2 %u "
|
||
|
|
"DPL_P1 %u "
|
||
|
|
"DPL_P0 %u]\n",
|
||
|
|
(unsigned)NRF24L01P_NG_VAL_DPL_P5(dynpd),
|
||
|
|
(unsigned)NRF24L01P_NG_VAL_DPL_P4(dynpd),
|
||
|
|
(unsigned)NRF24L01P_NG_VAL_DPL_P3(dynpd),
|
||
|
|
(unsigned)NRF24L01P_NG_VAL_DPL_P2(dynpd),
|
||
|
|
(unsigned)NRF24L01P_NG_VAL_DPL_P1(dynpd),
|
||
|
|
(unsigned)NRF24L01P_NG_VAL_DPL_P0(dynpd)
|
||
|
|
);
|
||
|
|
uint8_t features;
|
||
|
|
nrf24l01p_ng_read_reg(dev, NRF24L01P_NG_REG_FEATURES, &features, 1);
|
||
|
|
printf(
|
||
|
|
"FEATURES [EN_DPL %u EN_ACK_PAY %u DYN_ACK %u]\n",
|
||
|
|
(unsigned)NRF24L01P_NG_VAL_EN_DPL(features),
|
||
|
|
(unsigned)NRF24L01P_NG_VAL_EN_ACK_PAY(features),
|
||
|
|
(unsigned)NRF24L01P_NG_VAL_EN_DYN_ACK(features)
|
||
|
|
);
|
||
|
|
}
|
||
|
|
|
||
|
|
void nrf24l01p_ng_diagnostics_print_dev_info(const nrf24l01p_ng_t *dev)
|
||
|
|
{
|
||
|
|
printf("device: %p\n", (const void *)dev);
|
||
|
|
printf("address length: %u\n", (unsigned)NRF24L01P_NG_ADDR_WIDTH);
|
||
|
|
printf("device params:\n");
|
||
|
|
printf("\tChannel: %u\n",
|
||
|
|
dev->params.config.cfg_channel);
|
||
|
|
printf("\tCRC length: %u bytes\n",
|
||
|
|
(unsigned)nrf24l01p_ng_etoval_crc(dev->params.config.cfg_crc));
|
||
|
|
printf("\tData rate: %u kbps\n",
|
||
|
|
(unsigned)
|
||
|
|
nrf24l01p_ng_etoval_rfdr(dev->params.config.cfg_data_rate));
|
||
|
|
printf("\tMax. retransmissions: %u\n",
|
||
|
|
dev->params.config.cfg_max_retr);
|
||
|
|
printf("\tRetransmission delay: %u us\n",
|
||
|
|
(unsigned)
|
||
|
|
nrf24l01p_ng_etoval_ard(dev->params.config.cfg_retr_delay));
|
||
|
|
printf("\tTx power: %d dbm\n",
|
||
|
|
nrf24l01p_ng_etoval_tx_power(dev->params.config.cfg_tx_power));
|
||
|
|
printf("\tRx address p0: "ADDR_FMT"\n",
|
||
|
|
ADDR_P0(dev));
|
||
|
|
printf("\tRX address p1: "ADDR_FMT"\n",
|
||
|
|
ADDR_P1(dev));
|
||
|
|
printf("\tRX address p2: %02x\n",
|
||
|
|
NRF24L01P_NG_ADDR_PX_LSB(dev, NRF24L01P_NG_P2));
|
||
|
|
printf("\tRX address p3: %02x\n",
|
||
|
|
NRF24L01P_NG_ADDR_PX_LSB(dev, NRF24L01P_NG_P3));
|
||
|
|
printf("\tRX address p4: %02x\n",
|
||
|
|
NRF24L01P_NG_ADDR_PX_LSB(dev, NRF24L01P_NG_P4));
|
||
|
|
printf("\tRX address p5: %02x\n",
|
||
|
|
NRF24L01P_NG_ADDR_PX_LSB(dev, NRF24L01P_NG_P5));
|
||
|
|
|
||
|
|
printf("State: %s\n",
|
||
|
|
nrf24l01p_ng_diagnostics_state_to_string(dev->state));
|
||
|
|
}
|
||
|
|
|
||
|
|
void nrf24l01p_ng_diagnostics_print_frame(const nrf24l01p_ng_t *dev,
|
||
|
|
const void *frame, size_t len)
|
||
|
|
{
|
||
|
|
(void)dev;
|
||
|
|
puts("Rx frame");
|
||
|
|
for (uint8_t i = 0; i < len; i++) {
|
||
|
|
printf("0x%02X ", ((uint8_t *)frame)[i]);
|
||
|
|
}
|
||
|
|
puts("");
|
||
|
|
}
|