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RIOT/cpu/gd32v/Kconfig

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cpu/gd32v: Initial include of the GD32VF103 device This adds support for the gd32v class devices from Gigadevice. The gd32vf103 contains an 108 MHz RISC-V core with similar peripherals as the stm32f1 devices Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
2021-02-17 13:47:50 +01:00
# Copyright (c) 2020 Inria
#
# This file is subject to the terms and conditions of the GNU Lesser
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
#
config CPU_FAM_GD32V
bool
cpu/riscv,gd32: match Kconfig to Makefile changes
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select CPU_CORE_RV32IMAC
cpu/gdv32: add pm_layered support
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menu "GD32V configuration"
cpu/gd32v: model Kconfig
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boards/sipeed-longan-nano: initial support
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config CPU_MODEL_GD32VF103CBT6
bool
select CPU_FAM_GD32V
cpu/gd32v: Initial include of the GD32VF103 device This adds support for the gd32v class devices from Gigadevice. The gd32vf103 contains an 108 MHz RISC-V core with similar peripherals as the stm32f1 devices Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
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config CPU_MODEL_GD32VF103VBT6
bool
select CPU_FAM_GD32V
config CPU_FAM
default "gd32v" if CPU_FAM_GD32V
boards/sipeed-longan-nano: initial support
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config CPU_MODEL
default "gd32vf103cbt6" if CPU_MODEL_GD32VF103CBT6
cpu/gd32v: Initial include of the GD32VF103 device This adds support for the gd32v class devices from Gigadevice. The gd32vf103 contains an 108 MHz RISC-V core with similar peripherals as the stm32f1 devices Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
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config CPU_MODEL
default "gd32vf103vbt6" if CPU_MODEL_GD32VF103VBT6
config CPU
default "gd32v" if CPU_FAM_GD32V
cpu/riscv,gd32: match Kconfig to Makefile changes
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config CPU_CORE
default "rv32imac" if CPU_CORE_RV32IMAC
cpu/gd32v: model Kconfig
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rsource "periph/Kconfig"
cpu/gdv32: add pm_layered support
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endmenu
cpu/gd32v: Initial include of the GD32VF103 device This adds support for the gd32v class devices from Gigadevice. The gd32vf103 contains an 108 MHz RISC-V core with similar peripherals as the stm32f1 devices Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
2021-02-17 13:47:50 +01:00
source "$(RIOTCPU)/riscv_common/Kconfig"
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