2022-06-03 19:25:26 +02:00
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# If port selection via ttys.py is enabled by `MOST_RECENT_PORT=1`, filter
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# USB serials to only select the UART bridge of the embedded EDBG CMSIS-DAP
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# debugger.
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TTY_BOARD_FILTER := --model 'EDBG CMSIS-DAP'
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2023-11-06 10:39:14 +01:00
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# Overwrite GCLK definitions, so that GCLK_IO[2..7] can be connected to GPIOs.
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# This way the frequency of signals, connected to these pins, can be measured
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# with the FREQM peripheral.
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CFLAGS += -DSAM0_GCLK_TIMER=8
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CFLAGS += -DSAM0_GCLK_PERIPH=9
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CFLAGS += -DSAM0_GCLK_100MHZ=10
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2019-03-12 14:01:06 +01:00
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include $(RIOTMAKE)/boards/sam0.inc.mk
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