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172 lines
13 KiB
C
172 lines
13 KiB
C
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/**
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* \file
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*
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* \brief Instance description for TAL
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*
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* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#ifndef _SAML21_TAL_INSTANCE_
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#define _SAML21_TAL_INSTANCE_
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/* ========== Register definition for TAL peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_TAL_CTRLA (0x40002C00U) /**< \brief (TAL) Control A */
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#define REG_TAL_RSTCTRL (0x40002C04U) /**< \brief (TAL) Reset Control */
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#define REG_TAL_EXTCTRL (0x40002C05U) /**< \brief (TAL) External Break Control */
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#define REG_TAL_EVCTRL (0x40002C06U) /**< \brief (TAL) Event Control */
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#define REG_TAL_INTENCLR (0x40002C08U) /**< \brief (TAL) Interrupt Enable Clear */
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#define REG_TAL_INTENSET (0x40002C09U) /**< \brief (TAL) Interrupt Enable Set */
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#define REG_TAL_INTFLAG (0x40002C0AU) /**< \brief (TAL) Interrupt Flag Status and Clear */
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#define REG_TAL_GLOBMASK (0x40002C0BU) /**< \brief (TAL) Global Break Requests Mask */
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#define REG_TAL_HALT (0x40002C0CU) /**< \brief (TAL) Debug Halt Request */
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#define REG_TAL_RESTART (0x40002C0DU) /**< \brief (TAL) Debug Restart Request */
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#define REG_TAL_BRKSTATUS (0x40002C0EU) /**< \brief (TAL) Break Request Status */
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#define REG_TAL_CTICTRLA0 (0x40002C10U) /**< \brief (TAL) Cross-Trigger Interface 0 Control A */
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#define REG_TAL_CTIMASK0 (0x40002C11U) /**< \brief (TAL) Cross-Trigger Interface 0 Mask */
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#define REG_TAL_CTICTRLA1 (0x40002C12U) /**< \brief (TAL) Cross-Trigger Interface 1 Control A */
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#define REG_TAL_CTIMASK1 (0x40002C13U) /**< \brief (TAL) Cross-Trigger Interface 1 Mask */
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#define REG_TAL_CTICTRLA2 (0x40002C14U) /**< \brief (TAL) Cross-Trigger Interface 2 Control A */
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#define REG_TAL_CTIMASK2 (0x40002C15U) /**< \brief (TAL) Cross-Trigger Interface 2 Mask */
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#define REG_TAL_CTICTRLA3 (0x40002C16U) /**< \brief (TAL) Cross-Trigger Interface 3 Control A */
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#define REG_TAL_CTIMASK3 (0x40002C17U) /**< \brief (TAL) Cross-Trigger Interface 3 Mask */
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#define REG_TAL_INTSTATUS0 (0x40002C20U) /**< \brief (TAL) Interrupt 0 Status */
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#define REG_TAL_INTSTATUS1 (0x40002C21U) /**< \brief (TAL) Interrupt 1 Status */
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#define REG_TAL_INTSTATUS2 (0x40002C22U) /**< \brief (TAL) Interrupt 2 Status */
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#define REG_TAL_INTSTATUS3 (0x40002C23U) /**< \brief (TAL) Interrupt 3 Status */
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#define REG_TAL_INTSTATUS4 (0x40002C24U) /**< \brief (TAL) Interrupt 4 Status */
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#define REG_TAL_INTSTATUS5 (0x40002C25U) /**< \brief (TAL) Interrupt 5 Status */
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#define REG_TAL_INTSTATUS6 (0x40002C26U) /**< \brief (TAL) Interrupt 6 Status */
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#define REG_TAL_INTSTATUS7 (0x40002C27U) /**< \brief (TAL) Interrupt 7 Status */
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#define REG_TAL_INTSTATUS8 (0x40002C28U) /**< \brief (TAL) Interrupt 8 Status */
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#define REG_TAL_INTSTATUS9 (0x40002C29U) /**< \brief (TAL) Interrupt 9 Status */
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#define REG_TAL_INTSTATUS10 (0x40002C2AU) /**< \brief (TAL) Interrupt 10 Status */
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#define REG_TAL_INTSTATUS11 (0x40002C2BU) /**< \brief (TAL) Interrupt 11 Status */
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#define REG_TAL_INTSTATUS12 (0x40002C2CU) /**< \brief (TAL) Interrupt 12 Status */
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#define REG_TAL_INTSTATUS13 (0x40002C2DU) /**< \brief (TAL) Interrupt 13 Status */
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#define REG_TAL_INTSTATUS14 (0x40002C2EU) /**< \brief (TAL) Interrupt 14 Status */
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#define REG_TAL_INTSTATUS15 (0x40002C2FU) /**< \brief (TAL) Interrupt 15 Status */
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#define REG_TAL_INTSTATUS16 (0x40002C30U) /**< \brief (TAL) Interrupt 16 Status */
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#define REG_TAL_INTSTATUS17 (0x40002C31U) /**< \brief (TAL) Interrupt 17 Status */
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#define REG_TAL_INTSTATUS18 (0x40002C32U) /**< \brief (TAL) Interrupt 18 Status */
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#define REG_TAL_INTSTATUS19 (0x40002C33U) /**< \brief (TAL) Interrupt 19 Status */
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#define REG_TAL_INTSTATUS20 (0x40002C34U) /**< \brief (TAL) Interrupt 20 Status */
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#define REG_TAL_INTSTATUS21 (0x40002C35U) /**< \brief (TAL) Interrupt 21 Status */
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#define REG_TAL_INTSTATUS22 (0x40002C36U) /**< \brief (TAL) Interrupt 22 Status */
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#define REG_TAL_INTSTATUS23 (0x40002C37U) /**< \brief (TAL) Interrupt 23 Status */
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#define REG_TAL_INTSTATUS24 (0x40002C38U) /**< \brief (TAL) Interrupt 24 Status */
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#define REG_TAL_INTSTATUS25 (0x40002C39U) /**< \brief (TAL) Interrupt 25 Status */
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#define REG_TAL_INTSTATUS26 (0x40002C3AU) /**< \brief (TAL) Interrupt 26 Status */
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#define REG_TAL_INTSTATUS27 (0x40002C3BU) /**< \brief (TAL) Interrupt 27 Status */
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#define REG_TAL_INTSTATUS28 (0x40002C3CU) /**< \brief (TAL) Interrupt 28 Status */
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#define REG_TAL_DMACPUSEL0 (0x40002C40U) /**< \brief (TAL) DMA Channel Interrupts CPU Select 0 */
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#define REG_TAL_EVCPUSEL0 (0x40002C48U) /**< \brief (TAL) EVSYS Channel Interrupts CPU Select 0 */
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#define REG_TAL_EICCPUSEL0 (0x40002C50U) /**< \brief (TAL) EIC External Interrupts CPU Select 0 */
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#define REG_TAL_INTCPUSEL0 (0x40002C58U) /**< \brief (TAL) Interrupts CPU Select 0 */
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#define REG_TAL_INTCPUSEL1 (0x40002C5CU) /**< \brief (TAL) Interrupts CPU Select 1 */
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#define REG_TAL_IRQTRIG (0x40002C60U) /**< \brief (TAL) Interrupt Trigger */
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#else
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#define REG_TAL_CTRLA (*(RwReg8 *)0x40002C00U) /**< \brief (TAL) Control A */
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#define REG_TAL_RSTCTRL (*(RwReg8 *)0x40002C04U) /**< \brief (TAL) Reset Control */
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#define REG_TAL_EXTCTRL (*(RwReg8 *)0x40002C05U) /**< \brief (TAL) External Break Control */
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#define REG_TAL_EVCTRL (*(RwReg8 *)0x40002C06U) /**< \brief (TAL) Event Control */
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#define REG_TAL_INTENCLR (*(RwReg8 *)0x40002C08U) /**< \brief (TAL) Interrupt Enable Clear */
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#define REG_TAL_INTENSET (*(RwReg8 *)0x40002C09U) /**< \brief (TAL) Interrupt Enable Set */
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#define REG_TAL_INTFLAG (*(RwReg8 *)0x40002C0AU) /**< \brief (TAL) Interrupt Flag Status and Clear */
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#define REG_TAL_GLOBMASK (*(RwReg8 *)0x40002C0BU) /**< \brief (TAL) Global Break Requests Mask */
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#define REG_TAL_HALT (*(WoReg8 *)0x40002C0CU) /**< \brief (TAL) Debug Halt Request */
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#define REG_TAL_RESTART (*(WoReg8 *)0x40002C0DU) /**< \brief (TAL) Debug Restart Request */
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#define REG_TAL_BRKSTATUS (*(RoReg16*)0x40002C0EU) /**< \brief (TAL) Break Request Status */
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#define REG_TAL_CTICTRLA0 (*(RwReg8 *)0x40002C10U) /**< \brief (TAL) Cross-Trigger Interface 0 Control A */
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#define REG_TAL_CTIMASK0 (*(RwReg8 *)0x40002C11U) /**< \brief (TAL) Cross-Trigger Interface 0 Mask */
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#define REG_TAL_CTICTRLA1 (*(RwReg8 *)0x40002C12U) /**< \brief (TAL) Cross-Trigger Interface 1 Control A */
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#define REG_TAL_CTIMASK1 (*(RwReg8 *)0x40002C13U) /**< \brief (TAL) Cross-Trigger Interface 1 Mask */
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#define REG_TAL_CTICTRLA2 (*(RwReg8 *)0x40002C14U) /**< \brief (TAL) Cross-Trigger Interface 2 Control A */
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#define REG_TAL_CTIMASK2 (*(RwReg8 *)0x40002C15U) /**< \brief (TAL) Cross-Trigger Interface 2 Mask */
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#define REG_TAL_CTICTRLA3 (*(RwReg8 *)0x40002C16U) /**< \brief (TAL) Cross-Trigger Interface 3 Control A */
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#define REG_TAL_CTIMASK3 (*(RwReg8 *)0x40002C17U) /**< \brief (TAL) Cross-Trigger Interface 3 Mask */
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#define REG_TAL_INTSTATUS0 (*(RoReg8 *)0x40002C20U) /**< \brief (TAL) Interrupt 0 Status */
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#define REG_TAL_INTSTATUS1 (*(RoReg8 *)0x40002C21U) /**< \brief (TAL) Interrupt 1 Status */
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#define REG_TAL_INTSTATUS2 (*(RoReg8 *)0x40002C22U) /**< \brief (TAL) Interrupt 2 Status */
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#define REG_TAL_INTSTATUS3 (*(RoReg8 *)0x40002C23U) /**< \brief (TAL) Interrupt 3 Status */
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#define REG_TAL_INTSTATUS4 (*(RoReg8 *)0x40002C24U) /**< \brief (TAL) Interrupt 4 Status */
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#define REG_TAL_INTSTATUS5 (*(RoReg8 *)0x40002C25U) /**< \brief (TAL) Interrupt 5 Status */
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#define REG_TAL_INTSTATUS6 (*(RoReg8 *)0x40002C26U) /**< \brief (TAL) Interrupt 6 Status */
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#define REG_TAL_INTSTATUS7 (*(RoReg8 *)0x40002C27U) /**< \brief (TAL) Interrupt 7 Status */
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#define REG_TAL_INTSTATUS8 (*(RoReg8 *)0x40002C28U) /**< \brief (TAL) Interrupt 8 Status */
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#define REG_TAL_INTSTATUS9 (*(RoReg8 *)0x40002C29U) /**< \brief (TAL) Interrupt 9 Status */
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#define REG_TAL_INTSTATUS10 (*(RoReg8 *)0x40002C2AU) /**< \brief (TAL) Interrupt 10 Status */
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#define REG_TAL_INTSTATUS11 (*(RoReg8 *)0x40002C2BU) /**< \brief (TAL) Interrupt 11 Status */
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#define REG_TAL_INTSTATUS12 (*(RoReg8 *)0x40002C2CU) /**< \brief (TAL) Interrupt 12 Status */
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#define REG_TAL_INTSTATUS13 (*(RoReg8 *)0x40002C2DU) /**< \brief (TAL) Interrupt 13 Status */
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#define REG_TAL_INTSTATUS14 (*(RoReg8 *)0x40002C2EU) /**< \brief (TAL) Interrupt 14 Status */
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#define REG_TAL_INTSTATUS15 (*(RoReg8 *)0x40002C2FU) /**< \brief (TAL) Interrupt 15 Status */
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#define REG_TAL_INTSTATUS16 (*(RoReg8 *)0x40002C30U) /**< \brief (TAL) Interrupt 16 Status */
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#define REG_TAL_INTSTATUS17 (*(RoReg8 *)0x40002C31U) /**< \brief (TAL) Interrupt 17 Status */
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#define REG_TAL_INTSTATUS18 (*(RoReg8 *)0x40002C32U) /**< \brief (TAL) Interrupt 18 Status */
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#define REG_TAL_INTSTATUS19 (*(RoReg8 *)0x40002C33U) /**< \brief (TAL) Interrupt 19 Status */
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#define REG_TAL_INTSTATUS20 (*(RoReg8 *)0x40002C34U) /**< \brief (TAL) Interrupt 20 Status */
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#define REG_TAL_INTSTATUS21 (*(RoReg8 *)0x40002C35U) /**< \brief (TAL) Interrupt 21 Status */
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#define REG_TAL_INTSTATUS22 (*(RoReg8 *)0x40002C36U) /**< \brief (TAL) Interrupt 22 Status */
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#define REG_TAL_INTSTATUS23 (*(RoReg8 *)0x40002C37U) /**< \brief (TAL) Interrupt 23 Status */
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#define REG_TAL_INTSTATUS24 (*(RoReg8 *)0x40002C38U) /**< \brief (TAL) Interrupt 24 Status */
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#define REG_TAL_INTSTATUS25 (*(RoReg8 *)0x40002C39U) /**< \brief (TAL) Interrupt 25 Status */
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#define REG_TAL_INTSTATUS26 (*(RoReg8 *)0x40002C3AU) /**< \brief (TAL) Interrupt 26 Status */
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#define REG_TAL_INTSTATUS27 (*(RoReg8 *)0x40002C3BU) /**< \brief (TAL) Interrupt 27 Status */
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#define REG_TAL_INTSTATUS28 (*(RoReg8 *)0x40002C3CU) /**< \brief (TAL) Interrupt 28 Status */
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#define REG_TAL_DMACPUSEL0 (*(RwReg *)0x40002C40U) /**< \brief (TAL) DMA Channel Interrupts CPU Select 0 */
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#define REG_TAL_EVCPUSEL0 (*(RwReg *)0x40002C48U) /**< \brief (TAL) EVSYS Channel Interrupts CPU Select 0 */
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#define REG_TAL_EICCPUSEL0 (*(RwReg *)0x40002C50U) /**< \brief (TAL) EIC External Interrupts CPU Select 0 */
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#define REG_TAL_INTCPUSEL0 (*(RwReg *)0x40002C58U) /**< \brief (TAL) Interrupts CPU Select 0 */
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#define REG_TAL_INTCPUSEL1 (*(RwReg *)0x40002C5CU) /**< \brief (TAL) Interrupts CPU Select 1 */
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#define REG_TAL_IRQTRIG (*(RwReg16*)0x40002C60U) /**< \brief (TAL) Interrupt Trigger */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for TAL peripheral ========== */
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#define TAL_CPU_NUM 2 // Number of CPUs
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#define TAL_CTI_NUM 4 // Number of Cross-Trigger Interfaces
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#define TAL_DMA_CH_NUM 16 // Number of DMAC Channels
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#define TAL_EV_CH_NUM 12 // Number of EVSYS Channels
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#define TAL_EXTINT_NUM 16 // Number of EIC External Interrrupts
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#define TAL_INT_NUM 29 // Number of Interrupt Requests
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#endif /* _SAML21_TAL_INSTANCE_ */
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