2017-10-28 17:48:01 +02:00
|
|
|
FEATURES_PROVIDED += periph_cpuid
|
2018-12-18 21:50:34 +01:00
|
|
|
FEATURES_PROVIDED += periph_gpio periph_gpio_irq
|
2018-07-05 16:21:14 +02:00
|
|
|
FEATURES_PROVIDED += puf_sram
|
cpu/stm32_common: add support for uart_mode routine
Add support for specifying data bits, stop bits and parity at
runtime.
Introduce feature periph_uart_modecfg for uart_mode() till all
other CPUs implement it.
STM32 L1, F1, F2, F4 supports following modes:
* 7E1, 7E2
* 7O1, 7O2
* 8N1, 8N2
* 8E1, 8E2
* 8O1, 8O2
STM32 L0, L4, F0, F3, F7 supports following modes:
* 6E1, 6E2
* 6O1, 6O2
* 7E1, 7E2
* 7O1, 7O2
* 7N1, 7N2
* 8N1, 8N2
* 8E1, 8E2
* 8O1, 8O2
Use USART_CR1_M1 macro to detect 7-bit support because
even inside one family there could be devices that don't
support 7-bit mode. So just using a family macro is not
enough.
As stated in the datasheets for L0, L4, F0, F3, F7 devices,
data bits can only be changed when UART is disabled (UE=0).
Introduce uart_stop() routine to satisfy this requirement.
STM32 UART adds parity to the MSB of a byte to send. The same
also applies to the received bytes. As a result this bit must
be masked in order to get the pure data.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
2019-01-08 11:10:49 +01:00
|
|
|
FEATURES_PROVIDED += periph_uart_modecfg
|
2019-09-12 17:42:54 +02:00
|
|
|
FEATURES_PROVIDED += periph_wdt
|
2017-10-28 17:48:01 +02:00
|
|
|
|
|
|
|
|
ifneq (,$(filter $(BOARDS_WITHOUT_HWRNG),$(BOARD)))
|
|
|
|
|
FEATURES_PROVIDED := $(filter-out periph_hwrng,$(FEATURES_PROVIDED))
|
|
|
|
|
endif
|
|
|
|
|
|
|
|
|
|
-include $(RIOTCPU)/cortexm_common/Makefile.features
|
