2020-05-23 17:28:13 +02:00
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/*
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* Copyright (C) 2020 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_common_stm32
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* @{
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*
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* @file
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* @brief Configure STM32G4 clock
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef G4_CFG_CLOCK_DEFAULT_H
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#define G4_CFG_CLOCK_DEFAULT_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock settings
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* @{
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*/
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#define CLOCK_USE_HSI (0)
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#define CLOCK_USE_HSE (0)
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#define CLOCK_USE_PLL (1)
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#define CLOCK_HSI (16000000U)
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#ifndef CLOCK_HSE
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#define CLOCK_HSE (24000000U)
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#endif
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#ifndef CLOCK_LSE
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#define CLOCK_LSE (1U)
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#endif
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#if CLOCK_USE_HSI
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#define CLOCK_CORECLOCK (CLOCK_HSI)
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#elif CLOCK_USE_HSE
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#define CLOCK_CORECLOCK (CLOCK_HSE)
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#elif CLOCK_USE_PLL
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2020-08-24 15:28:13 +02:00
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/* The following parameters configure a 170MHz system clock with HSE as input clock */
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2020-05-23 17:28:13 +02:00
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#define CLOCK_PLL_M (6)
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#define CLOCK_PLL_N (85)
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#define CLOCK_PLL_R (2)
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#if CLOCK_HSE
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#define CLOCK_PLL_SRC (CLOCK_HSE)
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#else /* CLOCK_HSI */
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#define CLOCK_PLL_SRC (CLOCK_HSI)
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#endif
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#define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CLOCK_PLL_M) * CLOCK_PLL_N) / CLOCK_PLL_R
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#endif
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1) /* max 170MHz */
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 1) /* max 170MHz */
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) /* max 170MHz */
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* G4_CFG_CLOCK_DEFAULT_H */
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/** @} */
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