mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2024-12-29 04:50:03 +01:00
265 lines
10 KiB
C
265 lines
10 KiB
C
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/*
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* Copyright (C) 2014 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup board_msbiot
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* @{
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*
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* @file
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* @name Peripheral MCU configuration for the MSB-IoT board
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*
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* @author Fabian Nack <nack@inf.fu-berlin.de>
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*/
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#ifndef __PERIPH_CONF_H
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#define __PERIPH_CONF_H
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/**
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* @name Clock system configuration
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* @{
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*/
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#define CLOCK_HSE (16000000U) /* external oscillator */
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#define CLOCK_CORECLOCK (168000000U) /* desired core clock frequency */
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/* the actual PLL values are automatically generated */
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#define CLOCK_PLL_M (CLOCK_HSE / 1000000)
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#define CLOCK_PLL_N ((CLOCK_CORECLOCK / 1000000) * 2)
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#define CLOCK_PLL_P (2U)
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#define CLOCK_PLL_Q (CLOCK_PLL_N / 48)
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
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#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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#define TIMER_NUMOF (2U)
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#define TIMER_0_EN 1
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#define TIMER_1_EN 1
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#define TIMER_IRQ_PRIO 1
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/* Timer 0 configuration */
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#define TIMER_0_DEV TIM2
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#define TIMER_0_CHANNELS 4
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#define TIMER_0_PRESCALER (83U)
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#define TIMER_0_MAX_VALUE (0xffffffff)
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#define TIMER_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_TIM2EN)
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#define TIMER_0_ISR isr_tim2
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#define TIMER_0_IRQ_CHAN TIM2_IRQn
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/* Timer 1 configuration */
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#define TIMER_1_DEV TIM5
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#define TIMER_1_CHANNELS 4
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#define TIMER_1_PRESCALER (83U)
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#define TIMER_1_MAX_VALUE (0xffffffff)
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#define TIMER_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_TIM5EN)
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#define TIMER_1_ISR isr_tim5
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#define TIMER_1_IRQ_CHAN TIM5_IRQn
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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#define UART_NUMOF (3U)
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#define UART_0_EN 1
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#define UART_1_EN 1
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#define UART_2_EN 1
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#define UART_IRQ_PRIO 1
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/* UART 0 device configuration */
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#define UART_0_DEV USART2
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#define UART_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART2EN)
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#define UART_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
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#define UART_0_CLK (42000000) /* UART clock runs with 42MHz (F_CPU / 4) */
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#define UART_0_IRQ_CHAN USART2_IRQn
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#define UART_0_ISR isr_usart2
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/* UART 0 pin configuration */
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#define UART_0_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
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#define UART_0_PORT GPIOA
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#define UART_0_TX_PIN 2
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#define UART_0_RX_PIN 3
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#define UART_0_AF 7
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/* UART 1 device configuration */
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#define UART_1_DEV USART1
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#define UART_1_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_USART1EN)
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#define UART_1_CLKDIS() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
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#define UART_1_CLK (84000000) /* UART clock runs with 84MHz (F_CPU / 2) */
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#define UART_1_IRQ_CHAN USART1_IRQn
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#define UART_1_ISR isr_usart1
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/* UART 1 pin configuration */
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#define UART_1_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
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#define UART_1_PORT GPIOA
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#define UART_1_TX_PIN 9
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#define UART_1_RX_PIN 10
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#define UART_1_AF 7
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/* UART 2 device configuration */
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#define UART_2_DEV USART3
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#define UART_2_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART3EN)
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#define UART_2_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
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#define UART_2_CLK (42000000) /* UART clock runs with 42MHz (F_CPU / 4) */
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#define UART_2_IRQ_CHAN USART3_IRQn
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#define UART_2_ISR isr_usart3
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/* UART 2 pin configuration */
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#define UART_2_PORT_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN)
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#define UART_2_PORT GPIOD
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#define UART_2_TX_PIN 8
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#define UART_2_RX_PIN 9
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#define UART_2_AF 7
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/** @} */
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/**
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* @name GPIO configuration
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* @{
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*/
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#define GPIO_NUMOF 16
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#define GPIO_0_EN 1
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#define GPIO_1_EN 1
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#define GPIO_2_EN 1
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#define GPIO_3_EN 1
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#define GPIO_4_EN 1
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#define GPIO_5_EN 1
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#define GPIO_6_EN 1
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#define GPIO_7_EN 1
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#define GPIO_8_EN 1
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#define GPIO_9_EN 1
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#define GPIO_10_EN 1
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#define GPIO_11_EN 1
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#define GPIO_12_EN 1
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#define GPIO_13_EN 1
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#define GPIO_14_EN 1
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#define GPIO_15_EN 1
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#define GPIO_IRQ_PRIO 1
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/* IRQ config */
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#define GPIO_IRQ_0 GPIO_0 /* alternatively GPIO_4 or GPIO_9 could be used here */
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#define GPIO_IRQ_1 GPIO_1 /* alternatively GPIO_10 could be used here */
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#define GPIO_IRQ_2 GPIO_15
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#define GPIO_IRQ_3 -1/* not configured */
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#define GPIO_IRQ_4 GPIO_2 /* alternatively GPIO_11 could be used here */
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#define GPIO_IRQ_5 GPIO_12
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#define GPIO_IRQ_6 -1/* not configured */
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#define GPIO_IRQ_7 -1/* not configured */
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#define GPIO_IRQ_8 GPIO_13
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#define GPIO_IRQ_9 GPIO_5
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#define GPIO_IRQ_10 GPIO_3
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#define GPIO_IRQ_11 GPIO_6
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#define GPIO_IRQ_12 GPIO_7
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#define GPIO_IRQ_13 GPIO_8 /* alternatively GPIO_14 could be used here */
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#define GPIO_IRQ_14 -1/* not configured */
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#define GPIO_IRQ_15 -1/* not configured */
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/* GPIO channel 0 config */
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#define GPIO_0_PORT GPIOA /* User Button 2 */
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#define GPIO_0_PIN 0
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#define GPIO_0_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
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#define GPIO_0_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PA)
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#define GPIO_0_IRQ EXTI0_IRQn
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/* GPIO channel 1 config */
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#define GPIO_1_PORT GPIOA
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#define GPIO_1_PIN 1
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#define GPIO_1_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
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#define GPIO_1_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI1_PA)
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#define GPIO_1_IRQ EXTI1_IRQn
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/* GPIO channel 2 config */
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#define GPIO_2_PORT GPIOA
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#define GPIO_2_PIN 4
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#define GPIO_2_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
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#define GPIO_2_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI4_PA)
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#define GPIO_2_IRQ EXTI4_IRQn
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/* GPIO channel 3 config */
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#define GPIO_3_PORT GPIOA /* CC3000 SPI_IRQ */
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#define GPIO_3_PIN 10
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#define GPIO_3_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN)
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#define GPIO_3_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI10_PA)
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#define GPIO_3_IRQ EXTI15_10_IRQn
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/* GPIO channel 4 config */
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#define GPIO_4_PORT GPIOB
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#define GPIO_4_PIN 0
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#define GPIO_4_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
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#define GPIO_4_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PB)
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#define GPIO_4_IRQ EXTI0_IRQn
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/* GPIO channel 5 config */
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#define GPIO_5_PORT GPIOB /* BEEPER Input */
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#define GPIO_5_PIN 9
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#define GPIO_5_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
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#define GPIO_5_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI9_PB)
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#define GPIO_5_IRQ EXTI9_5_IRQn
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/* GPIO channel 6 config */
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#define GPIO_6_PORT GPIOB /* IMU-9150 INT */
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#define GPIO_6_PIN 11
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#define GPIO_6_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
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#define GPIO_6_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI11_PB)
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#define GPIO_6_IRQ EXTI15_10_IRQn
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/* GPIO channel 7 config */
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#define GPIO_7_PORT GPIOB /* CC1101 CS */
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#define GPIO_7_PIN 12
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#define GPIO_7_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
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#define GPIO_7_EXTI_CFG() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI12_PB)
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#define GPIO_7_IRQ EXTI15_10_IRQn
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/* GPIO channel 8 config */
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#define GPIO_8_PORT GPIOB /* User Button 1 */
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#define GPIO_8_PIN 13
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#define GPIO_8_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
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#define GPIO_8_EXTI_CFG() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI13_PB)
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#define GPIO_8_IRQ EXTI15_10_IRQn
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/* GPIO channel 9 config */
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#define GPIO_9_PORT GPIOC /* TCA6416 Reset */
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#define GPIO_9_PIN 0
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#define GPIO_9_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN)
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#define GPIO_9_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PC)
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#define GPIO_9_IRQ EXTI0_IRQn
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/* GPIO channel 10 config */
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#define GPIO_10_PORT GPIOC /* CC3000 CS */
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#define GPIO_10_PIN 1
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#define GPIO_10_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN)
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#define GPIO_10_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI1_PC)
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#define GPIO_10_IRQ EXTI1_IRQn
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/* GPIO channel 11 config */
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#define GPIO_11_PORT GPIOC /* CC1101 GDO 0 */
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#define GPIO_11_PIN 4
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#define GPIO_11_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN)
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#define GPIO_11_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI4_PC)
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#define GPIO_11_IRQ EXTI4_IRQn
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/* GPIO channel 12 config */
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#define GPIO_12_PORT GPIOC /* CC1101 GDO 2 */
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#define GPIO_12_PIN 5
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#define GPIO_12_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN)
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#define GPIO_12_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI5_PC)
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#define GPIO_12_IRQ EXTI9_5_IRQn
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/* GPIO channel 13 config */
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#define GPIO_13_PORT GPIOC /* TCA6416 INT */
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#define GPIO_13_PIN 8
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#define GPIO_13_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN)
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#define GPIO_13_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI8_PC)
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#define GPIO_13_IRQ EXTI9_5_IRQn
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/* GPIO channel 14 config */
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#define GPIO_14_PORT GPIOC /* CC3000 VBAT_SW_EN */
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#define GPIO_14_PIN 13
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#define GPIO_14_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN)
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#define GPIO_14_EXTI_CFG() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI13_PC)
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#define GPIO_14_IRQ EXTI15_10_IRQn
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/* GPIO channel 15 config */
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#define GPIO_15_PORT GPIOD /* Micro SD Sockel CS */
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#define GPIO_15_PIN 2
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#define GPIO_15_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN)
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#define GPIO_15_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI2_PD)
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#define GPIO_15_IRQ EXTI2_IRQn
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/** @} */
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#endif /* __PERIPH_CONF_H */
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/** @} */
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