2019-09-02 08:12:05 +02:00
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/*
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* Copyright (C) 2019 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_common_stm32
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* @{
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*
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* @file
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* @brief Common configuration for STM32 I2C
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef CFG_I2C1_PB6_PB7_H
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#define CFG_I2C1_PB6_PB7_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name I2C configuration
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* @{
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*/
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static const i2c_conf_t i2c_config[] = {
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{
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.dev = I2C1,
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.speed = I2C_SPEED_NORMAL,
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.scl_pin = GPIO_PIN(PORT_B, 6),
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.sda_pin = GPIO_PIN(PORT_B, 7),
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#if CPU_FAM_STM32L4
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.scl_af = GPIO_AF4,
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.sda_af = GPIO_AF4,
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#else /* CPU_FAM_STM32L0 */
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.scl_af = GPIO_AF1,
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.sda_af = GPIO_AF1,
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#endif
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.bus = APB1,
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#if CPU_FAM_STM32L4
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.rcc_mask = RCC_APB1ENR1_I2C1EN,
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2021-12-02 14:56:01 +01:00
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.rcc_sw_mask = RCC_CCIPR_I2C1SEL_1, /* HSI (16 MHz) */
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2019-09-02 08:12:05 +02:00
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.irqn = I2C1_ER_IRQn,
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#else /* CPU_FAM_STM32L0 */
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.rcc_mask = RCC_APB1ENR_I2C1EN,
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.irqn = I2C1_IRQn
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#endif
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}
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};
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#if CPU_FAM_STM32L4
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#define I2C_0_ISR isr_i2c1_er
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#else /* CPU_FAM_STM32L0 */
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#define I2C_0_ISR isr_i2c1
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#endif
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#define I2C_NUMOF ARRAY_SIZE(i2c_config)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* CFG_I2C1_PB6_PB7_H */
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/** @} */
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