RIOT/cpu/riscv_common/ldscripts/riscv.ld

/*
 * Copyright (C) 2017, 2019   Ken Rabold
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */

/**
 * @addtogroup         cpu_riscv_common
 * @{
 *
 * @file
 * @brief           Memory definitions for the RISC-V CPU
 *
 * @author          Ken Rabold
 * @author          Koen Zandberg <koen@bergzand.net>
 *
 * @}
 */
INCLUDE riscv_vars.ld

MEMORY
{
  flash (rxai!w) : ORIGIN = _rom_start_addr, LENGTH = _rom_length
  ram   (wxa!ri) : ORIGIN = _ram_start_addr, LENGTH = _ram_length
  itim  (wxa!ri) : ORIGIN = _itim_start_addr, LENGTH = _itim_length
}

INCLUDE riscv_base.ld
cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools 2018-04-16 19:03:33 +02:00			`/*`
cpu/fe310: Add support for FE310_G002 Added support for FE310_G002 CPU variant that is on new HiFive1B board 2019-06-25 19:13:15 +02:00			`* Copyright (C) 2017, 2019 Ken Rabold`
cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools 2018-04-16 19:03:33 +02:00			`*`
			`* This file is subject to the terms and conditions of the GNU Lesser`
			`* General Public License v2.1. See the file LICENSE in the top level`
			`* directory for more details.`
			`*/`

			`/**`
riscv_common: Refactor common fe310 code to riscv_common 2020-09-09 21:37:15 +02:00			`* @addtogroup cpu_riscv_common`
cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools 2018-04-16 19:03:33 +02:00			`* @{`
			`*`
			`* @file`
riscv_common: Refactor common fe310 code to riscv_common 2020-09-09 21:37:15 +02:00			`* @brief Memory definitions for the RISC-V CPU`
cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools 2018-04-16 19:03:33 +02:00			`*`
			`* @author Ken Rabold`
fe310: Unify linker scripts Similar to the cortex-m common linker scripts, the RISC-V linker scripts can be unified easily, requiring only the memory addresses and lengths. This simplifies adding new RISC-V CPU's later 2020-09-01 10:08:59 +02:00			`* @author Koen Zandberg <koen@bergzand.net>`
cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools 2018-04-16 19:03:33 +02:00			`*`
			`* @}`
			`*/`
riscv_common: Refactor common fe310 code to riscv_common 2020-09-09 21:37:15 +02:00			`INCLUDE riscv_vars.ld`
cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools 2018-04-16 19:03:33 +02:00
			`MEMORY`
			`{`
riscv_common: Refactor common fe310 code to riscv_common 2020-09-09 21:37:15 +02:00			`flash (rxai!w) : ORIGIN = _rom_start_addr, LENGTH = _rom_length`
fe310: Unify linker scripts Similar to the cortex-m common linker scripts, the RISC-V linker scripts can be unified easily, requiring only the memory addresses and lengths. This simplifies adding new RISC-V CPU's later 2020-09-01 10:08:59 +02:00			`ram (wxa!ri) : ORIGIN = _ram_start_addr, LENGTH = _ram_length`
			`itim (wxa!ri) : ORIGIN = _itim_start_addr, LENGTH = _itim_length`
cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools 2018-04-16 19:03:33 +02:00			`}`

riscv_common: Refactor common fe310 code to riscv_common 2020-09-09 21:37:15 +02:00			`INCLUDE riscv_base.ld`