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https://github.com/RIOT-OS/RIOT.git
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78 lines
1.6 KiB
C
78 lines
1.6 KiB
C
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/*
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* Copyright (C) 2017 Eistec AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_kinetis_common
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* @{
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*
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* @file
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* @brief CPU specific definitions common to all Kinetis CPUs
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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*/
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#ifndef CPU_CONF_KINETIS_H
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#define CPU_CONF_KINETIS_H
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#include "cpu_conf_common.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* @name ARM Cortex-M specific CPU configuration
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* @{
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*/
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#define CPU_DEFAULT_IRQ_PRIO (1U)
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/* Each interrupt priority setting is 8 bits wide, for both CM4 and CM0+, but
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* they are laid out differently. CM0+ concatenates the settings into 32 bit
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* words, CM4 and CM7 uses direct 8 bit access */
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#define CPU_IRQ_NUMOF (sizeof(NVIC->IP))
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#define CPU_FLASH_BASE (0x00000000)
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/** @} */
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/**
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* @name GPIO pin mux function numbers
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* @{
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*/
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#define PIN_MUX_FUNCTION_ANALOG 0
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#define PIN_MUX_FUNCTION_GPIO 1
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/** @} */
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/**
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* @name GPIO interrupt flank settings
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* @{
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*/
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#define PIN_INTERRUPT_RISING 0b1001
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#define PIN_INTERRUPT_FALLING 0b1010
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#define PIN_INTERRUPT_EDGE 0b1011
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/** @} */
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/**
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* @name Timer hardware information
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* @{
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*/
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#ifdef SIM_SCGC5_LPTMR_SHIFT
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/** Enable LPTMR clock gate */
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#define LPTMR_CLKEN() (bit_set32(&SIM->SCGC5, SIM_SCGC5_LPTMR_SHIFT))
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#endif
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#ifdef SIM_SCGC6_PIT_SHIFT
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/** Enable PIT clock gate */
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#define PIT_CLKEN() (bit_set32(&SIM->SCGC6, SIM_SCGC6_PIT_SHIFT))
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#endif
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* CPU_CONF_KINETIS_H */
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/** @} */
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