2021-02-11 15:00:04 +01:00
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PROGRAMMERS_SUPPORTED += jlink openocd
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2020-07-02 09:14:35 +02:00
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2023-01-08 19:48:24 +01:00
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# OpenOCD parameters
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OPENOCD_DEBUG_ADAPTER := jlink
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OPENOCD_TRANSPORT := jtag
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OPENOCD_PRE_FLASH_CMDS += "-c flash protect 0 1 last off"
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# setup JLink for flashing
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JLINK_DEVICE := FE310
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JLINK_IF := JTAG
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FLASH_ADDR := 0x20010000
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# keep name of `JLINK` in sync with script jlink.sh in $(RIOTTOOLS)/jlink
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# Default to J-Link as programmer when installed, otherwise go for OpenOCD
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JLINK ?= JLinkExe
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ifneq (,$(shell command -v $(JLINK)))
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PROGRAMMER ?= jlink
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else
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PROGRAMMER ?= openocd
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2020-07-02 09:14:35 +02:00
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endif
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2020-01-10 08:34:45 +01:00
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2023-01-08 19:55:38 +01:00
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# If port selection via ttys.py is enabled by `MOST_RECENT_PORT=1`, filter
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# USB serials to only select the first UART bridge of integrated J-Link
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# debugger (that identifies as "HiFive" as model). Use --iface-num 2 to select
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# the UART bridge to the ESP32-SOLO-1 MCU instead of the FE310 MCU on the board.
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TTY_BOARD_FILTER := --model HiFive --iface-num 0
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2023-01-10 09:37:29 +01:00
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# The TTY serial also is the ID of the debug adapter, as the TTY is provided by
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# the debug adapter
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DEBUG_ADAPTER_ID_IS_TTY_SERIAL := 1
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2020-01-10 08:34:45 +01:00
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TESTRUNNER_RESET_DELAY = 1
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$(call target-export-variables,test,TESTRUNNER_RESET_DELAY)
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