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https://github.com/RIOT-OS/RIOT.git
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70 lines
1.6 KiB
C
70 lines
1.6 KiB
C
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/*
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* Copyright (C) 2015 Eistec AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_k60
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* @{
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*
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* @file
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* @brief Compatibility definitions between MK60D10.h and MK60DZ10.h
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*
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* @author Joakim Gebart <joakim.gebart@eistec.se>
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*/
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#ifndef MK60_COMP_H_
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#define MK60_COMP_H_
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#if K60_CPU_REV == 1
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/* Some compatibility defines to minimize the ifdefs needed for the register
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* name changes */
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#define SIM_SCGC6_SPI0_MASK SIM_SCGC6_DSPI0_MASK
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#define SIM_SCGC6_SPI0_SHIFT SIM_SCGC6_DSPI0_SHIFT
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#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
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#define MCG_C5_PRDIV0_MASK MCG_C5_PRDIV_MASK
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#define MCG_C6_VDIV0_MASK MCG_C6_VDIV_MASK
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#define UART_BASES { UART0, UART1, UART2, UART3, UART4, UART5 }
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#define LPTMR0_IRQn LPTimer_IRQn
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/* Rev 2.x made the OSC32KSEL field into a bitfield (is a single bit in 1.x) */
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#define SIM_SOPT1_OSC32KSEL(a) (SIM_SOPT1_OSC32KSEL_MASK)
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#endif /* K60_CPU_REV == 1 */
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/* Compatibility defines for compatibility with differing module names between
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* MK60 and MKW22 headers */
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#define SIM_SCGC5_LPTMR_MASK SIM_SCGC5_LPTIMER_MASK
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#define SIM_SCGC5_LPTMR_SHIFT SIM_SCGC5_LPTIMER_SHIFT
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#ifndef OSC0
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/* Compatibility definition */
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#define OSC0 OSC
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#endif
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#ifndef MCG_C2_RANGE0
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/* Rev 2 parts renamed the parameter RANGE -> RANGE0 */
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#define MCG_C2_RANGE0 MCG_C2_RANGE
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* MK60_COMP_H_ */
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/** @} */
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