2021-03-30 14:14:37 +02:00
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# Copyright (c) 2021 Inria
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2021-07-07 13:41:56 +02:00
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# Copyright (c) 2021 Freie Universitaet Berlin
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2021-03-30 14:14:37 +02:00
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#
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# This file is subject to the terms and conditions of the GNU Lesser
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# General Public License v2.1. See the file LICENSE in the top level
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# directory for more details.
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#
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config CPU_FAM_WL
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bool
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select CPU_STM32
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select CPU_CORE_CORTEX_M4
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select HAS_CPU_STM32WL
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select HAS_PERIPH_FLASHPAGE
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2022-03-17 19:45:54 +01:00
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select HAS_PERIPH_FLASHPAGE_IN_ADDRESS_SPACE
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select HAS_PERIPH_FLASHPAGE_PAGEWISE
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2021-08-27 22:59:43 +02:00
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select HAS_PERIPH_GPIO_LL
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select HAS_PERIPH_GPIO_LL_IRQ
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select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_HIGH
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select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_LOW
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select HAS_PERIPH_RTC_MEM
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2021-10-12 13:16:57 +02:00
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select HAS_PERIPH_VBAT
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select HAS_PERIPH_WDT
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select HAS_BOOTLOADER_STM32
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config CPU_FAM
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default "wl" if CPU_FAM_WL
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config HAS_CPU_STM32WL
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bool
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help
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Indicates that the cpu being used belongs to the 'stm32wl' family.
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2021-07-07 13:41:56 +02:00
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config STM32_WL55JC_SUBGHZ_DEBUG
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bool "STM32WL->Enable Hardware Debugging"
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help
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Enable Hardware debug pins. This would affect onboard peripherals such as SPI
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as the pins are multiplexed. For more information check Alternate Functions
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column in Table 19 : STM32WL55/54xx pin definition in STM32WL55/54xx
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datasheet.
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