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69 lines
1.6 KiB
C
69 lines
1.6 KiB
C
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/*
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* Copyright (C) 2020 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_common_stm32
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* @{
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*
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* @file
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* @brief Default clock configuration for STM32F0
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author José Ignacio Alamos <jialamos@uc.cl>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef F0_CFG_CLOCK_DEFAULT_H
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#define F0_CFG_CLOCK_DEFAULT_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock settings
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* @{
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*/
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/* give the target core clock (HCLK) frequency [in Hz],
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* maximum: 48MHz */
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#define CLOCK_CORECLOCK MHZ(48)
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#ifndef CLOCK_HSE
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#define CLOCK_HSE MHZ(8)
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#endif
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#ifndef CLOCK_LSE
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#define CLOCK_LSE (0)
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#endif
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB2 (CLOCK_APB1)
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/* PLL factors */
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#ifndef CLOCK_PLL_PREDIV
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#define CLOCK_PLL_PREDIV (1)
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#endif
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#ifndef CLOCK_PLL_MUL
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#define CLOCK_PLL_MUL (6)
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#endif
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* F0_CFG_CLOCK_DEFAULT_H */
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/** @} */
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