RIOT/cpu/fe310/Makefile.dep

ifneq (,$(filter picolibc,$(FEATURES_USED)))
  USEMODULE += picolibc
else
  USEMODULE += newlib_nano
  USEMODULE += newlib_syscalls_fe310
endif

USEMODULE += sifive_drivers_fe310

USEMODULE += periph
USEMODULE += periph_pm

FEATURES_REQUIRED += periph_plic

ifneq (,$(filter periph_rtc,$(USEMODULE)))
  FEATURES_REQUIRED += periph_rtt
endif
picolibc: model as a feature 2020-09-11 14:23:25 +02:00			`ifneq (,$(filter picolibc,$(FEATURES_USED)))`
cpu/fe310: Add PICOLIBC support [v3] Disable the newlib-nano stubs code when picolibc is in use Signed-off-by: Keith Packard <keithp@keithp.com> --- v2: Squash fixes in v3: call stdio_init in _PICOLIBC_ mode to initialize uart v3: Remove call to stdio_init from nanostubs_init, always call from cpu_init. 2020-07-02 08:28:14 +02:00			`USEMODULE += picolibc`
			`else`
			`USEMODULE += newlib_nano`
			`USEMODULE += newlib_syscalls_fe310`
			`endif`
cpu/fe310: move dependencies to Makefile.dep 2019-12-07 17:12:48 +01:00
			`USEMODULE += sifive_drivers_fe310`

			`USEMODULE += periph`
			`USEMODULE += periph_pm`

fe310: Adapt peripherals to use the plic driver 2020-08-28 20:35:37 +02:00			`FEATURES_REQUIRED += periph_plic`

cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools 2018-04-16 19:03:33 +02:00			`ifneq (,$(filter periph_rtc,$(USEMODULE)))`
cpu/fe310: rtc depend on the rtt feature It is the role of boards based on 'cpu/fe310' to give the configuration for the rtc/rtt. The fe310/periph/rtc implementation depends on having periph/rtt configured by the board so depends on the board 'providing' the periph_rtt feature and declaring the required macros. It should not simply depend of the 'periph_rtt' module as this does not enforce having a configuration for the module in the board. In practice, when compiling, it would result in undefined 'RTT' symbols, instead of the build system detecting it. 2018-09-26 19:32:55 +02:00			`FEATURES_REQUIRED += periph_rtt`
cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools 2018-04-16 19:03:33 +02:00			`endif`