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98 lines
2.1 KiB
C
98 lines
2.1 KiB
C
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/*
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* Copyright (C) 2020 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup pkg_uwb_core
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* @{
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*
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* @file
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* @brief uwb-core DPL (Decawave Porting Layer) error types
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*
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* @author Francisco Molina <francois-xavier.molina@inria.fr>
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* @}
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*/
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#ifndef DPL_DPL_OS_H
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#define DPL_DPL_OS_H
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#include <assert.h>
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#include <stdint.h>
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#include <stdatomic.h>
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#include "irq.h"
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#include "dpl/dpl_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Entering and exiting critical section defines
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* @{
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*/
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#define DPL_ENTER_CRITICAL(_sr) (_sr = dpl_hw_enter_critical())
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#define DPL_EXIT_CRITICAL(_sr) (dpl_hw_exit_critical(_sr))
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#define DPL_ASSERT_CRITICAL() assert(dpl_hw_is_in_critical())
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/** @} */
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/**
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* @brief variable to check if ISR are disabled
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*/
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extern atomic_uint dpl_in_critical;
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/**
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* @brief CPU status register
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*/
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typedef uint32_t dpl_sr_t;
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/**
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* @brief Disable ISRs
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*
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* @return current isr context
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*/
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static inline uint32_t dpl_hw_enter_critical(void)
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{
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uint32_t ctx = irq_disable();
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unsigned int count = atomic_load(&dpl_in_critical);
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atomic_store(&dpl_in_critical, count + 1);
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return ctx;
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}
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/**
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* @brief Restores ISR context
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*
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* @param[in] ctx ISR context to restore.
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*/
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static inline void dpl_hw_exit_critical(uint32_t ctx)
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{
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unsigned int count = atomic_load(&dpl_in_critical);
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atomic_store(&dpl_in_critical, count - 1);
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irq_restore((unsigned)ctx);
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}
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/**
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* @brief Check if is in critical section
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*
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* @return true, if in critical section, false otherwise
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*/
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static inline bool dpl_hw_is_in_critical(void)
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{
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/*
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* XXX Currently RIOT does not support an API for finding out if interrupts
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* are currently disabled, hence in a critical section in this context.
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* So for now, we use this global variable to keep this state for us.
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*/
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return (atomic_load(&dpl_in_critical) > 0);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* DPL_DPL_OS_H */
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