2020-05-23 17:26:54 +02:00
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/*
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* Copyright (C) 2020 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief STM3G4 CPU specific definitions for internal peripheral handling
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*
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*/
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#ifndef PERIPH_G4_PERIPH_CPU_H
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#define PERIPH_G4_PERIPH_CPU_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef DOXYGEN
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/**
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* @brief Starting address of the ROM bootloader
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* see application note AN2606
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*/
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#define STM32_BOOTLOADER_ADDR (0x1FFF0000)
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2021-10-12 13:16:57 +02:00
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/**
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* @name Constants for internal VBAT ADC line
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* @{
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*/
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#define VBAT_ADC_RES ADC_RES_12BIT
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#define VBAT_ADC_MAX 4095
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/** @} */
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2020-05-23 17:26:54 +02:00
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#endif /* ndef DOXYGEN */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_G4_PERIPH_CPU_H */
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/** @} */
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