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RIOT/cpu/fe310/include/cpu_conf.h

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cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools
2018-04-16 19:03:33 +02:00
/*
* Copyright (C) 2017 Ken Rabold
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
make: add hifive1 to BOARD_INSUFFICIENT_MEMORY Added HiFive1 to BOARD_INSUFFICIENT_MEMORY list for examples and tests that are too big to fit build: fixed missing syscall and cpuid failures Added missing syscall stubs for nanostubs and fixed compile error with cpuid periph build: fixed whitespace error build: add hifive1 to more BOARD_INSUFFICIENT_MEMORY doc: fixed doxygen warnings Addressed Doxygen warnings in source file comments doc: more doxygen fixes doc: even more doxygen fixes doc: more changes build: fix pedantic and rdci_simple build failures make: exclude lua
2018-04-16 22:35:32 +02:00
* @ingroup cpu_fe310
cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools
2018-04-16 19:03:33 +02:00
* @{
*
* @file
* @brief CPU specific configuration options
*
* @author Ken Rabold
*/
#ifndef CPU_CONF_H
#define CPU_CONF_H
riscv_common: Refactor common fe310 code to riscv_common
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#include "cpu_conf_common.h"
#include "vendor/platform.h"
#ifdef __cplusplus
extern "C" {
cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools
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#endif
cpu/fe310: changes for common heap command
2019-02-05 16:59:36 +01:00
/**
riscv_common: Refactor common fe310 code to riscv_common
2020-09-09 21:37:15 +02:00
* @brief Base address of the CLINT
cpu/fe310: changes for common heap command
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*/
riscv_common: Refactor common fe310 code to riscv_common
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#define CLINT_BASE_ADDR (CLINT_CTRL_ADDR)
cpu/fe310: changes for common heap command
2019-02-05 16:59:36 +01:00
cpu/fe310: migrate to inlined irq API Co-authored-by: Marian Buschsieweke <marian.buschsieweke@ovgu.de>
2020-06-25 16:51:18 +02:00
/**
riscv_common: Refactor common fe310 code to riscv_common
2020-09-09 21:37:15 +02:00
* @brief Base address of the PLIC peripheral
cpu/fe310: migrate to inlined irq API Co-authored-by: Marian Buschsieweke <marian.buschsieweke@ovgu.de>
2020-06-25 16:51:18 +02:00
*/
riscv_common: Refactor common fe310 code to riscv_common
2020-09-09 21:37:15 +02:00
#define PLIC_BASE_ADDR (PLIC_CTRL_ADDR)
cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools
2018-04-16 19:03:33 +02:00
cpu/riscv: Add PMP driver
2023-06-06 17:30:51 +02:00
/**
* @brief Number of available PMP regions
* Note, the upper 8 regions are hardwired to zero!
*/
#define NUM_PMP_ENTRIES 16
cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools
2018-04-16 19:03:33 +02:00
#ifdef __cplusplus
}
#endif
#endif /* CPU_CONF_H */
/** @} */
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