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RIOT/cpu/gd32v/Makefile.features

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cpu/riscv,gd32v: add CPU_ARCH, CPU_CORE information adds CPU_ARCH to riscv_common preparing to handle it like cortex-m does adds CPU_CORE to gd32v
2021-09-22 13:02:19 +02:00
CPU_CORE := rv32imac
cpu/gd32v: use NMSIS SDK package
2023-01-21 16:06:53 +01:00
FEATURES_PROVIDED += arch_nuclei
cpu/gd32v: Initial include of the GD32VF103 device This adds support for the gd32v class devices from Gigadevice. The gd32vf103 contains an 108 MHz RISC-V core with similar peripherals as the stm32f1 devices Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
2021-02-17 13:47:50 +01:00
FEATURES_PROVIDED += periph_clic
FEATURES_PROVIDED += periph_gpio
cpu/gd32v: add periph_gpio_irq support
2023-01-23 22:51:26 +01:00
FEATURES_PROVIDED += periph_gpio_irq
cpu/gd32v: add gpio_ll support
2023-02-04 11:29:09 +01:00
FEATURES_PROVIDED += periph_gpio_ll
drivers/periph_gpio_ll: Add features for compile-time-checks This adds the features - periph_gpio_ll_input_pull_down: To indicate support for input mode with internal pull down - periph_gpio_ll_input_pull_keep: To indicate support for input mode with internal resistor pulling towards current level - periph_gpio_ll_input_pull_up: To indicate support for input mode with internal pull up - periph_gpio_ll_disconnect: To indicate a GPIO can be disconnected - periph_gpio_ll_open_drain: To indicate support for open drain mode - periph_gpio_ll_open_drain_pull_up: To indicate support for open drain mode with internal pull up - periph_gpio_ll_open_source: To indicate support for open source mode - periph_gpio_ll_open_source_pull_down: To indicate support for open source mode with internal pull down
2024-01-23 09:05:13 +01:00
FEATURES_PROVIDED += periph_gpio_ll_disconnect
FEATURES_PROVIDED += periph_gpio_ll_input_pull_down
FEATURES_PROVIDED += periph_gpio_ll_input_pull_up
cpu/gd32v: add perip_gpio_ll_irq support
2023-02-07 12:19:42 +01:00
FEATURES_PROVIDED += periph_gpio_ll_irq
drivers/periph_gpio_ll_irq: make support for both edges optional The assumption that every MCU has this feature turned out wrong. Hence, add a feature to allow testing for support of edge triggered IRQs on both flanks.
2024-05-20 10:39:10 +02:00
FEATURES_PROVIDED += periph_gpio_ll_irq_edge_triggered_both
cpu/gd32v: add perip_gpio_ll_irq support
2023-02-07 12:19:42 +01:00
FEATURES_PROVIDED += periph_gpio_ll_irq_level_triggered_high
FEATURES_PROVIDED += periph_gpio_ll_irq_level_triggered_low
drivers/periph_gpio_ll: Add features for compile-time-checks This adds the features - periph_gpio_ll_input_pull_down: To indicate support for input mode with internal pull down - periph_gpio_ll_input_pull_keep: To indicate support for input mode with internal resistor pulling towards current level - periph_gpio_ll_input_pull_up: To indicate support for input mode with internal pull up - periph_gpio_ll_disconnect: To indicate a GPIO can be disconnected - periph_gpio_ll_open_drain: To indicate support for open drain mode - periph_gpio_ll_open_drain_pull_up: To indicate support for open drain mode with internal pull up - periph_gpio_ll_open_source: To indicate support for open source mode - periph_gpio_ll_open_source_pull_down: To indicate support for open source mode with internal pull down
2024-01-23 09:05:13 +01:00
FEATURES_PROVIDED += periph_gpio_ll_open_drain
cpu/gd32v: add periph_rtc support
2023-01-22 17:53:44 +01:00
FEATURES_PROVIDED += periph_rtc
cpu/gd32v: add periph_rtc_mem support
2023-02-06 22:22:01 +01:00
FEATURES_PROVIDED += periph_rtc_mem
cpu/gd32v: add periph_rtt support
2023-01-24 00:31:52 +01:00
FEATURES_PROVIDED += periph_rtt
cpu/gd32v: Initial include of the GD32VF103 device This adds support for the gd32v class devices from Gigadevice. The gd32vf103 contains an 108 MHz RISC-V core with similar peripherals as the stm32f1 devices Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
2021-02-17 13:47:50 +01:00
FEATURES_PROVIDED += periph_timer
cpu/gd32v: enable periph_timer_periodic
2021-08-25 10:48:48 +02:00
FEATURES_PROVIDED += periph_timer_periodic
cpu/gd32v: Initial include of the GD32VF103 device This adds support for the gd32v class devices from Gigadevice. The gd32vf103 contains an 108 MHz RISC-V core with similar peripherals as the stm32f1 devices Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
2021-02-17 13:47:50 +01:00
FEATURES_PROVIDED += periph_wdt
FEATURES_PROVIDED += periph_pm
FEATURES_PROVIDED += periph_flashpage
periph/flashpage: Add _in_address_space feature
2022-03-17 19:45:54 +01:00
FEATURES_PROVIDED += periph_flashpage_in_address_space
cpu/gd32v: Initial include of the GD32VF103 device This adds support for the gd32v class devices from Gigadevice. The gd32vf103 contains an 108 MHz RISC-V core with similar peripherals as the stm32f1 devices Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
2021-02-17 13:47:50 +01:00
FEATURES_PROVIDED += periph_flashpage_pagewise
include $(RIOTCPU)/riscv_common/Makefile.features
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