RIOT/boards/hifive1/Makefile.features

CPU = fe310
CPU_MODEL = fe310_g000

# Put defined MCU peripherals here (in alphabetical order)
#FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
boards/hifive1*: move CPU/CPU_MODEL definition to Makefile.features cpu/$(CPU)/Makefile.features and cpu/$(CPU)/Makefile.dep are automatically included Part of moving CPU/CPU_MODEL definition to Makefile.features to have it available before Makefile.include. 2019-06-03 11:08:02 +02:00			`CPU = fe310`
			`CPU_MODEL = fe310_g000`

board/hifive1: add RISC-V board HiFive1 Add new RISC-V board HiFive1 from SiFive based on FE310 CPU 2018-04-16 19:07:04 +02:00			`# Put defined MCU peripherals here (in alphabetical order)`
make: add hifive1 to BOARD_INSUFFICIENT_MEMORY Added HiFive1 to BOARD_INSUFFICIENT_MEMORY list for examples and tests that are too big to fit build: fixed missing syscall and cpuid failures Added missing syscall stubs for nanostubs and fixed compile error with cpuid periph build: fixed whitespace error build: add hifive1 to more BOARD_INSUFFICIENT_MEMORY doc: fixed doxygen warnings Addressed Doxygen warnings in source file comments doc: more doxygen fixes doc: even more doxygen fixes doc: more changes build: fix pedantic and rdci_simple build failures make: exclude lua 2018-04-16 22:35:32 +02:00			`#FEATURES_PROVIDED += periph_pwm`
board/hifive1: add RISC-V board HiFive1 Add new RISC-V board HiFive1 from SiFive based on FE310 CPU 2018-04-16 19:07:04 +02:00			`FEATURES_PROVIDED += periph_rtc`
			`FEATURES_PROVIDED += periph_rtt`
boards/hifive1*: provide and configure SPI feature 2019-12-16 10:25:55 +01:00			`FEATURES_PROVIDED += periph_spi`
board/hifive1: add RISC-V board HiFive1 Add new RISC-V board HiFive1 from SiFive based on FE310 CPU 2018-04-16 19:07:04 +02:00			`FEATURES_PROVIDED += periph_timer`
			`FEATURES_PROVIDED += periph_uart`