2014-11-20 17:54:02 +01:00
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/*
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* Copyright (C) 2014 INRIA
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2015-08-26 18:46:57 +02:00
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* 2015 Freie Universität Berlin
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2014-11-20 17:54:02 +01:00
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup boards_z1
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* @{
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*
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* @file
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* @brief Zolertia Z1 peripheral configuration
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*
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* @author Oliver Hahm <oliver.hahm@inria.fr>
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2015-08-26 18:46:57 +02:00
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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2014-11-20 17:54:02 +01:00
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*/
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2015-08-26 18:46:57 +02:00
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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2014-11-20 17:54:02 +01:00
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2015-08-26 18:46:57 +02:00
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#ifdef __cplusplus
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extern "C" {
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#endif
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2014-11-25 15:37:21 +01:00
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2015-08-27 14:20:53 +02:00
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/**
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2017-04-10 19:04:32 +02:00
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* @name Clock configuration
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* @{
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2015-08-27 14:20:53 +02:00
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*/
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2017-04-10 19:04:32 +02:00
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/** @todo Move all clock configuration code here from the board.h */
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2015-08-27 14:20:53 +02:00
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#define CLOCK_CORECLOCK (8000000U)
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#define CLOCK_CMCLK CLOCK_CORECLOCK /* no divider programmed */
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/** @} */
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2015-08-26 18:46:57 +02:00
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/**
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2017-04-10 19:04:32 +02:00
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* @name Timer configuration
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2015-08-26 18:46:57 +02:00
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* @{
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*/
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2015-09-04 14:39:35 +02:00
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#define TIMER_NUMOF (1U)
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#define TIMER_BASE (TIMER_A)
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2015-08-26 18:46:57 +02:00
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#define TIMER_CHAN (3)
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#define TIMER_ISR_CC0 (TIMERA0_VECTOR)
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#define TIMER_ISR_CCX (TIMERA1_VECTOR)
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/** @} */
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2015-08-27 14:20:53 +02:00
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/**
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2017-04-10 19:04:32 +02:00
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* @name UART configuration
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2015-08-27 14:20:53 +02:00
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* @{
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*/
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#define UART_NUMOF (1U)
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#define UART_0_EN (1U)
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2016-03-24 09:42:59 +01:00
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#define UART_USE_USCI
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2015-10-20 16:30:11 +02:00
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#define UART_BASE (USCI_0)
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2015-08-27 14:20:53 +02:00
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#define UART_IE (SFR->IE2)
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#define UART_IF (SFR->IFG2)
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#define UART_IE_RX_BIT (1 << 0)
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#define UART_IE_TX_BIT (1 << 1)
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2016-03-30 03:17:33 +02:00
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#define UART_RX_PORT ((msp_port_t *)PORT_3)
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#define UART_RX_PIN (1 << 5)
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#define UART_TX_PORT ((msp_port_t *)PORT_3)
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#define UART_TX_PIN (1 << 4)
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2015-08-27 14:20:53 +02:00
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#define UART_RX_ISR (USCIAB0RX_VECTOR)
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#define UART_TX_ISR (USCIAB0TX_VECTOR)
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2015-09-02 14:06:19 +02:00
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/** @} */
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/**
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2017-04-10 19:04:32 +02:00
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* @name SPI configuration
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2015-09-02 14:06:19 +02:00
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* @{
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*/
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#define SPI_NUMOF (1U)
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/* SPI configuration */
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2016-03-24 09:42:59 +01:00
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#define SPI_USE_USCI
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2016-11-08 18:20:38 +01:00
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#define SPI_BASE (USCI_0_B_SPI)
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2015-09-02 14:06:19 +02:00
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#define SPI_IE (SFR->IE2)
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#define SPI_IF (SFR->IFG2)
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#define SPI_IE_RX_BIT (1 << 2)
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#define SPI_IE_TX_BIT (1 << 3)
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2015-09-15 11:45:21 +02:00
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#define SPI_PIN_MISO GPIO_PIN(P3,2)
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#define SPI_PIN_MOSI GPIO_PIN(P3,1)
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#define SPI_PIN_CLK GPIO_PIN(P3,3)
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2015-08-27 14:20:53 +02:00
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/** @} */
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2015-08-26 18:46:57 +02:00
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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