2015-01-06 00:22:42 +01:00
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/*
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* Copyright (C) 2014 Freie Universität Berlin
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* Copyright (C) 2014 PHYTEC Messtechnik GmbH
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup board_pba-d-01-kw2x
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* @{
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*
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* @file
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* @name Peripheral MCU configuration for the phyWAVE-KW22 Board
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Johann Fischer <j.fischer@phytec.de>
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* @author Jonas Remmert <j.remmert@phytec.de>
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*/
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#ifndef __PERIPH_CONF_H
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#define __PERIPH_CONF_H
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#include "cpu-conf.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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#define KINETIS_CPU_USE_MCG 1
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#define KINETIS_MCG_USE_ERC 1
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#define KINETIS_MCG_USE_PLL 1
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#define KINETIS_MCG_DCO_RANGE (24000000U)
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#define KINETIS_MCG_ERC_OSCILLATOR 0
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#define KINETIS_MCG_ERC_FRDIV 2
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#define KINETIS_MCG_ERC_RANGE 1
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#define KINETIS_MCG_ERC_FREQ 4000000
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#define KINETIS_MCG_PLL_PRDIV 1
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#define KINETIS_MCG_PLL_VDIV0 0
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#define KINETIS_MCG_PLL_FREQ 48000000
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#define CLOCK_CORECLOCK KINETIS_MCG_PLL_FREQ
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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#define TIMER_NUMOF (1U)
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#define TIMER_0_EN 1
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#define TIMER_1_EN 0
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#define TIMER_IRQ_PRIO 1
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#define TIMER_DEV PIT
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#define TIMER_MAX_VALUE (0xffffffff)
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#define TIMER_CLOCK CLOCK_CORECLOCK
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#define TIMER_CLKEN() (SIM->SCGC6 |= (SIM_SCGC6_PIT_MASK))
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/* Timer 0 configuration */
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#define TIMER_0_PRESCALER_CH 0
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#define TIMER_0_COUNTER_CH 1
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#define TIMER_0_ISR isr_pit1
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#define TIMER_0_IRQ_CHAN PIT1_IRQn
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/* Timer 1 configuration */
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#define TIMER_1_PRESCALER_CH 2
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#define TIMER_1_COUNTER_CH 3
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#define TIMER_1_ISR isr_pit3
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#define TIMER_1_IRQ_CHAN PIT3_IRQn
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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#define UART_NUMOF (1U)
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#define UART_0_EN 1
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#define UART_1_EN 0
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#define UART_IRQ_PRIO 1
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#define UART_CLK (48e6)
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/* UART 0 device configuration */
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#define KINETIS_UART UART_Type
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#define UART_0_DEV UART2
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#define UART_0_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_UART2_MASK))
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#define UART_0_CLK UART_CLK
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#define UART_0_IRQ_CHAN UART2_RX_TX_IRQn
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#define UART_0_ISR isr_uart2_rx_tx
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/* UART 0 pin configuration */
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#define UART_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
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#define UART_0_PORT PORTD
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#define UART_0_RX_PIN 2
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#define UART_0_TX_PIN 3
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#define UART_0_AF 3
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/* UART 1 device configuration */
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#define UART_1_DEV UART0
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#define UART_1_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_UART0_MASK))
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#define UART_1_CLK UART_CLK
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#define UART_1_IRQ_CHAN UART0_RX_TX_IRQn
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#define UART_1_ISR isr_uart0_rx_tx
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/* UART 1 pin configuration */
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#define UART_1_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
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#define UART_1_PORT PORTD
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#define UART_1_RX_PIN 6
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#define UART_1_TX_PIN 7
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#define UART_1_AF 3
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/** @} */
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/**
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* @name ADC configuration
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* @{
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*/
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#define ADC_NUMOF (1U)
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#define ADC_0_EN 1
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#define ADC_MAX_CHANNELS 6
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/* ADC 0 configuration */
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#define ADC_0_DEV ADC0
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#define ADC_0_MODULE_CLOCK CLOCK_CORECLOCK
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#define ADC_0_CHANNELS 6
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#define ADC_0_CLKEN() (SIM->SCGC6 |= (SIM_SCGC6_ADC0_MASK))
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#define ADC_0_CLKDIS() (SIM->SCGC6 &= ~(SIM_SCGC6_ADC0_MASK))
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#define ADC_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK))
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/* ADC 0 channel 0 pin config */
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#define ADC_0_CH0 1
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#define ADC_0_CH0_PIN 2
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#define ADC_0_CH0_PIN_AF 0
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#define ADC_0_CH0_PORT PORTE
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/* ADC 0 channel 1 pin config */
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#define ADC_0_CH1 1 /* PTE3 uses the same ADC_CH as PTE2, in single channel mode only one of them can be selected */
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#define ADC_0_CH1_PIN 3
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#define ADC_0_CH1_PIN_AF 0
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#define ADC_0_CH1_PORT PORTE
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/* ADC 0 channel 2 pin config */
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#define ADC_0_CH2 22
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#define ADC_0_CH2_PIN 7
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#define ADC_0_CH2_PIN_AF 0
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#define ADC_0_CH2_PORT PORTD
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/* ADC 0 channel 3 pin config */
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#define ADC_0_CH3 6
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#define ADC_0_CH3_PIN 5
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#define ADC_0_CH3_PIN_AF 0
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#define ADC_0_CH3_PORT PORTD
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/* ADC 0 channel 4 pin config */
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#define ADC_0_CH4 10
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#define ADC_0_CH4_PIN 0
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#define ADC_0_CH4_PIN_AF 0
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#define ADC_0_CH4_PORT PORTE
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/* ADC 0 channel 5 pin config */
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#define ADC_0_CH5 11
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#define ADC_0_CH5_PIN 1
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#define ADC_0_CH5_PIN_AF 0
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#define ADC_0_CH5_PORT PORTE
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/** @} */
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/**
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* @name PWM configuration
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* @{
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*/
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#define PWM_NUMOF (1U)
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#define PWM_0_EN 1
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#define PWM_MAX_CHANNELS 4
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2015-05-16 01:10:16 +02:00
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#define PWM_MAX_VALUE 0xffff
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2015-01-06 00:22:42 +01:00
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/* PWM 0 device configuration */
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#define PWM_0_DEV FTM0
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#define PWM_0_CHANNELS 3
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#define PWM_0_CLK (48e6)
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#define PWM_0_CLKEN() (SIM->SCGC6 |= (SIM_SCGC6_FTM0_MASK))
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#define PWM_0_CLKDIS() (SIM->SCGC6 &= ~(SIM_SCGC6_FTM0_MASK))
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/* PWM 0 pin configuration */
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#define PWM_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTA_MASK))
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#define PWM_0_PIN_CH0 4
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#define PWM_0_FTMCHAN_CH0 1
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#define PWM_0_PORT_CH0 PORTA
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#define PWM_0_PIN_AF_CH0 3
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#define PWM_0_PIN_CH1 4
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#define PWM_0_FTMCHAN_CH1 4
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#define PWM_0_PORT_CH1 PORTD
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#define PWM_0_PIN_AF_CH1 4
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#define PWM_0_PIN_CH2 6
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#define PWM_0_FTMCHAN_CH2 6
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#define PWM_0_PORT_CH2 PORTD
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#define PWM_0_PIN_AF_CH2 4
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#define PWM_0_PIN_CH3 1
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#define PWM_0_FTMCHAN_CH3 1
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#define PWM_0_PORT_CH3 PORTA
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#define PWM_0_PIN_AF_CH3 3
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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#define SPI_NUMOF (2U)
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#define SPI_0_EN 1
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#define SPI_1_EN 1
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#define SPI_IRQ_PRIO 1
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#define KINETIS_SPI_USE_HW_CS 1
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/* SPI 0 device config */
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#define SPI_0_DEV SPI0
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#define SPI_0_INDEX 0
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#define SPI_0_CTAS 0
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#define SPI_0_CLKEN() (SIM->SCGC6 |= (SIM_SCGC6_SPI0_MASK))
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#define SPI_0_CLKDIS() (SIM->SCGC6 &= ~(SIM_SCGC6_SPI0_MASK))
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#define SPI_0_IRQ SPI0_IRQn
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#define SPI_0_IRQ_HANDLER isr_spi0
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#define SPI_0_FREQ (48e6)
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/* SPI 0 pin configuration */
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#define SPI_0_PORT PORTC
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#define SPI_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTC_MASK))
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#define SPI_0_AF 2
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#define SPI_0_PCS0_PIN 4
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#define SPI_0_SCK_PIN 5
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#define SPI_0_SOUT_PIN 6
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#define SPI_0_SIN_PIN 7
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#define SPI_0_PCS0_ACTIVE_LOW 1
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/* SPI 1 device config */
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#define SPI_1_DEV SPI1
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#define SPI_1_INDEX 1
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#define SPI_1_CTAS 0
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#define SPI_1_CLKEN() (SIM->SCGC6 |= (SIM_SCGC6_SPI1_MASK))
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#define SPI_1_CLKDIS() (SIM->SCGC6 &= ~(SIM_SCGC6_SPI1_MASK))
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#define SPI_1_IRQ SPI1_IRQn
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#define SPI_1_IRQ_HANDLER isr_spi1
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#define SPI_1_FREQ (48e6)
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/* SPI 1 pin1configuration */
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#define SPI_1_PORT KW2XDRF_PORT
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#define SPI_1_PORT_CLKEN() KW2XDRF_PORT_CLKEN();
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#define SPI_1_AF KW2XDRF_PIN_AF
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#define SPI_1_PCS0_PIN KW2XDRF_PCS0_PIN
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#define SPI_1_SCK_PIN KW2XDRF_SCK_PIN
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#define SPI_1_SOUT_PIN KW2XDRF_SOUT_PIN
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#define SPI_1_SIN_PIN KW2XDRF_SIN_PIN
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#define SPI_1_PCS0_ACTIVE_LOW 1
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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#define I2C_NUMOF (1U)
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#define I2C_CLK (48e6)
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#define I2C_0_EN 1
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#define I2C_IRQ_PRIO 1
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/* Low (10 kHz): MUL = 4, SCL divider = 2560, total: 10240 */
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#define KINETIS_I2C_F_ICR_LOW (0x3D)
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#define KINETIS_I2C_F_MULT_LOW (2)
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/* Normal (100 kHz): MUL = 2, SCL divider = 240, total: 480 */
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#define KINETIS_I2C_F_ICR_NORMAL (0x1F)
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#define KINETIS_I2C_F_MULT_NORMAL (1)
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/* Fast (400 kHz): MUL = 1, SCL divider = 128, total: 128 */
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#define KINETIS_I2C_F_ICR_FAST (0x17)
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#define KINETIS_I2C_F_MULT_FAST (0)
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/* Fast plus (1000 kHz): MUL = 1, SCL divider = 48, total: 48 */
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#define KINETIS_I2C_F_ICR_FAST_PLUS (0x10)
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#define KINETIS_I2C_F_MULT_FAST_PLUS (0)
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/* I2C 0 device configuration */
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#define I2C_0_DEV I2C1
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#define I2C_0_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_I2C1_MASK))
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#define I2C_0_CLKDIS() (SIM->SCGC4 &= ~(SIM_SCGC4_I2C1_MASK))
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#define I2C_0_IRQ I2C1_IRQn
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#define I2C_0_IRQ_HANDLER isr_i2c1
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/* I2C 0 pin configuration */
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#define I2C_0_PORT PORTE
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#define I2C_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
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#define I2C_0_PIN_AF 6
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#define I2C_0_SDA_PIN 0
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#define I2C_0_SCL_PIN 1
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#define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
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/** @} */
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/**
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* @name GPIO configuration
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* @{
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*/
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#define GPIO_NUMOF 8
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#define GPIO_0_EN 1
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#define GPIO_1_EN 1
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#define GPIO_2_EN 1
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#define GPIO_3_EN 1
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#define GPIO_4_EN 1
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#define GPIO_5_EN 1
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#define GPIO_6_EN 0
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#define GPIO_7_EN 0
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#define GPIO_8_EN 0 /* I2CSDA */
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#define GPIO_9_EN 0 /* I2CSCL */
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#define GPIO_10_EN 0
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#define GPIO_11_EN 0
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#define GPIO_12_EN 0
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#define GPIO_13_EN 0 /* USB VOUT 3V3 */
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#define GPIO_14_EN 0 /* USB VREGIN */
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#define GPIO_15_EN 0
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#define GPIO_16_EN 0
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#define GPIO_17_EN 0
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#define GPIO_18_EN 0
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#define GPIO_19_EN 0 /* SPI0_CS0 */
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#define GPIO_20_EN 0 /* SPI0_CLK */
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#define GPIO_21_EN 0 /* SPI0_MOSI */
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#define GPIO_22_EN 0 /* SPI0_MISO */
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#define GPIO_23_EN 1 /* KW2XRF INT */
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#define GPIO_24_EN 1 /* KW2XRF CS */
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#define GPIO_IRQ_PRIO 1
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#define ISR_PORT_A isr_porta
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#define ISR_PORT_B isr_portb
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#define ISR_PORT_C isr_portc
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#define ISR_PORT_D isr_portd
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/* GPIO channel 0 config */
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#define GPIO_0_DEV GPIOD /* DIO9; extension connecotr D9; LED_G */
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#define GPIO_0_PORT PORTD
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#define GPIO_0_PORT_BASE PORTD_BASE
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#define GPIO_0_PIN 4
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#define GPIO_0_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
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#define GPIO_0_IRQ PORTD_IRQn
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/* GPIO channel 1 config */
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#define GPIO_1_DEV GPIOD /* DIO11; extension connecotr D5; LED_R */
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#define GPIO_1_PORT PORTD
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#define GPIO_1_PORT_BASE PORTD_BASE
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#define GPIO_1_PIN 6
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#define GPIO_1_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
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#define GPIO_1_IRQ PORTD_IRQn
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/* GPIO channel 2 config */
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#define GPIO_2_DEV GPIOA /* DIO27; extension connecotr D3; LED_B */
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#define GPIO_2_PORT PORTA
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#define GPIO_2_PORT_BASE PORTA_BASE
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#define GPIO_2_PIN 4
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#define GPIO_2_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK))
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#define GPIO_2_IRQ PORTA_IRQn
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/* GPIO channel 3 config */
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#define GPIO_3_DEV GPIOD /* DIO06; extension connecotr --; User_Button */
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#define GPIO_3_PORT PORTD
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#define GPIO_3_PORT_BASE PORTD_BASE
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#define GPIO_3_PIN 1
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#define GPIO_3_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
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#define GPIO_3_IRQ PORTD_IRQn
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/* GPIO channel 4 config */
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#define GPIO_4_DEV GPIOE /* DIO17; extension connecotr D2 */
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#define GPIO_4_PORT PORTE
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#define GPIO_4_PORT_BASE PORTE_BASE
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#define GPIO_4_PIN 4
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#define GPIO_4_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
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#define GPIO_4_IRQ PORTE_IRQn
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/* GPIO channel 5 config */
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#define GPIO_5_DEV GPIOA /* DIO29; extension connecotr D4 */
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#define GPIO_5_PORT PORTA
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#define GPIO_5_PORT_BASE PORTA_BASE
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#define GPIO_5_PIN 19
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#define GPIO_5_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK))
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#define GPIO_5_IRQ PORTA_IRQn
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/* GPIO channel 6 config */
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#define GPIO_6_DEV GPIOD /* DIO10; extension connecotr A3 */
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#define GPIO_6_PORT PORTD
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#define GPIO_6_PORT_BASE PORTD_BASE
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#define GPIO_6_PIN 5
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#define GPIO_6_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
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#define GPIO_6_IRQ PORTD_IRQn
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/* GPIO channel 7 config */
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#define GPIO_7_DEV GPIOD /* DIO12; extension connecotr A2 */
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#define GPIO_7_PORT PORTD
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#define GPIO_7_PORT_BASE PORTD_BASE
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#define GPIO_7_PIN 7
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#define GPIO_7_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
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#define GPIO_7_IRQ PORTD_IRQn
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/* GPIO channel 8 config */
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#define GPIO_8_DEV GPIOE /* DIO13; extension connecotr A4; I2CSDA */
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#define GPIO_8_PORT PORTE
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#define GPIO_8_PORT_BASE PORTE_BASE
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#define GPIO_8_PIN 0
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#define GPIO_8_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
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#define GPIO_8_IRQ PORTE_IRQn
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/* GPIO channel 9 config */
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#define GPIO_9_DEV GPIOE /* DIO14; extension connecotr A5; I2CSCL */
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#define GPIO_9_PORT PORTE
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#define GPIO_9_PORT_BASE PORTE_BASE
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#define GPIO_9_PIN 1
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#define GPIO_9_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
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#define GPIO_9_IRQ PORTE_IRQn
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/* GPIO channel 10 config */
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#define GPIO_10_DEV GPIOE /* DIO15; extension connecotr A0 */
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#define GPIO_10_PORT PORTE
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#define GPIO_10_PORT_BASE PORTE_BASE
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#define GPIO_10_PIN 2
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#define GPIO_10_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
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#define GPIO_10_IRQ PORTE_IRQn
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/* GPIO channel 11 config */
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#define GPIO_11_DEV GPIOE /* DIO16; extension connecotr A1 */
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#define GPIO_11_PORT PORTE
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#define GPIO_11_PORT_BASE PORTE_BASE
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#define GPIO_11_PIN 3
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#define GPIO_11_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
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#define GPIO_11_IRQ PORTE_IRQn
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/* GPIO channel 12 config */
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#define GPIO_12_DEV GPIOD /* DIO7; extension connecotr D0; UART2_RX */
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#define GPIO_12_PORT PORTD
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#define GPIO_12_PORT_BASE PORTD_BASE
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#define GPIO_12_PIN 2
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#define GPIO_12_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
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#define GPIO_12_IRQ PORTD_IRQn
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/* GPIO channel 13 config */
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#define GPIO_13_DEV GPIOE /* DIO20; extension connecotr D14, USB OUT3V3 */
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#define GPIO_13_PORT PORTE
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#define GPIO_13_PORT_BASE PORTE_BASE
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#define GPIO_13_PIN 18
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#define GPIO_13_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
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#define GPIO_13_IRQ PORTE_IRQn
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/* GPIO channel 14 config */
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#define GPIO_14_DEV GPIOE /* DIO21; extension connecotr D15, USB VREGIN */
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#define GPIO_14_PORT PORTE
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#define GPIO_14_PORT_BASE PORTE_BASE
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#define GPIO_14_PIN 19
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#define GPIO_14_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
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#define GPIO_14_IRQ PORTE_IRQn
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/* GPIO channel 15 config */
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#define GPIO_15_DEV GPIOA /* DIO24; extension connecotr D7 */
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#define GPIO_15_PORT PORTA
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#define GPIO_15_PORT_BASE PORTA_BASE
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#define GPIO_15_PIN 1
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#define GPIO_15_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK))
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#define GPIO_15_IRQ PORTA_IRQn
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/* GPIO channel 16 config */
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#define GPIO_16_DEV GPIOA /* DIO25; extension connecotr D6 */
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#define GPIO_16_PORT PORTA
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#define GPIO_16_PORT_BASE PORTA_BASE
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#define GPIO_16_PIN 2
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#define GPIO_16_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK))
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#define GPIO_16_IRQ PORTA_IRQn
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/* GPIO channel 17 config */
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#define GPIO_17_DEV GPIOA /* DIO28; extension connecotr D8 */
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#define GPIO_17_PORT PORTA
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#define GPIO_17_PORT_BASE PORTA_BASE
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#define GPIO_17_PIN 18
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#define GPIO_17_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK))
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#define GPIO_17_IRQ PORTA_IRQn
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/* GPIO channel 18 config */
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#define GPIO_18_DEV GPIOD /* DIO8; extension connecotr D1; UART2_TX */
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#define GPIO_18_PORT PORTD
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#define GPIO_18_PORT_BASE PORTD_BASE
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#define GPIO_18_PIN 3
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#define GPIO_18_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTD_MASK))
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#define GPIO_18_IRQ PORTD_IRQn
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/* GPIO channel 19 config */
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#define GPIO_19_DEV GPIOC /* DIO2; extension connecotr D10; SPI0_CS0 */
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#define GPIO_19_PORT PORTC
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#define GPIO_19_PORT_BASE PORTC_BASE
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#define GPIO_19_PIN 4
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#define GPIO_19_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTC_MASK))
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#define GPIO_19_IRQ PORTC_IRQn
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/* GPIO channel 20 config */
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#define GPIO_20_DEV GPIOC /* DIO3; extension connecotr D13; SPI0_CLK */
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#define GPIO_20_PORT PORTC
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#define GPIO_20_PORT_BASE PORTC_BASE
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#define GPIO_20_PIN 5
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#define GPIO_20_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTC_MASK))
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#define GPIO_20_IRQ PORTC_IRQn
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/* GPIO channel 21 config */
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#define GPIO_21_DEV GPIOC /* DIO4; extension connecotr D11; SPI0_MOSI */
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#define GPIO_21_PORT PORTC
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#define GPIO_21_PORT_BASE PORTC_BASE
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#define GPIO_21_PIN 6
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#define GPIO_21_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTC_MASK))
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#define GPIO_21_IRQ PORTC_IRQn
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/* GPIO channel 22 config */
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#define GPIO_22_DEV GPIOC /* DIO5; extension connecotr D12; SPI0_MISO */
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#define GPIO_22_PORT PORTC
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#define GPIO_22_PORT_BASE PORTC_BASE
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#define GPIO_22_PIN 7
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#define GPIO_22_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTC_MASK))
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#define GPIO_22_IRQ PORTC_IRQn
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/* GPIO channel 23 config */
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#define GPIO_23_DEV KW2XDRF_GPIO
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#define GPIO_23_PORT KW2XDRF_PORT
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#define GPIO_23_PORT_BASE KW2XDRF_PORT_BASE
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#define GPIO_23_PIN KW2XDRF_IRQ_PIN
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#define GPIO_23_CLKEN() KW2XDRF_PORT_CLKEN()
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#define GPIO_23_IRQ KW2XDRF_PORT_IRQn
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#define GPIO_KW2XDRF GPIO_23
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/* GPIO channel 24 config */
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#define GPIO_24_DEV KW2XDRF_GPIO
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#define GPIO_24_PORT KW2XDRF_PORT
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#define GPIO_24_PORT_BASE KW2XDRF_PORT_BASE
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#define GPIO_24_PIN KW2XDRF_PCS0_PIN
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#define GPIO_24_CLKEN() KW2XDRF_PORT_CLKEN()
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#define GPIO_24_IRQ KW2XDRF_PORT_IRQn
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#define KW2XRF_CS_GPIO GPIO_24
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/** @} */
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/**
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* @name RTT and RTC configuration
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* @{
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*/
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#define RTT_NUMOF (1U)
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#define RTC_NUMOF (1U)
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#define RTT_DEV RTC
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#define RTT_IRQ RTC_IRQn
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#define RTT_IRQ_PRIO 10
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#define RTT_UNLOCK() (SIM->SCGC6 |= (SIM_SCGC6_RTC_MASK))
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#define RTT_ISR isr_rtc
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#define RTT_FREQUENCY (1)
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#define RTT_MAX_VALUE (0xffffffff)
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/** @} */
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/**
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* @name Random Number Generator configuration
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* @{
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*/
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#define RANDOM_NUMOF (1U)
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#define KINETIS_RNGA RNG
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#define RANDOM_CLKEN() (SIM->SCGC6 |= (1 << 9))
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#define RANDOM_CLKDIS() (SIM->SCGC6 &= ~(1 << 9))
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __PERIPH_CONF_H */
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/** @} */
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