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https://github.com/RIOT-OS/RIOT.git
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78 lines
3.8 KiB
C
78 lines
3.8 KiB
C
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/*
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* Copyright (C) 2020 iosabi
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_qn908x
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* @{
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*
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* @file
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*
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* @brief Interrupt vector for NXP QN908x MCUs
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*
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* @author iosabi <iosabi@protonmail.com>
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*/
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/**
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* @name Interrupt vector definition
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* @{
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*/
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#include "board.h"
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#include "vectors_cortexm.h"
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#include "vectors_qn908x.h"
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/* CPU specific interrupt vector table */
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ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
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[EXT_GPIO_WAKEUP_IRQn] = isr_ext_gpio_wakeup, /* Ext GPIO wakeup */
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[OSC_IRQn ] = isr_osc, /* BLE wakeup */
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[ACMP0_IRQn ] = isr_acmp0, /* Analog comparator0 */
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[ACMP1_IRQn ] = isr_acmp1, /* Analog comparator1 */
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[RTC_SEC_IRQn ] = isr_rtc_sec, /* RTC second */
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[RTC_FR_IRQn ] = isr_rtc_fr, /* RTC free running */
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[CS_WAKEUP_IRQn ] = isr_cs_wakeup, /* Capacitive sense wakeup */
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[CS_IRQn ] = isr_cs, /* Capacitive sense */
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[GPIOA_IRQn ] = isr_gpioa, /* GPIO group A */
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[GPIOB_IRQn ] = isr_gpiob, /* GPIO group B */
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[DMA0_IRQn ] = isr_dma0, /* DMA controller */
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[PIN_INT0_IRQn ] = isr_pin_int0, /* pin or pattern match engine slice 0 */
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[PIN_INT1_IRQn ] = isr_pin_int1, /* pin or pattern match engine slice 1 */
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[PIN_INT2_IRQn ] = isr_pin_int2, /* pin or pattern match engine slice 2 */
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[PIN_INT3_IRQn ] = isr_pin_int3, /* pin or pattern match engine slice 3 */
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[OSC_INT_LOW_IRQn ] = isr_osc_int_low, /* Inverse of OSC */
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[USB0_IRQn ] = isr_usb0, /* USB device */
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[FLEXCOMM0_IRQn ] = isr_flexcomm0, /* Flexcomm Interface 0 (USART) */
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[FLEXCOMM1_IRQn ] = isr_flexcomm1, /* Flexcomm Interface 1 (USART, I2C) */
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[FLEXCOMM2_IRQn ] = isr_flexcomm2, /* Flexcomm Interface 2 (SPI, I2C) */
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[FLEXCOMM3_IRQn ] = isr_flexcomm3, /* Flexcomm Interface 3 (SPI) */
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[BLE_IRQn ] = isr_ble, /* BLE interrupts */
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[FSP_IRQn ] = isr_fsp, /* FSP */
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[QDEC0_IRQn ] = isr_qdec0, /* QDEC0 */
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[QDEC1_IRQn ] = isr_qdec1, /* QDEC1 */
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[CTIMER0_IRQn ] = isr_ctimer0, /* Standard counter/timer CTIMER0 */
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[CTIMER1_IRQn ] = isr_ctimer1, /* Standard counter/timer CTIMER1 */
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[CTIMER2_IRQn ] = isr_ctimer2, /* Standard counter/timer CTIMER2 */
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[CTIMER3_IRQn ] = isr_ctimer3, /* Standard counter/timer CTIMER3 */
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[WDT_IRQn ] = isr_wdt, /* Watch dog timer */
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[ADC_IRQn ] = isr_adc, /* ADC */
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[DAC_IRQn ] = isr_dac, /* DAC */
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[XTAL_READY_IRQn ] = isr_xtal_ready, /* High frequency crystal ready */
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[FLASH_IRQn ] = isr_flash, /* Flash */
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[SPIFI0_IRQn ] = isr_spifi0, /* SPI flash interface */
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[SCT0_IRQn ] = isr_sct0, /* SCTimer/PWM */
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[RNG_IRQn ] = isr_rng, /* Random number generator */
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[CALIB_IRQn ] = isr_calib, /* Calibration */
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[BLE_TX_IRQn ] = isr_ble_tx, /* ble tx flag */
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[BLE_RX_IRQn ] = isr_ble_rx, /* ble rx flag */
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[BLE_FREQ_HOP_IRQn] = isr_ble_freq_hop, /* ble frequency hop */
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[BOD_IRQn ] = isr_bod, /* Brown out detect */
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};
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__attribute__((weak)) const uint32_t isp_configuration = 0;
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/** @} */
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