RIOT-OS/RIOT
RIOT-OS/RIOT
1
0
Fork 0
mirror of https://github.com/RIOT-OS/RIOT.git synced 2024-12-29 04:50:03 +01:00
Code Releases Activity
2ae7566a89
RIOT/cpu/qn908x/include/gpio_mux.h

82 lines
1.9 KiB
C
Raw Normal View History

cpu/qn908x: Initial minimal support for NXP QN908x CPUs. The NXP QN908x CPU family is a Cortex-M4F CPU with integrated USB, Bluetooth Low Energy and in some variants NFC. This patch implements the first steps for having support for this CPU. While the QN908x can be considered the successor of similar chips from NXP like the KW41Z when looking at the feature set, the internal architecture, boot image format and CPU peripherals don't match those in the Kinetis line. Therefore, this patch creates a new directory for just the QN908x chip under cpu/qn908x. The minimal set of peripherals are implemented in this patch to allow the device to boot and enable a GPIO: the gpio and wdt peripheral modules only. The wdt driver is required to boot and disable the wdt. On reset, the wdt is disabled by the chip, however the QN908x bootloader stored in the internal ROM enables the wdt and sets a timer to reboot after 10 seconds, therefore it is needed to disable the wdt in RIOT OS soon after booting. This patch sets it up such that when no periph_wdt module is used the Watchdog is disabled, but if the periph_wdt is used it must be configured (initialized) within the first 10 seconds. Tests performed: Defined a custom board for this CPU and compiled a simple application that blinks some LEDs. Manually tested with periph_wdt and with periph_wdt_cb as well.
2020-04-10 14:26:17 +02:00
/*
* Copyright (C) 2020 iosabi
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_qn908x
*
* @{
*
* @file
* @brief Common Pin MUX functions.
*
* The pins in this CPU are multiplexed to several different function. This
* module allows to configure the pin multiplexer (MUX) from peripheral drivers.
*
* @author iosabi <iosabi@protonmail.com>
*/
#ifndef GPIO_MUX_H
#define GPIO_MUX_H
#include <stdint.h>
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Obtain the GPIO_BASE address from a GPIO_PIN(x, y) value.
*/
#define GPIO_T_ADDR_BASE(pin) (GPIOA_BASE + ((pin) & 0xf000u))
/**
* @brief Obtain the GPIO_BASE GPIO_Type* pointer from a GPIO_PIN(x, y) value.
*/
#define GPIO_T_ADDR(pin) ((GPIO_Type *)(GPIO_T_ADDR_BASE(pin)))
/**
* @brief Obtain the "x" port number (0 based) from a GPIO_PIN(x, y) value.
*
* This macro needs to be kept in sync with the definition of GPIO_PIN.
*/
#define GPIO_T_PORT(pin) ((gpio_t)(pin) >> 12u)
/**
* @brief Obtain the pin number "y" from a GPIO_PIN(x, y) value.
*/
#define GPIO_T_PIN(pin) ((pin) & 0x00ffu)
#if defined(GPIOB_BASE) && (GPIO_T_ADDR_BASE(GPIO_PIN(1, 1)) != GPIOB_BASE)
#error "GPIO_T_ADDR(GPIO_PIN(1, x)) must be the GPIOB address"
#endif
cpu/qn908x: Implement blocking SPI support. This patch implements the basic support the last of the FLEXCOMM modes, Serial Peripheral Interface, in a simple blocking mode with busy wait, which is enough to test all the SPI functionality end-to-end. Tested reading and writing registers on a SPI peripheral, and checked with the oscilloscope that the frequencies were as expected. Results from `tests/periph_spi`: ``` > init 0 0 2 -1 0 SPI_DEV(0) initialized: mode: 0, clk: 2, cs_port: -1, cs_pin: 0 > bench 1 - write 1000 times 1 byte: 16002 16009 2 - write 1000 times 2 byte: 18001 18008 3 - write 1000 times 100 byte: 802000 802007 4 - write 1000 times 1 byte to register: 24003 24010 5 - write 1000 times 2 byte to register: 26001 26008 6 - write 1000 times 100 byte to register: 810001 810008 7 - read 1000 times 2 byte: 23003 23009 8 - read 1000 times 100 byte: 807002 807009 9 - read 1000 times 2 byte from register: 32002 32009 10 - read 1000 times 100 byte from register: 816002 816009 11 - transfer 1000 times 2 byte: 23003 23009 12 - transfer 1000 times 100 byte: 807003 807010 13 - transfer 1000 times 2 byte to register: 32003 32009 14 - transfer 1000 times 100 byte to register:816002 816009 15 - acquire/release 1000 times: 7222 7228 -- - SUM: 5059250 5059351 ```
2020-12-20 19:17:44 +01:00
/**
* @brief Return whether the given pin is a CSHW pin.
*/
#define GPIO_T_IS_HWCS(pin) (((pin) & 0xff00u) == 0x8000)
/**
* @brief Return the given CSHW number from the gpio_t pin.
*/
#define GPIO_T_HWCS(pin) ((pin) & 0x0003u)
cpu/qn908x: Initial minimal support for NXP QN908x CPUs. The NXP QN908x CPU family is a Cortex-M4F CPU with integrated USB, Bluetooth Low Energy and in some variants NFC. This patch implements the first steps for having support for this CPU. While the QN908x can be considered the successor of similar chips from NXP like the KW41Z when looking at the feature set, the internal architecture, boot image format and CPU peripherals don't match those in the Kinetis line. Therefore, this patch creates a new directory for just the QN908x chip under cpu/qn908x. The minimal set of peripherals are implemented in this patch to allow the device to boot and enable a GPIO: the gpio and wdt peripheral modules only. The wdt driver is required to boot and disable the wdt. On reset, the wdt is disabled by the chip, however the QN908x bootloader stored in the internal ROM enables the wdt and sets a timer to reboot after 10 seconds, therefore it is needed to disable the wdt in RIOT OS soon after booting. This patch sets it up such that when no periph_wdt module is used the Watchdog is disabled, but if the periph_wdt is used it must be configured (initialized) within the first 10 seconds. Tests performed: Defined a custom board for this CPU and compiled a simple application that blinks some LEDs. Manually tested with periph_wdt and with periph_wdt_cb as well.
2020-04-10 14:26:17 +02:00
/**
* @brief Configure the pin mux to the given function.
*
* The meaning of the function value will depend on the gpio pin.
*/
void gpio_init_mux(gpio_t pin, uint32_t func);
#ifdef __cplusplus
}
#endif
#endif /* GPIO_MUX_H */
/** @} */
Copy Permalink