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RIOT/cpu/riscv_common/ldscripts/riscv_vars.ld

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fe310: Unify linker scripts Similar to the cortex-m common linker scripts, the RISC-V linker scripts can be unified easily, requiring only the memory addresses and lengths. This simplifies adding new RISC-V CPU's later
2020-09-01 10:08:59 +02:00
/*
* Copyright (C) 2020 Inria
* 2020 Koen Zandberg <koen@bergzand.net
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
riscv_common: Refactor common fe310 code to riscv_common
2020-09-09 21:37:15 +02:00
* @addtogroup cpu_riscv_common
fe310: Unify linker scripts Similar to the cortex-m common linker scripts, the RISC-V linker scripts can be unified easily, requiring only the memory addresses and lengths. This simplifies adding new RISC-V CPU's later
2020-09-01 10:08:59 +02:00
* @{
*
* @file
riscv_common: Refactor common fe310 code to riscv_common
2020-09-09 21:37:15 +02:00
* @brief Linker variables for the RISC-V CPU
fe310: Unify linker scripts Similar to the cortex-m common linker scripts, the RISC-V linker scripts can be unified easily, requiring only the memory addresses and lengths. This simplifies adding new RISC-V CPU's later
2020-09-01 10:08:59 +02:00
*
* @author Koen Zandberg <koen@bergzand.net>
*
* @}
*/
_itim_start_addr = DEFINED( _itim_start_addr ) ? _itim_start_addr : 0x0;
_itim_length = DEFINED( _itim_length ) ? _itim_length : 0x0;
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