2017-10-17 16:41:55 +02:00
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/*
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* Copyright (C) 2017 Inria
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2018-06-13 13:50:42 +02:00
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* 2018 Freie Universität Berlin
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2017-10-17 16:41:55 +02:00
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @addtogroup cpu_cortexm_common
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* @{
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*
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* @file
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* @brief Memory definitions for the Cortex-M family
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*
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* @author Francisco Acosta <francisco.acosta@inria.fr>
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2018-06-13 13:50:42 +02:00
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* Gaëtan Harter <gaetan.harter@inria.fr>
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2017-10-17 16:41:55 +02:00
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*
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* @}
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*/
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2018-06-13 13:50:42 +02:00
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_rom_offset = DEFINED( _rom_offset ) ? _rom_offset : 0x0;
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2018-06-13 17:31:32 +02:00
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_fw_rom_length = DEFINED( _fw_rom_length ) ? _fw_rom_length : _rom_length - _rom_offset;
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ASSERT((_fw_rom_length <= _rom_length - _rom_offset), "Specified firmware size does not fit in ROM");
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2017-10-17 16:41:55 +02:00
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MEMORY
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{
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2018-07-16 14:13:04 +02:00
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rom (rx) : ORIGIN = _rom_start_addr + _rom_offset, LENGTH = _fw_rom_length
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2018-06-13 13:50:42 +02:00
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ram (w!rx) : ORIGIN = _ram_start_addr, LENGTH = _ram_length
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2017-10-17 16:41:55 +02:00
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}
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INCLUDE cortexm_base.ld
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