RIOT/boards/hifive1b/Makefile.include

# set default port depending on operating system
PORT_LINUX ?= /dev/ttyACM0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))

# setup serial terminal
include $(RIOTMAKE)/tools/serial.inc.mk

# setup JLink for flashing
# export JLINK := JLink
JLINK_DEVICE = FE310
JLINK_IF = JTAG
FLASH_ADDR = 0x20010000
include $(RIOTMAKE)/tools/jlink.inc.mk

TESTRUNNER_RESET_DELAY = 1
$(call target-export-variables,test,TESTRUNNER_RESET_DELAY)
cpu/hifive1b: initial HiFive1B support Initial support for HiFive1B board with FE310_G002 CPU 2019-06-25 19:16:43 +02:00			`# set default port depending on operating system`
boards/hifive1b: fix default serial port The board provides a JLink adapter which is exposed as /dev/ttyACMx on Linux. STDIO UART is available on this port 2019-11-07 14:14:05 +01:00			`PORT_LINUX ?= /dev/ttyACM0`
cpu/hifive1b: initial HiFive1B support Initial support for HiFive1B board with FE310_G002 CPU 2019-06-25 19:16:43 +02:00			`PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))`

			`# setup serial terminal`
			`include $(RIOTMAKE)/tools/serial.inc.mk`

			`# setup JLink for flashing`
			`# export JLINK := JLink`
boards: unexport JLINK_DEVICE variable 2020-03-03 11:56:38 +01:00			`JLINK_DEVICE = FE310`
boards: don't export JLINK_IF 2020-03-03 16:14:54 +01:00			`JLINK_IF = JTAG`
boards: don't export FLASH_ADDR This variable is already export in vars.inc.mk 2020-03-03 16:22:30 +01:00			`FLASH_ADDR = 0x20010000`
cpu/hifive1b: initial HiFive1B support Initial support for HiFive1B board with FE310_G002 CPU 2019-06-25 19:16:43 +02:00			`include $(RIOTMAKE)/tools/jlink.inc.mk`
boards/hifive1b: set custom reset delay of 1s for tests 2020-01-10 08:34:45 +01:00
			`TESTRUNNER_RESET_DELAY = 1`
			`$(call target-export-variables,test,TESTRUNNER_RESET_DELAY)`