2018-04-16 19:03:33 +02:00
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/*
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2019-06-25 19:13:15 +02:00
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* Copyright (C) 2017, 2019 Ken Rabold
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2018-04-16 19:03:33 +02:00
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @addtogroup cpu_fe310
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* @{
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*
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* @file
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2019-06-25 19:13:15 +02:00
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* @brief Memory definitions for the SiFive FE310_G002
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2018-04-16 19:03:33 +02:00
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*
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* @author Ken Rabold
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*
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* @}
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*/
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MEMORY
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{
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2019-06-25 19:13:15 +02:00
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flash (rxai!w) : ORIGIN = 0x20010000, LENGTH = 0x0006a120
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ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x00004000
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itim (wxa!ri) : ORIGIN = 0x08000000, LENGTH = 0x00002000
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2018-04-16 19:03:33 +02:00
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}
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2019-09-19 20:21:15 +02:00
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INCLUDE fe310_base.ld
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